WO2020124767A1 - Tft基板的制作方法及tft基板 - Google Patents

Tft基板的制作方法及tft基板 Download PDF

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Publication number
WO2020124767A1
WO2020124767A1 PCT/CN2019/075528 CN2019075528W WO2020124767A1 WO 2020124767 A1 WO2020124767 A1 WO 2020124767A1 CN 2019075528 W CN2019075528 W CN 2019075528W WO 2020124767 A1 WO2020124767 A1 WO 2020124767A1
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Prior art keywords
layer
photoresist
metal
insulating layer
gate
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French (fr)
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李莎莎
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Priority to US16/485,441 priority Critical patent/US11158717B1/en
Publication of WO2020124767A1 publication Critical patent/WO2020124767A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/665—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum
    • H10D64/666—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum the conductor further comprising additional layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0314—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral top-gate TFTs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6731—Top-gate only TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
    • H10D30/6739—Conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6745—Polycrystalline or microcrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0231—Manufacture or treatment of multiple TFTs using masks, e.g. half-tone masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3434—Deposited materials, e.g. layers characterised by the chemical composition being oxide semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/301—Marks applied to devices, e.g. for alignment or identification for alignment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/601—Marks applied to devices, e.g. for alignment or identification for use after dicing
    • H10W46/607—Located on parts of packages, e.g. on encapsulations or on package substrates

Definitions

  • the present invention relates to the field of display technology, and in particular, to a method for manufacturing a TFT substrate and a TFT substrate.
  • LCD Liquid Crystal Display
  • AMOLED Active Matrix Organic Light-Emitting Flat panel display devices
  • LCD Liquid Crystal Display
  • AMOLED Active Matrix Organic Light-Emitting Flat panel display devices
  • the display panel is an important part of the liquid crystal display and the organic light emitting diode display.
  • the liquid crystal display panel is generally composed of a color filter substrate (CF, Color Filter), a thin film transistor substrate (TFT, Thin Film Transistor), and a liquid crystal (LC) sandwiched between the color filter substrate and the thin film transistor substrate , Liquid Crystal) and Sealant (Sealant).
  • the thin film transistor array (Array) substrate is currently the main component of the LCD device and the AMOLED device, which is directly related to the development direction of the high-performance flat panel display device, and is used to provide a driving circuit to the display, usually provided with several gate scanning lines And several data lines, the gate scanning lines and the data lines define a plurality of pixel units, each pixel unit is provided with a thin film transistor and a pixel electrode, the gate of the thin film transistor and the corresponding gate scanning line Connected, when the voltage on the gate scanning line reaches the turn-on voltage, the source and drain of the thin film transistor are turned on, thereby inputting the data voltage on the data line to the pixel electrode, thereby controlling the display of the corresponding pixel area.
  • a lot of alignment marks are prepared in the peripheral area of the TFT large board. Taking organic electroluminescent displays as an example, these marks are mainly used for the alignment of array exposure machines, the alignment of evaporation and packaging equipment.
  • the alignment process is generally through the alignment of charge-coupled components (Charge-coupled Device, CCD) Mark recognition of the camera. When the Mark pattern or film thickness is abnormal, it will affect the CCD camera recognition Mark, resulting in registration failure.
  • CCD Charge-coupled Device
  • the alignment marks on the TFT large board are generally made of metal alignment marks on the gate metal layer (GE) or the source-drain metal layer (SD) by dry etching.
  • the dry etching process can better ensure the accuracy of the graphics, the plasma bombardment in the dry etching process will also affect Mark, resulting in unevenness of the inorganic film layer around the Mark and affecting the recognition of Mark by the CCD camera in the subsequent process.
  • a schematic structural diagram of an existing TFT substrate includes a base substrate 1 and an active layer 2, a gate insulating layer 3, a gate metal layer 4, and layers that are sequentially stacked on the base substrate 1 Inter-insulation layer 5 and source-drain electrode layer 6.
  • the gate metal layer 4 includes a metal alignment mark 45 disposed on the periphery of the display area. Due to the dry etching process of the gate metal layer 4 on the surface of the gate insulating layer 3 and the source and drain electrode layer 6 dry etching process The damage to the surface of the interlayer insulating layer 5 results in unevenness of the surfaces of the gate insulating layer 3 and the interlayer insulating layer 5 around the metal alignment mark 45, thereby affecting the recognition of the metal alignment mark 45 by the CCD camera in the subsequent process.
  • the conventional solution is mainly to adjust the dry etching process parameters and increase the number of CCD cameras.
  • the damage of the inorganic film surface around Mark cannot be completely avoided, and the impact can only be reduced to a certain extent, and the adjustment of the process parameters also needs to consider other aspects brought by it Effects, such as uneven size (CD).
  • CD uneven size
  • this solution involves equipment modification and high cost.
  • the object of the present invention is to provide a method for manufacturing a TFT substrate, which can reduce the surface damage of the inorganic insulating layer in the dry etching process of the metal layer and avoid subsequent alignment abnormalities.
  • the object of the present invention is also to provide a TFT substrate, which can reduce the surface damage of the inorganic insulating layer in the dry etching process of the metal layer and avoid subsequent alignment abnormalities.
  • the present invention first provides a method for manufacturing a TFT substrate, the TFT substrate is divided into a display area and a display peripheral area surrounding the display area, the display peripheral area is divided into a marking area and surrounding the mark Mark the surrounding area;
  • the manufacturing method includes the steps of forming an inorganic insulating layer, forming a protective layer on the inorganic insulating layer, forming a metal layer on the inorganic insulating layer and the protective layer, and performing dry etching on the metal layer to obtain a metal pattern.
  • the protective layer is used to protect the surface of the inorganic insulating layer in the mark area and the mark surrounding area during the dry etching of the metal layer.
  • the protective layer includes a transparent conductive protective layer.
  • a transparent conductive pattern having the same pattern as the metal pattern is formed by the remaining transparent conductive protective layer.
  • the protective layer includes a photoresist protective layer. Before the metal layer is formed, the photoresist protective layer is formed outside the region corresponding to the pre-formed metal pattern. In the step of removing the protective layer not covered by the metal pattern, the The photoresist protective layer is completely removed.
  • the TFT substrate includes multiple layers of the inorganic insulating layer and multiple layers of the metal layer, the multiple layers of inorganic insulating layer includes a gate insulating layer and an interlayer insulating layer, and the multilayer metal layer includes the gate metal Layer and source-drain metal layer;
  • the metal pattern formed by the gate metal layer includes the gate located in the display area and the alignment mark located in the mark area;
  • the protective layer includes a surface that protects the surface of the gate insulating layer A transparent conductive protective layer and a photoresist protective layer that protects the surface of the interlayer insulating layer; the manufacturing method specifically includes the following steps:
  • Step S1 providing a base substrate, forming a buffer layer on the base substrate, and depositing and patterning an active layer on the buffer layer;
  • Step S2 a gate insulating layer, a transparent conductive protective layer and a gate metal layer are sequentially deposited on the buffer layer and the active layer;
  • Step S3 forming a first photoresist layer on the gate metal layer, using the first photoresist layer as a shielding layer, dry etching the gate metal layer to obtain a gate electrode and an alignment mark First metal pattern;
  • Step S4 using the first photoresist layer and the first metal pattern as a shielding layer, wet etching the transparent conductive protection layer to remove the transparent conductive protection layer not covered by the first metal pattern to form a first metal A transparent conductive pattern with the same pattern, removing the first photoresist layer;
  • Step S5. Deposit and form an interlayer insulating layer on the first metal pattern and the gate insulating layer, and form a second photoresist layer on the interlayer insulating layer by using a half-tone mask, the second light
  • the resist layer includes a first photoresist portion and a remaining second photoresist portion corresponding to the mark area and the mark peripheral area, and the thickness of the first photoresist portion is greater than the thickness of the second photoresist portion.
  • the resistance layer is a shielding layer, and contact holes corresponding to the two ends of the active layer are formed on the interlayer insulating layer and the gate insulating layer;
  • Step S6 Ashing the second photoresist layer to reduce the thickness of the second photoresist layer until the second photoresist portion is removed, and forming photoresist protection by the remaining first photoresist portion Floor;
  • Step S7 forming a source-drain metal layer on the interlayer insulating layer and the photoresist protection layer, forming a third photoresist layer on the source-drain metal layer, and using the third photoresist layer as a shielding layer , Dry etching the source-drain metal layer to obtain a second metal pattern including source and drain, the source and drain are connected to the active layer through the contact hole, and the third photoresist is removed Layer and photoresist protection layer.
  • the TFT substrate includes multiple layers of the inorganic insulating layer and multiple layers of the metal layer, the multiple layers of inorganic insulating layer includes a gate insulating layer and an interlayer insulating layer, and the multilayer metal layer includes the gate metal A layer and a source-drain metal layer; the metal pattern formed by the source-drain metal layer includes the source-drain in the display area and the alignment mark in the mark area; the protective layer includes the surface of the gate insulating layer Protected transparent conductive protective layer and photoresist protective layer that protects the surface of the interlayer insulating layer; the manufacturing method specifically includes the following steps:
  • Step S1' providing a base substrate, forming a buffer layer on the base substrate, depositing and patterning an active layer on the buffer layer;
  • Step S2' a gate insulating layer, a transparent conductive protective layer and a gate metal layer are sequentially deposited on the buffer layer and the active layer;
  • Step S3' forming a first photoresist layer on the gate metal layer, using the first photoresist layer as a shielding layer, dry etching the gate metal layer to obtain a first metal including a gate pattern;
  • Step S4' using the first photoresist layer and the first metal pattern as a shielding layer, wet etching the transparent conductive protective layer to remove the transparent conductive protective layer not covered by the first metal pattern, forming the first A transparent conductive pattern with the same pattern as the metal pattern, removing the first photoresist layer;
  • Step S5' depositing and forming an interlayer insulating layer on the first metal pattern and the gate insulating layer, and forming a second photoresist layer on the interlayer insulating layer using a half-tone mask, the second The photoresist layer includes a first photoresist portion corresponding to the peripheral area of the mark and the remaining second photoresist portion, the thickness of the first photoresist portion is greater than the thickness of the second photoresist portion, and the second photoresist layer As a shielding layer, contact holes corresponding to the two ends of the active layer are formed on the interlayer insulating layer and the gate insulating layer;
  • Step S6' performing an ashing process on the second photoresist layer to reduce the thickness of the second photoresist layer until the second photoresist portion is removed, and forming a photoresist from the remaining first photoresist portion
  • the protective layer
  • Step S7' forming a source-drain metal layer on the interlayer insulating layer and the photoresist protection layer, forming a third photoresist layer on the source-drain metal layer, and using the third photoresist layer as a shield Layer, dry etching the source-drain metal layer to obtain a second metal pattern including source-drain and alignment marks, the source-drain is connected to the active layer through the contact hole, and the The third photoresist layer and the photoresist protective layer are described.
  • the TFT substrate includes multiple layers of the inorganic insulating layer and multiple layers of the metal layer, the multiple layers of inorganic insulating layer includes a gate insulating layer and an interlayer insulating layer, and the multilayer metal layer includes the gate metal Layer and source-drain metal layer;
  • the metal pattern formed by the gate metal layer includes the gate located in the display area and the alignment mark located in the mark area;
  • the protective layer includes a surface that protects the surface of the gate insulating layer A first photoresist protective layer and a second photoresist protective layer that protects the surface of the interlayer insulating layer; the manufacturing method specifically includes the following steps:
  • Step S10 providing a base substrate, forming a buffer layer on the base substrate, and depositing and patterning an active layer on the buffer layer;
  • Step S20 Deposit and form a gate insulating layer on the buffer layer and the active layer, and form a first photoresist protective layer corresponding to the peripheral area of the mark on the gate insulating layer. Forming a gate metal layer on the insulating layer and the first photoresist protective layer;
  • Step S30 forming a first photoresist layer on the gate metal layer, using the first photoresist layer as a shielding layer, dry-etching the gate metal layer to obtain a gate electrode and an alignment mark First metal pattern;
  • Step S40 Remove the first photoresist layer and the first photoresist protective layer
  • Step S50 depositing and forming an interlayer insulating layer on the first metal pattern and the gate insulating layer, and forming a second photoresist layer on the interlayer insulating layer using a half-tone mask, the second light
  • the resist layer includes a first photoresist portion and a remaining second photoresist portion corresponding to the mark area and the mark peripheral area, and the thickness of the first photoresist portion is greater than the thickness of the second photoresist portion.
  • the resistance layer is a shielding layer, and contact holes corresponding to the two ends of the active layer are formed on the interlayer insulating layer and the gate insulating layer;
  • Step S60 Perform ashing treatment on the second photoresist layer to reduce the thickness of the second photoresist layer until the second photoresist portion is removed, and form a second light from the remaining first photoresist portion Resist protective layer;
  • Step S70 forming a source-drain metal layer on the interlayer insulating layer and the second photoresist protection layer, forming a third photoresist layer on the source-drain metal layer, using the third photoresist layer as A shielding layer, dry etching the source-drain metal layer to obtain a second metal pattern including source and drain, the source and drain are connected to the active layer through the contact hole, and the third is removed A photoresist layer and a second photoresist protective layer.
  • the TFT substrate includes multiple layers of the inorganic insulating layer and multiple layers of the metal layer, the multiple layers of inorganic insulating layer includes a gate insulating layer and an interlayer insulating layer, and the multilayer metal layer includes the gate metal A layer and a source-drain metal layer; the metal pattern formed by the source-drain metal layer includes the source-drain in the display area and the alignment mark in the mark area; the protective layer includes the surface of the gate insulating layer The protected first photoresist protection layer and the second photoresist protection layer protecting the surface of the interlayer insulating layer; the manufacturing method specifically includes the following steps:
  • Step S10' providing a base substrate, forming a buffer layer on the base substrate, and depositing and patterning an active layer on the buffer layer;
  • Step S20' depositing and forming a gate insulating layer on the buffer layer and the active layer, forming a first photoresist protective layer corresponding to the peripheral area of the mark on the gate insulating layer, Forming a gate metal layer on the polar insulating layer and the first photoresist protective layer;
  • Step S30' forming a first photoresist layer on the gate metal layer, using the first photoresist layer as a shielding layer, dry-etching the gate metal layer to obtain a gate and an alignment mark The first metal pattern;
  • Step S40' removing the first photoresist layer and the first photoresist protective layer
  • Step S50' depositing and forming an interlayer insulating layer on the first metal pattern and the gate insulating layer, and forming a second photoresist layer on the interlayer insulating layer by using a half-tone mask, the second The photoresist layer includes a first photoresist portion corresponding to the peripheral area of the mark and the remaining second photoresist portion, the thickness of the first photoresist portion is greater than the thickness of the second photoresist portion, and the second photoresist layer As a shielding layer, contact holes corresponding to the two ends of the active layer are formed on the interlayer insulating layer and the gate insulating layer;
  • Step S60' performing an ashing process on the second photoresist layer to reduce the thickness of the second photoresist layer until the second photoresist portion is removed, and forming the second from the remaining first photoresist portion Photoresist protective layer;
  • Step S70' forming a source-drain metal layer on the interlayer insulating layer and the second photoresist protection layer, forming a third photoresist layer on the source-drain metal layer, and using the third photoresist layer For the shielding layer, dry-etching the source-drain metal layer to obtain a second metal pattern including source-drain and alignment marks, the source-drain is connected to the active layer through the contact hole, The third photoresist layer and the second photoresist protective layer are removed.
  • the invention also provides a TFT substrate, which is divided into a display area and a display peripheral area surrounding the display area, the display peripheral area is divided into a marking area and a marking peripheral area surrounding the marking area; including an inorganic insulating layer, a metal A layer and a transparent conductive protective layer correspondingly provided between the inorganic insulating layer and the metal layer;
  • the transparent conductive protective layer is correspondingly located under the corresponding metal layer and has the same transparent conductive pattern as the metal pattern of the metal layer, the transparent conductive protective layer is used for During the dry etching of the metal layer to form the metal pattern, the surface of the inorganic insulating layer in the mark area and the mark surrounding area is protected.
  • the TFT substrate includes multiple layers of the inorganic insulating layer and multiple layers of the metal layer.
  • the multiple layers of inorganic insulating layer includes a gate insulating layer and an interlayer insulating layer.
  • a gate metal layer on the gate insulating layer and a source-drain metal layer provided on the interlayer insulating layer, the transparent conductive protective layer is correspondingly provided between the gate insulating layer and the gate metal layer ;
  • the TFT substrate specifically includes a base substrate, a buffer layer provided on the base substrate, an active layer provided on the buffer layer, and a gate insulating layer provided on the buffer layer and the active layer , A transparent conductive protective layer provided on the gate insulating layer, a gate metal layer provided on the transparent conductive protective layer, an interlayer insulating layer provided on the gate metal layer and the gate insulating layer And a source-drain metal layer provided on the interlayer insulating layer;
  • the gate metal layer has a first metal pattern including a gate
  • the transparent conductive protection layer is correspondingly located under the gate metal layer and has the same transparent conductive pattern as the first metal pattern;
  • the source-drain metal layer has a second metal pattern including source and drain.
  • One of the first metal pattern and the second metal pattern further includes an alignment mark corresponding to the mark area.
  • the manufacturing method of the TFT substrate provided by the present invention by providing a protective layer between the inorganic insulating layer and the metal layer, the inorganic insulating layer of the marking area and the surrounding area of the marking can be formed during the dry etching of the metal layer
  • the surface is effectively protected to reduce the surface damage of the inorganic insulating layer during the dry etching process, thereby effectively improving the recognition rate of the alignment mark by the CCD camera in the subsequent alignment process, improving the alignment detection accuracy, and avoiding the subsequent alignment anomalies.
  • a transparent conductive protective layer is correspondingly provided between the metal layer and the inorganic insulating layer, and the transparent conductive protective layer is correspondingly located below the corresponding metal layer and has the same transparent conductivity as the metal pattern of the metal layer Pattern, the transparent conductive protective layer can be used to protect the surface of the inorganic insulating layer in the marking area and the surrounding area of the marking in the process of dry etching the metal layer to form the metal pattern, which can reduce the inorganic insulating layer in the metal Surface damage during the dry etching process of the layer to avoid subsequent alignment anomalies.
  • FIG. 1 is a schematic structural view of a conventional TFT substrate and a partially enlarged schematic view of an inorganic film layer around an alignment mark;
  • FIG. 3-4 is a schematic diagram of step S3 of the first embodiment of the method for manufacturing a TFT substrate of the present invention.
  • step S5 is a schematic diagram of step S5 of the first embodiment of the method for manufacturing a TFT substrate of the present invention.
  • step S6 is a schematic diagram of step S6 of the first embodiment of the method for manufacturing a TFT substrate of the present invention.
  • FIG. 8-10 are schematic diagrams of step S7 of the first embodiment of the manufacturing method of the TFT substrate of the present invention and FIG. 10 is a schematic structural diagram of the fifth embodiment of the TFT substrate of the present invention.
  • step S3' of the second embodiment of the method for manufacturing a TFT substrate of the present invention is a schematic diagram of step S3' of the second embodiment of the method for manufacturing a TFT substrate of the present invention.
  • step S4' of the second embodiment of the method for manufacturing a TFT substrate of the present invention is a schematic diagram of step S4' of the second embodiment of the method for manufacturing a TFT substrate of the present invention.
  • step S5' of the second embodiment of the method for manufacturing a TFT substrate of the present invention is a schematic diagram of step S5' of the second embodiment of the method for manufacturing a TFT substrate of the present invention.
  • step S6' of the second embodiment of the method for manufacturing a TFT substrate of the present invention is a schematic diagram of step S6' of the second embodiment of the method for manufacturing a TFT substrate of the present invention.
  • step S7' of the second embodiment of the method for manufacturing a TFT substrate of the present invention are schematic views of step S7' of the second embodiment of the method for manufacturing a TFT substrate of the present invention.
  • step S20 of the third embodiment of the method for manufacturing a TFT substrate of the present invention is a schematic diagram of step S20 of the third embodiment of the method for manufacturing a TFT substrate of the present invention.
  • step S30 of the third embodiment of the method for manufacturing a TFT substrate of the present invention is a schematic diagram of step S30 of the third embodiment of the method for manufacturing a TFT substrate of the present invention.
  • step S50 of the third embodiment of the method for manufacturing a TFT substrate of the present invention is a schematic diagram of step S50 of the third embodiment of the method for manufacturing a TFT substrate of the present invention.
  • step S60 of the third embodiment of the method for manufacturing a TFT substrate of the present invention is a schematic diagram of step S60 of the third embodiment of the method for manufacturing a TFT substrate of the present invention.
  • step S70 of the third embodiment of the method for manufacturing a TFT substrate of the present invention are schematic diagrams of step S70 of the third embodiment of the method for manufacturing a TFT substrate of the present invention.
  • step S20' of the fourth embodiment of the method for manufacturing a TFT substrate of the present invention is a schematic diagram of step S20' of the fourth embodiment of the method for manufacturing a TFT substrate of the present invention.
  • 26 is a schematic diagram of step S30' of the fourth embodiment of the method for manufacturing a TFT substrate of the present invention.
  • step S50' of the fourth embodiment of the method for manufacturing a TFT substrate of the present invention is a schematic diagram of step S50' of the fourth embodiment of the method for manufacturing a TFT substrate of the present invention.
  • step S60' of the fourth embodiment of the method for manufacturing a TFT substrate of the present invention is a schematic diagram of step S60' of the fourth embodiment of the method for manufacturing a TFT substrate of the present invention.
  • 29-31 are schematic views of step S70' of the fourth embodiment of the method for manufacturing a TFT substrate of the present invention.
  • the invention provides a TFT Substrate manufacturing method, the TFT
  • the substrate divides a display area and a display peripheral area surrounding the display area, the display peripheral area divides a mark area and a mark peripheral area surrounding the mark area, wherein the mark area is used to form an alignment mark;
  • a protective layer is provided between the layer and the metal layer, which can effectively protect the surface of the inorganic insulating layer in the marking area and the surrounding area of the marking during the dry etching process of the metal layer, and reduce the surface damage of the inorganic insulating layer in the dry etching process.
  • the alignment mark is provided on the gate metal layer
  • the protective layer includes a transparent conductive protective layer that protects the surface of the gate insulating layer and a surface that protects the surface of the interlayer insulating layer
  • the photoresist protection layer this embodiment specifically includes the following steps:
  • step S1 As shown 2 As shown, a base substrate is provided 10 , Forming a buffer layer on the base substrate 20 , In the buffer layer 20 Deposited and patterned to form an active layer 30 .
  • the active layer 30 Can be low temperature polysilicon (LTPS ) Active layer.
  • step S2 In the buffer layer 20 Active layer 30 Sequentially deposited on to form a gate insulating layer 40 ⁇ Transparent conductive protective layer 58 Gate metal layer 50 .
  • the transparent conductive protective layer 58 The material is indium tin oxide ( ITO ).
  • step S3 As shown 3-4 As shown, in the gate metal layer 50 Forming a first photoresist layer 91 , With the first photoresist layer 91 For the shielding layer, the gate metal layer 50 Perform dry etching to obtain the gate 51 Alignment marks 55 First metal pattern.
  • the steps S3 Through the gate metal layer 50 Add a transparent conductive protective layer under 58 , Can be in the gate metal layer 50 Effectively protect the gate insulating layer during the dry etching process 40 The surface is not damaged.
  • step S4 As shown 5 As shown, with the first photoresist layer 91 And the first metal pattern is a shielding layer, the transparent conductive protective layer 58 Perform wet etching to remove the transparent conductive protective layer not covered by the first metal pattern 58 , A transparent conductive pattern with the same pattern as the first metal pattern is formed, and the first photoresist layer is removed.
  • the gate insulating layer is removed using the wet etching process 40
  • the exposed transparent conductive protective layer not covered by the first metal pattern 58 Because the etching method of wet etching is chemical etching, the choice of etching is better, so after removing the transparent conductive protective layer 58 Gate insulating layer 40 Cause damage.
  • step S5 As shown 6 As shown, the first metal pattern and the gate insulating layer 40 Deposited to form an interlayer insulating layer 60 And use a halftone mask ( HTM ) In the interlayer insulating layer 60 Forming a second photoresist layer 92 , The second photoresist layer 92 It includes a first photoresist portion and a remaining second photoresist portion corresponding to the mark area and the mark peripheral area, the thickness of the first photoresist portion is greater than the thickness of the second photoresist portion, and the second photoresist layer 92 For the shielding layer, the interlayer insulating layer 60 Gate insulating layer 40 Formed on the active layer 30 Contact holes above both ends.
  • HTM halftone mask
  • step S6 As shown 7 As shown, the second photoresist layer 92 Performing an ashing process to thin the second photoresist layer 92 The thickness of the second photoresist part is removed, and a photoresist protective layer is formed by the remaining first photoresist part 98 .
  • step S7 As shown 8-10 As shown, in the interlayer insulating layer 60 And photoresist protective layer 98 Forming a source-drain metal layer 70 , In the source-drain metal layer 70 Forming a third photoresist layer 93 , With the third photoresist layer 93 As a shielding layer, the source-drain metal layer 70 Perform dry etching to obtain source and drain 71 Second metal pattern of the source and drain 71 Through the contact hole and the active layer 30 Connected to remove the third photoresist layer 93 And photoresist protective layer 98 .
  • the invention TFT
  • the first embodiment of the manufacturing method of the substrate, compared with the prior art, in the gate metal layer 50 Add a transparent conductive protective layer under 58 , Can be in the gate metal layer 50 Effectively protect the gate insulating layer during the dry etching process 40
  • the surface is not damaged, in the gate metal layer 50
  • the gate insulating layer is removed using the wet etching process 40 Exposed transparent conductive protective layer 58 , Because the etching choice of wet etching is better, so remove the transparent conductive protective layer 58
  • Gate insulating layer 40 Cause damage and adopt HTM Technology uses a half-tone mask on the interlayer insulating layer 60 Formed on the contact hole ( Contact hole ) Of the second photoresist layer 92 So that the second photoresist layer 92
  • the thickness of the first photoresist portion corresponding to the mark area and the mark peripheral area is greater than the thickness of the remaining second photoresist portion, and only the second photoresist layer is removed after the contact hole is
  • the alignment mark is provided on the source-drain metal layer. This embodiment specifically includes the following steps:
  • step S1 ’ Provide a substrate 10 ', on the base substrate 10 A buffer layer is formed on 20 ', in the buffer layer 20 ’S deposited and patterned to form an active layer 30 ’.
  • step S2 In the buffer layer 20 ’And active layer 30
  • the gate insulating layer is deposited in sequence on the 40 ’ ⁇ Transparent conductive protective layer 58 ’And gate metal layer 50 ’.
  • the transparent conductive protective layer 58 ''S material is indium tin oxide.
  • step S3 as shown 11
  • the gate metal layer 50 On the first photoresist layer 91 ', with the first photoresist layer 91 'Is a shielding layer, which 50 ’Dry etching to get the included gate 51 ’S first metal pattern.
  • step S4 as shown 12
  • the transparent conductive protective layer 58 Wet etching to remove the transparent conductive protective layer not covered by the first metal pattern 58 ', forming a transparent conductive pattern with the same pattern as the first metal pattern, removing the first photoresist layer 91 ’.
  • step S5 as shown 13
  • the second photoresist layer 92 ' including the first photoresist portion corresponding to the peripheral area of the mark and the remaining second photoresist portion, the thickness of the first photoresist portion is greater than the thickness of the second photoresist portion, wherein the second photoresist portion includes corresponding to A portion of the mark area to form an alignment mark in the mark area subsequently, with the second photoresist layer 92 ’Is a shielding layer, an insulating layer between the layers 60 'And the gate insulating layer are formed corresponding to the active layer 30 ’Contact holes above both ends.
  • step S6 as shown 14
  • the second photoresist layer 92 Ashing to thin the second photoresist layer 92
  • the thickness of the'to the second photoresist portion is removed, and the remaining first photoresist portion forms a photoresist protective layer 98 ’.
  • step S7 as shown 15-17
  • the interlayer insulating layer 60 And photoresist protective layer 95 Forming a source-drain metal layer on 70 ', in the source-drain metal layer 70
  • the steps S7 Medium due to the photoresist protective layer corresponding to the surrounding area of the mark 98 'Protection, in the source-drain metal layer 70 ’S dry-etching process to mark the interlayer insulating layer in the surrounding area 60 ’S surface is protected from damage.
  • the gate metal layer 50 "Add a transparent conductive protective layer underneath 58 ', can be in the gate metal layer 50 ’Effectively protects the gate insulating layer during the dry etching process 40 ’S surface is not damaged, and the metal layer of the gate 50
  • the gate insulating layer is removed using the wet etching process 40 ’Exposed transparent conductive protective layer 58 ', due to the better etching choice for wet etching, the transparent conductive protective layer is removed 58 ’Will not affect the gate insulating layer 40 ’Cause damage and use HTM Technology uses a half-tone mask on the interlayer insulating layer 60 Forming a second photoresist layer for forming contact holes 92 ', so that the second photoresist layer 92 'The thickness of the first photoresist corresponding to the peripheral area of the mark is greater than the thickness of the
  • the protective layer includes a first photoresist protective layer that protects the surface of the gate insulating layer and a surface that protects the interlayer insulating layer
  • the second photoresist protective layer specifically includes the following steps:
  • step S10 Provide substrate 100 , In the base substrate 100 Buffer layer 200 , In the buffer layer 200 Deposited and patterned to form an active layer 300 .
  • step S20 As shown 18 As shown in the buffer layer 200 Active layer 300 Deposited on top to form a gate insulating layer 400 , In the gate insulating layer 400 Forming a first photoresist protection layer corresponding to the peripheral area of the mark 580 , In the gate insulating layer 400 And the first photoresist protective layer 580 Gate metal layer 500 .
  • the steps S20 In the first photoresist protection layer 580 Exposing the gate insulating layer corresponding to the mark area 400 To form the gate metal layer later 500 Alignment mark.
  • step S30 As shown 19 As shown, in the gate metal layer 500 Forming a first photoresist layer 910 , With the first photoresist layer 910 For the shielding layer, the gate metal layer 500 Perform dry etching to obtain the gate 510 Alignment marks 550 First metal pattern.
  • step S40 Removing the first photoresist layer 910 And the first photoresist protective layer 580 .
  • step S50 As shown 20 As shown, the first metal pattern and the gate insulating layer 400 Deposited to form an interlayer insulating layer 600 And use a half-tone mask on the interlayer insulating layer 600 Forming a second photoresist layer 920 ,
  • the second photoresist layer 920 It includes a first photoresist portion and a remaining second photoresist portion corresponding to the mark area and the mark peripheral area, the thickness of the first photoresist portion is greater than the thickness of the second photoresist portion, and the second photoresist layer For the shielding layer, the interlayer insulating layer 600 Gate insulating layer 400 Formed on the active layer 300 Contact holes above both ends.
  • step S60 As shown twenty one As shown, the second photoresist layer 920 Performing an ashing process to thin the second photoresist layer 920 The thickness of the second photoresist part is removed, and the second photoresist protective layer is formed by the remaining first photoresist part 980 .
  • step S70 As shown 22-24 As shown, in the interlayer insulating layer 600 And the second photoresist protective layer 980 Forming a source-drain metal layer 700 , In the source-drain metal layer 700 Forming a third photoresist layer 930 , With the third photoresist layer 930 As a shielding layer, the source-drain metal layer 700 Perform dry etching to obtain source and drain 710 Second metal pattern of the source and drain 710 Through the contact hole and the active layer 300 Connected to remove the third photoresist layer 930 And the second photoresist protective layer 980 .
  • the gate metal layer 500 Add a layer of first photoresist protection layer corresponding to the surrounding area of the mark 580 ,
  • the first photoresist protection layer 580 Exposing the gate insulating layer corresponding to the mark area 400 , Can be in the gate metal layer 500 Alignment marks in the marking area during the dry etching process 550 And protect the protective layer through the first photoresist 580
  • Gate insulating layer 400 The surface is protected by HTM Technology uses a half-tone mask on the interlayer insulating layer 600 Forming a second photoresist layer for forming a contact hole 920 So that the second photoresist layer 920
  • the thickness of the first photoresist portion corresponding to the mark area and the mark peripheral area is greater than the thickness of the remaining second photoresist portion, and only the second photoresist layer is removed after the contact hole is formed 920 Of the second photoresist, the remaining first photoresist serves as the second
  • the alignment mark is provided on the source-drain metal layer. This embodiment specifically includes the following steps:
  • step S10 ’ Provide a substrate 100 ', on the base substrate 100 A buffer layer is formed on 200 ', in the buffer layer 200 ’S deposited and patterned to form an active layer 300 ’.
  • step S20 as shown 25
  • step S30 as shown 26
  • the gate metal layer 500 On the first photoresist layer 910 ', with the first photoresist layer 910 'Is a shielding layer, which 500 ’Dry etching to get the included gate 510 ’S first metal pattern.
  • the steps S30 ', the first photoresist protection layer 580 ’ Can be in the gate metal layer 500 ’S gate insulating layer for the mark area and the alignment peripheral area in the dry etching process 400 ’S surface is protected.
  • step S40 Removing the first photoresist layer 910 ’And the first photoresist protective layer 580 ’.
  • step S50 As shown 27 As shown, the first metal pattern and the gate insulating layer 400 ’Deposited to form an interlayer insulating layer 600 'And use a half-tone mask on the interlayer insulating layer 600 On the second photoresist layer 920 ', the second photoresist layer 920 'Including the first photoresist portion corresponding to the peripheral area of the mark and the remaining second photoresist portion, the thickness of the first photoresist portion is greater than the thickness of the second photoresist portion, and the second photoresist layer is used as a shield Layer, insulating layer in the interlayer 600 ’And gate insulation 400 On the active layer corresponding to 300 ’Contact holes above both ends.
  • step S60 As shown 28 As shown, the second photoresist layer 920 ’Ashing to thin the second photoresist layer 920 The thickness of the second photoresist is removed to form the second photoresist protective layer from the remaining first photoresist 980 ’. At this time, the second photoresist protective layer 980 'Exposure of the gate insulating layer corresponding to the mark area 400 To form the alignment mark of the source-drain metal layer later.
  • step S70 As shown 29-31
  • the second photoresist protective layer 980 Forming a source-drain metal layer on 700 ', in the source-drain metal layer 700
  • the third photoresist layer 930 ' With the third photoresist layer 930 'Is a shielding layer, which 700 'Dry etching, including the source and drain 710 ’And alignment marks 750
  • the second metal pattern of the source and drain 710 Through the contact hole and the active layer 300 ’Connected to remove the third photoresist layer 930 ’And the second photoresist protective layer 980 ’.
  • the fourth embodiment of the manufacturing method of the substrate is 500 "Add a layer of first photoresist protection layer corresponding to the mark area and the mark surrounding area underneath 580 ', can be in the gate metal layer 500 ’S gate insulating layer for the mark area and the alignment peripheral area in the dry etching process 400 ’S surface is protected and adopted HTM Technology uses a half-tone mask on the interlayer insulating layer 600 Forming a second photoresist layer for forming contact holes 920 ', so that the second photoresist layer 920 'The thickness of the first photoresist corresponding to the peripheral area of the mark is greater than the thickness of the remaining second photoresist, and only the second photoresist layer is removed after the contact hole is formed 920 ''S second photoresist, the remaining first photoresist serves as the second photoresist protective layer 980 'So that the source-drain metal layer 700 ’S alignment marks corresponding to the marked areas during the dry etch
  • the TFT Made by the manufacturing method of the substrate TFT The substrate, by subsequently forming a flat layer on it, OLED Layers and thin-film encapsulation layers can be used for manufacturing OLED panel.
  • the present invention also provides a TFT Substrate, as shown 10
  • TFT Fifth embodiment of substrate including base substrate 10 1.
  • a buffer layer is formed on the base substrate 20 ⁇ Installed in the buffer layer 20 Active layer 30 ⁇ Installed in the buffer layer 20 Active layer 30
  • Gate insulating layer 40 Provided on the gate insulating layer 40
  • Gate metal layer 50 Provided on the gate insulating layer 40 Interlayer insulation 60 And the interlayer insulating layer 60 Source-drain metal layer 70 .
  • the active layer 30 It may be a low-temperature polysilicon active layer.
  • the transparent conductive protective layer 58 The material is indium tin oxide.
  • the interlayer insulating layer 60 Gate insulating layer 40 On the active layer 30 Contact holes above both ends.
  • the gate metal layer 50 Has a gate 51 Alignment marks 55 First metal pattern.
  • the transparent conductive protective layer 58 Corresponding to the first metal pattern, the transparent conductive pattern has the same pattern as the first metal pattern.
  • the gate metal layer 50 Add a transparent conductive protective layer under 58 , Can be in the gate metal layer 50 In the dry etching process to effectively protect the gate insulating layer of the mark area and the mark surrounding area 40 The surface is not damaged, to avoid subsequent alignment abnormalities.
  • the present invention provides TFT
  • the manufacturing method of the substrate has an upper light source and a lower light source, and can provide two types of epi-illumination and transmissive illumination, which can effectively improve the alignment CCD
  • the recognition rate of the alignment mark by the camera has a high accuracy of alignment detection.
  • a combination of both epi-illumination and transmissive illumination can be used to effectively improve the alignment CCD
  • the recognition rate of the registration mark by the camera thereby improving the detection accuracy of the registration.
  • the invention TFT A transparent conductive protective layer is correspondingly provided between the metal layer and the inorganic insulating layer on the substrate, and the transparent conductive protective layer is correspondingly located under the corresponding metal layer and has the same transparent conductive pattern as the metal pattern of the metal layer.
  • the transparent conductive protective layer can be used to protect the surface of the inorganic insulating layer in the marking area and the surrounding area of the mark during the dry etching of the metal layer to form the metal pattern, which can reduce the dry etching of the inorganic insulating layer in the metal layer Surface damage during the process to avoid subsequent alignment anomalies.

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Abstract

本发明提供一种TFT基板的制作方法及TFT基板。本发明的TFT基板的制作方法，通过在无机绝缘层和金属层之间设置保护层，可在金属层的干蚀刻过程中对标记区及标记周边区的无机绝缘层的表面进行有效保护，减小无机绝缘层在干蚀刻制程中的表面损伤，从而有效提高后续对位过程中CCD摄像机对对位标记的识别率，提高对位检测精度，避免后续对位异常，且无需调整金属层的干蚀刻参数，间接降低了干蚀刻制程的制程约束条件，避免了对位CCD摄像机的设备改造及调试，节约了生产成本。

Description

TFT基板的制作方法及TFT基板 技术领域
本发明涉及显示技术领域，尤其涉及一种TFT基板的制作方法及TFT基板。
 背景技术
在显示技术领域，液晶显示器（Liquid Crystal Display，LCD）和有源矩阵驱动式有机电致发光（Active Matrix Organic Light-Emitting Diode，AMOLED）显示器等平板显示装置因具有机身薄、高画质、省电、无辐射等众多优点，得到了广泛的应用，如：移动电话、个人数字助理（PDA）、数字相机、计算机屏幕或笔记本屏幕等。
显示面板是液晶显示器与有机发光二极管显示器的重要组成部分。以液晶显示器的显示面板为例，通常液晶显示面板由彩膜基板（CF，Color Filter）、薄膜晶体管基板（TFT，Thin Film Transistor）、夹于彩膜基板与薄膜晶体管基板之间的液晶（LC，Liquid Crystal）及密封框胶（Sealant）组成。其中，薄膜晶体管阵列（Array）基板是目前LCD装置和AMOLED装置中的主要组成部件，直接关系到高性能平板显示装置的发展方向，用于向显示器提供驱动电路，通常设置有数条栅极扫描线和数条数据线，该数条栅极扫描线和数条数据线限定出多个像素单元，每个像素单元内设置有薄膜晶体管和像素电极，薄膜晶体管的栅极与相应的栅极扫描线相连，当栅极扫描线上的电压达到开启电压时，薄膜晶体管的源极和漏极导通，从而将数据线上的数据电压输入至像素电极，进而控制相应像素区域的显示。
在显示面板制作过程中，TFT大板外围区域制备有很多对位标记（Mark）。以有机电致发光显示器为例，这些Mark主要用于阵列曝光机的对位，蒸镀及封装设备的对位。对位过程一般通过对位电荷耦合元件（Charge-coupled Device，CCD）摄像机进行Mark识别，当Mark 图形（Pattern）或膜厚异常时便会影响CCD摄像机识别Mark，导致对位失败。
TFT大板上的对位标记一般是通过干蚀刻方法制作在栅极金属层（GE）或源漏极金属层（SD）的金属对位标记。虽然干蚀刻制程能较好的保证图形精准度，但干蚀刻制程中的等离子轰击也会对Mark产生影响，导致Mark周围无机膜层凹凸不平，影响后续制程CCD摄像机对Mark的识别。如图1所示的一种现有TFT基板的结构示意图，包括衬底基板1以及依次层叠设置于衬底基板1上的有源层2、栅极绝缘层3、栅极金属层4、层间绝缘层5及源漏极电极层6。其中，栅极金属层4包括设置在显示区外围的金属对位标记45，由于栅极金属层4的干蚀刻制程对栅极绝缘层3表面的损伤以及源漏极电极层6的干蚀刻制程对层间绝缘层5表面的损伤，导致金属对位标记45周围的栅极绝缘层3和层间绝缘层5表面凹凸不平，从而影响了后续制程CCD摄像机对金属对位标记45的识别。
针对上述Mark对位异常，常规的解决方案主要为调整干蚀刻制程参数及增加CCD摄像机数。然而，通过调整干蚀刻制程参数的方式并不能完全避免Mark周围无机膜层表面的损伤（loss），只能在一定程度上降低影响，而且调整制程参数还需考虑其所带来的其他方面的影响，如尺寸（CD）不均等。另外，通过多个CCD摄像机搭配运作虽然能有效解决Mark对位异常，但此方案涉及设备改造，成本较高。
 技术问题
本发明的目的在于提供一种TFT基板的制作方法，可减小无机绝缘层在金属层的干蚀刻制程中的表面损伤，避免后续对位异常。
本发明的目的还在于提供一种TFT基板，可减小无机绝缘层在金属层的干蚀刻制程中的表面损伤，避免后续对位异常。
 技术解决方案
为实现上述目的，本发明首先提供一种TFT基板的制作方法，所述TFT基板划分出显示区及围绕所述显示区的显示外围区，所述显示外围区划分出标记区及围绕所述标记区的标记周边区；
该制作方法包括：形成无机绝缘层的步骤，在无机绝缘层上形成保护层的步骤，在无机绝缘层及保护层上形成金属层的步骤，对金属层进行干蚀刻而得到金属图案的步骤，去除未被金属图案覆盖的保护层的步骤；
所述保护层用于在对金属层进行干蚀刻过程中对标记区及标记周边区的无机绝缘层的表面进行保护。
所述保护层包括透明导电保护层，在去除未被金属图案覆盖的保护层的步骤中，由剩余的透明导电保护层形成与金属图案相同图案的透明导电图案。
所述保护层包括光阻保护层，在形成金属层之前，所述光阻保护层形成在对应预形成金属图案的区域之外，在去除未被金属图案覆盖的保护层的步骤中，所述光阻保护层被完全去除。
可选地，所述TFT基板包括多层所述无机绝缘层及多层所述金属层，该多层无机绝缘层包括栅极绝缘层及层间绝缘层，该多层金属层包括栅极金属层及源漏极金属层；由所述栅极金属层形成的金属图案包括位于显示区的栅极及位于标记区的对位标记；所述保护层包括对栅极绝缘层的表面进行保护的透明导电保护层及对层间绝缘层的表面进行保护的光阻保护层；该制作方法具体包括如下步骤：
步骤S1、提供衬底基板，在所述衬底基板上形成缓冲层，在所述缓冲层上沉积并图案化形成有源层；
步骤S2、在所述缓冲层及有源层上依次沉积形成栅极绝缘层、透明导电保护层及栅极金属层；
步骤S3、在所述栅极金属层上形成第一光阻层，以所述第一光阻层为遮蔽层，对所述栅极金属层进行干蚀刻，得到包括栅极及对位标记的第一金属图案；
步骤S4、以所述第一光阻层和第一金属图案为遮蔽层，对所述透明导电保护层进行湿蚀刻，去除未被第一金属图案覆盖的透明导电保护层，形成与第一金属图案相同图案的透明导电图案，去除第一光阻层；
步骤S5、在所述第一金属图案及栅极绝缘层上沉积形成层间绝缘层，并利用半色调掩膜板在所述层间绝缘层上形成第二光阻层，所述第二光阻层包括对应于标记区及标记周边区的第一光阻部及剩余的第二光阻部，所述第一光阻部的厚度大于第二光阻部的厚度，以所述第二光阻层为遮蔽层，在所述层间绝缘层及栅极绝缘层上形成对应位于所述有源层两端上方的接触孔；
步骤S6、对所述第二光阻层进行灰化处理以减薄所述第二光阻层的厚度至所述第二光阻部被去除，由剩余的第一光阻部形成光阻保护层；
步骤S7、在所述层间绝缘层及光阻保护层上形成源漏极金属层，在所述源漏极金属层上形成第三光阻层，以所述第三光阻层为遮蔽层，对所述源漏极金属层进行干蚀刻，得到包括源漏极的第二金属图案，所述源漏极通过所述接触孔与所述有源层相连接，去除所述第三光阻层及光阻保护层。
可选地，所述TFT基板包括多层所述无机绝缘层及多层所述金属层，该多层无机绝缘层包括栅极绝缘层及层间绝缘层，该多层金属层包括栅极金属层及源漏极金属层；由所述源漏极金属层形成的金属图案包括位于显示区的源漏极及位于标记区的对位标记；所述保护层包括对栅极绝缘层的表面进行保护的透明导电保护层及对层间绝缘层的表面进行保护的光阻保护层；该制作方法具体包括如下步骤：
步骤S1’、提供衬底基板，在所述衬底基板上形成缓冲层，在所述缓冲层上沉积并图案化形成有源层；
步骤S2’、在所述缓冲层及有源层上依次沉积形成栅极绝缘层、透明导电保护层及栅极金属层；
步骤S3’、在所述栅极金属层上形成第一光阻层，以所述第一光阻层为遮蔽层，对所述栅极金属层进行干蚀刻，得到包括栅极的第一金属图案；
步骤S4’、以所述第一光阻层和第一金属图案为遮蔽层，对所述透明导电保护层进行湿蚀刻，去除未被第一金属图案覆盖的透明导电保护层，形成与第一金属图案相同图案的透明导电图案，去除第一光阻层；
步骤S5’、在所述第一金属图案及栅极绝缘层上沉积形成层间绝缘层，并利用半色调掩膜板在所述层间绝缘层上形成第二光阻层，所述第二光阻层包括对应于标记周边区的第一光阻部及剩余的第二光阻部，所述第一光阻部的厚度大于第二光阻部的厚度，以所述第二光阻层为遮蔽层，在所述层间绝缘层及栅极绝缘层上形成对应位于所述有源层两端上方的接触孔；
步骤S6’、对所述第二光阻层进行灰化处理以减薄所述第二光阻层的厚度至所述第二光阻部被去除，由剩余的第一光阻部形成光阻保护层；
步骤S7’、在所述层间绝缘层及光阻保护层上形成源漏极金属层，在所述源漏极金属层上形成第三光阻层，以所述第三光阻层为遮蔽层，对所述源漏极金属层进行干蚀刻，得到包括源漏极及对位标记的第二金属图案，所述源漏极通过所述接触孔与所述有源层相连接，去除所述第三光阻层及光阻保护层。
可选地，所述TFT基板包括多层所述无机绝缘层及多层所述金属层，该多层无机绝缘层包括栅极绝缘层及层间绝缘层，该多层金属层包括栅极金属层及源漏极金属层；由所述栅极金属层形成的金属图案包括位于显示区的栅极及位于标记区的对位标记；所述保护层包括对栅极绝缘层的表面进行保护的第一光阻保护层及对层间绝缘层的表面进行保护的第二光阻保护层；该制作方法具体包括如下步骤：
步骤S10、提供衬底基板，在所述衬底基板上形成缓冲层，在所述缓冲层上沉积并图案化形成有源层；
步骤S20、在所述缓冲层及有源层上沉积形成栅极绝缘层，在所述栅极绝缘层上形成对应于所述标记周边区的第一光阻保护保护层，在所述栅极绝缘层及第一光阻保护层上形成栅极金属层；
步骤S30、在所述栅极金属层上形成第一光阻层，以所述第一光阻层为遮蔽层，对所述栅极金属层进行干蚀刻，得到包括栅极及对位标记的第一金属图案；
步骤S40、去除第一光阻层及第一光阻保护层；
步骤S50、在所述第一金属图案及栅极绝缘层上沉积形成层间绝缘层，并利用半色调掩膜板在所述层间绝缘层上形成第二光阻层，所述第二光阻层包括对应于标记区及标记周边区的第一光阻部及剩余的第二光阻部，所述第一光阻部的厚度大于第二光阻部的厚度，以所述第二光阻层为遮蔽层，在所述层间绝缘层及栅极绝缘层上形成对应位于所述有源层两端上方的接触孔；
步骤S60、对所述第二光阻层进行灰化处理以减薄所述第二光阻层的厚度至所述第二光阻部被去除，由剩余的第一光阻部形成第二光阻保护层；
步骤S70、在所述层间绝缘层及第二光阻保护层上形成源漏极金属层，在所述源漏极金属层上形成第三光阻层，以所述第三光阻层为遮蔽层，对所述源漏极金属层进行干蚀刻，得到包括源漏极的第二金属图案，所述源漏极通过所述接触孔与所述有源层相连接，去除所述第三光阻层及第二光阻保护层。
可选地，所述TFT基板包括多层所述无机绝缘层及多层所述金属层，该多层无机绝缘层包括栅极绝缘层及层间绝缘层，该多层金属层包括栅极金属层及源漏极金属层；由所述源漏极金属层形成的金属图案包括位于显示区的源漏极及位于标记区的对位标记；所述保护层包括对栅极绝缘层的表面进行保护的第一光阻保护层及对层间绝缘层的表面进行保护的第二光阻保护层；该制作方法具体包括如下步骤：
步骤S10’、提供衬底基板，在所述衬底基板上形成缓冲层，在所述缓冲层上沉积并图案化形成有源层；
步骤S20’、在所述缓冲层及有源层上沉积形成栅极绝缘层，在所述栅极绝缘层上形成对应于所述标记周边区的第一光阻保护保护层，在所述栅极绝缘层及第一光阻保护层上形成栅极金属层；
步骤S30’、在所述栅极金属层上形成第一光阻层，以所述第一光阻层为遮蔽层，对所述栅极金属层进行干蚀刻，得到包括栅极及对位标记的第一金属图案；
步骤S40’、去除第一光阻层及第一光阻保护层；
步骤S50’、在所述第一金属图案及栅极绝缘层上沉积形成层间绝缘层，并利用半色调掩膜板在所述层间绝缘层上形成第二光阻层，所述第二光阻层包括对应于标记周边区的第一光阻部及剩余的第二光阻部，所述第一光阻部的厚度大于第二光阻部的厚度，以所述第二光阻层为遮蔽层，在所述层间绝缘层及栅极绝缘层上形成对应位于所述有源层两端上方的接触孔；
步骤S60’、对所述第二光阻层进行灰化处理以减薄所述第二光阻层的厚度至所述第二光阻部被去除，由剩余的第一光阻部形成第二光阻保护层；
步骤S70’、在所述层间绝缘层及第二光阻保护层上形成源漏极金属层，在所述源漏极金属层上形成第三光阻层，以所述第三光阻层为遮蔽层，对所述源漏极金属层进行干蚀刻，得到包括源漏极及对位标记的第二金属图案，所述源漏极通过所述接触孔与所述有源层相连接，去除所述第三光阻层及第二光阻保护层。
本发明还提供一种TFT基板，划分出显示区及围绕所述显示区的显示外围区，所述显示外围区划分出标记区及围绕所述标记区的标记周边区；包括无机绝缘层、金属层及对应设于所述无机绝缘层及金属层之间的透明导电保护层；
其中，所述金属层具有金属图案，所述透明导电保护层对应位于所对应的金属层的下方并具有与该金属层的金属图案相同的透明导电图案，所述透明导电保护层用于在对金属层进行干蚀刻以形成所述金属图案的过程中对标记区及标记周边区的无机绝缘层的表面进行保护。
可选地，所述TFT基板包括多层所述无机绝缘层及多层所述金属层，该多层无机绝缘层包括栅极绝缘层及层间绝缘层，该多层金属层包括设于所述栅极绝缘层上的栅极金属层及设于所述层间绝缘层上的源漏极金属层，所述透明导电保护层对应设于所述栅极绝缘层和栅极金属层之间；
所述TFT基板具体包括衬底基板、设于所述衬底基板上的缓冲层、设于所述缓冲层上的有源层、设于所述缓冲层及有源层上的栅极绝缘层、设于所述栅极绝缘层上的透明导电保护层、设于所述透明导电保护层上的栅极金属层、设于所述栅极金属层及栅极绝缘层上的层间绝缘层及设于所述层间绝缘层上的源漏极金属层；
所述栅极金属层具有包括栅极的第一金属图案；
所述透明导电保护层对应位于所述栅极金属层下方并具有与所述第一金属图案相同的透明导电图案；
所述源漏极金属层具有包括源漏极的第二金属图案。
所述第一金属图案和第二金属图案中的一个还包括对应位于所述标记区的对位标记。
 有益效果
本发明的有益效果：本发明提供的TFT基板的制作方法，通过在无机绝缘层和金属层之间设置保护层，可在金属层的干蚀刻过程中对标记区及标记周边区的无机绝缘层的表面进行有效保护，减小无机绝缘层在干蚀刻制程中的表面损伤，从而有效提高后续对位过程中CCD摄像机对对位标记的识别率，提高对位检测精度，避免后续对位异常，且无需调整金属层的干蚀刻参数，间接降低了干蚀刻制程的制程约束条件，避免了对位CCD摄像机的设备改造及调试，节约了生产成本。本发明的TFT基板，金属层与无机绝缘层之间对应设有透明导电保护层，所述透明导电保护层对应位于所对应的金属层的下方并具有与该金属层的金属图案相同的透明导电图案，所述透明导电保护层可用于在对金属层进行干蚀刻以形成所述金属图案的过程中对标记区及标记周边区的无机绝缘层的表面进行保护，可减小无机绝缘层在金属层的干蚀刻制程中的表面损伤，避免后续对位异常。
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
 附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其它有益效果显而易见。
附图中，
图1为现有一种TFT基板的结构示意图及对位标记周围的无机膜层的局部放大示意图；
图2为本发明的TFT基板的制作方法的第一实施例的步骤S1的示意图；
图3-4为本发明的TFT基板的制作方法的第一实施例的步骤S3的示意图；
图5为本发明的TFT基板的制作方法的第一实施例的步骤S4的示意图；
图6为本发明的TFT基板的制作方法的第一实施例的步骤S5的示意图；
图7为本发明的TFT基板的制作方法的第一实施例的步骤S6的示意图；
图8-10为本发明的TFT基板的制作方法的第一实施例的步骤S7的示意图且图10为本发明的TFT基板的第五实施例的结构示意图；
图11为本发明的TFT基板的制作方法的第二实施例的步骤S3’的示意图；
图12为本发明的TFT基板的制作方法的第二实施例的步骤S4’的示意图；
图13为本发明的TFT基板的制作方法的第二实施例的步骤S5’的示意图；
图14为本发明的TFT基板的制作方法的第二实施例的步骤S6’的示意图；
图15-17为本发明的TFT基板的制作方法的第二实施例的步骤S7’的示意图；
图18为本发明的TFT基板的制作方法的第三实施例的步骤S20的示意图；
图19为本发明的TFT基板的制作方法的第三实施例的步骤S30的示意图；
图20为本发明的TFT基板的制作方法的第三实施例的步骤S50的示意图；
图21为本发明的TFT基板的制作方法的第三实施例的步骤S60的示意图；
图22-24为本发明的TFT基板的制作方法的第三实施例的步骤S70的示意图；
图25为本发明的TFT基板的制作方法的第四实施例的步骤S20’的示意图；
图26为本发明的TFT基板的制作方法的第四实施例的步骤S30’的示意图；
图27为本发明的TFT基板的制作方法的第四实施例的步骤S50’的示意图；
图28为本发明的TFT基板的制作方法的第四实施例的步骤S60’的示意图；
图29-31为本发明的TFT基板的制作方法的第四实施例的步骤S70’的示意图。
 本发明的实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
本发明提供一种 TFT 基板的制作方法，所述 TFT 基板划分出显示区及围绕所述显示区的显示外围区，所述显示外围区划分出标记区及围绕所述标记区的标记周边区，其中标记区用于形成对位标记；通过在无机绝缘层和金属层之间设置保护层，可在金属层的干蚀刻过程中对标记区及标记周边区的无机绝缘层的表面进行有效保护，减小无机绝缘层在干蚀刻制程中的表面损伤。
本发明的 TFT 基板的制作方法的第一实施例，对位标记设置在栅极金属层，所述保护层包括对栅极绝缘层的表面进行保护的透明导电保护层及对层间绝缘层的表面进行保护的光阻保护层，本实施例具体包括如下步骤：
步骤 S1 、如图 2 所示，提供衬底基板 10 ，在所述衬底基板上形成缓冲层 20 ，在所述缓冲层 20 上沉积并图案化形成有源层 30 。
具体地，所述有源层 30 可以为低温多晶硅（ LTPS ）有源层。
步骤 S2 、在缓冲层 20 及有源层 30 上依次沉积形成栅极绝缘层 40 、透明导电保护层 58 及栅极金属层 50 。
具体地，所述透明导电保护层 58 的材料为氧化铟锡（ ITO ）。
步骤 S3 、如图 3-4 所示，在所述栅极金属层 50 上形成第一光阻层 91 ，以所述第一光阻层 91 为遮蔽层，对所述栅极金属层 50 进行干蚀刻，得到包括栅极 51 及对位标记 55 的第一金属图案。
具体地，相对于现有技术，所述步骤 S3 中，通过在栅极金属层 50 下增加一层透明导电保护层 58 ，可以在栅极金属层 50 的干蚀刻制程中有效保护栅极绝缘层 40 的表面不受损伤。
步骤 S4 、如图 5 所示，以所述第一光阻层 91 和第一金属图案为遮蔽层，对所述透明导电保护层 58 进行湿蚀刻，去除未被第一金属图案覆盖的透明导电保护层 58 ，形成与第一金属图案相同图案的透明导电图案，去除第一光阻层。
具体地，在所述步骤 S4 中，在栅极金属层 50 的干蚀刻制程完成后，利用湿蚀刻制程去除栅极绝缘层 40 上裸露的未被被第一金属图案覆盖的透明导电保护层 58 ，由于湿蚀刻的蚀刻方式为化学性蚀刻，蚀刻选择比较好，因此在去除透明导电保护层 58 时不会对栅极绝缘层 40 造成损伤。
步骤 S5 、如图 6 所示，在所述第一金属图案及栅极绝缘层 40 上沉积形成层间绝缘层 60 ，并利用半色调掩膜板（ HTM ）在所述层间绝缘层 60 上形成第二光阻层 92 ，所述第二光阻层 92 包括对应于标记区及标记周边区的第一光阻部及剩余的第二光阻部，所述第一光阻部的厚度大于第二光阻部的厚度，以所述第二光阻层 92 为遮蔽层，在所述层间绝缘层 60 及栅极绝缘层 40 上形成对应位于所述有源层 30 两端上方的接触孔。
步骤 S6 、如图 7 所示，对所述第二光阻层 92 进行灰化处理以减薄所述第二光阻层 92 的厚度至所述第二光阻部被去除，由剩余的第一光阻部形成光阻保护层 98 。
步骤 S7 、如图 8-10 所示，在所述层间绝缘层 60 及光阻保护层 98 上形成源漏极金属层 70 ，在所述源漏极金属层 70 上形成第三光阻层 93 ，以所述第三光阻层 93 为遮蔽层，对所述源漏极金属层 70 进行干蚀刻，得到包括源漏极 71 的第二金属图案，所述源漏极 71 通过所述接触孔与所述有源层 30 相连接，去除所述第三光阻层 93 及光阻保护层 98 。
具体地，所述步骤 S7 中，由于对应于标记区及标记周边区的光阻保护层 98 的保护，在源漏极金属层 70 的干蚀刻制程中标记区及标记周边区的层间绝缘层 60 的表面得以受到保护而免于受损。
本发明的 TFT 基板的制作方法的第一实施例，相对于现有技术，在栅极金属层 50 下增加一层透明导电保护层 58 ，可以在栅极金属层 50 的干蚀刻制程中有效保护栅极绝缘层 40 的表面不受损伤，在栅极金属层 50 的干蚀刻制程完成后，利用湿蚀刻制程去除栅极绝缘层 40 上裸露的透明导电保护层 58 ，由于湿蚀刻的蚀刻选择比较好，因此在去除透明导电保护层 58 时不会对栅极绝缘层 40 造成损伤，并采用 HTM 技术利用半色调掩膜板在所述层间绝缘层 60 上形成用于形成接触孔（ Contact hole ）的第二光阻层 92 ，使得所述第二光阻层 92 对应于标记区及标记周边区的第一光阻部的厚度大于剩余的第二光阻部的厚度，在接触孔形成后仅仅去除第二光阻层 92 的第二光阻部，剩余的第一光阻部作为光阻保护层 98 ，从而可以在源漏极金属层 70 的干蚀刻制程中对标记区及标记周边区的层间绝缘层 60 的表面进行保护。
本发明的 TFT 基板的制作方法的第二实施例，与上述第一实施例相比，对位标记设置在源漏极金属层，本实施例具体包括如下步骤：
步骤 S1 ’、提供衬底基板 10 ’，在所述衬底基板 10 ’上形成缓冲层 20 ’，在所述缓冲层 20 ’上沉积并图案化形成有源层 30 ’。
步骤 S2 ’、在缓冲层 20 ’及有源层 30 ’上依次沉积形成栅极绝缘层 40 ’、透明导电保护层 58 ’及栅极金属层 50 ’。
具体地，所述透明导电保护层 58 ’的材料为氧化铟锡。
步骤 S3 ’、如图 11 所示，在所述栅极金属层 50 ’上形成第一光阻层 91 ’，以所述第一光阻层 91 ’为遮蔽层，对所述栅极金属层 50 ’进行干蚀刻，得到包括栅极 51 ’的第一金属图案。
步骤 S4 ’、如图 12 所示，以所述第一光阻层 91 ’和第一金属图案为遮蔽层，对所述透明导电保护层 58 ’进行湿蚀刻，去除未被第一金属图案覆盖的透明导电保护层 58 ’，形成与第一金属图案相同图案的透明导电图案，去除第一光阻层 91 ’。
步骤 S5 ’、如图 13 所示，在所述第一金属图案及栅极绝缘层 40 ’上沉积形成层间绝缘层 60 ’，并利用半色调掩膜板在所述层间绝缘层 60 ’上形成第二光阻层 92 ’，所述第二光阻层 92 ’包括对应于标记周边区的第一光阻部及剩余的第二光阻部，所述第一光阻部的厚度大于第二光阻部的厚度，其中，第二光阻部包括对应于标记区的部分以在后续在标记区形成对位标记，以所述第二光阻层 92 ’为遮蔽层，在所述层间绝缘层 60 ’及栅极绝缘层上形成对应位于所述有源层 30 ’两端上方的接触孔。
步骤 S6 ’、如图 14 所示，对所述第二光阻层 92 ’进行灰化处理以减薄所述第二光阻层 92 ’的厚度至所述第二光阻部被去除，由剩余的第一光阻部形成光阻保护层 98 ’。
步骤 S7 ’、如图 15-17 所示，在所述层间绝缘层 60 ’及光阻保护层 95 ’上形成源漏极金属层 70 ’，在所述源漏极金属层 70 ’上形成第三光阻层 93 ’，以所述第三光阻层 93 ’为遮蔽层，对所述源漏极金属层 70 ’进行干蚀刻，得到包括源漏极 71 ’及对位标记 75 ’的第二金属图案，所述源漏极 71 ’通过所述接触孔与所述有源层 30 ’相连接，去除所述第三光阻层 93 ’及光阻保护层 98 ’。
具体地，所述步骤 S7 中，由于对应于标记周边区的光阻保护层 98 ’的保护，在源漏极金属层 70 ’的干蚀刻制程中标记周边区的层间绝缘层 60 ’的表面得以受到保护而免于受损。
本发明的 TFT 基板的制作方法的第二实施例，相对于现有技术，在栅极金属层 50 ’下增加一层透明导电保护层 58 ’，可以在栅极金属层 50 ’的干蚀刻制程中有效保护栅极绝缘层 40 ’的表面不受损伤，在栅极金属层 50 ’的干蚀刻制程完成后，利用湿蚀刻制程去除栅极绝缘层 40 ’上裸露的透明导电保护层 58 ’，由于湿蚀刻的蚀刻选择比较好，因此在去除透明导电保护层 58 ’时不会对栅极绝缘层 40 ’造成损伤，并采用 HTM 技术利用半色调掩膜板在所述层间绝缘层 60 ’上形成用于形成接触孔的第二光阻层 92 ’，使得所述第二光阻层 92 ’对应于标记周边区的第一光阻部的厚度大于剩余的第二光阻部的厚度，在接触孔形成后仅仅去除第二光阻层 92 ’的第二光阻部，剩余的第一光阻部作为光阻保护层 98 ’，从而可以在源漏极金属层 70 ’的干蚀刻制程中形成对应标记区的对位标记 75 ’并通过光阻保护层 98 ’对标记周边区的层间绝缘层 60 ’的表面进行保护。
本发明 TFT 基板的制作方法的第三实施例，与上述第一实施例相比，所述保护层包括对栅极绝缘层的表面进行保护的第一光阻保护层及对层间绝缘层的表面进行保护的第二光阻保护层，本实施例具体包括如下步骤：
步骤 S10 、提供衬底基板 100 ，在所述衬底基板 100 上形成缓冲层 200 ，在所述缓冲层 200 上沉积并图案化形成有源层 300 。
步骤 S20 、如图 18 所示，在所述缓冲层 200 及有源层 300 上沉积形成栅极绝缘层 400 ，在所述栅极绝缘层 400 上形成对应于所述标记周边区的第一光阻保护保护层 580 ，在所述栅极绝缘层 400 及第一光阻保护层 580 上形成栅极金属层 500 。
具体地，所述步骤 S20 中，所述第一光阻保护保护层 580 露出对应于标记区的栅极绝缘层 400 ，以在后续形成栅极金属层 500 的对位标记。
步骤 S30 、如图 19 所示，在所述栅极金属层 500 上形成第一光阻层 910 ，以所述第一光阻层 910 为遮蔽层，对所述栅极金属层 500 进行干蚀刻，得到包括栅极 510 及对位标记 550 的第一金属图案。
步骤 S40 、去除第一光阻层 910 及第一光阻保护层 580 。
步骤 S50 、如图 20 所示，在所述第一金属图案及栅极绝缘层 400 上沉积形成层间绝缘层 600 ，并利用半色调掩膜板在所述层间绝缘层 600 上形成第二光阻层 920 ，所述第二光阻层 920 包括对应于标记区及标记周边区的第一光阻部及剩余的第二光阻部，所述第一光阻部的厚度大于第二光阻部的厚度，以所述第二光阻层为遮蔽层，在所述层间绝缘层 600 及栅极绝缘层 400 上形成对应位于所述有源层 300 两端上方的接触孔。
步骤 S60 、如图 21 所示，对所述第二光阻层 920 进行灰化处理以减薄所述第二光阻层 920 的厚度至所述第二光阻部被去除，由剩余的第一光阻部形成第二光阻保护层 980 。
步骤 S70 、如图 22-24 所示，在所述层间绝缘层 600 及第二光阻保护层 980 上形成源漏极金属层 700 ，在所述源漏极金属层 700 上形成第三光阻层 930 ，以所述第三光阻层 930 为遮蔽层，对所述源漏极金属层 700 进行干蚀刻，得到包括源漏极 710 的第二金属图案，所述源漏极 710 通过所述接触孔与所述有源层 300 相连接，去除所述第三光阻层 930 及第二光阻保护层 980 。
本发明的 TFT 基板的制作方法的第三实施例，相对于现有技术，在栅极金属层 500 下增加一层对应于标记周边区的第一光阻保护保护层 580 ，所述第一光阻保护保护层 580 露出对应于标记区的栅极绝缘层 400 ，可以在栅极金属层 500 的干蚀刻制程中在标记区形成对位标记 550 并通过第一光阻保护保护层 580 对对位周边区的栅极绝缘层 400 的表面进行保护，采用 HTM 技术利用半色调掩膜板在所述层间绝缘层 600 上形成用于形成接触孔的第二光阻层 920 ，使得所述第二光阻层 920 对应于标记区及标记周边区的第一光阻部的厚度大于剩余的第二光阻部的厚度，在接触孔形成后仅仅去除第二光阻层 920 的第二光阻部，剩余的第一光阻部作为第二光阻保护层 980 ，从而可以在源漏极金属层 700 的干蚀刻制程中对标记区及标记周边区的层间绝缘层 600 的表面进行保护。
本发明的 TFT 基板的制作方法的第四实施例，与上述第三实施例相比，对位标记设置在源漏极金属层，本实施例具体包括如下步骤：
步骤 S10 ’、提供衬底基板 100 ’，在所述衬底基板 100 ’上形成缓冲层 200 ’，在所述缓冲层 200 ’上沉积并图案化形成有源层 300 ’。
步骤 S20 ’、如图 25 所示，在所述缓冲层 200 ’及有源层 300 ’上沉积形成栅极绝缘层 400 ’，在所述栅极绝缘层 400 ’上形成对应于所述标记区及标记周边区的第一光阻保护保护层 580 ’，在所述栅极绝缘层 400 ’及第一光阻保护层 580 ’上形成栅极金属层 500 ’。
步骤 S30 ’、如图 26 所示，在所述栅极金属层 500 ’上形成第一光阻层 910 ’，以所述第一光阻层 910 ’为遮蔽层，对所述栅极金属层 500 ’进行干蚀刻，得到包括栅极 510 ’的第一金属图案。
具体地，所述步骤 S30 ’中，所述第一光阻保护保护层 580 ’可以在栅极金属层 500 ’的干蚀刻制程中对标记区及对位周边区的栅极绝缘层 400 ’的表面进行保护。
步骤 S40 、去除第一光阻层 910 ’及第一光阻保护层 580 ’。
步骤 S50 、如图 27 所示，在所述第一金属图案及栅极绝缘层 400 ’上沉积形成层间绝缘层 600 ’，并利用半色调掩膜板在所述层间绝缘层 600 ’上形成第二光阻层 920 ’，所述第二光阻层 920 ’包括对应于标记周边区的第一光阻部及剩余的第二光阻部，所述第一光阻部的厚度大于第二光阻部的厚度，以所述第二光阻层为遮蔽层，在所述层间绝缘层 600 ’及栅极绝缘层 400 ’上形成对应位于所述有源层 300 ’两端上方的接触孔。
步骤 S60 、如图 28 所示，对所述第二光阻层 920 ’进行灰化处理以减薄所述第二光阻层 920 ’的厚度至所述第二光阻部被去除，由剩余的第一光阻部形成第二光阻保护层 980 ’。此时，所述第二光阻保护层 980 ’露出对应于标记区的栅极绝缘层 400 ，以在后续形成源漏极金属层的对位标记。
步骤 S70 、如图 29-31 所示，在所述层间绝缘层 600 ’及第二光阻保护层 980 ’上形成源漏极金属层 700 ’，在所述源漏极金属层 700 ’上形成第三光阻层 930 ’，以所述第三光阻层 930 ’为遮蔽层，对所述源漏极金属层 700 ’进行干蚀刻，得到包括源漏极 710 ’及对位标记 750 ’的第二金属图案，所述源漏极 710 ’通过所述接触孔与所述有源层 300 ’相连接，去除所述第三光阻层 930 ’及第二光阻保护层 980 ’。
本发明的 TFT 基板的制作方法的第四实施例，相对于现有技术，在栅极金属层 500 ’下增加一层对应于标记区及标记周边区的第一光阻保护保护层 580 ’，可以在栅极金属层 500 ’的干蚀刻制程中对标记区及对位周边区的栅极绝缘层 400 ’的表面进行保护，并采用 HTM 技术利用半色调掩膜板在所述层间绝缘层 600 ’上形成用于形成接触孔的第二光阻层 920 ’，使得所述第二光阻层 920 ’对应于标记周边区的第一光阻部的厚度大于剩余的第二光阻部的厚度，在接触孔形成后仅仅去除第二光阻层 920 ’的第二光阻部，剩余的第一光阻部作为第二光阻保护层 980 ’，从而可以在源漏极金属层 700 ’的干蚀刻制程中形成对应标记区的对位标记 750 ’并通过第二光阻保护层 980 ’对标记周边区的层间绝缘层 600 ’的表面进行保护。
具体地，示例性地，本发明的 TFT 基板的制作方法所制作的 TFT 基板，通过后续在其上依次形成平坦层、 OLED 层及薄膜封装层等结构，可以用于制作 OLED 面板。
基于上述的 TFT 基板的制作方法，请参阅图 10 ，本发明还提供一种 TFT 基板，如图 10 所述，本发明 TFT 基板的第五实施例，包括衬底基板 10 、设于所述衬底基板上形成缓冲层 20 、设于所述缓冲层 20 上的有源层 30 、设于所述缓冲层 20 及有源层 30 上的栅极绝缘层 40 、设于所述栅极绝缘层 40 上的导电保护层 58 、设于所述导电保护层 58 上的栅极金属层 50 、设于所述栅极绝缘层 40 上的层间绝缘层 60 及设于所述层间绝缘层 60 上的源漏极金属层 70 。
具体地，所述有源层 30 可以为低温多晶硅有源层。
具体地，所述透明导电保护层 58 的材料为氧化铟锡。
具体地，所述层间绝缘层 60 及栅极绝缘层 40 上设有对应位于所述有源层 30 两端上方的接触孔。
具体地，所述栅极金属层 50 具有包括栅极 51 及对位标记 55 的第一金属图案。
具体地，所述透明导电保护层 58 对应位于所述第一金属图案下方，具有与第一金属图案相同图案的透明导电图案。
具体地，所述源漏极金属层 70 具有包括源漏极 71 的第二金属图案，所述源漏极 71 通过所述接触孔与所述有源层 30 相连接。
本发明的 TFT 基板的第五实施例，相对于现有技术，在栅极金属层 50 下增加一层透明导电保护层 58 ，可以在栅极金属层 50 的干蚀刻制程中有效保护标记区及标记周边区的栅极绝缘层 40 的表面不受损伤，避免后续对位异常。
综上所述，本发明提供的 TFT 基板的制作方法，具有上光源及下光源，能够提供落射式照明与透射式照明两种方式，从而可以有效提高对位 CCD 摄像机对对位标记的识别率，具有较高的对位检测精度。本发明的液晶显示面板的对位检查方法，在对位标记与透明定盘边缘重叠时，采用落射式照明与透射式照明两者结合的方式，可以有效提高对位 CCD 摄像机对对位标记的识别率，进而提高对位检测精度。本发明的 TFT 基板，金属层与无机绝缘层之间对应设有透明导电保护层，所述透明导电保护层对应位于所对应的金属层的下方并具有与该金属层的金属图案相同的透明导电图案，所述透明导电保护层可用于在对金属层进行干蚀刻以形成所述金属图案的过程中对标记区及标记周边区的无机绝缘层的表面进行保护，可减小无机绝缘层在金属层的干蚀刻制程中的表面损伤，避免后续对位异常。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (10)

  1. 一种TFT基板的制作方法，所述TFT基板划分出显示区及围绕所述显示区的显示外围区，所述显示外围区划分出标记区及围绕所述标记区的标记周边区；包括如下步骤：
    形成无机绝缘层的步骤，在无机绝缘层上形成保护层的步骤，在无机绝缘层及保护层上形成金属层的步骤，对金属层进行干蚀刻而得到金属图案的步骤，去除未被金属图案覆盖的保护层的步骤；
    所述保护层用于在对金属层进行干蚀刻过程中对标记区及标记周边区的无机绝缘层的表面进行保护。
  2. 如权利要求1所述的TFT基板的制作方法，其中，所述保护层包括透明导电保护层，在去除未被金属图案覆盖的保护层的步骤中，由剩余的透明导电保护层形成与金属图案相同图案的透明导电图案。
  3. 如权利要求1所述的TFT基板的制作方法，其中，所述保护层包括光阻保护层，在形成金属层之前，所述光阻保护层形成在对应预形成金属图案的区域之外，在去除未被金属图案覆盖的保护层的步骤中，所述光阻保护层被完全去除。
  4. 如权利要求1所述的TFT基板的制作方法，其中，所述TFT基板包括多层所述无机绝缘层及多层所述金属层，该多层无机绝缘层包括栅极绝缘层及层间绝缘层，该多层金属层包括栅极金属层及源漏极金属层；由所述栅极金属层形成的金属图案包括位于显示区的栅极及位于标记区的对位标记；所述保护层包括对栅极绝缘层的表面进行保护的透明导电保护层及对层间绝缘层的表面进行保护的光阻保护层；
    该制作方法具体包括如下步骤：
    步骤S1、提供衬底基板，在所述衬底基板上形成缓冲层，在所述缓冲层上沉积并图案化形成有源层；
    步骤S2、在所述缓冲层及有源层上依次沉积形成栅极绝缘层、透明导电保护层及栅极金属层；
    步骤S3、在所述栅极金属层上形成第一光阻层，以所述第一光阻层为遮蔽层，对所述栅极金属层进行干蚀刻，得到包括栅极及对位标记的第一金属图案；
    步骤S4、以所述第一光阻层和第一金属图案为遮蔽层，对所述透明导电保护层进行湿蚀刻，去除未被第一金属图案覆盖的透明导电保护层，形成与第一金属图案相同图案的透明导电图案，去除第一光阻层；
    步骤S5、在所述第一金属图案及栅极绝缘层上沉积形成层间绝缘层，并利用半色调掩膜板在所述层间绝缘层上形成第二光阻层，所述第二光阻层包括对应于标记区及标记周边区的第一光阻部及剩余的第二光阻部，所述第一光阻部的厚度大于第二光阻部的厚度，以所述第二光阻层为遮蔽层，在所述层间绝缘层及栅极绝缘层上形成对应位于所述有源层两端上方的接触孔；
    步骤S6、对所述第二光阻层进行灰化处理以减薄所述第二光阻层的厚度至所述第二光阻部被去除，由剩余的第一光阻部形成光阻保护层；
    步骤S7、在所述层间绝缘层及光阻保护层上形成源漏极金属层，在所述源漏极金属层上形成第三光阻层，以所述第三光阻层为遮蔽层，对所述源漏极金属层进行干蚀刻，得到包括源漏极的第二金属图案，所述源漏极通过所述接触孔与所述有源层相连接，去除所述第三光阻层及光阻保护层。
  5. 如权利要求1所述的TFT基板的制作方法，其中，所述TFT基板包括多层所述无机绝缘层及多层所述金属层，该多层无机绝缘层包括栅极绝缘层及层间绝缘层，该多层金属层包括栅极金属层及源漏极金属层；由所述源漏极金属层形成的金属图案包括位于显示区的源漏极及位于标记区的对位标记；所述保护层包括对栅极绝缘层的表面进行保护的透明导电保护层及对层间绝缘层的表面进行保护的光阻保护层；
    该制作方法具体包括如下步骤：
    步骤S1’、提供衬底基板，在所述衬底基板上形成缓冲层，在所述缓冲层上沉积并图案化形成有源层；
    步骤S2’、在所述缓冲层及有源层上依次沉积形成栅极绝缘层、透明导电保护层及栅极金属层；
    步骤S3’、在所述栅极金属层上形成第一光阻层，以所述第一光阻层为遮蔽层，对所述栅极金属层进行干蚀刻，得到包括栅极的第一金属图案；
    步骤S4’、以所述第一光阻层和第一金属图案为遮蔽层，对所述透明导电保护层进行湿蚀刻，去除未被第一金属图案覆盖的透明导电保护层，形成与第一金属图案相同图案的透明导电图案，去除第一光阻层；
    步骤S5’、在所述第一金属图案及栅极绝缘层上沉积形成层间绝缘层，并利用半色调掩膜板在所述层间绝缘层上形成第二光阻层，所述第二光阻层包括对应于标记周边区的第一光阻部及剩余的第二光阻部，所述第一光阻部的厚度大于第二光阻部的厚度，以所述第二光阻层为遮蔽层，在所述层间绝缘层及栅极绝缘层上形成对应位于所述有源层两端上方的接触孔；
    步骤S6’、对所述第二光阻层进行灰化处理以减薄所述第二光阻层的厚度至所述第二光阻部被去除，由剩余的第一光阻部形成光阻保护层；
    步骤S7’、在所述层间绝缘层及光阻保护层上形成源漏极金属层，在所述源漏极金属层上形成第三光阻层，以所述第三光阻层为遮蔽层，对所述源漏极金属层进行干蚀刻，得到包括源漏极及对位标记的第二金属图案，所述源漏极通过所述接触孔与所述有源层相连接，去除所述第三光阻层及光阻保护层。
  6. 如权利要求1所述的TFT基板的制作方法，其中，所述TFT基板包括多层所述无机绝缘层及多层所述金属层，该多层无机绝缘层包括栅极绝缘层及层间绝缘层，该多层金属层包括栅极金属层及源漏极金属层；由所述栅极金属层形成的金属图案包括位于显示区的栅极及位于标记区的对位标记；所述保护层包括对栅极绝缘层的表面进行保护的第一光阻保护层及对层间绝缘层的表面进行保护的第二光阻保护层；
    该制作方法具体包括如下步骤：
    步骤S10、提供衬底基板，在所述衬底基板上形成缓冲层，在所述缓冲层上沉积并图案化形成有源层；
    步骤S20、在所述缓冲层及有源层上沉积形成栅极绝缘层，在所述栅极绝缘层上形成对应于所述标记周边区的第一光阻保护保护层，在所述栅极绝缘层及第一光阻保护层上形成栅极金属层；
    步骤S30、在所述栅极金属层上形成第一光阻层，以所述第一光阻层为遮蔽层，对所述栅极金属层进行干蚀刻，得到包括栅极及对位标记的第一金属图案；
    步骤S40、去除第一光阻层及第一光阻保护层；
    步骤S50、在所述第一金属图案及栅极绝缘层上沉积形成层间绝缘层，并利用半色调掩膜板在所述层间绝缘层上形成第二光阻层，所述第二光阻层包括对应于标记区及标记周边区的第一光阻部及剩余的第二光阻部，所述第一光阻部的厚度大于第二光阻部的厚度，以所述第二光阻层为遮蔽层，在所述层间绝缘层及栅极绝缘层上形成对应位于所述有源层两端上方的接触孔；
    步骤S60、对所述第二光阻层进行灰化处理以减薄所述第二光阻层的厚度至所述第二光阻部被去除，由剩余的第一光阻部形成第二光阻保护层；
    步骤S70、在所述层间绝缘层及第二光阻保护层上形成源漏极金属层，在所述源漏极金属层上形成第三光阻层，以所述第三光阻层为遮蔽层，对所述源漏极金属层进行干蚀刻，得到包括源漏极的第二金属图案，所述源漏极通过所述接触孔与所述有源层相连接，去除所述第三光阻层及第二光阻保护层。
  7. 如权利要求1所述的TFT基板的制作方法，其中，所述TFT基板包括多层所述无机绝缘层及多层所述金属层，该多层无机绝缘层包括栅极绝缘层及层间绝缘层，该多层金属层包括栅极金属层及源漏极金属层；由所述源漏极金属层形成的金属图案包括位于显示区的源漏极及位于标记区的对位标记；所述保护层包括对栅极绝缘层的表面进行保护的第一光阻保护层及对层间绝缘层的表面进行保护的第二光阻保护层；
    该制作方法具体包括如下步骤：
    步骤S10’、提供衬底基板，在所述衬底基板上形成缓冲层，在所述缓冲层上沉积并图案化形成有源层；
    步骤S20’、在所述缓冲层及有源层上沉积形成栅极绝缘层，在所述栅极绝缘层上形成对应于所述标记周边区的第一光阻保护保护层，在所述栅极绝缘层及第一光阻保护层上形成栅极金属层；
    步骤S30’、在所述栅极金属层上形成第一光阻层，以所述第一光阻层为遮蔽层，对所述栅极金属层进行干蚀刻，得到包括栅极及对位标记的第一金属图案；
    步骤S40’、去除第一光阻层及第一光阻保护层；
    步骤S50’、在所述第一金属图案及栅极绝缘层上沉积形成层间绝缘层，并利用半色调掩膜板在所述层间绝缘层上形成第二光阻层，所述第二光阻层包括对应于标记周边区的第一光阻部及剩余的第二光阻部，所述第一光阻部的厚度大于第二光阻部的厚度，以所述第二光阻层为遮蔽层，在所述层间绝缘层及栅极绝缘层上形成对应位于所述有源层两端上方的接触孔；
    步骤S60’、对所述第二光阻层进行灰化处理以减薄所述第二光阻层的厚度至所述第二光阻部被去除，由剩余的第一光阻部形成第二光阻保护层；
    步骤S70’、在所述层间绝缘层及第二光阻保护层上形成源漏极金属层，在所述源漏极金属层上形成第三光阻层，以所述第三光阻层为遮蔽层，对所述源漏极金属层进行干蚀刻，得到包括源漏极及对位标记的第二金属图案，所述源漏极通过所述接触孔与所述有源层相连接，去除所述第三光阻层及第二光阻保护层。
  8. 一种TFT基板，划分出显示区及围绕所述显示区的显示外围区，所述显示外围区划分出标记区及围绕所述标记区的标记周边区；包括无机绝缘层、金属层及对应设于所述无机绝缘层及金属层之间的透明导电保护层；
    其中，所述金属层具有金属图案，所述透明导电保护层对应位于所对应的金属层的下方并具有与该金属层的金属图案相同的透明导电图案，所述透明导电保护层用于在对金属层进行干蚀刻以形成所述金属图案的过程中对标记区及标记周边区的无机绝缘层的表面进行保护。
  9. 如权利要求8所述的TFT基板，包括多层所述无机绝缘层及多层所述金属层，该多层无机绝缘层包括栅极绝缘层及层间绝缘层，该多层金属层包括设于所述栅极绝缘层上的栅极金属层及设于所述层间绝缘层上的源漏极金属层，所述透明导电保护层对应设于所述栅极绝缘层和栅极金属层之间；
    所述TFT基板具体包括衬底基板、设于所述衬底基板上的缓冲层、设于所述缓冲层上的有源层、设于所述缓冲层及有源层上的栅极绝缘层、设于所述栅极绝缘层上的透明导电保护层、设于所述透明导电保护层上的栅极金属层、设于所述栅极金属层及栅极绝缘层上的层间绝缘层及设于所述层间绝缘层上的源漏极金属层；
    所述栅极金属层具有包括栅极的第一金属图案；
    所述透明导电保护层对应位于所述栅极金属层下方并具有与所述第一金属图案相同的透明导电图案；
    所述源漏极金属层具有包括源漏极的第二金属图案。
  10. 如权利要求8所述的TFT基板，其中，所述第一金属图案和第二金属图案中的一个还包括对应位于所述标记区的对位标记。
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