WO2020124470A1 - 模数转换电路、图像传感器和模数转换方法 - Google Patents

模数转换电路、图像传感器和模数转换方法 Download PDF

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Publication number
WO2020124470A1
WO2020124470A1 PCT/CN2018/122251 CN2018122251W WO2020124470A1 WO 2020124470 A1 WO2020124470 A1 WO 2020124470A1 CN 2018122251 W CN2018122251 W CN 2018122251W WO 2020124470 A1 WO2020124470 A1 WO 2020124470A1
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Prior art keywords
signal
analog
terminal
charge accumulation
current
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PCT/CN2018/122251
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English (en)
French (fr)
Inventor
李欣伦
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Shenzhen Goodix Technology Co Ltd
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Shenzhen Goodix Technology Co Ltd
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Priority to PCT/CN2018/122251 priority Critical patent/WO2020124470A1/zh
Priority to CN201880002862.4A priority patent/CN109792499B/zh
Publication of WO2020124470A1 publication Critical patent/WO2020124470A1/zh
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components

Definitions

  • the present disclosure relates to analog-to-digital conversion technology, and in particular, to an analog-to-digital conversion circuit that performs analog-to-digital conversion on analog signals generated by pixels, and related image sensors and analog-to-digital conversion methods.
  • CMOS image sensor CIS
  • CMOS image sensor CIS
  • column-parallel analog-to-digital conversion structure column-parallel ADC
  • single-slope analog-to-digital converter single ADC
  • the column parallel analog-to-digital conversion structure is almost implemented by the single-slope analog-to-digital converter.
  • the power consumption of the counter of the single-slope analog-to-digital converter increases.
  • One of the objectives of the present disclosure is to provide an analog-to-digital conversion circuit that performs analog-to-digital conversion on an analog signal generated by a pixel, and its related image sensor and analog-to-digital conversion method, to solve the above problems.
  • An embodiment of the present disclosure provides an analog-to-digital conversion circuit.
  • the analog-to-digital conversion circuit is used to convert an analog signal into a digital signal.
  • the analog-to-digital conversion circuit includes a comparison circuit, a first counter, a charge accumulation circuit, a discharge circuit, and a second counter.
  • the comparison circuit is used to compare the analog signal with a ramp signal to generate a first comparison signal, and to compare the analog signal with the ramp signal plus a predetermined offset to generate a second comparison signal.
  • the first counter is coupled to the comparison circuit, and is used for counting the number of cycles of the clock signal when the first comparison signal indicates that the signal level of the analog signal is greater than the signal level of the ramp signal Count to obtain the first part of the digital signal.
  • the charge accumulation circuit is coupled to the comparison circuit to indicate that the signal level of the analog signal is greater than the signal level of the ramp signal when the first comparison signal indicates, and the second comparison signal indicates When the signal level of the analog signal is less than the signal level of the ramp signal plus the predetermined offset, the charge from the first current is accumulated at the charge accumulation end of the charge accumulation circuit.
  • the discharge circuit is coupled to the charge accumulation terminal for discharging the charge accumulation terminal with a second current while the first counter stops counting, wherein the second current is less than the first Current.
  • the second counter is coupled to the charge accumulation circuit for counting the number of cycles of the clock signal during the discharge of the charge accumulation terminal to obtain the second part of the digital signal.
  • An embodiment of the present disclosure provides an image sensor.
  • the image sensor includes a pixel array, a control circuit, and at least one analog-to-digital conversion circuit.
  • the pixel array includes multiple pixels arranged in multiple rows and multiple columns.
  • the control circuit is used to generate a clock signal and a ramp signal.
  • the at least one analog-to-digital conversion circuit is coupled to the pixel array and the control circuit, and is configured to convert an analog signal generated by a column of pixels in the pixel array into a digital signal.
  • An embodiment of the present disclosure provides an analog-to-digital conversion method.
  • the analog-to-digital conversion method includes the steps of: comparing an analog signal with a ramp signal to generate a first comparison signal; comparing the analog signal with the ramp signal plus a predetermined offset to generate a second comparison signal; When the first comparison signal indicates that the signal level of the analog signal is greater than the signal level of the ramp signal, the number of cycles of the clock signal is counted to obtain a first count value; the first comparison signal indicates The signal level of the analog signal is greater than the signal level of the ramp signal, and the second comparison signal indicates that the signal level of the analog signal is less than the signal level of the ramp signal plus the predetermined When shifting, the charge from the first current is accumulated at the charge accumulation end; while the charge accumulation end stops accumulating the charge from the first current, the charge accumulation end is discharged with the second current, wherein the The second current is smaller than the first current; and during the discharge of the charge accumulation terminal, the number of cycles of the clock signal is counted to obtain
  • FIG. 1 is a functional block diagram of an embodiment of an image sensor of the present disclosure.
  • FIG. 2 shows a schematic diagram of a specific implementation manner of at least one analog-to-digital conversion circuit among the multiple analog-to-digital conversion circuits shown in FIG. 1.
  • FIG. 3 is a schematic diagram of an embodiment of the analog-to-digital conversion circuit shown in FIG. 2.
  • FIG. 4 is a signal timing diagram of an embodiment of the signal processing operation involved in the analog-to-digital conversion circuit shown in FIG. 3.
  • FIG. 5 is a flowchart of an embodiment of the analog-to-digital conversion method of the present disclosure.
  • A32 The second AND gate is the second AND gate
  • A33 The third AND gate is the third AND gate
  • A34 The fourth AND gate, the fourth AND gate, A34, A34, A34, A34, A34, A34, A34, A34, A34, A34
  • the second switch is the second switch
  • the third switch is the third switch
  • the fourth switch is the fourth switch
  • the fifth switch is the fifth switch
  • the sixth switch is the sixth switch
  • VA 1 -VA K VA analog signal
  • VD 1 VD digital signal
  • CV_C The first count value of CV_C
  • FIG. 1 is a functional block diagram of an embodiment of an image sensor of the present disclosure.
  • the image sensor 100 may use a column parallel analog-to-digital conversion structure to perform analog-to-digital conversion operations on the sensor signal, and may include (but not limited to) a pixel array 102, a control circuit 110, and multiple analog-to-digital Conversion circuit (labeled "ADC") 120_1-120_K, where K is a positive integer greater than 1.
  • ADC analog-to-digital Conversion circuit
  • the pixel array 102 may include a plurality of pixels (or pixel units) P 11 -P MK arranged in M rows and K columns, where M is a positive integer greater than 1, and each pixel P 11 -P MK may perform image sensing separately
  • An analog signal (such as a sensing voltage or a sensing current) is generated.
  • the control circuit 110 can generate a clock signal CLK and a ramp signal VR.
  • the analog-to-digital conversion circuits 120_1-120_K are coupled to the pixel array 102 and the control circuit 110.
  • Each analog-to-digital conversion circuit can convert the analog signals generated by the pixels P 11 -P MK (such as multiple The corresponding analog signal among the analog signals VA 1 -VA K ) is converted into a digital signal.
  • the analog-to-digital conversion circuit 120_1 can convert the analog signal VA 1 into a digital signal VD 1 according to the clock signal CLK and the ramp signal VR.
  • the digital-to-analog conversion circuits shown in FIG. 1 can directly receive the analog signals generated by the pixels in each column, this is only for convenience of explanation, and the present disclosure is not limited thereto.
  • the analog signals generated by the pixels in each column can be processed by the relevant signal before being transmitted to the corresponding digital-to-analog conversion circuit.
  • a programmable gain amplifier programmable gain amplifier, PGA
  • the analog signal generated by the column of pixels can be first signaled by the programmable gain amplifier After the amplification process, it is transferred to the corresponding digital-to-analog conversion circuit.
  • each analog-to-digital conversion circuit may count the number of cycles of the clock signal CLK in different counting stages according to the ramp signal VR and the corresponding analog signal to convert the corresponding analog signal to a digital signal.
  • the analog-to-digital conversion circuit 120_1 can first perform a first counting operation on the number of cycles of the clock signal CLK according to the ramp signal VR and the analog signal VA 1 .
  • the clock signal CLK can be implemented by a low-frequency clock signal, thereby reducing the power consumption of signal processing.
  • the first counting operation can be regarded as coarse counting.
  • the analog-to-digital conversion circuit 120_1 can also accumulate the charge from the first current I1. After stopping the first counting operation, the analog-to-digital conversion circuit 120_1 may discharge the accumulated charge based on the second current I2, where the second current I2 is less than the first current I1.
  • the charge accumulated by the analog-to-digital conversion circuit 120_1 can indicate the time point between the last increase of the count value before stopping the first counting operation and the time point when the first counting operation is stopped.
  • the accumulated charge Therefore, a smaller current (second current I2) can be used to release the charge accumulated from the larger current, and the number of cycles of the clock signal CLK is counted during this period, thereby improving the resolution of the analog-to-digital conversion circuit 120_1 rate.
  • the second current I2 may be one eighth of the first current I1, therefore, the time required to release the accumulated charge with the second current I2 is approximately the first current Eight times the time required for I1 to accumulate charge. Therefore, counting the number of cycles of the clock signal CLK during the period of discharging the accumulated charge with the second current I2 is equivalent to counting another clock signal (frequency is the clock during the period of accumulating the charge with the first current I1 The number of cycles of eight times the frequency of the signal CLK is counted. In other words, the second counting operation can be regarded as a fine counting operation.
  • the analog-to-digital conversion circuit 120_1 can use a clock signal of a lower frequency to realize a high-precision digital-to-analog conversion operation. In this way, the image sensor 100 can greatly reduce the power consumption of the analog-to-digital conversion operation while meeting the requirements of high resolution and high-speed imaging.
  • FIG. 2 shows a schematic diagram of a specific implementation manner of at least one analog-to-digital conversion circuit among the multiple analog-to-digital conversion circuits 120_1-120_K shown in FIG. 1.
  • the analog-to-digital conversion circuit 220 can convert an analog signal VA (such as one of a plurality of analog signals VA 1 -VA K ) into a digital signal VD, and can include (but not limited to) a comparison circuit 230 and a first counter 240, a charge accumulation circuit 250, a discharge circuit 260, and a second counter 270.
  • the comparison circuit 230 is used to compare the analog signal VA with the ramp signal VR to generate a first comparison signal CP1, and to compare the analog signal VA with the digital signal VD plus a predetermined offset Vos to generate a second comparison signal CP2 .
  • the first comparison signal CP1 can indicate the magnitude relationship between the "analog signal VA” and the "slope signal VR”
  • the second comparison signal CP2 can indicate the "analog signal VA” and the "slope”
  • the magnitude relationship between the signal VR and the signal VR plus a predetermined offset Vos Therefore, in the process of gradually increasing the signal level of the ramp signal VR to approximate the signal level of the analog signal VA, the signal level of the second comparison signal CP2 will first toggle compared to the first comparison signal CP1, Indicate the change of signal size relationship.
  • the comparison circuit 230 may include (but not limited to) a first comparator 232 and a second comparator 234.
  • the first comparator 232 is used to receive the analog signal VA and the ramp signal VR, and compare the analog signal VA with the ramp signal VR to generate a first comparison signal CP1.
  • the second comparator 234 compares the analog signal VA with the ramp signal VR plus a predetermined offset Vos to generate a second comparison signal CP2.
  • the predetermined offset Vos may be (but not limited to) a comparator offset inherent within the second comparator 234. That is, similar to the first comparator 232, the second comparator 234 can also receive the analog signal VA and the ramp signal VR.
  • the comparison operation performed by the second comparator 234 can be regarded as a comparison between the analog signal VA and the ramp signal VR plus a predetermined offset Vos.
  • the offset of the predetermined offset Vos can be adjusted according to design requirements.
  • the first comparator 232 and the second comparator 234 may be combined into a single comparison circuit with two output terminals.
  • the second comparator 234 may be incorporated into the first comparator 232.
  • the design changes related to the comparison circuit 230 are included in the protection scope of the present disclosure.
  • the first counter 240 is coupled to the comparison circuit 230 for controlling the counting operation of the number of cycles of the clock signal CLK according to the first comparison signal CP1. For example, when the first comparison signal CP1 indicates that the signal level of the analog signal VA is greater than the signal level of the ramp signal VR, the first counter 240 may count the number of cycles of the clock signal CLK to obtain the first part of the digital signal VD ( That is, the first count value CV_C).
  • the first counter 240 may start the counting operation of the number of cycles of the clock signal CLK at an appropriate timing to reduce power consumption. For example, before the ramp signal VR is generated, the control circuit 110 does not allow the first counter 240 to start the counting operation; when the ramp signal VR is generated, the counting operation of the first counter 240 is started.
  • the charge accumulation circuit 250 is coupled to the comparison circuit 230 for indicating that the signal level of the analog signal VA is greater than the signal level of the ramp signal VR in the first comparison signal CP1, and the signal of the analog signal VA is indicated in the second comparison signal CP2
  • the charge from the first current I1 is accumulated at a charge accumulation terminal TCA of the charge accumulation circuit 250.
  • the charge accumulated at the charge accumulation terminal TCA may indicate the charge accumulated between the time point at which the first count value CV_C last increased before the first counter 240 stopped counting, and the time point at which the first counter 240 stopped counting.
  • the charge accumulation circuit 250 may start accumulating charge from the first current I1 at the charge accumulation terminal TCA when the first count value CV_C increases. For example, when the signal level of the analog signal VA is greater than the signal level of the ramp signal VR and less than the signal level of the ramp signal VR plus a predetermined offset Vos, when the clock signal CLK is at a predetermined signal edge (rising edge or falling edge) At the time), the charge accumulation circuit 250 may start to accumulate charge from the first current I1 at the charge accumulation terminal TCA.
  • the charge accumulation circuit 250 may perform one or more charge accumulation operations on the charge accumulation terminal TCA, wherein when the first count value CV_C increases, the charge accumulation circuit 250 may reset the charge accumulation terminal TCA and restart The charge from the first current I1 is accumulated at the charge accumulation terminal TCA. For example, during the period when the difference between the signal level of the analog signal VA and the signal level of the ramp signal VR is less than the predetermined offset Vos, the charge accumulation circuit 250 may reset the charge accumulation terminal whenever the first count value CV_C increases TCA, and re-accumulate the charge from the first current I1 at the charge accumulation terminal TCA.
  • the charge accumulation circuit 250 may stop accumulating the first current I1 at the charge accumulation terminal TCA Of charge.
  • the discharge circuit 260 is coupled to the charge accumulation terminal TCA, and is used for discharging the charge accumulation terminal TCA with the second current I2 while the first counter 240 stops counting. For example, when the first comparison signal CP1 indicates that the signal level of the analog signal VA is less than the signal level of the ramp signal VR, the first counter 240 may stop counting the number of cycles of the clock signal CLK. The discharge circuit 260 may discharge the charge accumulation terminal TCA with the second current I2 when the signal level of the analog signal VA is less than the signal level of the ramp signal VR.
  • the second counter 270 is coupled to the charge accumulation circuit 250 for counting the number of cycles of the clock signal CLK during the discharge of the charge accumulation terminal TCA to obtain the second part of the digital signal VD (ie, the second count value CV_F) .
  • the second current I2 is smaller than the first current I1. Therefore, the counting operation of the number of cycles of the clock signal CLK during the discharge of the charge accumulation terminal TCA is equivalent to the period during which the charge accumulation terminal TCA accumulates the charge from the first current I1, to another clock signal (frequency greater than The number of cycles of the clock signal CLK is counted.
  • the first counter 240 can be regarded as a coarse counter
  • the second counter 270 can be regarded as a fine counter, in which the charge accumulated at the charge accumulation terminal TCA can correspond to the first count value CV_C The numerical scale between two adjacent values.
  • the K-column pixels shown in FIG. 1 can also share a single digital-analog conversion circuit through a switch circuit, wherein the single digital-analog conversion circuit can be implemented by the digital-analog conversion circuit 220 shown in FIG. 2.
  • FIG. 3 is a schematic diagram of an embodiment of the analog-to-digital conversion circuit 220 shown in FIG. 2.
  • the analog-to-digital conversion circuit 320 may include a first comparator 332, a second comparator 334 (with a predetermined offset Vos), a first counter 340, a charge accumulation circuit 350, a discharge circuit 360, and a second counter 370 Among them, the first comparator 232, the second comparator 234, the first counter 242, the charge accumulation circuit 250, the discharge circuit 260 and the second counter 270 shown in FIG. 2 can be respectively composed of the first comparator 332 and the second comparator 334, the first counter 340, the charge accumulation circuit 350, the discharge circuit 360, and the second counter 370 are implemented.
  • the first counter 340 may include (but is not limited to) an AND gate A11 and Y flip-flops (Y is a positive integer greater than 1).
  • the Y flip-flops can be implemented by 9 D flip-flops DF11-DF19, and the AND gate A11 can receive the clock signal CLK and the first comparison signal at the two input terminals, respectively CP1, so that the output terminal of the AND gate A11 generates a first input clock signal CKD1.
  • D flip-flops DF11-DF19 are cascaded in sequence (ie, the respective data output terminals Q of the D flip-flops DF11-DF18 are respectively coupled to the clock input terminals of the D flip-flops DF12-DF19); and, the D flip-flop DF11 is coupled To the output terminal of the AND gate A11 (that is, the clock input terminal of the D flip-flop DF11 is coupled to the first input clock signal CKD1), wherein the data input terminal D and the inverted data output terminal Q′ of each D flip-flop DF11-DF19 Are connected to each other, and the reset terminals R of the D flip-flops DF11-DF19 can be coupled to a control circuit (such as the control circuit 110 shown in FIG.
  • Multiple D flip-flops DF11-DF19 can be used to count the number of cycles of the first input clock signal CKD1 to generate a first count value CV_C (including the output of the data output terminal Q of each flip-flop DF11-DF19) as an analog signal VA phase Corresponding to the first part of a digital signal (such as the digital signal VD shown in FIG. 2).
  • the charge accumulation circuit 350 may include, but is not limited to, a switch control circuit 352 and a charge accumulation unit 354.
  • the switch control circuit 352 may include, but is not limited to, a plurality of first AND gates A31, a second AND gate A32, a third AND gate A33, a fourth AND gate A34, and a plurality of inverters I1 and I2.
  • the two input terminals of the first AND gate A31 can respectively receive the data output q1 of the D flip-flop DF11 and an inverted signal CP2b of the second comparison signal CP2 to generate a first switch control at the output terminal of the first AND gate A31 Signal qp.
  • the analog-to-digital conversion circuit 320 may further include an inverter (not shown) for inverting the second comparison signal CP2 to generate an inverted signal CP2b.
  • the two input terminals of the second AND gate A32 can respectively receive the inverted data output q1n and the inverted signal CP2b of the D flip-flop DF11 to generate a second switch control signal qn at the output terminal of the second AND gate A32.
  • the two input terminals of the third AND gate A33 can respectively receive the first comparison signal CP1 and the first switch control signal qp, so as to generate a third switch control signal q1g at the output terminal of the third AND gate A33.
  • the two input terminals of the fourth AND gate A34 can respectively receive the first comparison signal CP1 and the second switch control signal qn, so that a fourth switch control signal qn1g is generated at the output terminal of the fourth AND gate A34.
  • the inverter I1 is used to invert the first switch control signal qp to generate a first inverted control signal qp'.
  • the inverter I2 is used to invert the second switch control signal qn to generate a second inverted control signal qn'.
  • the charge accumulation unit 354 may include, but is not limited to, a first storage terminal TO1, a second storage terminal TO2, a first capacitor C1, a second capacitor C2, and a current source CS1.
  • the first storage terminal TO1 is selectively coupled to the charge accumulation terminal TCA
  • the second storage terminal TO2 is selectively coupled to the charge accumulation terminal TCA.
  • the first capacitor C1 is coupled between the first storage terminal TO1 and a reference node Nref
  • the second capacitor C2 is coupled between the second storage terminal TO2 and the reference node Nref.
  • the current source CS1 is coupled to the first capacitor C1 through the first storage terminal TO1 and is coupled to the second capacitor C2 through the second storage terminal TO2.
  • the current source CS1 is used to provide the first current I1, and can alternately charge the first capacitor C1 and the second capacitor C2 with the first current I1 at different periods of the clock signal CLK to alternate between the first storage terminal TO1 and the second
  • the storage terminal TO2 accumulates the charge from the first current I1.
  • the current source CS1 charges the first capacitor C1
  • the first storage terminal TO1 is coupled to the charge accumulation terminal TCA
  • the second storage terminal TO2 is coupled to the charge accumulation terminal TCA.
  • the current source CS1 may use the first current I1 to charge one of the first capacitor C1 and the second capacitor C2 to accumulate the first current from the corresponding storage terminal The charge of I1; in the next cycle of the clock signal CLK, the current source CS1 can use the first current I1 to charge the other of the first capacitor C1 and the second capacitor C2 to accumulate from the corresponding other storage terminal. The charge of the first current I1.
  • the current source CS1 when the current source CS1 charges the first capacitor C1, the second storage terminal TO2 can be reset; when the current source CS1 charges the second capacitor C2, the first storage terminal TO1 can be reset. In this way, the current source CS1 can recharge the first capacitor C1/second capacitor C2 at different periods of the clock signal CLK.
  • the charge accumulation unit 354 may further include a first switch S1, a second switch S2, a third switch S3, and a fourth switch S4.
  • the first switch S1 is controlled by the first inverted control signal qp' for selectively coupling between the first storage terminal TO1 and the reference node Nref.
  • the second switch S2 is controlled by the second inverted control signal qn' for selectively coupling between the second storage terminal TO2 and the reference node Nref.
  • the third switch S3 is controlled by the first switch control signal qp for selectively coupling between the first storage terminal TO1 and the charge accumulation terminal TCA.
  • the fourth switch S4 is controlled by the second switch control signal qn for selectively coupling between the second storage terminal TO2 and the charge accumulation terminal TCA.
  • the first switch S1 and the fourth switch S4 will be closed, and the second switch S2 and the third switch S3 will be turned on;
  • the current source CS1 charges the second capacitor C2
  • the first A switch S1 and a fourth switch S4 will be turned on, and a second switch S2 and a third switch S3 will be turned off. Therefore, when the current source CS1 charges the first capacitor C1, the first storage terminal TO1 may be coupled to the charge accumulation terminal TCA, and the second storage terminal TO2 may be reset.
  • the second storage terminal TO2 may be coupled to the charge accumulation terminal TCA, and the first storage terminal TO1 may be reset
  • the charge accumulation unit 354 may further include a fifth switch S5, a sixth switch S6, and a comparator 356.
  • the fifth switch S5 is controlled by the third switch control signal q1g for selectively coupling between the current source CS1 and the first storage terminal TO1.
  • the sixth switch S6 is controlled by the fourth switch control signal qn1g for selectively coupling between the current source CS1 and the second storage terminal TO2.
  • the comparator 356 has a first input terminal TI1, a second input terminal TI2, and an output terminal TO, wherein the first input terminal TI1 is coupled to the charge accumulation terminal TCA, the second input terminal TI2 is coupled to the reference node Nref, and the output terminal TO Coupled to the second counter 370.
  • the comparator 356 may output an enable signal EN from the output terminal TO to enable the second counter 370.
  • the discharge circuit 360 is used to discharge the charge accumulation terminal TCA based on the second current I2, and may include (but not limited to) a current source CS2 and a switch SD.
  • the current source CS2 is used to receive the second current I2.
  • the switch SD is selectively coupled between the charge accumulation terminal TCA and the current source CS2. During the period when the charge accumulation circuit 350 stops accumulating the charge from the first current I1, the switch SD may be coupled to the charge accumulation terminal TCA and the current source CS2 In between, the second current I2 is poured into the current source CS2 from the charge accumulation terminal TCA. That is, while the charge accumulation circuit 350 stops accumulating charges from the first current I1, the charges accumulated at the charge accumulation terminal TCA may be discharged to the current source CS2.
  • the second counter 370 may include (but is not limited to) an AND gate A21 and P flip-flops (P is a positive integer greater than 1).
  • the P flip-flops can be implemented by three D flip-flops DF21-DF23, and the AND gate A21 can receive the clock signal CLK and the enable signal EN at the two input terminals, respectively To generate a second input clock signal CKD2 at the output of the AND gate A21.
  • Multiple D flip-flops DF21-DF23 are cascaded in sequence (that is, the respective data output terminals Q of the D flip-flops DF21 and DF22 are respectively coupled to the clock input terminals of the D flip-flops DF22 and DF23); and, the D flip-flop DF21 is coupled To the output terminal of the AND gate A21 (ie, the clock input terminal of the D flip-flop DF21 is coupled to the second input clock signal CKD2), wherein the data input terminal D and the inverted data output terminal Q'of each D flip-flop DF21-DF23 Connected to each other, and the reset terminals R of the D flip-flops DF21-DF23 can be coupled to a control circuit (such as the control circuit 110 shown in FIG.
  • Multiple D flip-flops DF21-DF23 can be used to count the number of cycles of the second input clock signal CKD2 to generate a second count value CV_F (including the output of the data output terminal Q of each flip-flop DF21-DF23) as an analog signal VA phase Corresponding to the second part of a digital signal (such as the digital signal VD shown in FIG. 2).
  • FIG. 4 is a signal timing diagram of an embodiment of the signal processing operation involved in the analog-to-digital conversion circuit 320 shown in FIG. 3.
  • the current of the second current I2 may be one-eighth of the first current I1.
  • the invention is not limited to this.
  • the signal level of the analog signal VA is greater than the signal level of the ramp signal VR, therefore, the first counter 340 can count the number of cycles of the first input clock signal CKD1.
  • the signal level of the analog signal VA is greater than the signal level of the ramp signal VR plus a predetermined offset Vos, therefore, the charge accumulation operation of the charge accumulation circuit 350 may not be started.
  • the signal level of the analog signal VA is still greater than the signal level of the ramp signal VR, however, the signal level of the analog signal VA is less than the signal level of the ramp signal VR plus a predetermined offset Vos. Therefore, the signal level of the second comparison signal CP2 is inverted, and the charge accumulation circuit 350 may start to accumulate the charge from the first current I1 at the charge accumulation terminal TCA.
  • the charge accumulation circuit 350 may reset the charge accumulation terminal TCA and re-accumulate the charge from the first current I1 at the charge accumulation terminal TCA .
  • the first switch S1 will be turned on, and the fifth switch S5 will be turned off, so that the first storage terminal TO1 (having the signal level V1) is reset.
  • the second switch S2 is turned off, and the sixth switch S6 is turned on, so that the current source CS1 can charge the second capacitor C2 to accumulate the charge from the first current I1 at the second storage terminal TO2 (having the signal level V2).
  • the third switch S3 is turned off, and the fourth switch S4 is turned on, so that the second storage terminal TO2 is coupled to the charge accumulation terminal TCA.
  • the charge accumulation circuit 350 may reset the charge accumulation terminal TCA again, and restart the charge accumulation terminal TCA
  • the charge from the first current I1 is accumulated.
  • the second switch S2 will be turned on, and the sixth switch S6 will be turned off, so that the second storage terminal TO2 is reset.
  • the first switch S1 is turned off, and the fifth switch S5 is turned on, so that the current source CS1 can charge the first capacitor C1 to accumulate the charge from the first current I1 at the first storage terminal TO1.
  • the third switch S3 is turned on, and the fourth switch S4 is turned off, so that the first storage terminal TO1 is coupled to the charge accumulation terminal TCA.
  • the signal level of the analog signal VA is less than the signal level of the ramp signal VR, so that the signal level of the first comparison signal CP1 is inverted. Therefore, the first counter 340 may stop the related counting operation, and the charge accumulation circuit 350 may stop the related charge accumulation operation.
  • the discharge circuit 360 may discharge the charge accumulation terminal TCA based on the second current I2.
  • the second counter 370 may count the number of cycles of the clock signal CLK during the discharge of the charge accumulation terminal TCA to obtain the second part of the digital signal VD. For example, after the charge accumulation circuit 350 stops accumulating the charge from the first current I1 (after the time point t4), when the clock signal CLK first appears a predetermined signal edge, the second counter 370 may start to cycle the clock signal CLK. Count.
  • the switch SD of the discharge circuit 360 may couple the charge accumulation terminal TCA to the current source according to the second reset signal rstb2 CS2 to release the charge accumulated in the charge accumulation terminal TCA (that is, the charge accumulated in the first capacitor C1/first storage terminal TO1 between the time point t4 and the time point t5).
  • the second counter 370 may reset the second count value CV_F according to the second reset signal rstb2, and count the number of cycles of the clock signal CLK to update the second count value CV_F.
  • the output of the output terminal TO is enabled.
  • the signal EN will be at a low signal level, and the second counter 370 may stop the counting operation.
  • the first count value CV_C(N+2) and the second count value CV_F(3) can be used as part of the digital signal VD, respectively.
  • an image sensor having both low power consumption and high frame rate can be realized by using a clock signal of lower frequency.
  • LSB least significant bit
  • a lower frequency clock signal CLK can be used to meet the design requirements of the image sensor.
  • the frequency of the clock signal CLK can be set to one eighth (250 MHz) of 2 GHz. That is, the cycle time of the clock signal CLK is 4ns.
  • the magnitude of the second current I2 may be set to one-eighth the magnitude of the first current I1.
  • the time required for discharging with the second current I2 is at most 32 ns (that is, 8 ⁇ 4 ns). Therefore, the overall conversion time of the digital-to-analog conversion circuit 3205 is 2080 ns (that is, 2 9 ⁇ 4 ns + 8 ⁇ 4 ns). In other words, even if a clock signal with a lower frequency is used, the digital-to-analog conversion circuit 320 can still obtain a frame within 2.5 ⁇ s, thereby meeting the design requirements of a high frame rate.
  • the predetermined offset Vos may be provided by a signal source external to the second comparator 334.
  • the analog-to-digital conversion circuit 320 may include a signal source that generates a predetermined offset Vos and transmits the predetermined offset Vos to the negative input terminal of the second comparator 334.
  • the control circuit 110 shown in FIG. 1 may generate another ramp signal different from the ramp signal VR, where the signal level of the other ramp signal is equal to the signal level of the ramp signal VR plus a predetermined offset Vos, The second comparator 334 can receive the other ramp signal at the negative input.
  • the another ramp signal may be an advanced copy of the ramp signal VR, where the advanced copy of the ramp signal VR and the ramp signal VR have a predetermined phase offset, so that the signal of the advanced copy of the ramp signal VR The level is equal to the signal level of the ramp signal VR plus a predetermined offset Vos.
  • the first counter 340 and/or the second counter 370 may adopt different circuit structures.
  • the number and/or types of triggers included in the first counter 340 can be determined according to design requirements, and/or the number and/or types of triggers included in the second counter 370 can be determined according to design requirements .
  • the charge accumulation circuit 350 may adopt a different circuit structure to accumulate charge from the first current I1 at the charge accumulation terminal TCA.
  • the charge accumulation circuit 350 may employ more than three capacitors to accumulate charge. As long as the charge from the first current can be accumulated at the charge accumulation terminal before the counting operation (ie, the coarse counting operation) is stopped, and released with a smaller second current after the counting operation is stopped, the number of cycles of the clock signal.
  • the analog-to-digital conversion circuit that performs counting to achieve fine counting, and the related changes in design all follow the spirit of the present invention and fall within the scope of the present invention.
  • FIG. 5 is a flowchart of an embodiment of the analog-to-digital conversion method of the present invention. If the results obtained are substantially the same, the steps need not be performed in the order shown in FIG. For example, certain steps may be inserted therein.
  • the analog-to-digital conversion circuit 320 shown in FIG. 3 is described below to explain the analog-to-digital conversion method shown in FIG. 5.
  • the analog-to-digital conversion method shown in Fig. 5 can be simply summarized as follows.
  • Step 502 Compare an analog signal with a ramp signal to generate a first comparison signal.
  • the first comparator 332 compares the analog signal VA with the ramp signal VR to generate the first comparison signal CP1.
  • Step 504 Compare the analog signal with the ramp signal plus a predetermined offset to generate a second comparison signal.
  • the second comparator 334 compares the analog signal VA with the ramp signal VR plus a predetermined offset Vos to generate a second comparison signal CP2.
  • Step 506 When the first comparison signal indicates that the signal level of the analog signal is greater than the signal level of the ramp signal, count the number of cycles of the clock signal to obtain a first count value. For example, when the first comparison signal CP1 indicates that the signal level of the analog signal VA is greater than the signal level of the ramp signal VR (as shown in FIG. 4 before time t4), the first counter 340 may compare the period of the clock signal CLK. Count to obtain the first count value CV_C.
  • Step 508 The first comparison signal indicates that the signal level of the analog signal is greater than the signal level of the ramp signal, and the second comparison signal indicates that the signal level of the analog signal is less than the
  • the charge from the first current is accumulated at the charge accumulation terminal.
  • the charge accumulation circuit 350 may accumulate the charge from the first current I1 at the charge accumulation terminal TCA.
  • Step 510 While the charge accumulation terminal stops accumulating charges from the first current, discharge the charge accumulation terminal with a second current, where the second current is less than the first current.
  • the discharge circuit 350 may discharge the charge accumulation terminal TCA based on the second current I2 (at a time point t5 shown in FIG. 4), where the second current I2 is less than the first current I1.
  • Step 512 During the discharge of the charge accumulation terminal, count the number of cycles of the clock signal to obtain a second count value, wherein the first count value and the second count value are respectively used as the digital signal Part I and Part II.
  • the number of cycles of the clock signal CLK is counted to obtain a second count value CV_F (between time t5 and time t6 shown in FIG. 4).
  • the first count value CV_C and the second count value CV_F serve as the first and second parts of the digital signal VD, respectively.
  • step 508 when the first count value increases, the charge accumulation terminal may be reset, and the charge from the first current may be accumulated again at the charge accumulation terminal.
  • the charge accumulation circuit 350 may reset the charge accumulation terminal TCA when the first count value CV_C increases (eg, time t2/t3 shown in FIG. 4), and re-accumulate the charge from the first current I1 at the charge accumulation terminal TCA .
  • step 512 after the charge accumulation terminal stops accumulating charges from the first current, when the clock signal first appears a predetermined signal edge, it may start to count the number of cycles of the clock signal .
  • the charge accumulation circuit 350 stops accumulating the charge from the first current I1 at the charge accumulation terminal TCA, when the clock signal CLK first appears a predetermined signal edge (for example, a rising edge; time point t5 shown in FIG. 4), You can start counting the number of cycles of the clock signal CLK.
  • the analog-to-digital conversion mechanism provided by the present disclosure can achieve coarse count operation and fine count operation without increasing the number of ramp signal generating circuits, and can use a low-frequency clock signal, thereby effectively reducing power consumption and achieving Power saving effect.

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Abstract

一种模数转换电路、图像传感器和模数转换方法。所述模数转换电路（220）包括比较电路（230）、第一计数器（240）、电荷累积电路（250）、放电电路（260）及第二计数器（270）。所述比较电路（230）比较模拟信号（VA）与斜坡信号（VR），并比较所述模拟信号（VA）与所述斜坡信号（VR）加上预定偏移（Vos）。所述第一计数器（240）在所述模拟信号（VA）的信号电平大于所述斜坡信号（VR）的信号电平时，对时钟信号（CLK）的周期个数进行计数。所述电荷累积电路（250）在所述模拟信号（VA）的信号电平小于所述斜坡信号（VR）的信号电平加上所述预定偏移（Vos）时，累积来自第一电流（I1）的电荷。在所述第一计数器（240）停止计数的期间，所述放电电路（260）以第二电流（I2）释放所累积的电荷。在电荷释放的期间，所述第二计数器（270）对所述时钟信号（CLK）的周期个数进行计数。所述模数转换电路（220）具备节电的功效。

Description

模数转换电路、图像传感器和模数转换方法 技术领域
本公开涉及模数转换技术，尤其涉及一种对于像素所产生的模拟信号进行模数转换的模数转换电路及其相关的图像传感器和模数转换方法。
背景技术
为了满足高分辨率和高速成像的需求，通常互补式金属氧化物半导体图像传感器(CMOS image sensor,CIS)使用了列并行模数转换结构(column-parallel ADC architecture)来对像素所产生的信号进行采集和转换。由于单斜模数转换器(single slope ADC)可以满足小尺寸的像素设计，列并行模数转换结构几乎由单斜模数转换器来实施。然而，随着图像分辨率进一步的增加，不仅单斜模数转换器的转换速度无法满足高速成像的需求，单斜模数转换器的计数器的耗电量也随之增加。
因此，需要一种创新的模数转换结构，其可同时满足高分辨率、高速成像、小尺寸像素设计以及低耗电的需求。
发明内容
本公开的目的之一在于提供一种对于像素所产生的模拟信号进行模数转换的模数转换电路及其相关的图像传感器和模数转换方法，来解决上述问题。
本公开的一实施例提供了一种模数转换电路。所述模数转换电路用于将模拟信号转换为数字信号。所述模数转换电路包括比较电 路、第一计数器、电荷累积电路、放电电路以及第二计数器。所述比较电路用以将所述模拟信号与斜坡信号作比较以产生第一比较信号，以及将所述模拟信号与所述斜坡信号加上预定偏移作比较以产生第二比较信号。所述第一计数器耦接于所述比较电路，用以在所述第一比较信号指示出所述模拟信号的信号电平大于所述斜坡信号的信号电平时，对时钟信号的周期个数进行计数以获得所述数字信号的第一部分。所述电荷累积电路耦接于所述比较电路，用以在所述第一比较信号指示出所述模拟信号的信号电平大于所述斜坡信号的信号电平，且所述第二比较信号指示出所述模拟信号的信号电平小于所述斜坡信号的信号电平加上所述预定偏移时，在所述电荷累积电路的电荷累积端累积来自第一电流的电荷。所述放电电路，耦接于所述电荷累积端，用以在所述第一计数器停止计数的期间，以第二电流对所述电荷累积端放电，其中所述第二电流小于所述第一电流。所述第二计数器耦接于所述电荷累积电路，用以在所述电荷累积端放电的期间，对所述时钟信号的周期个数进行计数以获得所述数字信号的第二部分。
本公开的一实施例提供了一种图像传感器。所述图像传感器包括像素阵列、控制电路以及至少一模数转换电路。所述像素阵列包括排列成多行与多列的多个像素。所述控制电路用以产生时钟信号以及斜坡信号。所述至少一模数转换电路耦接于所述像素阵列与所述控制电路，用以将所述像素阵列中一列像素所产生的模拟信号转换为数字信号。
本公开的一实施例提供了一种模数转换方法。所述模数转换方法包括以下步骤：将模拟信号与斜坡信号作比较以产生第一比较信号；将所述模拟信号与所述斜坡信号加上预定偏移作比较以产生第二比较信号；在所述第一比较信号指示出所述模拟信号的信号电平大于所述斜坡信号的信号电平时，对时钟信号的周期个数进行计数以获得第一计数值；在所述第一比较信号指示出所述模拟信号的信号电平大于所述斜坡信号的信号电平，且所述第二比较信号指示出所述模拟信号的信号电平小于所述斜坡信号的信号电平加上所述预 定偏移时，在电荷累积端累积来自第一电流的电荷；在所述电荷累积端停止累积来自所述第一电流的电荷的期间，以第二电流对所述电荷累积端放电，其中所述第二电流小于所述第一电流；以及在所述电荷累积端放电的期间，对所述时钟信号的周期个数进行计数以获得第二计数值，其中所述第一计数值和所述第二计数值分别作为数字信号的第一部分和第二部分。
附图说明
图1是本公开图像传感器的一实施例的功能方框示意图。
图2示出了图1所示的多个模数转换电路其中的至少一模数转换电路的一具体实施方式的示意图。
图3是图2所示的模数转换电路的一实施例的示意图。
图4是图3所示的模数转换电路所涉及的信号处理操作的一实施例的信号时序图。
图5是本公开模数转换方法的一实施例的流程图。
其中，附图标记说明如下：
100                              图像传感器
102                              像素阵列
110                              控制电路
120_1-120_K、220、320            模数转换电路
232、332                         第一比较器
234、334                         第二比较器
240、340                         第一计数器
250、350                         电荷累积电路
260、360                         放电电路
270、370                         第二计数器
352                               开关控制电路
354                               电荷累积单元
356                               比较器
502-512                           步骤
P 11-P MK                            像素
A11、A21                          与门
A31                               第一与门
A32                               第二与门
A33                               第三与门
A34                               第四与门
I1、I2                            反相器
DF11-DF19、DF21-DF23              D触发器
D                                 数据输入端
Q                                 数据输出端
Q'                                反相数据输出端
R                                 复位端
TCA                               电荷累积端
S1                                第一开关
S2                                第二开关
S3                                第三开关
S4                                第四开关
S5                                第五开关
S6                                第六开关
SD                                开关
CS1、CS2                          电流源
TI1                               第一输入端
TI2                               第二输入端
TO                                输出端
Nref                              参考节点
CLK                               时钟信号
VR                               斜坡信号
VA 1-VA K、VA                      模拟信号
Vos                              预定偏移
VD 1、VD                          数字信号
CP1                              第一比较信号
CP2                              第二比较信号
CV_C                             第一计数值
CV_F                             第二计数值
CP2b                             反相信号
CKD1                             第一输入时钟信号
CKD2                             第二输入时钟信号
EN                               始能信号
t1-t6                            时间点
rstb1                            第一复位信号
rstb2                            第二复位信号
V1、V2、Vr                       信号电平
qp                               第一开关控制信号
qn                               第二开关控制信号
q1g                              第三开关控制信号
qn1g                             第四开关控制信号
qp’                             第一反相控制信号
qn’                             第二反相控制信号
具体实施方式
在说明书及之前的权利要求书当中使用了某些词汇来指称特定的组件。本领域的技术人员应可理解，制造商可能会用不同的名词来称呼同样的组件。本说明书及之前的权利要求书并不以名称的差异来作为区分组件的方式，而是以组件在功能上的差异来作为区分的基准。在通篇说明书及之前的权利要求书当中所提及的“包含” 为一开放式的用语，故应解释成“包含但不限定于”。此外，“耦接”一词在此包含任何直接和间接的电连接手段。因此，若文中描述一第一装置耦接于一第二装置，则代表所述第一装置可直接电连接于所述第二装置，或通过其它装置或连接手段间接地电连接到所述第二装置。
图1是本公开图像传感器的一实施例的功能方框示意图。于此实施例中，图像传感器100可采用列并行模数转换结构来对传感信号进行模数转换操作，并可包含(但不限于)一像素阵列102、一控制电路110以及多个模数转换电路(标记为“ADC”)120_1-120_K，其中K是大于1的正整数。像素阵列102可包含排列成M行与K列的多个像素(或像素单元)P 11-P MK，其中M是大于1的正整数，各像素P 11-P MK可分别进行图像传感以产生一模拟信号(诸如一传感电压或一传感电流)。
控制电路110可产生一时钟信号CLK以及一斜坡信号(ramp signal)VR。模数转换电路120_1-120_K耦接于像素阵列102和控制电路110，各模数转换电路可依据时钟信号CLK及斜坡信号VR将各列像素P 11-P MK所产生的模拟信号(诸如多个模拟信号VA 1-VA K之中相对应的模拟信号)转换为一数字信号。以一列像素P 11-P M1为例，模数转换电路120_1可依据时钟信号CLK以及斜坡信号VR将模拟信号VA 1转换为一数字信号VD 1。
值得注意的是，虽然图1所示的各数模转换电路可直接接收各列像素所产生的模拟信号，然而，这只是方便说明而已，本公开并不以此为限。在某些实施例中，各列像素所产生的模拟信号可先通过相关的信号处理之后，再传送到相对应的数模转换电路。举例来说，可编程增益放大器(programmable gain amplifier，PGA)可设置于一列像素和相对应的数模转换电路之间，因此，所述列像素产生的模拟信号可先通过可编程增益放大器进行信号放大处理之后，再传送到相对应的数模转换电路。
在此实施例中，各模数转换电路可根据斜坡信号VR和相应的模 拟信号，在不同的计数阶段对时钟信号CLK的周期个数进行计数，以将相应的模拟信号转换为数字信号。以模数转换电路120_1为例，模数转换电路120_1首先可依据斜坡信号VR和模拟信号VA 1来对时钟信号CLK的周期个数进行第一计数操作。时钟信号CLK可由低频的时钟信号来实施，从而减少信号处理的功耗。也就是说，所述第一计数操作可视为粗计数操作(coarse counting)。当斜坡信号VR的信号电平即将到达模拟信号VA 1的信号电平时(例如，斜坡信号VR的信号电平与模拟信号VA 1的信号电平两者的差距位于一预定范围内)，除了根据进行所述第一计数操作，模数转换电路120_1还可累积来自第一电流I1的电荷。在停止所述第一计数操作之后，模数转换电路120_1可基于第二电流I2释放所累积的电荷，其中第二电流I2小于第一电流I1。
值得注意的是，模数转换电路120_1所累积的电荷可指示出停止所述第一计数操作之前计数值最后一次增加的时间点与停止所述第一计数操作的时间点，两者之间所累积的电荷。因此，可采用较小的电流(第二电流I2)来释放来自较大的电流所累积的电荷，并且在此期间对时钟信号CLK的周期个数进行计数，从而提高模数转换电路120_1的分辨率。
举例来说(但本公开不限于此)，第二电流I2可以是第一电流I1的八分之一，因此，以第二电流I2释放所累积的电荷所需的时间大致是以第一电流I1累积电荷所需的时间的八倍。因此，在以第二电流I2释放所累积的电荷的期间内对时钟信号CLK的周期个数进行计数，相当于在以第一电流I1累积电荷的期间内，对另一时钟信号(频率是时钟信号CLK的频率的八倍)的周期个数进行计数。也就是说，所述第二计数操作可视为精细计数操作(fine counting)。通过在释放所累积的电荷的期间内对时钟信号CLK的周期个数进行计数，模数转换电路120_1可以采用较低频率的时钟信号以实现高精度的数模转换操作。这样，图像传感器100可以在满足高分辨率和高速成像的需求下，大幅降低模数转换操作的功耗。
请连同图1来参阅图2。图2示出了图1所示的多个模数转换电路120_1-120_K其中的至少一模数转换电路的一具体实施方式的示意图。模数转换电路220可将一模拟信号VA(诸如多个模拟信号VA 1-VA K其中之一)转换为一数字信号VD，并可包含(但不限于)一比较电路230、一第一计数器240、一电荷累积电路250、一放电电路260以及一第二计数器270。比较电路230用以将模拟信号VA与斜坡信号VR作比较以产生一第一比较信号CP1，以及将模拟信号VA与数字信号VD加上一预定偏移Vos作比较以产生一第二比较信号CP2。也就是说，第一比较信号CP1可指示出“模拟信号VA”与“斜坡信号VR”两者之间信号电平的大小关系，第二比较信号CP2可指示出“模拟信号VA”与“斜坡信号VR加上预定偏移Vos”两者之间信号电平的大小关系。因此，在斜坡信号VR的信号电平逐渐增加以逼近模拟信号VA的信号电平的过程中，相比于第一比较信号CP1，第二比较信号CP2的信号电平会先翻转(toggle)，指示出信号大小关系的改变。
举例来说(但本公开不限于此)，比较电路230可包括(但不限于)一第一比较器232和一第二比较器234。第一比较器232用以接收模拟信号VA和斜坡信号VR，并将模拟信号VA与斜坡信号VR作比较以产生第一比较信号CP1。第二比较器234则是将模拟信号VA与斜坡信号VR加上预定偏移Vos作比较，据以产生第二比较信号CP2。预定偏移Vos可以是(但不限于)第二比较器234内部固有的比较器偏移(comparator offset)。也就是说，与第一比较器232相似，第二比较器234也可接收模拟信号VA与斜坡信号VR。由于第二比较器234具有比较器偏移，因此，第二比较器234所进行的比较操作可视为对模拟信号VA与斜坡信号VR加上预定偏移Vos进行比较。预定偏移Vos的偏移量可依设计需求来调整。
值得注意的是，在某些实施例中，第一比较器232和第二比较器234可合并成具有两个输出端的单一比较电路。在某些实施例中，第二比较器234可并入第一比较器232中。也就是说，比较电路230相关的设计变化，均包含在本公开的保护范围内。
第一计数器240耦接于比较电路230，用以依据第一比较信号CP1来控制时钟信号CLK的周期个数的计数操作。例如，在第一比较信号CP1指示出模拟信号VA的信号电平大于斜坡信号VR的信号电平时，第一计数器240可对时钟信号CLK的周期个数进行计数以获得数字信号VD的第一部分(即第一计数值CV_C)。
在某些实施例中，第一计数器240可在适当的时机才启动时钟信号CLK的周期个数的计数操作，以降低功耗。例如，在斜坡信号VR产生之前，控制电路110不允许第一计数器240启动计数操作；当斜坡信号VR产生时，第一计数器240的计数操作才会启动。
电荷累积电路250耦接于比较电路230，用以在第一比较信号CP1指示出模拟信号VA的信号电平大于斜坡信号VR的信号电平，且第二比较信号CP2指示出模拟信号VA的信号电平小于斜坡信号VR的信号电平加上预定偏移Vos时，在电荷累积电路250的一电荷累积端TCA累积来自第一电流I1的电荷。电荷累积端TCA所累积的电荷可指示出第一计数器240停止计数之前第一计数值CV_C最后一次增加的时间点，与第一计数器240停止计数的时间点两者之间所累积的电荷。
在某些实施例中，电荷累积电路250可在第一计数值CV_C增加时，开始在电荷累积端TCA累积来自第一电流I1的电荷。例如，在模拟信号VA的信号电平大于斜坡信号VR的信号电平，而小于斜坡信号VR的信号电平加上预定偏移Vos的期间，当时钟信号CLK处于预定信号沿(上升沿或下降沿)时，电荷累积电路250可开始在电荷累积端TCA累积来自第一电流I1的电荷。
在某些实施例中，电荷累积电路250可对电荷累积端TCA进行一次或多次的电荷累积操作，其中当第一计数值CV_C增加时，电荷累积电路250可复位电荷累积端TCA，并重新在电荷累积端TCA累积来自第一电流I1的电荷。例如，在模拟信号VA的信号电平与斜坡信号VR的信号电平之间的差距小于预定偏移Vos的期间内，每当第一计数值CV_C增加时，电荷累积电路250可复位电荷累积端TCA， 并重新在电荷累积端TCA累积来自第一电流I1的电荷。
此外，在某些实施例中，当第一比较信号CP1指示出模拟信号VA的信号电平小于斜坡信号VR的信号电平时，电荷累积电路250可停止在电荷累积端TCA累积来自第一电流I1的电荷。
放电电路260耦接于电荷累积端TCA，用以在第一计数器240停止计数的期间，以第二电流I2对电荷累积端TCA放电。举例来说，在第一比较信号CP1指示出模拟信号VA的信号电平小于斜坡信号VR的信号电平时，第一计数器240可停止对时钟信号CLK的周期个数进行计数。放电电路260可在模拟信号VA的信号电平小于斜坡信号VR的信号电平时，以第二电流I2对电荷累积端TCA放电。
第二计数器270耦接于电荷累积电路250，用以在电荷累积端TCA放电的期间，对时钟信号CLK的周期个数进行计数以获得数字信号VD的第二部分(即第二计数值CV_F)。值得注意的是，第二电流I2小于第一电流I1。因此，在电荷累积端TCA放电的期间对时钟信号CLK的周期个数进行的计数操作，相当于在电荷累积端TCA累积来自第一电流I1的电荷的期间内，对另一时钟信号(频率大于时钟信号CLK的频率)的周期个数进行计数。也就是说，第一计数器240可视为粗计数器(coarse counter)，而第二计数器270可视为精细计数器(fine counter)，其中在电荷累积端TCA累积的电荷可对应于第一计数值CV_C相邻两个数值之间的数值刻度。
值得注意的是，虽然以上是以列并行模数转换结构来说明本发明所公开的数模转换电路，然而，本发明并不以此为限。举例来说，图1所示的K列像素也可以通过一开关电路共享单一数模转换电路，其中所述单一数模转换电路可由图2所示的数模转换电路220来实施。
为了便于理解本发明的技术特征，以下采用一示范性电路结构来说明本发明所公开的模数转换的细节。然而，这只是方便说明而已。任何采用基于图2所示的电路结构的实施方式均是可行的。请参阅图3，其为图2所示的模数转换电路220的一实施例的示意图。 模数转换电路320可包含一第一比较器332、一第二比较器334(具有预定偏移Vos)、一第一计数器340、一电荷累积电路350、一放电电路360以及一第二计数器370，其中图2所示的第一比较器232、第二比较器234、第一计数器242、电荷累积电路250、放电电路260以及第二计数器270可分别由第一比较器332、第二比较器334、第一计数器340、电荷累积电路350、放电电路360以及第二计数器370来实施。
第一计数器340可包括(但不限于)一与门A11和Y个触发器(Y是大于1的正整数)。于此实施例中，所述Y个触发器可由9个D触发器(D flip-flop)DF11-DF19来实施，其中与门A11可在两个输入端分别接收时钟信号CLK和第一比较信号CP1，以于与门A11的输出端产生一第一输入时钟信号CKD1。多个D触发器DF11-DF19依次级联(即，D触发器DF11-DF18各自的数据输出端Q分别耦接到D触发器DF12-DF19的时钟输入端)；并且，D触发器DF11耦接到与门A11的输出端(即，D触发器DF11的时钟输入端耦接到第一输入时钟信号CKD1)，其中各D触发器DF11-DF19的数据输入端D与反相数据输出端Q'彼此连接，且各D触发器DF11-DF19的复位端R可耦接到一控制电路(诸如图1所示的控制电路110；未绘示)，用以接收所述控制电路所产生的一第一复位信号rstb1。多个D触发器DF11-DF19可用来计数第一输入时钟信号CKD1的周期个数以产生第一计数值CV_C(包含各触发器DF11-DF19的数据输出端Q的输出)，作为模拟信号VA相对应的一数字信号(诸如图2所示的数字信号VD)的第一部分。
电荷累积电路350可包括(但不限于)一开关控制电路352及一电荷累积单元354。开关控制电路352可包括(但不限于)多个第一与门A31、第二与门A32、第三与门A33、第四与门A34以及多个反相器I1和I2。第一与门A31的两个输入端可分别接收D触发器DF11的数据输出q1和第二比较信号CP2的一反相信号CP2b，以于第一与门A31的输出端产生一第一开关控制信号qp。例如，模数转换电路320可进一步包含一反相器(未绘示)，用来反相第二比较 信号CP2以产生反相信号CP2b。第二与门A32的两个输入端可分别接收D触发器DF11的反相数据输出q1n和反相信号CP2b，以于第二与门A32的输出端产生一第二开关控制信号qn。第三与门A33的两个输入端可分别接收第一比较信号CP1和第一开关控制信号qp，以于第三与门A33的输出端产生一第三开关控制信号q1g。第四与门A34的两个输入端可分别接收第一比较信号CP1和第二开关控制信号qn，以于第四与门A34的输出端产生一第四开关控制信号qn1g。此外，反相器I1用以反相第一开关控制信号qp以产生一第一反相控制信号qp’。反相器I2用以反相第二开关控制信号qn以产生一第二反相控制信号qn’。
电荷累积单元354可包括(但不限于)一第一储存端TO1、一第二储存端TO2、一第一电容C1、一第二电容C2以及一电流源CS1。第一储存端TO1选择性地耦接于电荷累积端TCA，以及第二储存端TO2选择性地耦接于电荷累积端TCA。第一电容C1耦接于第一储存端TO1与一参考节点Nref之间，以及第二电容C2耦接于第二储存端TO2与参考节点Nref之间。电流源CS1通过第一储存端TO1耦接到第一电容C1，以及通过第二储存端TO2耦接到第二电容C2。电流源CS1用以提供第一电流I1，并可在时钟信号CLK的不同周期以第一电流I1交替地对第一电容C1与第二电容C2充电，以轮流在第一储存端TO1与第二储存端TO2累积来自第一电流I1的电荷。当电流源CS1对第一电容C1充电时，第一储存端TO1耦接于电荷累积端TCA；当电流源CS1对第二电容C2充电时，第二储存端TO2耦接于电荷累积端TCA。也就是说，在时钟信号CLK的某一个周期中，电流源CS1可采用第一电流I1对第一电容C1与第二电容C2其中的一个进行充电，以在相应的储存端累积来自第一电流I1的电荷；在时钟信号CLK的下一个周期中，电流源CS1可采用第一电流I1对第一电容C1与第二电容C2其中的另一个进行充电，以在相应的另一个储存端累积来自第一电流I1的电荷。
此外，在此实施例中，当电流源CS1对第一电容C1充电时，第二储存端TO2可被复位；当电流源CS1对第二电容C2充电时，第一 储存端TO1可被复位。这样，电流源CS1可在时钟信号CLK的不同周期重新对第一电容C1/第二电容C2充电。
举例来说(但本公开不限于此)，电荷累积单元354还可包括一第一开关S1、一第二开关S2、一第三开关S3以及一第四开关S4。第一开关S1由第一反相控制信号qp’所控制，用以选择性地耦接于第一储存端TO1与参考节点Nref之间。第二开关S2由第二反相控制信号qn’所控制，用以选择性地耦接于第二储存端TO2与参考节点Nref之间。第三开关S3由第一开关控制信号qp所控制，用以选择性地耦接于第一储存端TO1与电荷累积端TCA之间。第四开关S4由第二开关控制信号qn所控制，用以选择性地耦接于第二储存端TO2与电荷累积端TCA之间。当电流源CS1对第一电容C1充电时，第一开关S1和第四开关S4会关闭，以及第二开关S2和第三开关S3会开启；当电流源CS1对第二电容C2充电时，第一开关S1和第四开关S4会开启，以及第二开关S2和第三开关S3会关闭。因此，当电流源CS1对第一电容C1充电时，第一储存端TO1可耦接于电荷累积端TCA，而第二储存端TO2可被复位。相似地，当电流源CS1对第二电容C2充电时，第二储存端TO2可耦接于电荷累积端TCA，而第一储存端TO1可被复位
在此实施例中，电荷累积单元354还可包括一第五开关S5、一第六开关S6以及一比较器356。第五开关S5由第三开关控制信号q1g所控制，用以选择性地耦接于电流源CS1与第一储存端TO1之间。第六开关S6由第四开关控制信号qn1g所控制，用以选择性地耦接于电流源CS1与第二储存端TO2之间。比较器356具有第一输入端TI1、第二输入端TI2及输出端TO，其中第一输入端TI1耦接于电荷累积端TCA，第二输入端TI2耦接于参考节点Nref，以及输出端TO耦接于第二计数器370。当第一输入端TI1的信号电平大于第二输入端TI2的信号电平时，比较器356可从输出端TO输出一使能信号EN以启用第二计数器370。
放电电路360用以基于第二电流I2对电荷累积端TCA放电，并 可包括(但不限于)一电流源CS2及一开关SD。电流源CS2用以接收第二电流I2。开关SD选择性耦接于电荷累积端TCA与电流源CS2之间，其中在电荷累积电路350停止累积来自第一电流I1的电荷的期间，开关SD可耦接于电荷累积端TCA与电流源CS2之间，使第二电流I2从电荷累积端TCA灌入电流源CS2。也就是说，在电荷累积电路350停止累积来自第一电流I1的电荷的期间，电荷累积端TCA累积的电荷可释放至电流源CS2。
第二计数器370可包含(但不限于)一与门A21和P个触发器(P是大于1的正整数)。于此实施例中，所述P个触发器可由3个D触发器(D flip-flop)DF21-DF23来实施，其中与门A21可在两个输入端分别接收时钟信号CLK和使能信号EN，以于与门A21的输出端产生一第二输入时钟信号CKD2。多个D触发器DF21-DF23依次级联(即，D触发器DF21和DF22各自的数据输出端Q分别耦接到D触发器DF22和DF23的时钟输入端)；并且，D触发器DF21耦接到与门A21的输出端(即，D触发器DF21的时钟输入端耦接到第二输入时钟信号CKD2)，其中各D触发器DF21-DF23的数据输入端D与反相数据输出端Q'彼此连接，且各D触发器DF21-DF23的复位端R可耦接到一控制电路(诸如图1所示的控制电路110；未绘示)，用以接收所述控制电路所产生的一第二复位信号rstb2。多个D触发器DF21-DF23可用来计数第二输入时钟信号CKD2的周期个数以产生第二计数值CV_F(包含各触发器DF21-DF23的数据输出端Q的输出)，作为模拟信号VA相对应的一数字信号(诸如图2所示的数字信号VD)的第二部分。
请一并参阅图3和图4。图4是图3所示的模数转换电路320所涉及的信号处理操作的一实施例的信号时序图。为了方便说明，于此实施例中，第二电流I2的电流大小可以是第一电流I1的八分之一。然而，本发明并不以此为限。在时间点t1之前，模拟信号VA的信号电平大于斜坡信号VR的信号电平，因此，第一计数器340可对第一输入时钟信号CKD1的周期个数进行计数。此外，在时间点t1之前，模拟信号VA的信号电平大于斜坡信号VR的信号电平加上 预定偏移Vos，因此，电荷累积电路350的电荷累积操作可不被启动。
在时间点t1，模拟信号VA的信号电平仍大于斜坡信号VR的信号电平，然而，模拟信号VA的信号电平小于斜坡信号VR的信号电平加上预定偏移Vos。因此，第二比较信号CP2的信号电平翻转，电荷累积电路350可开始在电荷累积端TCA累积来自第一电流I1的电荷。
在时间点t2，第一计数器340的第一计数值CV_C由N增加为N+1时，电荷累积电路350可复位电荷累积端TCA，并重新在电荷累积端TCA累积来自第一电流I1的电荷。例如，第一开关S1会开启，第五开关S5会关闭，使第一储存端TO1(具有信号电平V1)被复位。第二开关S2会关闭，第六开关S6会开启，使电流源CS1可对第二电容C2充电，以在第二储存端TO2(具有信号电平V2)累积来自第一电流I1的电荷。此外，第三开关S3会关闭，第四开关S4会开启，使第二储存端TO2耦接到电荷累积端TCA。
在时间点t3，当第一计数器340的第一计数值CV_C再次增加时(由N+1增加为N+2)，电荷累积电路350可再次复位电荷累积端TCA，并重新在电荷累积端TCA累积来自第一电流I1的电荷。例如，第二开关S2会开启，第六开关S6会关闭，使第二储存端TO2被复位。第一开关S1会关闭，第五开关S5会开启，使电流源CS1可对第一电容C1充电，以在第一储存端TO1累积来自第一电流I1的电荷。此外，第三开关S3会开启，第四开关S4会关闭，使第一储存端TO1耦接到电荷累积端TCA。
在时间点t4，模拟信号VA的信号电平小于斜坡信号VR的信号电平，使得第一比较信号CP1的信号电平翻转。因此，第一计数器340可停止相关的计数操作，且电荷累积电路350可停止相关的电荷累积操作。
在第一计数器340停止计数的期间，放电电路360可基于第二电流I2对电荷累积端TCA放电。第二计数器370可在电荷累积端 TCA放电的期间，对时钟信号CLK的周期个数进行计数以获得数字信号VD的第二部分。例如，在电荷累积电路350停止累积来自第一电流I1的电荷之后(时间点t4之后)，当时钟信号CLK第一次出现预定信号沿时，第二计数器370可开始对时钟信号CLK的周期个数进行计数。
在此实施例中，在时间点t5(时钟信号CLK在时间点t4之后第一次的上升沿)，放电电路360的开关SD可根据第二复位信号rstb2将电荷累积端TCA耦接到电流源CS2，以释放电荷累积端TCA所累积的电荷(即，第一电容C1/第一储存端TO1在时间点t4与时间点t5之间所累积的电荷)。第二计数器370可根据第二复位信号rstb2复位第二计数值CV_F，并对时钟信号CLK的周期个数进行计数，以更新第二计数值CV_F。
在时间点t6，当比较器356的第一输入端TI1的信号电平小于第一输入端TI2的信号电平(即参考节点Vref具有的信号电平Vr)时，输出端TO所输出使能信号EN会处于低信号电平，第二计数器370可停止计数操作。第一计数值CV_C(N+2)及第二计数值CV_F(3)分别可作为数字信号VD的一部分。
通过本公开的数模转换机制，采用较低频率的时钟信号即可实现同时具备低功耗与高帧率的图像传感器。举例来说(但本公开不限于此)，在每2.5μs获得一个帧的图像传感器中，若采用12比特的数模转换电路，现有技术需要的时钟信号频率大约是2GHz(2 12/2.5μs＝1.638GHz)的时钟信号来处理，以满足计数值中最低有效位(least significant bit，LSB)的比特值变动的频率。然而，在将图3所示的数模转换电路320应用至每2.5μs获得一个帧的图像传感器的某些实施例中，采用较低频率的时钟信号CLK即可满足图像传感器的设计需求。例如，可将时钟信号CLK的频率设为2GHz的八分之一(250MHz)。也就是说，时钟信号CLK的周期时间是4ns。此外，第二电流I2的大小可设为第一电流I1的大小的八分之一。采用第二电流I2进行放电所需的时间最多是32ns(即8 ×4ns)。因此，数模转换电路3205整体的转换时间是2080ns(即2 9×4ns+8×4ns)。也就是说，即使采用较低频率的时钟信号，数模转换电路320仍可在2.5μs内获得一个帧，从而满足高帧率的设计需求。
请注意，以上仅供说明的目的，并非用来作为本发明的限制。在某些设计变化例中，预定偏移Vos可以是第二比较器334外部的信号源所提供。例如，模数转换电路320可包含一信号源，所述信号源可产生预定偏移Vos，并将预定偏移Vos传送到第二比较器334的负输入端。又例如，图1所示的控制电路110可产生不同于斜坡信号VR的另一斜坡信号，其中所述另一斜坡信号的信号电平等于斜坡信号VR的信号电平加上预定偏移Vos，而第二比较器334可接收于负输入端接收所述另一斜坡信号。又例如，所述另一斜坡信号可以是斜坡信号VR的超前副本(advanced replica)，其中斜坡信号VR的超前副本与斜坡信号VR之间具有预定相位偏移，使斜坡信号VR的超前副本的信号电平等于斜坡信号VR的信号电平加上预定偏移Vos。
在某些设计变化例中，第一计数器340和/或第二计数器370可采用不同的电路结构。举例来说，第一计数器340所包含的触发器个数和/或种类可以依照设计需求来决定，和/或第二计数器370所包含的触发器个数和/或种类可以依照设计需求来决定。
在某些设计变化例中，电荷累积电路350可采用不同的电路结构以在电荷累积端TCA累积来自第一电流I1的电荷。举例来说，电荷累积电路350可采用三个以上的电容来累积电荷。只要可在计数操作(即粗计数操作)停止之前于电荷累积端累积来自第一电流的电荷，并且在所述计数操作停止之后以较小的第二电流释放，同时对时钟信号的周期个数进行计数以实现精细计数的模数转换电路，设计上相关的变化均遵循本发明的精神而落入本发明的范畴。
本发明所公开的模数转换机制可简单归纳为图5所示的流程图。图5是本发明模数转换方法的一实施例的流程图。假若所得到 的结果实质上大致相同，则步骤不一定要按照图5所示的顺序来进行。举例来说，某些步骤可安插于其中。为了方便说明，以下搭配图3所示的模数转换电路320来说明来说明图5所示的模数转换方法。然而，将图5所示的模数转换方法应用于图2所示的模数转换电路220和/或图1所示的各模数转换电路也是可行的。图5所示的模数转换方法可简单归纳如下。
步骤502：将一模拟信号与一斜坡信号作比较以产生一第一比较信号。例如，第一比较器332将模拟信号VA与斜坡信号VR作比较以产生第一比较信号CP1。
步骤504：将所述模拟信号与所述斜坡信号加上一预定偏移作比较以产生一第二比较信号。例如，第二比较器334将模拟信号VA与斜坡信号VR加上预定偏移Vos作比较以产生第二比较信号CP2。
步骤506：在所述第一比较信号指示出所述模拟信号的信号电平大于所述斜坡信号的信号电平时，对时钟信号的周期个数进行计数以获得第一计数值。例如，在第一比较信号CP1指示出模拟信号VA的信号电平大于斜坡信号VR的信号电平时(如图4所示的时间点t4之前)，第一计数器340可对时钟信号CLK的周期个数进行计数以获得第一计数值CV_C。
步骤508：在所述第一比较信号指示出所述模拟信号的信号电平大于所述斜坡信号的信号电平，且所述第二比较信号指示出所述模拟信号的信号电平小于所述斜坡信号的信号电平加上所述预定偏移时，在电荷累积端累积来自第一电流的电荷。例如，在第一比较信号CP1指示出模拟信号VA的信号电平大于斜坡信号VR的信号电平时，且第二比较信号CP2指示出模拟信号VA的信号电平小于斜坡信号VR的信号电平加上预定偏移Vos时(如图4所示的时间点t1与时间点t4之间)， 电荷累积电路350可在电荷累积端TCA累积来自第一电流I1的电荷。
步骤510：在所述电荷累积端停止累积来自所述第一电流的电荷的期间，以第二电流对所述电荷累积端放电，其中所述第二电流小于所述第一电流。例如，在电荷累积端TCA停止累积来自第一电流I1的电荷的期间，放电电路350可基于第二电流I2对电荷累积端TCA放电(如图4所示的时间点t5)，其中第二电流I2小于第一电流I1。
步骤512：在所述电荷累积端放电的期间，对所述时钟信号的周期个数进行计数以获得第二计数值，其中所述第一计数值和所述第二计数值分别作为数字信号的第一部分和第二部分。例如，在电荷累积端TCA放电的期间，对时钟信号CLK的周期个数进行计数以获得第二计数值CV_F(如图4所示的时间点t5与时间点t6之间)。第一计数值CV_C和第二计数值CV_F分别作为数字信号VD的第一部分和第二部分。
于步骤508中，当所述第一计数值增加时，可复位所述电荷累积端，并重新在所述电荷累积端累积来自所述第一电流的电荷。例如，电荷累积电路350可在第一计数值CV_C增加时(例如图4所示的时间点t2/t3)，复位电荷累积端TCA，并重新在电荷累积端TCA累积来自第一电流I1的电荷。
于步骤512中，在所述电荷累积端停止累积来自所述第一电流的电荷之后，当所述时钟信号第一次出现预定信号沿时，可开始对所述时钟信号的周期个数进行计数。例如，在电荷累积电路350停止在电荷累积端TCA累积来自第一电流I1的电荷之后，当时钟信号CLK第一次出现预定信号沿时(例如上升沿；图4所示的时间点t5)，可开始对时钟信号CLK的周期个数进行计数。
由于本领域的技术人员通过阅读图1到图4相关的段落说明之 后，应可了解图5所示的模数转换方法中每一步骤的细节，因此进一步的说明在此便不再赘述。
由上可知，本公开所提供的模数转换机制可无需增加斜坡信号产生电路的数量，且可采用低频率的时钟信号，即可实现粗计数操作和精细计数操作，从而有效降低功耗，达到节电的功效。
以上所述仅为本公开的实施例而已，并不用于限制本公开，对于本领域的技术人员来说，本公开可以有各种更改和变化。凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (20)

  1. 一种模数转换电路，用于将模拟信号转换为数字信号，其特征在于，包括：
    比较电路，用以将所述模拟信号与斜坡信号作比较以产生第一比较信号，以及将所述模拟信号与所述斜坡信号加上预定偏移作比较以产生第二比较信号；
    第一计数器，耦接于所述比较电路，用以在所述第一比较信号指示出所述模拟信号的信号电平大于所述斜坡信号的信号电平时，对时钟信号的周期个数进行计数以获得所述数字信号的第一部分；
    电荷累积电路，耦接于所述比较电路，用以在所述第一比较信号指示出所述模拟信号的信号电平大于所述斜坡信号的信号电平，且所述第二比较信号指示出所述模拟信号的信号电平小于所述斜坡信号的信号电平加上所述预定偏移时，在所述电荷累积电路的电荷累积端累积来自第一电流的电荷；
    放电电路，耦接于所述电荷累积端，用以在所述第一计数器停止计数的期间，以第二电流对所述电荷累积端放电，其中所述第二电流小于所述第一电流；以及
    第二计数器，耦接于所述电荷累积电路，用以在所述电荷累积端放电的期间，对所述时钟信号的周期个数进行计数以获得所述数字信号的第二部分。
  2. 如权利要求1所述的模数转换电路，其特征在于，在所述第一比较信号指示出所述模拟信号的信号电平小于所述斜坡信号的信号电平时，所述第一计数器停止对所述时钟信号的周期个数进行计数。
  3. 如权利要求1所述的模数转换电路，其特征在于，当所述第一比 较信号指示出所述模拟信号的信号电平小于所述斜坡信号的信号电平时，所述电荷累积电路停止在所述电荷累积端累积来自所述第一电流的电荷。
  4. 如权利要求1所述的模数转换电路，其特征在于，当所述第一计数器的计数值增加时，所述电荷储存电路会复位所述电荷累积端，并重新在所述电荷累积端累积来自所述第一电流的电荷。
  5. 如权利要求1所述的模数转换电路，其特征在于，所述电荷累积电路包括：
    第一储存端，选择性地耦接于所述电荷累积端；
    第二储存端，选择性地耦接于所述电荷累积端；
    第一电容，耦接于所述第一储存端与参考节点之间；
    第二电容，耦接于所述第二储存端与所述参考节点之间，
    电流源，通过所述第一储存端耦接到所述第一电容，以及通过所述第二储存端耦接到所述第二电容，所述第一电流源用以提供所述第一电流，并在所述时钟信号的不同周期以所述第一电流交替地对所述第一电容与所述第二电容充电，以轮流在所述第一储存端与所述第二储存端累积来自所述第一电流的电荷，其中当所述第一电流源对所述第一电容充电时，所述第一储存端耦接于所述电荷累积端；当所述第一电流源对所述第二电容充电时，所述第二储存端耦接于所述电荷累积端。
  6. 如权利要求5所述的模数转换电路，其特征在于，其中当所述电流源对所述第一电容充电时，所述第二储存端会被复位；当所述电流源对所述第二电容充电时，所述第一储存端会被复位。
  7. 如权利要求5所述的模数转换电路，其特征在于，还包括：
    第一开关，选择性地耦接于所述第一储存端与所述参考节点之间；
    第二开关，选择性地耦接于所述第二储存端与所述参考节点之间；
    第三开关，选择性地耦接于所述第一储存端与所述电荷累积端之间；以及
    第四开关，选择性地耦接于所述第二储存端与所述电荷累积端之间；
    其中当所述电流源对所述第一电容充电时，所述第一开关和所述第四开关会关闭，以及所述第二开关和所述第三开关会开启；
    当所述电流源对所述第二电容充电时，所述第一开关和所述第四开关会开启，以及所述第二开关和所述第三开关会关闭。
  8. 如权利要求5所述的模数转换电路，其特征在于，所述电荷累积电路还包括：
    比较器，具有第一输入端、第二输入端及输出端，其中所述第一输入端耦接于所述电荷累积端，所述第二输入端耦接于所述参考节点，以及所述输出端耦接于所述第二计数器。
  9. 如权利要求8所述的模数转换电路，其特征在于，其中当所述第一输入端的信号电平大于所述第二输入端的信号电平时，所述比较器从所述输出端输出使能信号以启用所述第二计数器。
  10. 如权利要求1所述的模数转换电路，其特征在于，其中在所述 电荷累积电路停止累积来自所述第一电流的电荷之后，当所述时钟信号第一次出现预定信号沿时，所述第二计数器开始对所述时钟信号的周期个数进行计数。
  11. 如权利要求1所述的模数转换电路，其特征在于，所述放电电路包括：
    电流源，用以接收所述第二电流；以及
    开关，选择性耦接于所述电荷累积端与所述电流源之间，其中在所述电荷累积电路停止累积来自所述第一电流的电荷的期间，所述开关耦接于所述电荷累积端与所述电流源之间，使所述第二电流从所述电荷累积端灌入所述电流源。
  12. 如权利要求1所述的模数转换电路，其特征在于，所述比较电路包括：
    第一比较器，用以接收所述模拟信号与所述第一斜坡信号，以将所述模拟信号与所述斜坡信号作比较；以及
    第二比较器，其中所述预定偏移是所述第二比较器固有的比较器偏移，所述第二比较器用以接收所述模拟信号与所述第一斜坡信号，以将所述模拟信号与所述斜坡信号加上所述预定偏移作比较。
  13. 一种图像传感器，其特征在于，包括：
    像素阵列，包括排列成多行与多列的多个像素；
    控制电路，用以产生时钟信号以及斜坡信号；以及
    至少一如权利要求1至12中任一项所述的模数转换电路，耦接于所述像素阵列与所述控制电路，用以将所述像素阵列中一 列像素所产生的模拟信号转换为数字信号。
  14. 一种模数转换方法，其特征在于，包括：
    将模拟信号与斜坡信号作比较以产生第一比较信号；
    将所述模拟信号与所述斜坡信号加上预定偏移作比较以产生第二比较信号；
    在所述第一比较信号指示出所述模拟信号的信号电平大于所述斜坡信号的信号电平时，对时钟信号的周期个数进行计数以获得第一计数值；
    在所述第一比较信号指示出所述模拟信号的信号电平大于所述斜坡信号的信号电平，且所述第二比较信号指示出所述模拟信号的信号电平小于所述斜坡信号的信号电平加上所述预定偏移时，在电荷累积端累积来自第一电流的电荷；
    在所述电荷累积端停止累积来自所述第一电流的电荷的期间，以第二电流对所述电荷累积端放电，其中所述第二电流小于所述第一电流；以及
    在所述电荷累积端放电的期间，对所述时钟信号的周期个数进行计数以获得第二计数值，其中所述第一计数值和所述第二计数值分别作为数字信号的第一部分和第二部分。
  15. 如权利要求14所述的模数转换方法，其特征在于，还包括：
    在所述第一比较信号指示出所述模拟信号的信号电平小于所述斜坡信号的信号电平时，停止在所述电荷累积端累积来自所述第一电流的电荷。
  16. 如权利要求14所述的模数转换方法，其特征在于，还包括：
    当所述第一比较信号指示出所述模拟信号的信号电平小于所述斜坡信号的信号电平时，停止对所述时钟信号的周期个数进行计数。
  17. 如权利要求14所述的模数转换方法，其特征在于，在电荷累积端累积来自第一电流的电荷的步骤包括：
    当所述第一计数值增加时，复位所述电荷累积端，并重新在所述电荷累积端累积来自所述第一电流的电荷。
  18. 如权利要求14所述的模数转换方法，其特征在于，在所述电荷累积端累积来自所述第一电流的电荷的步骤包括：
    在所述时钟信号的不同周期以所述第一电流交替地对第一电容与第二电容充电，以轮流在第一储存端与第二储存端累积来自所述第一电流的电荷，其中所述第一电容耦接于所述第一储存端与参考节点之间，所述第二电容耦接于所述第二储存端与所述参考节点之间；
    当所述第一电容被充电时，将所述第一储存端耦接到所述电荷累积端；以及
    当所述第二电容被充电时，将所述第二储存端耦接到所述电荷累积端。
  19. 如权利要求18所述的模数转换方法，其特征在于，在所述电荷累积端累积来自所述第一电流的电荷的步骤还包括：
    当所述第一电容被充电时，复位所述第二储存端；以及
    当所述第二电容被充电时，复位所述第一储存端。
  20. 如权利要求14所述的模数转换方法，其特征在于，对所述时钟信号的周期个数进行计数以获得所述第二计数值的步骤包括：
    在所述电荷累积端停止累积来自所述第一电流的电荷之后，当所述时钟信号第一次出现预定信号沿时，开始对所述时钟信号的周期个数进行计数。
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