WO2020121508A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2020121508A1
WO2020121508A1 PCT/JP2018/046035 JP2018046035W WO2020121508A1 WO 2020121508 A1 WO2020121508 A1 WO 2020121508A1 JP 2018046035 W JP2018046035 W JP 2018046035W WO 2020121508 A1 WO2020121508 A1 WO 2020121508A1
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WO
WIPO (PCT)
Prior art keywords
region
trench
semiconductor substrate
semiconductor device
semiconductor
Prior art date
Application number
PCT/JP2018/046035
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English (en)
French (fr)
Japanese (ja)
Inventor
嘉寿子 小川
Original Assignee
サンケン電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by サンケン電気株式会社 filed Critical サンケン電気株式会社
Priority to JP2020559662A priority Critical patent/JP7201005B2/ja
Priority to CN201880098705.8A priority patent/CN112913030B/zh
Priority to KR1020217011061A priority patent/KR102472577B1/ko
Priority to PCT/JP2018/046035 priority patent/WO2020121508A1/ja
Publication of WO2020121508A1 publication Critical patent/WO2020121508A1/ja

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the present invention relates to a semiconductor device in which a structure for improving breakdown voltage is formed.
  • a structure for improving the breakdown voltage is formed in the peripheral region around the element region where the semiconductor element is formed.
  • the withstand voltage of a semiconductor device is improved by arranging a trench in which an electrode is embedded inside a groove having an insulating film formed on an inner wall surface in a peripheral region to reduce concentration of an electric field (Patent Document 1). See 1.).
  • a plurality of trenches each having a conductor film arranged inside the groove are multiply arranged in the peripheral region surrounding the periphery of the element region, and the width of the semiconductor substrate sandwiched between adjacent trenches is Provided is a semiconductor device in which the inner region close to the element region is wider than the outer region located around the inner region.
  • FIG. 9 is a schematic cross-sectional view showing another configuration of the trench of the semiconductor device according to the modified example of the first embodiment of the present invention. It is a typical sectional view showing composition of a semiconductor device concerning a 2nd embodiment of the present invention.
  • the semiconductor device As shown in FIG. 1, the semiconductor device according to the first exemplary embodiment of the present invention includes a semiconductor substrate 10 in which an element region 110 and a peripheral region 120 surrounding the element region 110 are defined on the upper surface.
  • the semiconductor substrate 10 has a configuration in which a second conductive type second semiconductor layer 12 is stacked on a first conductive type first semiconductor layer 11.
  • a protective film 30 is formed on the upper surface of the semiconductor substrate 10.
  • the first conductivity type and the second conductivity type are opposite conductivity types. That is, if the first conductivity type is n-type, the second conductivity type is p-type, and if the first conductivity type is p-type, the second conductivity type is n-type.
  • the first conductivity type is n-type and the second conductivity type is p-type will be described. That is, the first semiconductor layer 11 of the semiconductor substrate 10 is n-type and the second semiconductor layer 12 is p-type.
  • a plurality of trenches 20 surrounding the element region 110 are arranged in multiple and spaced from each other. That is, in plan view, the plurality of annular trenches 20 are arranged around the element region 110.
  • the trench 20 has an insulating film 21 arranged on the inner wall surface of the groove extending from the upper surface of the semiconductor substrate 10 in the film thickness direction, and a conductor film 22 arranged on the insulating film 21 inside the groove.
  • the trench of the trench 20 extends from the upper surface of the second semiconductor layer 12 and reaches the first semiconductor layer 11.
  • the conductor film 22 and the semiconductor substrate 10 face each other with the insulating film 21 in between, and the bottom portion of the insulating film 21 includes the first semiconductor layer 11 and the second semiconductor layer 12 that are in contact with the side surface of the groove. It is located below the joint.
  • the conductor film 22 arranged inside the trench 20 is in an electrically floating state.
  • the second semiconductor layer 12 in the element region 110 is electrically connected to the surface electrode (not shown) of the semiconductor device.
  • the second semiconductor layer 12 in the peripheral region 120 is in an electrically floating state.
  • the channel stopper electrode 50 formed on the upper surface of the semiconductor substrate 10 on the end side is electrically connected to the back surface electrode 60 via the channel stopper region 40 arranged along the outer edge of the upper surface of the semiconductor substrate 10. ..
  • a part of the upper portion of the conductor film 22 of the trench 20 of the semiconductor substrate 10 is interposed via the insulating film. It extends to the upper surface of the region where the trench 20 is not arranged.
  • a portion of the conductor film 22 extending on the upper surface of the semiconductor substrate 10 is shown as an extending portion 221 (the same applies below).
  • the extending portion 221 is electrically connected to the conductor film 22.
  • the conductor film 22 of the trench 20 does not have to extend to the upper surface of the semiconductor substrate 10.
  • the distance (length L in FIG. 1) along the upper surface of the semiconductor substrate 10 of the extending portion 221 may be shorter in the outer region 122 than in the inner region 121.
  • vertical switching elements such as MOSFETs and IGBTs having a gate trench structure are formed in the element region 110.
  • the back surface electrode is formed on the back surface of the semiconductor substrate 10.
  • the semiconductor device When the semiconductor device is turned off or in the reverse bias state, a potential distribution as shown by the equipotential surface S in FIG. 2 occurs in the peripheral region 120.
  • the depletion layer By extending the depletion layer from the side surface and the bottom surface of the trench 20, the depletion layer spreads laterally and downward in the peripheral region 120, and the concentration of the electric field is relaxed. As a result, the breakdown voltage of the semiconductor device can be improved.
  • the electric field concentrates closer to the element region 110. Therefore, the distance between the trenches 20 in the inner region 121 (the width of the semiconductor substrate 10 in a region sandwiched by the adjacent trenches 20 in plan view) is longer than the distance between the trenches 20 in the outer region 122. Further, in the inner region 121, the closer the distance between the trenches 20 is to the element region 110, the wider the distance is set. Incidentally, the distance between the trenches 20 may be wider as it is closer to the element region 110, or may be constant.
  • the trench 20 is formed as follows, for example. That is, after forming the groove of the trench 20 in the peripheral region 120, the insulating film 21 is formed on the inner wall surface of the groove by using a thermal oxidation method or the like. Next, the conductor film 22 is formed inside the groove.
  • the conductor film 22 is, for example, a polysilicon film doped with impurities.
  • the conductor film 22 is formed on the entire upper surface of the semiconductor substrate 10 so that the groove is filled with the conductor film 22.
  • the conductor film 22 of the trench 20 in the inner region 121 is patterned by photolithography or the like so that the extending portion 221 remains on the upper surface of the semiconductor substrate 10.
  • the upper surface of the conductor film 22 may be lower than the upper surface of the semiconductor substrate 10 when the conductor film 22 is flattened. There is a problem of going down.
  • the structure in which the extending portion 221 remains on the upper surface of the semiconductor substrate 10 has an advantage that a stable breakdown voltage can be obtained without being affected by etching variations.
  • the upper surface of the semiconductor substrate 10 is positioned so that the position of the upper surface of the conductor film 22 of the trench 20 is lower than or substantially the same as the position of the upper surface of the semiconductor substrate 10. The conductor film 22 above is removed.
  • the groove of the trench 20 may be formed at the same time when the gate trench is formed. Then, the insulating film 21 of the trench 20 is formed simultaneously with the formation of the gate insulating film on the inner wall surface of the gate trench, and the conductor film 22 is formed simultaneously with the formation of the gate electrode. At this time, the width of the trench 20 may be the same throughout the peripheral region 120.
  • the electric field is concentrated in the corner portion C facing the element region 110 at the bottom of the trench 20.
  • the electric field is more concentrated in the corner portion C of the bottom of the trench 20 closer to the element region 110 and facing the element region 110.
  • the extending portion 221 of the trench 20 extends from the opening of the trench 20 onto the upper surface of the semiconductor substrate 10 with the insulating film interposed therebetween. Extending to the side. Thereby, as described below, the concentration of the electric field at the corner portion C can be relaxed.
  • a depletion layer is formed on the side surface and the bottom surface of the trench 20.
  • the electric field concentration is more likely to occur on the side surface of the trench 20 on the element region side than on the side surface outside the trench 20.
  • electric field concentration is more likely to occur in the trench 20 in the inner region 121 than in the outer region 122.
  • the inner region 121 since a depletion layer is also formed in the semiconductor substrate 10 below the extending part 221, the interval between the equipotential surfaces on the side surface side of the trench 20 in the inner region 121 on the element region 110 side is wide, and the corner part is formed. The concentration of the electric field at C is relaxed.
  • FIG. 3 and 4 show examples of results of simulation of the potential distribution of the semiconductor substrate 10 and the state of the depletion layer.
  • FIG. 3 shows the equipotential surfaces S1 to S4 and the depletion layer of the trench 20 of the comparative example in which the extending portion 221 is not formed.
  • FIG. 4 shows an example of a situation of equipotential surfaces S1 to S4 of the trench 20 in which the extension portion 221 is formed and the depletion layer.
  • the equipotential surface S1 is an equipotential surface near the element region 110, and the equipotential surfaces S2 to S4 are equipotential surfaces outside the equipotential surface S1.
  • the equipotential surface spacing becomes wider, the concentration of the electric field is further alleviated, and the side surface and the extending portion of the trench 20 are extended.
  • the depletion layer spreads near the upper surface of the semiconductor substrate 10 below the portion 221. As a result, the breakdown voltage of the semiconductor device is improved.
  • the length L of the extending portion 221 that extends in the direction toward the element region 110 may be increased as the trench 20 is closer to the element region 110. Further, the length L of the extension portion 221 extending from the trench 20 close to the element region 110 may be longer than the length L of the extension portion 221 extending from the trench 20 close to the outer region 122.
  • the length L of the extending portion 221 extending from the remaining trench 20 in the middle thereof is, for example, 4 ⁇ m, 4 ⁇ m, 3.5 ⁇ m, 3 ⁇ m, 2.5 ⁇ m, 2 ⁇ m, and stepwise for each single or plural trenches 20. It may be shorter in order from the trench 20 on the element region 110 side. Further, the extending portion 221 extending from the remaining trench 20 may have a constant length.
  • the conductor film 22 is not arranged on the upper surface of the semiconductor substrate 10 in the trench 20 arranged in the outer region 122 of the peripheral region 120. This prevents the equipotential surfaces from being widened in the outer region 122 as in the inner region 121. Therefore, the depletion layer is suppressed from extending to the outer edge of the semiconductor substrate 10.
  • the extending portion 221 of the trench 20 is preferable to form only in the inner region 121 where the electric field is likely to be concentrated because it is close to the element region 110.
  • the position of the boundary between the inner region 121 and the outer region 122 of the peripheral region 120 can be set according to the breakdown voltage required for the semiconductor device. As the number of trenches 20 forming the extending portion 221 increases and the inner region 121 expands outward, a region having a wide equipotential surface interval extends outward. As a result, there is a possibility that reliability problems such as generation of leakage current and reduction of breakdown voltage may occur.
  • FIG. 5 shows the results of the investigation conducted by the present inventors on the relationship between the trench ratio P1/P2 and the breakdown voltage of the semiconductor device.
  • the trench ratio P1/P2 exceeds 1.5, the breakdown voltage becomes stable. Therefore, the region where the trench ratio P1/P2 is smaller than 1.5 is defined as the inner region 121. As a result, the breakdown voltage of the semiconductor device can be effectively improved without expanding the inner region 121 too much.
  • the extending portion 221 that is a part of the conductor film 22 has the semiconductor substrate 10. It extends on the upper surface through an insulating film. This widens the equipotential surface of the semiconductor substrate 10 to control the extension of the depletion layer and alleviate the concentration of the electric field in the peripheral region 120.
  • the breakdown voltage can be improved without increasing the number of surrounding trenches 20 surrounding the element region 110. Therefore, it is possible to realize a semiconductor device having an improved breakdown voltage while suppressing an increase in chip size.
  • a capacitance is generated between the extending portion 221 and the semiconductor substrate 10 below the extending portion 221, and the capacitance generated inside the trench 20 is larger than that when the extending portion 221 is not provided.
  • the voltage applied to the insulating film 21 of the trench 20 can be reduced. This also improves the reliability of the semiconductor device.
  • the extending portion 221 of the conductor film 22 of the trench 20 extends from the opening of the trench 20 toward the region near the element region 110.
  • the extending portion 221 may be arranged at the portion.
  • the extending portion 221 may be arranged only in the portion extending from the opening of the trench 20 toward the region near the outer edge of the semiconductor substrate 10.
  • the depth of the trench 20 is shallower in the inner region 121 than in the outer region 122. That is, the inner region 121 and the outer region 122 have different groove depths of the trench 20, which is a difference from the first embodiment.
  • Other configurations are similar to those of the first embodiment shown in FIG.
  • the distance T from the bottom of the groove of the trench 20 to the PN junction surface of the first semiconductor layer 11 and the second semiconductor layer 12 which is in contact with the groove of the trench 20. Can be shortened.
  • the interval between the equipotential surfaces at the bottom of the trench 20 in the inner region 121 becomes wider, and the concentration of electric field can be relaxed. Therefore, the breakdown voltage of the semiconductor device can be improved.
  • the depth of the groove of the trench 20 in the inner region 121 is, for example, about 4.0 ⁇ m, and from the bottom of the groove of the trench 20 to the PN junction surface between the first semiconductor layer 11 and the second semiconductor layer 12 that is in contact with the side surface of the groove.
  • the distance T is 0 to 0.5 ⁇ m.
  • the depth of the groove of the trench 20 in the outer region 122 is, for example, about 4.5 ⁇ m, and the PN junction between the first semiconductor layer 11 and the second semiconductor layer 12 in contact with the side surface of the groove from the bottom of the groove of the trench 20.
  • the distance T to the surface is 0.5 ⁇ m to 1.5 ⁇ m.
  • the width of the groove of the trench 20 in the inner region 121 is made narrower than the width of the groove of the trench 20 in the outer region 122.
  • a mask for forming such a groove is provided on the semiconductor substrate 10, the grooves of the trench 20 in the inner region 121 and the outer region 122 are simultaneously formed under the same process condition, and the trench 20 is formed in the region 121 inside the outer region 122.
  • the groove can be formed shallowly.
  • the groove of the trench 20 in the inner region 121 and the groove of the trench 20 in the outer region 122 may be formed in different steps under different process conditions.
  • the depth of the second conductivity type (p-type) semiconductor region such as the base region formed on the upper surface side of the semiconductor substrate 10 of the element region 110 formed with the FET or the IGBT and the depth of the second semiconductor layer 12 are The depths may be the same or different. For example, when the depth of the second-conductivity-type semiconductor region such as the base region of the element region 110 is shallower than the depth of the trench 20, the depth of the second-conductivity-type semiconductor region such as the base region of the element region 110 is smaller than that of the second-conductivity-type semiconductor region. 2 The depth of the semiconductor layer 12 may be increased. Thus, the distance T can be adjusted as appropriate without depending on the depth of the second conductivity type semiconductor region of the element region 110.
  • the depth of the trench 20 in the inner region 121 and the depth of the trench 20 in the outer region 122 are set to be substantially the same, and the depth of the second semiconductor layer 12 in the inner region 121 is set to the second semiconductor in the outer region 122. It may be deeper than the depth of layer 12. Accordingly, even if the groove depth of the trench 20 in the inner region 121 and the groove depth of the trench 20 in the outer region 122 are substantially the same, the distance T can be appropriately adjusted.
  • the breakdown voltage can be further improved while suppressing the increase in chip size.
  • Others are substantially the same as those in the first embodiment, and duplicate description will be omitted.
  • the second embodiment also has the configuration including the extending portion 221 as in the first embodiment, but the second embodiment does not include the extending portion 221. Even without it, the concentration of the electric field can be relaxed and the breakdown voltage of the semiconductor device can be improved.
  • the semiconductor device of the present invention can be used in the electronic equipment industry including the manufacturing industry that manufactures semiconductor devices that require high breakdown voltage.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
PCT/JP2018/046035 2018-12-14 2018-12-14 半導体装置 WO2020121508A1 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2020559662A JP7201005B2 (ja) 2018-12-14 2018-12-14 半導体装置
CN201880098705.8A CN112913030B (zh) 2018-12-14 2018-12-14 半导体装置
KR1020217011061A KR102472577B1 (ko) 2018-12-14 2018-12-14 반도체 장치
PCT/JP2018/046035 WO2020121508A1 (ja) 2018-12-14 2018-12-14 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2018/046035 WO2020121508A1 (ja) 2018-12-14 2018-12-14 半導体装置

Publications (1)

Publication Number Publication Date
WO2020121508A1 true WO2020121508A1 (ja) 2020-06-18

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PCT/JP2018/046035 WO2020121508A1 (ja) 2018-12-14 2018-12-14 半導体装置

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JP (1) JP7201005B2 (zh)
KR (1) KR102472577B1 (zh)
CN (1) CN112913030B (zh)
WO (1) WO2020121508A1 (zh)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007123570A (ja) * 2005-10-28 2007-05-17 Toyota Industries Corp 半導体装置
JP2008085086A (ja) * 2006-09-27 2008-04-10 Toyota Industries Corp 半導体装置
JP2009032728A (ja) * 2007-07-24 2009-02-12 Sanken Electric Co Ltd 半導体装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9484451B2 (en) * 2007-10-05 2016-11-01 Vishay-Siliconix MOSFET active area and edge termination area charge balance
US8969954B2 (en) * 2009-08-28 2015-03-03 Sanken Electric Co., Ltd. Semiconductor device having plurality of peripheral trenches in peripheral region around cell region
US9184286B2 (en) * 2011-02-02 2015-11-10 Rohm Co., Ltd. Semiconductor device having a breakdown voltage holding region
JP2013055347A (ja) 2012-11-08 2013-03-21 Sanken Electric Co Ltd 半導体装置
JP5838176B2 (ja) * 2013-02-12 2016-01-06 サンケン電気株式会社 半導体装置
WO2017099095A1 (ja) * 2015-12-11 2017-06-15 富士電機株式会社 半導体装置および製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007123570A (ja) * 2005-10-28 2007-05-17 Toyota Industries Corp 半導体装置
JP2008085086A (ja) * 2006-09-27 2008-04-10 Toyota Industries Corp 半導体装置
JP2009032728A (ja) * 2007-07-24 2009-02-12 Sanken Electric Co Ltd 半導体装置

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CN112913030A (zh) 2021-06-04
KR20210055769A (ko) 2021-05-17
JP7201005B2 (ja) 2023-01-10
JPWO2020121508A1 (ja) 2021-10-21
KR102472577B1 (ko) 2022-11-29
CN112913030B (zh) 2024-05-10

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