WO2020118985A1 - 电介质膜层结构及制作方法 - Google Patents

电介质膜层结构及制作方法 Download PDF

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Publication number
WO2020118985A1
WO2020118985A1 PCT/CN2019/082280 CN2019082280W WO2020118985A1 WO 2020118985 A1 WO2020118985 A1 WO 2020118985A1 CN 2019082280 W CN2019082280 W CN 2019082280W WO 2020118985 A1 WO2020118985 A1 WO 2020118985A1
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Prior art keywords
layer
substrate
silicon nitride
light
baffle
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PCT/CN2019/082280
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English (en)
French (fr)
Inventor
赵凯祥
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武汉华星光电半导体显示技术有限公司
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Priority to US16/468,285 priority Critical patent/US11043552B2/en
Publication of WO2020118985A1 publication Critical patent/WO2020118985A1/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/018—Dielectrics
    • H01G4/06—Solid dielectrics
    • H01G4/08—Inorganic dielectrics
    • H01G4/12—Ceramic dielectrics
    • H01G4/129—Ceramic dielectrics containing a glassy phase, e.g. glass ceramic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/30—Stacked capacitors
    • H01G4/306—Stacked capacitors made by thin film techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0288—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods

Definitions

  • the present disclosure relates to the field of display device manufacturing, and particularly to a dielectric film layer structure and manufacturing method.
  • a matrix structure is implemented, that is, the electrodes of a horizontal group of display pixels are connected together and lead out, called row electrodes; the vertical group of display pixels The segment electrodes are connected together and led out together, called column electrodes.
  • Each display pixel on the display device is determined by the position of the column and row where it is located.
  • the raster scanning method is adopted accordingly.
  • the dynamic driving method of the display device is to apply selection pulses to the row electrodes cyclically through the scan lines, and at the same time, all the column electrodes displaying data provide corresponding selection or non-selection driving pulses through the data lines, thereby realizing the display of all display pixels in a row Function, this line scan is carried out in a line-by-line sequence, with a short cycle period, which makes the screen display a stable picture.
  • the materials of the scan line and the data line are metal. Due to the resistance of the metal, the voltage will decrease with the increase of the transmission distance, that is, the voltage away from the signal input terminal should be less than the voltage near the signal input terminal, resulting in insufficient output uniformity of the display device .
  • the existing display device has the problem of insufficient output uniformity due to voltage drop during signal transmission. Therefore, it is necessary to provide a dielectric film structure and manufacturing method to improve this defect.
  • the materials of the scan line and the data line are metal. Due to the resistance of the metal, the voltage will decrease with the increase of the transmission distance, that is, the voltage away from the signal input terminal should be less than the voltage near the signal input terminal, resulting in insufficient output uniformity of the display device .
  • the present disclosure provides a dielectric film layer structure and a manufacturing method thereof, which are used to solve the problem of insufficient output uniformity caused by a voltage drop during signal transmission of an existing display device.
  • the present disclosure provides a method for manufacturing a dielectric film layer, including:
  • S10 Provide a substrate, and deposit a layer of SiNx on the first capacitor electrode of the substrate to form a silicon nitride layer;
  • S20 deposit a layer of SiOx on the silicon nitride layer to form a silicon oxide layer, and the silicon nitride layer and the silicon oxide layer together form a dielectric layer;
  • the proportion of SiNx in the dielectric layer is increasing, and the proportion of SiOx is decreasing.
  • the step S10 includes:
  • S102 Cover the first photomask on the substrate, and expose and develop the first photoresist layer
  • S103 Deposit a layer of SiNx on the first photoresist layer, and after the silicon nitride layer is deposited, strip the first photoresist layer to form the silicon nitride layer.
  • the step S20 includes:
  • S203 Deposit a layer of SiOx on the second photoresist layer, and after the silicon oxide layer is deposited, strip the second photoresist layer to form the silicon oxide layer.
  • the first photomask is provided with a plurality of first light-transmitting areas, the first light-transmitting areas are arranged in an array along the data line scanning direction and the scanning line scanning direction, and The first light-transmitting area corresponds to a pixel of the substrate.
  • the second photomask is provided with a plurality of second light-transmitting areas, the second light-transmitting areas are arranged in an array along the data line scanning direction and the scanning line scanning direction, and The second light-transmitting area corresponds to a pixel of the substrate.
  • the area of the first light-transmitting area gradually increases along the data line scanning direction and the scan line scanning direction, and the area of the second light-transmitting area scans along the data line Both the direction and the scanning line scanning direction gradually decrease.
  • a first baffle is used to cover the surface of the substrate, and after the silicon nitride layer is deposited, the first block Plate peeling.
  • a second shutter is used to cover the surface of the substrate, and after the silicon nitride layer is deposited, the second shutter Peel off.
  • both the first baffle and the second baffle are provided with a plurality of grids, the grids are arranged in an array along the data line scanning direction and the scanning line scanning direction, The grid corresponds to pixels of the substrate, and the grid area of the first baffle gradually decreases along the data line scanning direction and the scan line scanning direction, and the grid of the second baffle The area gradually increases along the data line scanning direction and the scanning line scanning direction.
  • the present disclosure provides a method for manufacturing a dielectric film layer, including:
  • S10 Provide a substrate, and deposit a layer of SiNx on the first capacitor electrode of the substrate to form a silicon nitride layer;
  • S20 deposit a layer of SiOx on the silicon nitride layer to form a silicon oxide layer, and the silicon nitride layer and the silicon oxide layer together form a dielectric layer;
  • the proportion of SiNx in the dielectric layer is increasing, and the proportion of SiOx is decreasing, and the second direction is perpendicular to the first direction.
  • the step S10 includes:
  • S102 Cover the first photomask on the substrate, and expose and develop the first photoresist layer
  • S103 Deposit a layer of SiNx on the first photoresist layer, and after the silicon nitride layer is deposited, strip the first photoresist layer to form the silicon nitride layer.
  • the step S20 includes:
  • S203 Deposit a layer of SiOx on the second photoresist layer, and after the silicon oxide layer is deposited, strip the second photoresist layer to form the silicon oxide layer.
  • the first photomask is provided with a plurality of first light-transmitting regions, the first light-transmitting regions are arranged in an array along the first direction and the second direction, and the The first light-transmitting area corresponds to a pixel of the substrate.
  • the second photomask is provided with a plurality of second light-transmitting regions, the second light-transmitting regions are arranged in an array along the first direction and the second direction, and the The second light-transmitting area corresponds to pixels of the substrate.
  • the area of the first light-transmitting area gradually increases along the first direction and the second direction, and the area of the second light-transmitting area is along the first direction and the The second direction is gradually reduced.
  • a first baffle is used to cover the surface of the substrate, and after the silicon nitride layer is deposited, the first block Plate peeling.
  • a second shutter is used to cover the surface of the substrate, and after the silicon nitride layer is deposited, the second shutter Peel off.
  • each of the first baffle and the second baffle is provided with a plurality of grids, the grids are arranged in an array along the first direction and the second direction, the grids Corresponding to the pixels of the substrate, and the grid area of the first baffle gradually decreases along the first direction and the second direction, and the grid area of the second baffle is along the first Both the direction and the second direction gradually increase.
  • the present disclosure provides a dielectric film structure including:
  • a dielectric layer provided on the first capacitor electrode
  • a second capacitor electrode, the second capacitor electrode is disposed on the dielectric layer, and the first capacitor electrode, the dielectric layer, and the second capacitor electrode together constitute a storage capacitor of the display panel;
  • the dielectric layer is composed of two substances, SiNx and SiOx, and along the first direction and the second direction, the proportion of SiNx is increasing, and the proportion of SiOx is decreasing.
  • the second direction is perpendicular to the first direction
  • the first direction is a data line scanning direction
  • the second direction is a scanning line scanning direction
  • the beneficial effects of the present disclosure use SiNx and SiOx as the materials of the capacitor dielectric layer, and along the signal transmission direction, the proportion of SiNx is in an increasing state, and the proportion of SiOx is in a decreasing state, because the dielectric constant of SiNx SiOx is large, and SiNx is used as the dielectric layer where the voltage drop is large, storing more charge, and the capacitor charges the thin film transistor with a larger current, so that the thin film transistor is in a high voltage state; where the voltage drop is small, more SiOx is used as the dielectric layer to store less charge, and the current charged by the capacitor to the thin film transistor is small, so that the thin film transistor is in a low voltage state, thereby changing the amount of current charged to the thin film transistor, reducing the effect of voltage drop, and improving the output of the panel. Uniformity.
  • FIG. 1 is a schematic structural diagram of a dielectric film layer provided by an embodiment of the disclosure
  • FIG. 2 is a schematic flowchart of a method for manufacturing a dielectric film layer provided by an embodiment of the disclosure
  • FIG. 3 is a schematic flowchart of a method for manufacturing a dielectric film layer provided by an embodiment of the disclosure
  • FIG. 4 is a schematic flow chart of a method for manufacturing a dielectric film provided by an embodiment of the disclosure.
  • FIG. 5 is a top view of a pixel structure of a display device provided by an embodiment of the present disclosure.
  • the embodiment of the present disclosure provides a dielectric film layer structure.
  • FIG. 1 it is a schematic structural diagram of the dielectric film layer provided in this embodiment.
  • the dielectric film layer structure includes: a first capacitor electrode 101; a dielectric layer 102, The dielectric layer 102 is disposed on the first capacitor electrode 101; the second capacitor electrode 103, the second capacitor electrode 103 is disposed on the dielectric layer 102, the first capacitor electrode 101, the dielectric layer 102 and The second capacitor electrodes 103 together constitute the storage capacitor of the display panel.
  • the dielectric layer 102 is composed of a silicon nitride layer 104 and a silicon oxide layer 105, and along the first direction and the second direction, the proportion of SiNx is increasing, and the proportion of SiOx is decreasing. Since the dielectric constant of SiNx is larger than that of SiOx, SiNx stores more charge than SiOx under the same quality, so at the end close to the data line and the scanning line, the voltage drop is small, so choose more SiOx with less stored charge is used as the material of the dielectric layer 102. At this time, the current charged by the capacitor to the thin film transistor is small, so that the thin film transistor is in a low voltage state. SiNx, which has more stored charge, is used as the material of the dielectric layer. At this time, the current that the capacitor charges the thin film transistor is large, so that the thin film transistor is in a high voltage state.
  • FIG. 5 is a top view of a pixel structure of a display device, wherein the first direction is a data line scanning direction, the second direction is a scanning line scanning direction, and the second direction is perpendicular to the first direction.
  • a plurality of pixels are arranged in an array along the first direction and the second direction, and together constitute a driving circuit of the display device. Only a part of pixels are shown in FIG. 5, the first pixel 501, the second pixel 502, the third pixel 503, and the fourth pixel 504.
  • the shaded part of the pixel is SiNx, and the blank part is SiOx.
  • the first pixel 501 is closest to the data line and the scan line, and the voltage drop is the smallest, so the dielectric layer of the first pixel 501 has the largest proportion of SiOx and the least SiNx; the second pixel 502 and the third pixel 503 are far from the data line or the scan
  • the line is slightly farther and the voltage drop is larger than that of the first pixel 501, so the second pixel 502 and the third pixel 503 have less SiOx and more SiNx in the dielectric layer; the fourth pixel 504 is farthest from the data line and scan line.
  • the voltage drop is the largest, so the dielectric layer of the fourth pixel 504 portion has the smallest proportion, and SiNx has the largest proportion.
  • This embodiment provides a method for manufacturing a dielectric film layer.
  • the dielectric film layer structure provided in Embodiment 1 is cited in this embodiment.
  • the manufacturing method provided in this embodiment will be described in detail below with reference to FIGS. 1 to 5.
  • FIG. 2 it is a schematic flowchart of a method for manufacturing a dielectric film layer provided by this embodiment.
  • the method includes:
  • S10 providing a substrate (not shown in the figure), depositing a layer of SiNx on the first capacitor electrode 101 of the substrate to form a silicon nitride layer 104;
  • S20 deposit a layer of SiOx on the silicon nitride layer 104 to form a silicon oxide layer 105, and the silicon nitride layer 104 and the silicon oxide layer 105 together constitute a dielectric layer 102;
  • the proportion of SiNx in the dielectric layer 102 is increasing, and the proportion of SiOx is decreasing.
  • the first direction is the data line scanning direction
  • the second direction is the scanning line scanning direction .
  • step S10 further includes:
  • S101 coat a layer of photoresist on the first capacitor electrode 101 to form a first photoresist layer
  • S102 Cover the first photomask on the substrate, and expose and develop the first photoresist layer
  • a layer of SiNx is deposited on the first photoresist layer. After the silicon nitride layer is deposited, the first photoresist layer is stripped to form the silicon nitride layer 104.
  • step S20 further includes:
  • S203 deposit a layer of SiOx on the second photoresist layer, and after depositing the silicon oxide layer, strip the second photoresist layer to form the silicon oxide layer 105 and the silicon nitride layer 104 and the silicon oxide layer 105 together constitute a dielectric layer 102.
  • the ratio of the dielectric layer SiNx to the SiOx is changed through the yellow light process, mainly by the first photoresist layer coated on the silicon nitride layer 104 and the second light on the silicon oxide layer 105
  • the resist layer is exposed and developed to obtain the required photoresist pattern, and then the desired ratio of SiNx and SiOx is obtained by depositing SiNx and SiOx.
  • a plurality of first light-transmitting areas are provided on the first photomask (not shown in the figure).
  • the first light-transmitting areas are arranged in an array, and the first light-transmitting areas correspond to the pixels on the substrate.
  • a plurality of second light-transmitting regions are provided, the second light-transmitting regions are arranged in an array, and the second light-transmitting regions also correspond to pixels on the substrate.
  • the area of the first light-transmitting area gradually increases along the first direction and the second direction
  • the area of the second light-transmitting area is along the first direction and the The second direction gradually decreases.
  • the selected photoresist is a positive photoresist.
  • the first photomask is used. As shown in FIG. 5, the first pixel 501 has the smallest light-transmitting area and the fourth pixel 504 The light-transmitting area is the largest, so after step S102, the light-blocking area at the first pixel 501 is the largest, and the light-blocking area at the fourth pixel 504 is the smallest; after the step S103 deposits SiNx, the SiNx at the first pixel 501 The proportion is the smallest, and the SiNx at the fourth pixel 504 is the largest.
  • the light transmission area at the first pixel 501 is the largest and the light transmission area at the fourth pixel 504 is the smallest, so after step S202, the first pixel 501 is blocked by light The area is the smallest, and the photoresist blocking area at the fourth pixel 504 is the largest; after depositing SiOx in step S202, the first pixel 501 has the largest proportion of SiOx, and the fourth pixel 504 has the smallest proportion of SiNx. In this way, along the first direction and the second direction, the proportion of SiNx in the dielectric layer 102 is increasing, and the proportion of SiOx is decreasing.
  • This embodiment provides a method for manufacturing a dielectric film layer.
  • the dielectric film layer structure provided in Embodiment 1 is cited.
  • the manufacturing method provided in this embodiment will be described in detail below with reference to FIGS. 1 to 5.
  • FIG. 2 it is a schematic flowchart of a method for manufacturing a dielectric film layer provided by this embodiment.
  • the method includes:
  • S10 providing a substrate (not shown in the figure), depositing a layer of SiNx on the first capacitor electrode 101 of the substrate to form a silicon nitride layer 104;
  • S20 deposit a layer of SiOx on the silicon nitride layer 104 to form a silicon oxide layer 105, and the silicon nitride layer 104 and the silicon oxide layer 105 together constitute a dielectric layer 102;
  • the proportion of SiNx in the dielectric layer 102 is increasing, and the proportion of SiOx is decreasing.
  • the first direction is the scanning direction of the data line, and the second direction is the scanning line. Scanning direction.
  • step S10 is performed.
  • a first baffle (not shown) is used to cover the surface of the substrate.
  • the first One baffle peeled off.
  • the first baffle is provided with a plurality of grids, the grids are arranged in an array along the first direction and the second direction, and the grids have corresponding pixels on the substrate.
  • the mesh area of the first baffle gradually decreases in both the first direction and the second direction, so that the proportion of SiNx in the dielectric layer 102 increases in both the first direction and the second direction.
  • step S20 is performed.
  • a second baffle (not shown) is used to cover the surface of the substrate. After the silicon oxide layer 105 is deposited, the second The bezel is peeled off.
  • the second baffle is also provided with a plurality of grids, the grids are arranged in an array along the first direction and the second direction, and the grids have corresponding pixels on the substrate.
  • the grid area of the second baffle gradually increases in both the first direction and the second direction, so that the proportion of SiOx in the dielectric layer 102 takes a decreasing state along the first direction and the second direction.
  • SiNx and SiOx are used as the materials of the capacitor dielectric layer, and along the signal transmission direction, the proportion of SiNx is increasing, and the proportion of SiOx is decreasing. Since SiNx has a larger dielectric coefficient than SiOx, the voltage drop In large places, SiNx is used as the dielectric layer, which stores more charge, and the capacitor charges the thin film transistor with a larger current, which makes the thin film transistor in a high voltage state; where the voltage drop is small, more SiOx is used as the dielectric layer.
  • the current charged by the capacitor to the thin film transistor is smaller, so that the thin film transistor is in a low voltage state, thereby changing the amount of current charged to the thin film transistor, reducing the effect of voltage drop, and improving the uniformity of the panel output.

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Abstract

本揭示公开了一种电介质膜层结构及制作方法，所述电介质膜层结构至少包括：第一电容电极、电介质层以及第二电容电极，其中所述电介质层由SiNx和SiOx两种物质组成，在压降大的地方更多的用SiNx做电介质层，在压降小的地方更多的用SiOx做电介质层，从而改变给薄膜晶体管充电的电流大小，减小压降的影响，改善面板输出的均一性。

Description

电介质膜层结构及制作方法 技术领域
本揭示涉及显示装置制造领域，尤其涉及一种电介质膜层结构及制作方法。
 背景技术
显示装置上的显示像素众多，为了节省庞大的硬件驱动电路，实施了矩阵型的结构，即把水平一组显示像素的电极都连接在一起引出，称之为行电极；把纵向一组显示像素的段电极都连接起来一起引出，称之为列电极。在显示装置上每一个显示像素都由其所在的列与行的位置确定。在驱动方式上，相应的采用了光栅扫描方法。显示装置的动态驱动法就是通过扫描线循环的给行电极施加选择脉冲，同时所有显示数据的列电极通过数据线给出相应的选择或非选择的驱动脉冲，从而实现某行所有显示像素的显示功能，这种行扫描是逐行顺序进行的，循环周期短，使得显示屏上呈现出稳定的画面。
扫描线和数据线的材质均为金属，由于金属存在电阻，随着传输距离的增大，电压会降低，即远离信号输入端的电压要小于靠近信号输入端的电压，从而导致显示装置输出均一性不足。
综上所述，现有显示装置信号传输时存在压降导致输出均一性不足的问题。故，有必要提供一种电介质膜层结构及其制作方法来改善这一缺陷。
 技术问题
扫描线和数据线的材质均为金属，由于金属存在电阻，随着传输距离的增大，电压会降低，即远离信号输入端的电压要小于靠近信号输入端的电压，从而导致显示装置输出均一性不足。
 技术解决方案
本揭示提供一种电介质膜层结构及其制作方法，用于解决现有显示装置信号传输时存在压降导致输出均一性不足的问题。
本揭示提供一种电介质膜层的制作方法，包括:
S10：提供一块基板，在所述基板的第一电容电极上沉积一层SiNx，形成氮化硅层；
S20：在所述氮化硅层上沉积一层SiOx，形成氧化硅层，所述氮化硅层和所述氧化硅层共同构成电介质层；
S30：在所述电介质层上形成第二电容电极；
其中，沿数据线扫描方向和扫描线扫描方向，所述电介质层中SiNx的比例均呈递增状态，SiOx的比例均呈递减状态。
根据本揭示一实施例，所述步骤S10包括：
S101：在所述第一电容电极上涂布一层光阻，形成第一光阻层；
S102：在所述基板上遮盖第一光罩，对所述第一光阻层进行曝光显影；
S103：在所述第一光阻层上沉积一层SiNx，沉积完成所述氮化硅层后，对所述第一光阻层进行剥离，形成所述氮化硅层。
根据本揭示一实施例，所述步骤S20包括：
S201：在所述氮化硅层上涂布一层光阻，形成第二光阻层；
S202：在所述基板上遮盖第二光罩，对所述第二光阻层进行曝光显影；
S203：在所述第二光阻层上沉积一层SiOx，沉积完成所述氧化硅层后，对所述第二光阻层进行剥离，形成所述氧化硅层。
根据本揭示一实施例，所述第一光罩设有多个第一透光区域，所述第一透光区域沿所述数据线扫描方向和所述扫描线扫描方向呈阵列排布，且所述第一透光区域对应所述基板的像素。
根据本揭示一实施例，所述第二光罩设有多个第二透光区域，所述第二透光区域沿所述数据线扫描方向和所述扫描线扫描方向呈阵列排布，且所述第二透光区域对应所述基板的像素。
根据本揭示一实施例，所述第一透光区域的面积沿所述数据线扫描方向和所述扫描线扫描方向均逐渐增大，所述第二透光区域的面积沿所述数据线扫描方向和所述扫描线扫描方向均逐渐减小。
根据本揭示一实施例，所述步骤S10中，当形成所述氮化硅层时，使用第一挡板遮盖所述基板表面，沉积完成所述氮化硅层后，将所述第一挡板剥离。
根据本揭示一实施例，所述步骤S20中，当形成所述氧化硅层时，使用第二挡板遮盖所述基板表面，沉积完成所述氮化硅层后，将所述第二挡板剥离。
根据本揭示一实施例，所述第一挡板和所述第二挡板均设有多个网格，所述网格沿所述数据线扫描方向和所述扫描线扫描方向阵列排布，所述网格对应所述基板的像素，且所述第一挡板的网格面积沿所述数据线扫描方向和所述扫描线扫描方向均逐渐减小，所述第二挡板的网格面积沿所述数据线扫描方向和所述扫描线扫描方向逐渐增大。
本揭示提供一种电介质膜层的制作方法，包括:
S10：提供一块基板，在所述基板的第一电容电极上沉积一层SiNx，形成氮化硅层；
S20：在所述氮化硅层上沉积一层SiOx，形成氧化硅层，所述氮化硅层和所述氧化硅层共同构成电介质层；
S30：在所述电介质层上形成第二电容电极；
其中，沿第一方向和第二方向，所述电介质层中SiNx的比例均呈递增状态，SiOx的比例均呈递减状态，所述第二方向垂直于所述第一方向。
根据本揭示一实施例，所述步骤S10包括：
S101：在所述第一电容电极上涂布一层光阻，形成第一光阻层；
S102：在所述基板上遮盖第一光罩，对所述第一光阻层进行曝光显影；
S103：在所述第一光阻层上沉积一层SiNx，沉积完成所述氮化硅层后，对所述第一光阻层进行剥离，形成所述氮化硅层。
根据本揭示一实施例，所述步骤S20包括：
S201：在所述氮化硅层上涂布一层光阻，形成第二光阻层；
S202：在所述基板上遮盖第二光罩，对所述第二光阻层进行曝光显影；
S203：在所述第二光阻层上沉积一层SiOx，沉积完成所述氧化硅层后，对所述第二光阻层进行剥离，形成所述氧化硅层。
根据本揭示一实施例，所述第一光罩设有多个第一透光区域，所述第一透光区域沿所述第一方向和所述第二方向呈阵列排布，且所述第一透光区域对应所述基板的像素。
根据本揭示一实施例，所述第二光罩设有多个第二透光区域，所述第二透光区域沿所述第一方向和所述第二方向呈阵列排布，且所述第二透光区域对应所述基板的像素。
根据本揭示一实施例，所述第一透光区域的面积沿所述第一方向和所述第二方向均逐渐增大，所述第二透光区域的面积沿所述第一方向和所述第二方向均逐渐减小。
根据本揭示一实施例，所述步骤S10中，当形成所述氮化硅层时，使用第一挡板遮盖所述基板表面，沉积完成所述氮化硅层后，将所述第一挡板剥离。
根据本揭示一实施例，所述步骤S20中，当形成所述氧化硅层时，使用第二挡板遮盖所述基板表面，沉积完成所述氮化硅层后，将所述第二挡板剥离。
根据本揭示一实施例，所述第一挡板和所述第二挡板均设有多个网格，所述网格沿第一方向和所述第二方向阵列排布，所述网格对应所述基板的像素，且所述第一挡板的网格面积沿所述第一方向和所述第二方向均逐渐减小，所述第二挡板的网格面积沿所述第一方向和所述第二方向均逐渐增大。
本揭示提供一种电介质膜层结构，包括：
第一电容电极；
电介质层，所述电介质层设置于所述第一电容电极上；以及
第二电容电极，所述第二电容电极设置于所述电介质层上，所述第一电容电极、所述电介质层以及所述第二电容电极共同构成显示面板的储存电容；
其中，所述电介质层由SiNx和SiOx两种物质组成，且沿第一方向和所述第二方向，SiNx的比例均呈递增状态，SiOx的比例均呈递减状态。
根据本揭示一实施例，所述第二方向垂直于所述第一方向，所述第一方向为数据线扫描方向，所述第二方向为扫描线扫描方向。
 有益效果
本揭示的有益效果：本揭示实施例将SiNx和SiOx作为电容电介质层的材料，且沿信号传输方向，SiNx的比例均呈递增状态，SiOx的比例均呈递减状态，由于SiNx的介电系数较SiOx大，在压降大的地方更多的用SiNx做电介质层，储存较多电荷，电容给薄膜晶体管充电的电流较大，使薄膜晶体管处于高电压状态；在压降小的地方更多的用SiOx做电介质层，储存较少电荷，电容给薄膜晶体管充电的电流较小，使薄膜晶体管处于低电压状态，从而改变给薄膜晶体管充电的电流大小，减小压降的影响，改善面板输出的均一性。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是揭示的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本揭示一实施例提供的电介质膜层的结构示意图；
图2为本揭示一实施例提供的电介质膜层制作方法的流程示意图；
图3为本揭示一实施例提供的电介质膜层制作方法的流程示意图；
图4为本揭示一实施例提供的电介质膜层制作方法的流程示意图；以及
图5为本揭示一实施例提供的显示装置像素结构的俯视图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。在图中，结构相似的单元是用以相同标号表示。
下面结合附图和具体实施例对本揭示做详细说明：
实施例一：
本揭示实施例提供了一种电介质膜层结构，如图1所示，是本实施例提供的电介质膜层的结构示意图，所述电介质膜层结构包括：第一电容电极101；电介质层102，所述电介质层102设置于所述第一电容电极101上；第二电容电极103，所述第二电容电极103设置于所述电介质层102上，所述第一电容电极101、电介质层102以及第二电容电极103共同构成显示面板的储存电容。
在本实施例中，电介质层102由氮化硅层104和氧化硅层105组成，且沿第一方向和第二方向，SiNx的比例均呈递增状态，SiOx的比例均呈递减状态。由于SiNx的介电常数比SiOx的介电常数大，在同等质量的情况下SiNx存储的电荷较SiOx存储的电荷多，所以在靠近数据线和扫描线的一端，压降小，选择更多的储存电荷较少的SiOx作为电介质层102的材料，此时电容给薄膜晶体管充电的电流较小，使薄膜晶体管处于低电压状态；在远离数据线和扫描线的一端，压降大，选择更多的储存电荷较多的SiNx作为电介质层的材料，此时电容给薄膜晶体管充电的电流较大，使得薄膜晶体管处于高电压状态。
如图5所示为显示装置像素结构的俯视图，其中第一方向为数据线扫描方向，第二方向为扫描线扫描方向，所述第二方向垂直于所述第一方向。多个像素沿第一方向和第二方向阵列排布，共同构成显示装置的驱动电路。图5中仅示出部分像素，第一像素501、第二像素502、第三像素503以及第四像素504，像素中阴影部分为SiNx，空白部分为SiOx。其中第一像素501距离数据线以及扫描线最近，压降最小，所以第一像素501的电介质层中SiOx占比最多，SiNx占比最少；第二像素502以及第三像素503距离数据线或扫描线稍远，压降较第一像素501要大，所以第二像素502以及第三像素503的电介质层中SiOx占比较少，SiNx较多；第四像素504距离数据线以及扫描线最远，压降最大，所以第四像素504部分的电介质层中SiOx占比最少，SiNx占比最多。
本实施例提供了一种电介质膜层的制作方法，在本实施例中引用实施例一所提供的电介质膜层结构，下面结合图1至图5详细说明本实施例提供的制作方法。
如图2所示，为本实施例提供的电介质膜层制作方法的流程示意图，所述方法包括：
S10：提供一块基板（图中未示出），在所述基板的第一电容电极101上沉积一层SiNx，形成氮化硅层104；
S20：在所述氮化硅层104上沉积一层SiOx，形成氧化硅层105，所述氮化硅层104和所述氧化硅层105共同构成电介质层102；
S30：在所述电介质层102上形成第二电容电极103；
其中，沿第一方向和第二方向，电介质层102中SiNx的比例均呈递增状态，SiOx的比例均呈递减状态，所述第一方向为数据线扫描方向，第二方向为扫描线扫描方向。
实施例二：
在本实施例中，如图3所示，步骤S10还包括：
S101：在所述第一电容电极101上涂布一层光阻，形成第一光阻层；
S102：在所述基板上遮盖第一光罩，对所述第一光阻层进行曝光显影；
S103在所述第一光阻层上沉积一层SiNx，沉积完成所述氮化硅层后，对所述第一光阻层进行剥离，形成所述氮化硅层104。
在本实施例中，如图4所示，步骤S20还包括包括：
S201：在所述氮化硅层104上涂布一层光阻，形成第二光阻层；
S202：在所述基板上遮盖第二光罩，对所述第二光阻层进行曝光显影；
S203：在所述第二光阻层上沉积一层SiOx，沉积完成所述氧化硅层后，对所述第二光阻层进行剥离，形成所述氧化硅层105，所述氮化硅层104和所述氧化硅层105共同构成电介质层102。
在本实施例中，通过黄光制程改变了电介质层SiNx与SiOx的配比，主要是通过对涂布在氮化硅层104上的第一光阻层以及氧化硅层105上的第二光阻层进行曝光显影，获得所需要光阻图案，再通过沉积SiNx以及SiOx，获得所需要的SiNx以及SiOx比例。
第一光罩（图中未示出）上设有多个第一透光区域，第一透光区域呈阵列排布，并且第一透光区域对应基板上的像素，第二光罩上同样设有多个第二透光区域，所述第二透光区域呈阵列排布，且所述第二透光区域同样对应所述基板上的像素。
在本实施例中，所述第一透光区域的面积沿所述第一方向和所述第二方向均逐渐增大，所述第二透光区域的面积沿所述第一方向和所述第二方向均逐渐减小。
在本实施例中，所选用的光阻为正性光阻，当进行步骤S102时，使用第一光罩，如图5所示，第一像素501处透光区域最小，第四像素504处的透光区域最大，所以经过步骤S102之后，第一像素501处有光阻遮挡区域最大，第四像素504处有光阻遮挡区域最小；经过步骤S103沉积SiNx之后，第一像素501处的SiNx占比最少，第四像素504处SiNx占比最多。
同样的，当进行步骤S202时，使用第二光罩，第一像素501处透光区域最大，第四像素504处透光区域最小，所以经过步骤S202之后，第一像素501处有光阻遮挡区域最小，第四像素504处有光阻遮挡区域最大；经过步骤S202沉积SiOx之后，第一像素501处SiOx占比最多，第四像素504处SiNx占比最少。这样就可以获得沿第一方向和第二方向，电介质层102中SiNx的比例均呈递增状态，SiOx的比例均呈递减状态的效果。
实施例三：
本实施例提供了一种电介质膜层的制作方法，在本实施例中引用实施例一所提供的电介质膜层结构，下面结合图1至图5详细说明本实施例提供的制作方法
如图2所示，为本实施例提供的电介质膜层制作方法的流程示意图，所述方法包括：
S10：提供一块基板（图中未示出），在所述基板的第一电容电极101上沉积一层SiNx，形成氮化硅层104；
S20：在所述氮化硅层104上沉积一层SiOx，形成氧化硅层105，所述氮化硅层104和所述氧化硅层105共同构成电介质层102；
S30：在所述电介质层102上形成第二电容电极103；
其中，沿第一方向和第二方向，电介质层102中SiNx的比例均呈递增状态，SiOx的比例均呈递减状态，所述第一方向为数据线扫描方向，所述第二方向为扫描线扫描方向。
在本实施例中，进行步骤S10，当形成所述氮化硅层时，使用第一挡板（图中未示出）遮盖所述基板表面，沉积完成氮化硅层104后将所述第一挡板剥离。其中，所述第一挡板设有多个网格，所述网格沿第一方向和第二方向阵列排布，并且所述网格在基板上均有对应的像素。所述第一挡板的网格面积沿第一方向和第二方向均逐渐减小，使得电介质层102中SiNx的比例沿第一方向和第二方向均呈递增状态。
在本实施例中，进行步骤S20，当形成所述氧化硅层时，使用第二挡板（图中未示出）遮盖所述基板表面，沉积完成氧化硅层105后，将所述第二挡板剥离。其中，所述第二挡板同样设有多个网格，所述网格沿第一方向和第二方向阵列排布，并且所述网格在基板上均有对应的像素。所述第二挡板的网格面积沿第一方向和第二方向均逐渐增大，使得电介质层102中SiOx的比例沿第一方向和第二方向均呈递减状态。
本揭示实施例将SiNx和SiOx作为电容电介质层的材料，且沿信号传输方向，SiNx的比例均呈递增状态，SiOx的比例均呈递减状态，由于SiNx的介电系数较SiOx大，在压降大的地方更多的用SiNx做电介质层，储存较多电荷，电容给薄膜晶体管充电的电流较大，使薄膜晶体管处于高电压状态；在压降小的地方更多的用SiOx做电介质层，储存较少电荷，电容给薄膜晶体管充电的电流较小，使薄膜晶体管处于低电压状态，从而改变给薄膜晶体管充电的电流大小，减小压降的影响，改善面板输出的均一性。
综上所述，虽然本揭示以优选实施例揭露如上，但上述优选实施例并非用以限制本揭示，本领域的普通技术人员，在不脱离本揭示的精神和范围内，均可作各种更动与润饰，因此本揭示的保护范围以权利要求界定的范围为基准。

Claims (20)

  1. 一种电介质膜层的制作方法，包括:
    S10：提供基板，在所述基板的第一电容电极上沉积一层SiNx，形成氮化硅层；
    S20：在所述氮化硅层上沉积一层SiOx，形成氧化硅层，所述氮化硅层和所述氧化硅层共同构成电介质层；
    S30：在所述电介质层上形成第二电容电极；
    其中，沿数据线扫描方向和扫描线扫描方向，所述电介质层中SiNx的比例均呈递增状态，SiOx的比例均呈递减状态。
  2. 如权利要求1所述的制作方法，其中，所述步骤S10包括：
    S101：在所述第一电容电极上涂布一层光阻，形成第一光阻层；
    S102：在所述基板上遮盖第一光罩，对所述第一光阻层进行曝光显影；
    S103：在所述第一光阻层上沉积一层SiNx，沉积完成所述氮化硅层后，对所述第一光阻层进行剥离，形成所述氮化硅层。
  3. 如权利要求2所述的制作方法，其中，所述步骤S20包括：
    S201：在所述氮化硅层上涂布一层光阻，形成第二光阻层；
    S202：在所述基板上遮盖第二光罩，对所述第二光阻层进行曝光显影；
    S203：在所述第二光阻层上沉积一层SiOx，沉积完成所述氧化硅层后，对所述第二光阻层进行剥离，形成所述氧化硅层。
  4. 如权利要求3所述的制作方法，其中，所述第一光罩设有多个第一透光区域，所述第一透光区域沿所述数据线扫描方向和所述扫描线扫描方向呈阵列排布，且所述第一透光区域对应所述基板的像素。
  5. 如权利要求4所述的制作方法，其中，所述第二光罩设有多个第二透光区域，所述第二透光区域沿所述数据线扫描方向和所述扫描线扫描方向呈阵列排布，且所述第二透光区域对应所述基板的像素。
  6. 如权利要求5所述的制作方法，其中，所述第一透光区域的面积沿所述数据线扫描方向和所述扫描线扫描方向均逐渐增大，所述第二透光区域的面积沿所述数据线扫描方向和所述扫描线扫描方向均逐渐减小。
  7. 如权利要求1所述的制作方法，其中，所述步骤S10中，当形成所述氮化硅层时，使用第一挡板遮盖所述基板表面，沉积完成所述氮化硅层后，将所述第一挡板剥离。
  8. 如权利要求7所述的制作方法，其中，所述步骤S20中，当形成所述氧化硅层时，使用第二挡板遮盖所述基板表面，沉积完成所述氮化硅层后，将所述第二挡板剥离。
  9. 如权利要求8所述的制作方法，其中，所述第一挡板和所述第二挡板均设有多个网格，所述网格沿所述数据线扫描方向和所述扫描线扫描方向阵列排布，所述网格对应所述基板的像素，且所述第一挡板的网格面积沿所述数据线扫描方向和所述扫描线扫描方向均逐渐减小，所述第二挡板的网格面积沿所述数据线扫描方向和所述扫描线扫描方向逐渐增大。
  10. 一种电介质膜层的制作方法，包括：
    S10：提供基板，在所述基板的第一电容电极上沉积一层SiNx，形成氮化硅层；
    S20：在所述氮化硅层上沉积一层SiOx，形成氧化硅层，所述氮化硅层和所述氧化硅层共同构成电介质层；
    S30：在所述电介质层上形成第二电容电极；
    其中，沿第一方向和第二方向，所述电介质层中SiNx的比例均呈递增状态，SiOx的比例均呈递减状态，所述第二方向垂直于所述第一方向。
  11. 如权利要求10所述的制作方法，其中，所述步骤S10包括：
    S101：在所述第一电容电极上涂布一层光阻，形成第一光阻层；
    S102：在所述基板上遮盖第一光罩，对所述第一光阻层进行曝光显影；
    S103：在所述第一光阻层上沉积一层SiNx，沉积完成所述氮化硅层后，对所述第一光阻层进行剥离，形成所述氮化硅层。
  12. 如权利要求11所述的制作方法，其中，所述步骤S20包括：
    S201：在所述氮化硅层上涂布一层光阻，形成第二光阻层；
    S202：在所述基板上遮盖第二光罩，对所述第二光阻层进行曝光显影；
    S203：在所述第二光阻层上沉积一层SiOx，沉积完成所述氧化硅层后，对所述第二光阻层进行剥离，形成所述氧化硅层。
  13. 如权利要求12所述的制作方法，其中，所述第一光罩设有多个第一透光区域，所述第一透光区域沿所述第一方向和所述第二方向呈阵列排布，且所述第一透光区域对应所述基板的像素。
  14. 如权利要求13所述的制作方法，其中，所述第二光罩设有多个第二透光区域，所述第二透光区域沿所述第一方向和所述第二方向呈阵列排布，且所述第二透光区域对应所述基板的像素。
  15. 如权利要求14所述的制作方法，其中，所述第一透光区域的面积沿所述第一方向和所述第二方向均逐渐增大，所述第二透光区域的面积沿所述第一方向和所述第二方向均逐渐减小。
  16. 如权利要求10所述的制作方法，其中，所述步骤S10中，当形成所述氮化硅层时，使用第一挡板遮盖所述基板表面，沉积完成所述氮化硅层后，将所述第一挡板剥离。
  17. 如权利要求16所述的制作方法，其中，所述步骤S20中，当形成所述氧化硅层时，使用第二挡板遮盖所述基板表面，沉积完成所述氮化硅层后，将所述第二挡板剥离。
  18. 如权利要求17所述的制作方法，其中，所述第一挡板和所述第二挡板均设有多个网格，所述网格沿第一方向和所述第二方向阵列排布，所述网格对应所述基板的像素，且所述第一挡板的网格面积沿所述第一方向和所述第二方向均逐渐减小，所述第二挡板的网格面积沿所述第一方向和所述第二方向均逐渐增大。
  19. 一种电介质膜层结构，包括：
    第一电容电极；
    电介质层，所述电介质层设置于所述第一电容电极上；以及
    第二电容电极，所述第二电容电极设置于所述电介质层上，所述第一电容电极、所述电介质层以及所述第二电容电极共同构成显示面板的储存电容；
    其中，所述电介质层由SiNx和SiOx两种物质组成，且沿第一方向和所述第二方向，SiNx的比例均呈递增状态，SiOx的比例均呈递减状态。
  20. 如权利要求19所述的电介质膜层结构，其中，所述第二方向垂直于所述第一方向，所述第一方向为数据线扫描方向，所述第二方向为扫描线扫描方向。
PCT/CN2019/082280 2018-12-14 2019-04-11 电介质膜层结构及制作方法 WO2020118985A1 (zh)

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