WO2020102934A1 - 信号产生电路以及相关方法 - Google Patents

信号产生电路以及相关方法

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Publication number
WO2020102934A1
WO2020102934A1 PCT/CN2018/116164 CN2018116164W WO2020102934A1 WO 2020102934 A1 WO2020102934 A1 WO 2020102934A1 CN 2018116164 W CN2018116164 W CN 2018116164W WO 2020102934 A1 WO2020102934 A1 WO 2020102934A1
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WO
WIPO (PCT)
Prior art keywords
circuit
comparison
circuits
comparison circuits
voltage
Prior art date
Application number
PCT/CN2018/116164
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English (en)
French (fr)
Inventor
杨孟达
Original Assignee
深圳市汇顶科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市汇顶科技股份有限公司 filed Critical 深圳市汇顶科技股份有限公司
Priority to PCT/CN2018/116164 priority Critical patent/WO2020102934A1/zh
Priority to CN201880002190.7A priority patent/CN111465935B/zh
Publication of WO2020102934A1 publication Critical patent/WO2020102934A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information

Definitions

  • the present application relates to a signal generating circuit, in particular to a signal generating circuit for generating identification codes of devices such as chip cards and electronic devices including radio frequency chips and related methods.
  • Physical non-cloning technology can be used for mutual authentication between tags and readers.
  • the physical non-cloning function technology uses the unique physical characteristics of the silicon wafer and the variability of the chip manufacturing process to identify each silicon chip and judge their authenticity, without the need to use a key or store a key.
  • Traditionally relying on the physical characteristics of static random access memory technology to implement a key circuit that uses a physical non-cloning function. After the security component is powered on, the institutional organizations in the interim also start randomly. The startup behavior is different in every chip. Therefore, its content is a unique "fingerprint" after startup, such a fingerprint can be used as a key to protect the key or protect the memory.
  • the key circuit implemented by the static random access memory is likely to lose the key due to unstable output due to environmental factors such as temperature or voltage.
  • One of the purposes of the present application is to provide a signal generation circuit that uses a physically uncloned function to solve the above problem.
  • a signal generating circuit for generating an identification code including: a plurality of processing circuits and a conversion circuit.
  • Each processing circuit has its own process offset, and each processing circuit of the plurality of processing circuits receives an input voltage and generates an output voltage according to the input voltage and the process offset of each processing circuit.
  • the conversion circuit generates the identification code according to the output voltage of each processing circuit of the plurality of processing circuits.
  • a signal generation method for generating an identification code including: obtaining a plurality of comparison circuits; according to the process offset voltage of each of the plurality of comparison circuits, the The comparison circuit is divided into a plurality of groups of comparison circuits; at least one group of comparison circuits in the plurality of groups of comparison circuits is set so that the output voltage of the at least one group of comparison circuits is a specific voltage; and the plurality of comparison circuits are read The output voltage of each.
  • FIG. 1 is a schematic diagram of a signal generating circuit according to an embodiment of the application.
  • FIG. 2 is a schematic diagram of multiple processing circuits according to an embodiment of the present application.
  • FIG. 3 is a schematic diagram of multiple processing circuits configured as a single gain buffer according to an embodiment of the present application.
  • FIG. 4 is a schematic diagram of a processing circuit configured as a gain amplifier according to an embodiment of the present application.
  • FIG. 5 is a schematic diagram of a conversion circuit according to an embodiment of the application.
  • FIG. 6 is a schematic diagram of a conversion circuit according to another embodiment of the present application.
  • FIG. 7 is a schematic diagram of multiple processing circuits according to another embodiment of the present application.
  • FIG. 8 is a schematic diagram of determining a process offset voltage of a comparison circuit according to an embodiment of the application.
  • FIG. 9 is a schematic diagram of a threshold distribution of a comparison circuit according to an embodiment of the application.
  • FIG. 10 is a schematic diagram of a fuse according to an embodiment of the application.
  • FIG. 11 is a schematic diagram of a conversion circuit according to yet another embodiment of the present application.
  • FIG. 12 is a schematic diagram of a signal generation method according to an embodiment of the application.
  • FIG. 13 is a schematic diagram of a signal generation method according to another embodiment of the present application.
  • the present application uses a process offset generated by a semiconductor process to an electronic circuit when manufacturing an electronic circuit to implement a signal generating circuit using a physical non-cloning function technology, and the signal generating circuit may thus generate an identification code.
  • the process offset is a phenomenon in which the properties (such as length, width, oxide thickness, etc.) of the transistor will shift when an integrated circuit is manufactured, resulting in an observable difference in the performance of the electronic circuit.
  • FIG. 1 is a schematic diagram of a signal generating circuit 100 according to an embodiment of the application.
  • the signal generating circuit 100 includes a plurality of processing circuits and a conversion circuit 120.
  • the signal generating circuit 100 includes N * M processing circuits, where N and M are both positive integers.
  • both N and M are 64.
  • the multiple processing circuits are arranged in an array.
  • the plurality of processing circuits are arranged in N columns and M rows, and the processing circuit located in the first row and first column can be marked as the processing circuit 110 11 and the second row and first column
  • the processing circuit can be labeled as processing circuit 110 21 , and so on.
  • the plurality of processing circuits are not limited to be arranged in an array.
  • the multiple processing circuits may be arranged at will. An embodiment in which a plurality of processing circuits 110 are arranged in an array or not will be described later.
  • Each of the plurality of processing circuits has its own process offset, and after each of the plurality of processing circuits receives the input voltage Vin, each is generated according to the input voltage Vin and the respective process offset Output voltage.
  • the output voltage generated by the processing circuit 110 11 in the first row and first column can be labeled as the output voltage Vout 11
  • the output voltage generated by the processing circuit 110 21 in the second row and first column can be labeled Is the output voltage Vout 21 , and so on.
  • Converting circuit 120 receives the plurality of the processing circuit (processing circuit 11011, 11021 ...) generated in each of the output voltage (output voltage Vout 11, Vout 21 ...) to generate the identification code ID.
  • the signal generating circuit 100 can be applied to a chip card or an electronic device including a radio frequency chip, and the identification code ID generated by the signal generating circuit 100 represents a physical uncloneable identification code of the chip card or the electronic device.
  • FIG. 2 is a schematic diagram of multiple processing circuits according to an embodiment of the present application.
  • each of the plurality of processing circuits processing circuits 110 11 , 110 21 ...) Of the signal generating circuit 100 includes an operational amplifier circuit.
  • a plurality of operational amplifier circuits are arranged in N columns and M rows, and have corresponding labels.
  • the processing circuit 110 11 includes an operational amplifier circuit OP 11 and the processing circuit 110 21 includes an operational amplifier circuit OP 21 , and so on.
  • An input terminal of each operational amplifier circuit receives the input voltage Vin, and generates an output voltage according to the input voltage Vin and the process offset of the operational amplifier circuit itself.
  • FIG. 3 is a schematic diagram of multiple processing circuits configured as a single gain buffer according to an embodiment of the present application.
  • a plurality of the operational amplifier circuit 3 (the operational amplifier OP 11, OP 21 ...) each configured as a unity gain was, in other words, each of said plurality of visual operational amplifier circuit It is a single gain buffer.
  • the single gain buffer receives the input voltage Vin from the input terminal, it will output the input voltage Vin from the output terminal.
  • the output voltage on the output terminal will be The input voltage Vin is slightly different.
  • the difference is caused by the process offset voltage of the operational amplifier circuit, and the process offset voltage of each operational amplifier circuit is different, so that the output generated by each operational amplifier circuit The voltage is different.
  • the output voltage of each operational amplifier circuit is generated according to the process offset voltage of the operational amplifier circuit itself and the input voltage Vin.
  • the output voltage Vout 11 is different from the other output voltages, so that the signal generation circuit 100 can be based on multiple different To generate the identification code ID.
  • FIG. 3 is only an example and is not a limitation of the present invention.
  • the multiple operational amplifier circuits may be configured as a single gain in other ways, or the multiple The operational amplifier circuit is configured as an amplifier with a gain greater than or less than 1.
  • 4 is a schematic diagram of an amplifier with a processing circuit configured to have a gain greater than or less than 1 according to an embodiment of the present application. As shown in FIG.
  • the processing circuit 110 11 further includes resistors R 1 and R 2 , wherein one end of the resistor R 1 receives the input voltage Vin, and the other end of the resistor R 1 is coupled to the operation In the negative input terminal of the amplifier circuit OP 11 , one end of the resistor R 2 is coupled to the negative input terminal of the operational amplifier circuit OP 11 , and the other end of the resistor R 2 is coupled to the output terminal of the operational amplifier circuit OP 11 .
  • the positive input terminal of the operational amplifier circuit OP 11 is coupled to ground, but due to the process offset, the positive input terminal of the operational amplifier circuit OP 11 can be equivalently coupled to a voltage source, and the voltage value of the voltage source is offset voltage of the operational amplifier OP 11 Vos 11.
  • the relationship between the output voltage Vout of the operational amplifier circuit OP 11 and the input voltage Vin can be regarded as It can be seen that the signal of the input voltage Vin and the offset voltage Vos 11 can be amplified by the ratio of the resistors R 1 and R 2 , so the multiple processing circuits can be configured as the operational amplifier circuit architecture shown in FIG. 4 To amplify the signal.
  • FIG. 5 is a schematic diagram of a conversion circuit 120 according to an embodiment of the present application.
  • the conversion circuit 120 includes an analog-to-digital converter 410 and a feature extraction circuit 420.
  • the analog-to-digital converter 410 is coupled to the plurality of processing circuits 110 11 , 110 21 ..., and sequentially receives the output voltage (output voltage Vout 11 , each of the plurality of processing circuits 110 11 , 110 21 ... Vout 21 ...), and perform an analog-to-digital conversion operation on each output voltage received, and then sequentially output the digital output voltage.
  • the analog-to-digital converter 410 receives the output voltage Vout 11 from the processing circuit 110 11 and performs the analog-to-digital conversion operation on the output voltage Vout 11 to generate the digital output voltage D 11 ; the analog-to-digital converter 410 receives the processing voltage from the processing circuit The output voltage Vout 21 of 110 21 performs the analog-digital conversion operation on the output voltage Vout 21 to generate a digital output voltage D 21 , and so on.
  • the analog-to-digital converter 410 may be a successive approximation type analog-to-digital converter.
  • the analog-to-digital converter 410 may be a 10-bit successive approximation type analog-to-digital converter.
  • the feature extraction circuit 420 sequentially receives the digital output voltages (digital output voltages D 11 , D 21 ”) From the analog-to-digital conversion circuit 410 and generates an identification code ID according to the plurality of digital output voltages.
  • the feature extraction circuit 420 may be a scale-invariant feature transform (SIFT) circuit for performing scale-invariant feature conversion operations on the plurality of digital output voltages, the scale being unchanged
  • SIFT scale-invariant feature transform
  • Feature transformation is a machine vision algorithm used to detect and describe local features in an image. It looks for extreme points in the spatial scale and extracts its position, scale, and rotation invariants.
  • the feature extraction circuit 420 obtains the distribution trend of the multiple digital output voltages from the multiple digital output voltages (digital output voltages D 11 , D 21 ).
  • the multiple processing circuits use N * M two In the case of dimensional distribution, the distribution trend of the corresponding multiple digital output voltages will also form an N * M two-dimensional distribution map with high and low value fluctuations, and the feature extraction circuit 420 will generate an identification code according to the two-dimensional distribution map of the output voltage ID.
  • the highest point eg, the largest output voltage among the plurality of digital output voltages
  • the lowest point eg, the smallest among the plurality of digital output voltages
  • the corresponding processing circuit of the output voltage is found from N columns and M rows, and an identification code ID is generated according to the position of the found processing circuit.
  • the corresponding coordinates of the processing circuit corresponding to the highest point and the lowest point in N columns and M rows can be output as the identification code ID.
  • the corresponding position of each operational amplifier circuit in the 64 * 64 array can be expressed as a 6-bit abscissa and a 6-bit ordinate, by which the feature extraction circuit 420 After extracting the coordinates corresponding to the relative highest point and the relative lowest point in the distribution trend, output all corresponding coordinates as the identification code ID.
  • the feature extraction circuit 420 After extracting the coordinates corresponding to the relative highest point and the relative lowest point in the distribution trend, output all corresponding coordinates as the identification code ID.
  • a plurality of relatively high In addition to the highest point and the lowest point in the two-dimensional distribution map of the output voltage, a plurality of relatively high The point and the low point are combined to generate an identification code ID.
  • the conversion circuit 120 shown in FIG. 5 may further include a multiplexer.
  • the conversion circuit 120 further includes a multiplexer 430 coupled between the plurality of processing circuits 110 11 , 110 21 ... And the analog-to-digital conversion circuit 410.
  • the multiplexer is based on The control signal CTRL sequentially outputs the output voltages Vout 11 , Vout 21 ... generated by the plurality of processing circuits 110 11 , 110 21 ... To the analog-to-digital conversion circuit 410.
  • the control signal CTRL may be generated by a circuit other than the signal generating circuit 100.
  • FIG. 7 is a schematic diagram of multiple processing circuits according to another embodiment of the present application.
  • each of the plurality of processing circuits processing circuits 110 11 , 110 21 ...) Of the signal generating circuit 100 includes a comparison circuit.
  • the processing circuit 110 11 includes a comparison circuit COM 11 and the processing circuit 110 21 includes a comparison circuit COM 21 , and so on.
  • One input terminal of each comparison circuit receives the input voltage Vin, and the other input terminal receives a reference voltage Vref and generates an output voltage according to the input voltage Vin and the process offset of the comparison circuit itself.
  • multiple comparison circuits need not be arranged in an array.
  • FIG. 8 is a schematic diagram of determining a process offset voltage of a comparison circuit according to an embodiment of the application. As shown in FIG. 8, taking the comparison circuit COM 11 as an example, the positive input terminal of the comparison circuit COM 11 receives the input voltage Vin and the negative input terminal receives the reference voltage Vref.
  • the output voltage Vout 11 is a logic low level (e.g., logic value '0'); as the input voltage Vin rises, when the input voltage Vin is greater than the reference voltage Vref, the output voltage Vout 11 ideally should be converted to a high logic level ( For example the logic value '1'), however, because of the offset process, the output voltage Vout of 11 until the input voltage Vin rises to the voltage value Vref + Vos 11 when converted to the logic high level, which is the voltage comparator circuit 11 Vos COM 11 process offset voltage.
  • the process offset voltage Vos 11 of the comparison circuit COM 11 is only an example.
  • the process offset voltage Vos 11 of the comparison circuit COM 11 may have a negative value. In this way, when the input voltage Vin has not risen to the reference voltage Vref, the output voltage Vout 11 is converted to a logic high level.
  • the multiple comparison circuits (for example, the comparison circuits COM 11 and COM 21 ) can be classified into the first group, the second group, and the third group according to the process offset voltage of each comparison circuit.
  • the process offset voltage of the comparison circuit included in the first group is greater than a preset first threshold Vth1, and the process offset voltage of the comparison circuit included in the second group is less than a preset second threshold Vth2
  • the process offset voltage of the comparison circuit included in the third group is greater than the second threshold Vth2 and less than the first threshold Vth1, where the second threshold Vth2 is lower than the first threshold Vth1.
  • 9 is a schematic diagram of a threshold distribution of a comparison circuit according to an embodiment of the present application, where the X axis represents the threshold value and the Y axis represents the number of comparison circuits. As shown in FIG.
  • the comparison circuits in which the process offset voltage is greater than the first threshold Vth1 among the plurality of comparison circuits are divided into the first group, and the plurality of comparison circuits
  • the comparison circuits with the mid-process offset voltage less than the second threshold Vth2 are divided into the second group, and the comparison circuits with the process offset voltage greater than the second threshold Vth2 and less than the first threshold Vth1 among the multiple comparison circuits
  • the third group the plurality of comparison circuits (for example, the comparison circuits COM 11 and COM 21 ) exhibit a Gaussian distribution according to the pattern of the process offset voltage distribution.
  • the second threshold Vth2 is a negative value less than 0V and the first threshold Vth1 is a positive value greater than 0V.
  • the absolute values of the first threshold Vth1 and the second threshold Vth2 are greater than the noise intensity of the plurality of comparison circuits (for example, comparison circuits COM 11 , COM 21 ).
  • Common noises in electronic components are thermal noise, scattered noise, flicker noise, and random telegraph noise, and the absolute values of the first threshold Vth1 and the second threshold Vth2 are greater than the multiple comparison circuits (for example, comparison circuits COM 11 , COM 21 ... ) The intensity of all noise that may be generated by each comparison circuit in).
  • the absolute values of the first threshold Vth1 and the second threshold Vth2 are greater than the noise floor of each comparison circuit.
  • one input terminal of the plurality of comparison circuits (for example, the comparison circuits COM 11 , COM 21 ). Receives the input voltage Vin and the other input terminal receives the reference voltage Vref.
  • the output voltage will be fixedly output as a logic low potential (such as a logic value of 0); because the process offset voltage of the comparison circuit divided into the second group is less than the second threshold Vth2, and the absolute value of the second threshold Vth2 is greater than the noise Intensity, when the input voltage Vin is equal to the reference voltage Vref, the output voltage will be fixed and output to a logic high potential (such as logic value 1). Therefore, in actual operation, the user gives the input voltage Vin the same potential value as the reference voltage Vref, which can make the comparison circuit divided into the first
  • the plurality of processing circuits may further include fuses for matching with the comparison circuit.
  • the process offset voltages of the comparison circuits divided into the third group may be less than the noise intensity of the comparison circuit, so that they are divided into the third group
  • the output voltage may not be predictable. Therefore, before the signal generating circuit 100 leaves the factory, the fuses of the comparison circuits classified into the third group are blown, so that the output voltage of the comparison circuits divided into the third group will only output a specific voltage fixed
  • the specific voltage may be the logic high potential or the logic low potential, or may be another potential value different from the logic high potential or the logic low potential for distinction.
  • the comparison circuits divided into the first group and the second group will not produce an undefined output like the third group, that is, the comparison circuits of the first group and the second group will stabilize the output
  • the logic low potential and the logic high potential do not require a fuse operation for the fuse of the comparison circuits of the first group and the second group.
  • the plurality of comparison circuits (comparison circuits COM 11 , COM 21 ) Each have their fixed output output voltages (output voltages Vout 11 , Vout 21 ) when receiving the input voltage Vin equal to the reference voltage Vref. 7), so that the conversion circuit 120 can generate the identification code ID according to the output voltages of the plurality of comparison circuits.
  • the fusing the fuse may include any method of fixing the output voltage of the comparison circuit divided into the third group to the specific voltage through the fuse. As shown in FIG.
  • the fuse 910 receives the output of the comparison circuit COM 21 and a specific voltage Vspec, and the fuse 910 is controlled by the fuse signal Vfuse. If the process offset voltage of the comparison circuits COM 21 is checked before delivery, the result of the process offset voltage of the comparison circuit COM 21 is higher than the second threshold Vth2 and lower than the first threshold Vth1, then the comparison circuit COM 21 Will be divided into the third group, therefore, the fuse signal Vfuse is transmitted to the fuse 910 corresponding to the comparison circuit COM 21 , thereby fusing the fuse 910 such that the fuse 910 will only output a specific voltage Vspec as the output voltage Vout 21 , therefore, every time the user uses it after leaving the factory, the comparison circuit divided into the third group will output a specific voltage Vspec fixedly.
  • the fuse 910 is a circuit architecture implemented in software, hardware, or firmware, and the output of the output comparison circuit COM 21 or the specific voltage Vspec is selected as the output voltage Vout 21 according to
  • the comparison circuits divided into the first group and the second group can stably output the logic low potential and the logic high potential, and by blowing the fuse, the comparison circuit divided into the third group can also be stabilized A specific voltage is output. Therefore, all of the multiple comparison circuits can stably output a potential value. In this configuration, the output voltages of the multiple comparison circuits generate a stable identification code ID.
  • the arrangement of the output voltages of the multiple comparison circuits is not limited, as long as the electronic device applying the signal generating circuit 100 and the electronic device communicating with it have a good agreement.
  • FIG. 11 is a schematic diagram of a conversion circuit 120 according to another embodiment of the present application.
  • the MUX converting circuit 120 includes a multiplexer, sequentially from a plurality of the comparison circuit 11 (comparison circuit COM 11, COM 21 ...) receives the output voltage (output voltage Vout 11, Vout 21 ...) , And sequentially output the output voltages (output voltages Vout 11 , Vout 21 %) according to the control signal CTRL ′ to generate the identification code ID.
  • the control signal CTRL ' may be generated by a circuit other than the signal generating circuit 100.
  • FIG. 12 is a flowchart of a signal generation method 1200 according to an embodiment of the application. Provided that substantially the same result can be obtained, the present application is not limited to completely follow the steps shown in FIG. 12.
  • the signal generation method 1200 can be summarized as follows:
  • Step 1202 Obtain multiple operational amplifier circuits.
  • Step 1204 Configure the plurality of operational amplifier circuits as a single gain buffer or an amplifier with a gain greater than or less than 1.
  • Step 1206 Read the output voltage of each of the plurality of operational amplifier circuits.
  • Step 1208 Generate multiple digital output voltages based on multiple output voltages.
  • Step 1210 Generate a distribution trend of the output voltage according to multiple digital output voltages.
  • Step 1212 Generate an identification code according to the distribution trend of the output voltage.
  • FIG. 13 is a flowchart of a signal generation method 1300 according to another embodiment of the present application. Provided that substantially the same result can be obtained, the present application is not limited to completely follow the steps shown in FIG. 13.
  • the signal generation method 1300 can be summarized as follows:
  • Step 1302 Obtain multiple comparison circuits.
  • Step 1304 Divide the plurality of comparison circuits into groups of comparison circuits according to the process offset voltage of each of the plurality of comparison circuits.
  • Step 1306 Set at least one group of comparison circuits among the plurality of groups of comparison circuits, so that the output voltage of the at least one group of comparison circuits is a specific voltage.
  • Step 1308 Read the output voltage of each of the plurality of comparison circuits.
  • Step 1310 Generate an identification code based on multiple output voltages.

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Abstract

本发明公开一种信号产生电路，用于产生识别码，包括:多个处理电路及转换电路。每一处理电路具有各自的制程偏移量，且所述多个处理电路的每一处理电路接收输入电压，并依据所述输入电压以及每一处理电路的制程偏移量产生输出电压。转换电路依据所述多个处理电路的每一处理电路的输出电压产生所述识别码。

Description

信号产生电路以及相关方法 技术领域
本申请是有关于一种信号产生电路，尤指一种用以产生装置如芯片卡、包括有射频芯片的电子装置之识别码的信号产生电路以及相关方法。
背景技术
物理不可克隆功能技术可用于制作标签与阅读器之间的相互认证。物理不可克隆功能技术采用硅片独特的物理特性和芯片制造过程的变异性来识别各个硅芯片，判断它们的真伪性，无需采用密钥或储存密钥。传统上依赖静态随机存取内存技术的物理特性来实现采用物理不可克隆功能的密钥电路，在安全性组件通电后，期中的基层组织也随机启动，此种在0与1之间位切换的启动行为，在每一个芯片中皆不相同。因此，在启动后其内容就是一个独特的「指纹」，这样的指纹可作为钥匙用以保护密钥或保护内存。然而，以静态随机存取内存所实现的密钥电路容易因环境因素如温度或电压造成输出不稳定造成密钥流失。
发明内容
本申请的目的之一在于提供一种采用物理不可克隆功能的信号产生电路来解决上述问题。
依据本申请一实施例，提供一种信号产生电路，用于产生识别码，包括:多个处理电路及转换电路。每一处理电路具有各自的制程偏移量，且所述多个处理电路的每一处理电路接收输入电压，并依据所述输入电压以及每一处理电路的制程偏移量产生输出电压。转换电路依据所述多个处理电路的每一处理电路的输出电压产生所述识别码。
依据本申请一实施例，提供一种信号产生方法，用于产生识别码，包括:取得多个比较电路；依据所述多个比较电路中的每一个的制程偏移电压，将所述多个比较电路分为多组比较电路；设置所述多组比较电路中的至少一组比较 电路，使所述至少一组比较电路的输出电压为特定电压；及读取所述多个比较电路中的每一个的输出电压。
附图说明
图1是依据本申请一实施例之信号产生电路的示意图。
图2是依据本申请一实施例之多个处理电路的示意图。
图3是依据本申请一实施例之多个处理电路组态为单一增益缓冲器的示意图。
图4是依据本申请一实施例之处理电路组态为具有增益的放大器的示意图。
图5是依据本申请一实施例之转换电路的示意图。
图6是依据本申请另一实施例之转换电路的示意图。
图7是依据本申请另一实施例之多个处理电路的示意图。
图8是依据本申请一实施例之判断比较电路的制程偏移电压的示意图。
图9是依据本申请一实施例之比较电路的阈值分布的示意图。
图10是依据本申请一实施例之熔断器的示意图。
图11是依据本申请又另一实施例之转换电路的示意图。
图12是依据本申请一实施例之信号产生方法的示意图。
图13是依据本申请另一实施例之信号产生方法的示意图。
具体实施方式
为更好的理解本发明的精神，以下结合本发明的部分优选实施例对其作进一步说明。
为了使本技术领域中具有通常知识者能制造并使用本发明的实施例，以下描述是针对一个特别的应用及其条件的情况。各种针对本发明的实施例所进行 的修改方式，对本技术领域中具有通常知识者是显而易见的。而在此所定义的一般原理，在不偏离本发明的实施例的精神与范围下，可用于其他的实施方式和应用。因此，本发明的实施方式并不局限于已显示的实施例，而可得到与在此所揭示内容的原理与特征相符的最宽广范围。
本申请利用在制作电子电路时半导体制程对电子电路产生的制程偏移量来实现利用物理不可克隆功能技术的信号产生电路，所述信号产生电路可因此产生识别码。所述制程偏移是制作集成电路时，晶体管的属性(如长度、宽度、氧化物厚度等)会产生偏移的现象，从而导致电子电路的性能具有可观察的差异。
图1是依据本申请一实施例之信号产生电路100的示意图。如图1所示，信号产生电路100包括多个处理电路以及转换电路120。信号产生电路100包含N＊M个处理电路，其中N与M皆为正整数。可选地，N与M皆为64。可选地，所述多个处理电路以阵列形式排列。换句话说，所述多个处理电路排列成N个列(column)M个行(row)，而位于第1行第1列的处理电路可标示为处理电路110 11，第2行第1列的处理电路可标示为处理电路110 21，依此类推。然而，所述多个处理电路并不限定要排列成阵列。可选地，所述多个处理电路可以随意排列。后续将说明多个处理电路110排列成阵列与否的实施例。
所述多个处理电路中的每一个皆具有各自的制程偏移量，且所述多个处理电路中的每一个接收输入电压Vin后，依据输入电压Vin与各自的制程偏移量来产生各自的输出电压。如图1所示，位于第1行第1列的处理电路110 11所产生的输出电压可标示为输出电压Vout 11，而第2行第1列的处理电路110 21所产生的输出电压可标示为输出电压Vout 21，依此类推。转换电路120接收所述 多个处理电路(处理电路110 11、110 21…)中的每一个所产生的输出电压(输出电压Vout 11、Vout 21…)来产生识别码ID。
信号产生电路100可以应用于一芯片卡或包括射频芯片的电子装置中，信号产生电路100所产生的识别码ID代表所述芯片卡或所述电子装置的物理不可克隆识别码。
接续图1的实施例，图2是依据本申请一实施例之多个处理电路的示意图。如图2所示，信号产生电路100的所述多个处理电路(处理电路110 11、110 21…)中的每一个包括运算放大电路。如图1实施例所述，多个运算放大电路排列成N个列M个行，并且具有相对应的标号。举例来说，处理电路110 11包括运算放大电路OP 11而处理电路110 21包括运算放大电路OP 21，依此类推。每一个运算放大电路的一输入端接收输入电压Vin，并且依据输入电压Vin以及运算放大电路本身的制程偏移量产生输出电压。
接续图2的实施例，图3是依据本申请一实施例之多个处理电路组态为单一增益缓冲器的示意图。如图3所示，所述多个运算放大电路(运算放大电路OP 11、OP 21…)的每一个经组态为单一增益，换句话说，所述多个运算放大电路的每一个可视为单一增益缓冲器。依据单一增益缓冲器的电路特性，当单一增益缓冲器自输入端接收输入电压Vin后，会把输入电压Vin自输出端输出，然而由于制程偏移的关系，输出端上的输出电压将会与输入电压Vin有些许差异，所述差异即是由运算放大电路的制程偏移电压所造成，而每一个运算放大电路的制程偏移电压皆有所不同，使得每一个运算放大电路所产生的输出电压不同。每一运算放大电路的输出电压依据运算放大电路本身的制程偏移电压与输入电 压Vin产生。以运算放大电路OP 11为例，运算放大电路OP 11依据输入电压Vin以及本身的制程偏移电压Vos 11产生输出电压Vout 11，详细来说，输出电压Vout 11可表示为Vout 11＝输入电压Vin+制程偏移电压Vos 11，依此类推。如上所述，由于运算放大电路OP 11的制程偏移电压Vos 11与其他运算放大电路的制程偏移电压不同，因此输出电压Vout 11与其他输出电压不同，使得信号产生电路100可以依据多个不同的输出电压来产生识别码ID。
然而，图3所示仅为一范例说明，并非本发明的一限制，在其他实施例中所述多个运算放大电路可透过其他种方式组态为单一增益，或者，将所述多个运算放大电路组态为增益大于或小于1的放大器。图4是依据本申请一实施例之处理电路组态为增益大于或小于1的放大器的示意图。如图4所示，以处理电路110 11为例，处理电路110 11另包括电阻R 1和R 2，其中电阻R 1的一端点接收输入电压Vin，电阻R 1的另一端点耦接至运算放大电路OP 11的负输入端，电阻R 2的一端点耦接至运算放大电路OP 11的负输入端，电阻R 2的另一端点耦接至运算放大电路OP 11的输出端。运算放大电路OP 11的正输入端耦接至地，但由于制程偏移的关系，运算放大电路OP 11的正输入端可以等效为耦接至一电压源，所述电压源的电压值为运算放大电路OP 11的偏移电压Vos 11。在此组态下，运算放大电路OP 11的输出电压Vout以及输入电压Vin的关系可视为
Figure PCTCN2018116164-appb-000001
由此可知，通过电阻R 1和R 2的比値可以放大输入电压Vin以及偏移电压Vos 11的讯号，因此可将所述多个处理电路皆组态如图4所示的运算放大电路架构以放大讯号。
接续图3的实施例，图5是依据本申请一实施例之转换电路120的示意图。如图5所示，转换电路120包括模拟数字转换器410与特征撷取电路420。模拟数字转换器410耦接至所述多个处理电路110 11、110 21…，并依序地接收所述多个处理电路110 11、110 21…的每一个的输出电压(输出电压Vout 11、Vout 21…)，并对所接收到的每一个输出电压执行模拟数字转换操作，之后，依序地输出数字输出电压。举例来说，模拟数字转换器410接收来自处理电路110 11的输出电压Vout 11，对输出电压Vout 11执行所述模拟数字转换操作来产生数字输出电压D 11；模拟数字转换器410接收来自处理电路110 21的输出电压Vout 21，对输出电压Vout 21执行所述模拟数字转换操作来产生数字输出电压D 21，依此类推。可选地，模拟数字转换器410可以是逐次逼近型类比数位转换器。可选地，模拟数字转换器410可以是10位的逐次逼近型类比数位转换器。
特征撷取电路420依序地接收来自模拟数字转换电路410的数字输出电压(数字输出电压D 11、D 21…)并且依据多个数字输出电压来产生识别码ID。可选地，特征撷取电路420可以是尺度不变特征转换(Scale-invariant feature transform,SIFT)电路，用于对所述多个数字输出电压执行尺度不变特征转换操作，所述尺度不变特征转换是一种机器视觉的算法用来侦测与描述影像中的局部性特征，它在空间尺度中寻找极值点，并提取出其位置、尺度、旋转不变量。特征撷取电路420从所述多个数字输出电压(数字输出电压D 11、D 21…)得到多个数字输出电压的分布趋势，具体来说，当所述多个处理电路以N＊M二维分布时，对应的多个数字输出电压的分布趋势亦会形成具有高低数值起伏的N＊M二 维分布图，特征撷取电路420会依据所述输出电压的二维分布图来产生识别码ID。
在一实施例中，可将所述输出电压的二维分布图的最高点(例如所述多个数字输出电压中最大的输出电压)与最低点(例如所述多个数字输出电压中最小的输出电压)的相对应处理电路从N个列M个行中找出，并依据所述找出的处理电路的位置产生识别码ID。举例来说，可将对应最高点与最低点的处理电路在N个列M个行中的相对应坐标输出为识别码ID。举例来说，当N与M皆为64时，每一个运算放大电路在64＊64的阵列中的对应位置可以表示为6位的横坐标与6位的纵坐标，借此，特征撷取电路420在撷取所述分布趋势中的所述相对最高点与所述相对最低点所对应到的坐标后，将所有对应坐标输出为识别码ID。可选地，为避免误判，除了输出电压的二维分布图中的所述最高点与所述最低点之外，可以再依据输出电压的二维分布图的梯度变化来取得多个相对高点与低点并据以产生识别码ID。
可选地，图5所示的转换电路120还可包括复用器。如图6所示，转换电路120还包括复用器430，复用器430耦接于所述多个处理电路110 11、110 21…与模拟数字转换电路410之间，所述复用器依据控制信号CTRL将所述多个处理电路110 11、110 21…所产生的输出电压Vout 11、Vout 21…依序地输出至模拟数字转换电路410。可选地，控制信号CTRL可以由信号产生电路100以外的电路所产生。
接续图1的实施例，图7是依据本申请另一实施例之多个处理电路的示意图。如图7所示，信号产生电路100的所述多个处理电路(处理电路110 11、 110 21…)中的每一个包括比较电路。举例来说，处理电路110 11包括比较电路COM 11而处理电路110 21包括比较电路COM 21，依此类推。每一个比较电路的一输入端接收输入电压Vin，另一输入端接收一参考电压Vref并且依据输入电压Vin以及比较电路本身的制程偏移量产生输出电压。可选地，多个比较电路不需排列成阵列。
图8是依据本申请一实施例之判断比较电路的制程偏移电压的示意图。如图8所示，以比较电路COM 11为例，比较电路COM 11的正输入端接收输入电压Vin而负输入端接收参考电压Vref，起初，当输入电压Vin小于参考电压Vref时，比较电路COM 11的输出电压Vout 11为逻辑低电位(例如逻辑值’0’)；随着输入电压Vin上升，当输入电压Vin大于参考电压Vref时，理想状况下输出电压Vout 11应转换为逻辑高电位(例如逻辑值’1’)，然而，由于制程偏移的关系，输出电压Vout 11直到输入电压Vin上升至电压值为Vref+Vos 11时才转换为逻辑高电位，其中电压Vos 11即为比较电路COM 11的制程偏移电压。图8所示实施例中，比较电路COM 11的制程偏移电压Vos 11仅为一范例说明。可选地，比较电路COM 11的制程偏移电压Vos 11可以为负值，如此一来，当输入电压Vin尚未上升到参考电压Vref时，输出电压Vout 11即转换为逻辑高电位。在信号产生电路100出厂前，可以依据每一个比较电路的制程偏移电压将所述多个比较电路(例如比较电路COM 11与COM 21)分类为第一组、第二组及第三组，其中所述第一组中所包括的比较电路的制程偏移电压大于预设的第一阈值Vth1，所述第二组中所包括的比较电路的制程偏移电压小于预设的第二阈值Vth2，所述第三组中 所包括的比较电路的制程偏移电压大于所述第二阈值Vth2且小于所述第一阈值Vth1，其中第二阈值Vth2低于所述第一阈值Vth1。图9是依据本申请一实施例之比较电路的阈值分布的示意图，其中X轴表示阈值大小，Y轴表示比较电路的个数。如图9所示，所述多个比较电路(例如比较电路COM 11与COM 21)中制程偏移电压大于第一阈值Vth1的比较电路被分为所述第一组，所述多个比较电路中制程偏移电压小于第二阈值Vth2的比较电路被分为所述第二组，而所述多个比较电路中制程偏移电压大于第二阈值Vth2且小于第一阈值Vth1的比较电路分为所述第三组。可选地，所述多个比较电路(例如比较电路COM 11与COM 21)依照制程偏移电压分布的图形呈现高斯分布。可选地，第二阈值Vth2为小于0V的负值而第一阈值Vth1为大于0V的正值。
可选地，第一阈值Vth1与第二阈值Vth2的绝对值大于所述多个比较电路(例如比较电路COM 11、COM 21…)的噪声强度。电子组件中常见的噪声有热噪声、散射噪声、闪烁噪声与随机电报噪声，而第一阈值Vth1与第二阈值Vth2的绝对值大于所述多个比较电路(例如比较电路COM 11、COM 21…)中的每一比较电路所可能产生的所有噪声的强度。换句话说，第一阈值Vth1与第二阈值Vth2的绝对值大于每一比较电路的噪声水平(noise floor)。
回到图7的实施例，所述多个比较电路(例如比较电路COM 11、COM 21…)的一输入端接收输入电压Vin且另一输入端接收参考电压Vref。在此组态下，由于被分为所述第一组的比较电路的制程偏移电压大于第一阈值Vth1，并且第 一阈值Vth1大于噪声强度，在输入电压Vin与参考电压Vref等电位时，输出电压将会固定输出为逻辑低电位(如逻辑值0)；由于被分为所述第二组的比较电路的制程偏移电压小于第二阈值Vth2，并且第二阈值Vth2的绝对值大于噪声强度，在输入电压Vin与参考电压Vref等电位时，输出电压将会固定输出为逻辑高电位(如逻辑值1)。因此在实际操作时，用户将输入电压Vin给予与参考电压Vref相同的电位値，将可以使得被分为所述第一组的比较电路固定输出逻辑低电位而被分为所述第二组的比较电路固定输出逻辑高电位。
可选地，所述多个处理电路还可包括熔断器，用于搭配比较电路。在检验所述多个比较电路的制程偏移电压后，由于被分为所述第三组的比较电路其制程偏移电压可能小于比较电路的躁声强度，使得被分为所述第三组的比较电路在输入电压Vin与参考电压Vref等电位时，输出电压可能无法预测。因此在信号产生电路100出厂前，将划归为所述第三组的那些比较电路的熔断器熔断，使得被分为所述第三组的比较电路的输出电压仅会固定输出特定电压，所述特定电压可以是所述逻辑高电位或逻辑低电位，亦可以是不同于所述逻辑高电位或逻辑低电位的另一电位值以做区别。除外，由于被分为所述第一组及第二组的比较电路不会像所述第三组产生无法确定的输出，也就是所述第一组及第二组的比较电路会稳定输出所述逻辑低电位和所述逻辑高电位，因此，不需要对所述第一组及第二组的比较电路的熔断器进行熔断操作。
在此组态下，即便被分为所述第三组的比较电路的两输入端皆接收输入电压Vin，仍会固定输出所述特定电压。如此一来，所述多个比较电路(比较电路COM 11、COM 21…)在接收与参考电压Vref等电位的输入电压Vin时，各自有其固定输出的输出电压(输出电压Vout 11、Vout 21…)，使得转换电路120可依据所述多个比较电路的输出电压来产生识别码ID。所述将熔断器熔断可以包括透过 熔断器使被分为所述第三组的比较电路的输出电压固定为所述特定电压的任何方式。如图10所示，以比较电路COM 21为例，熔断器910接收比较电路COM 21的输出以及特定电压Vspec，并且熔断器910透过熔断信号Vfuse来控制。若在出厂前，检验所述多个比较电路的制程偏移电压后，得到比较电路COM 21的制程偏移电压高于第二阈值Vth2且低于第一阈值Vth1的结果，则比较电路COM 21将被分至所述第三组，因此，传送熔断信号Vfuse至比较电路COM 21所对应的熔断器910，借此将熔断器910熔断使得熔断器910仅会固定输出特定电压Vspec为输出电压Vout 21，因此，在出厂后使用者每一次使用时，被分为第三组的比较电路都会固定地输出特定电压Vspec。可选地，熔断器910是一以软件、硬件或固件所实现的电路架构，根据熔断信号Vfuse的控制来选择输出比较电路COM 21的输出或特定电压Vspec为输出电压Vout 21。
详细说明如下，由于被分为第一组和第二组的比较电路可以稳定输出所述逻辑低电位和逻辑高电位，并且通过将熔断器熔断，被分为第三组的比较电路也可以稳定输出特定电压，因此，所述多个比较电路皆能稳定输出一电位値，如此组态下，所述多个比较电路的输出电压产生稳定的识别码ID。此处不限定所述多个比较电路的输出电压的排列方式，只要应用信号产生电路100的电子装置与和其通讯的电子装置做好协议即可。
接续图7的实施例，图11是依据本申请另一实施例之转换电路120的示意图。如图11所示，转换电路120包括复用器MUX，用于依序地自所述多个比较电路(比较电路COM 11、COM 21…)接收输出电压(输出电压Vout 11、Vout 21…)，并依据控制信号CTRL'依序地将输出电压(输出电压Vout 11、Vout 21…)输出以产 生识别码ID。可选地，控制信号CTRL'可以由信号产生电路100以外的电路所产生。
图12是依据本申请一实施例之信号产生方法1200的流程图。倘若大体上可以得到相同的结果，本申请并不限定完全依照图12所示的步骤执行。信号产生方法1200可归纳如下:
步骤1202:取得多个运算放大电路。
步骤1204:将所述多个运算放大电路组态为单一增益缓冲器或增益大于或小于1的放大器。
步骤1206:读取所述多个运算放大电路的每一个的输出电压。
步骤1208:依据多个输出电压产生多个数字输出电压。
步骤1210:依据多个数字输出电压产生输出电压的分布趋势。
步骤1212:依据所述输出电压的分布趋势产生识别码。
熟悉本领域的技术人员在阅读完图2至图6的实施例后，应能轻易理解图12所示的信号产生方法1200，详细说明在此省略。
图13是依据本申请另一实施例之信号产生方法1300的流程图。倘若大体上可以得到相同的结果，本申请并不限定完全依照图13所示的步骤执行。信号产生方法1300可归纳如下:
步骤1302:取得多个比较电路。
步骤1304:依据所述多个比较电路中的每一个的制程偏移电压，将所述多个比较电路分为多组比较电路。
步骤1306:设置所述多组比较电路中的至少一组比较电路，使所述至少一组比较电路的输出电压为特定电压。
步骤1308:读取所述多个比较电路中的每一个的输出电压。
步骤1310:依据多个输出电压产生识别码。
熟悉本领域的技术人员在阅读完图7至图11的实施例后，应能轻易理解图13所示的信号产生方法1300，详细说明在此省略。
本发明的技术内容及技术特点已揭示如上，然而熟悉本领域的技术人员仍可能基于本发明的教示及揭示而作种种不背离本发明精神的替换及修饰。因此，本发明的保护范围应不限于实施例所揭示的内容，而应包括各种不背离本发明的替换及修饰，并为本专利申请权利要求书所涵盖。

Claims (20)

  1. 一种信号产生电路，用于产生识别码，其特征在于，包括:
    多个处理电路，其中每一处理电路具有各自的制程偏移量，且所述多个处理电路的每一处理电路接收输入电压，并依据所述输入电压以及每一处理电路的制程偏移量产生输出电压；及
    转换电路，用于依据所述多个处理电路的每一处理电路的输出电压产生所述识别码。
  2. 如权利要求1的信号产生电路，其特征在于，所述多个处理电路以阵列形式排列。
  3. 如权利要求1的信号产生电路，其特征在于，所述多个处理电路包括多个运算放大电路，其中每一个运算放大电路的输入端接收所述输入电压并在输出端输出所述输出电压。
  4. 如权利要求3的信号产生电路，其特征在于，所述多个运算放大电路经组态为多个单一增益缓冲器。
  5. 如权利要求4的信号产生电路，其特征在于，所述多个运算放大电路中的每一个依据所述输入电压以及对应运算放大电路的制程偏移量所贡献的制程偏移电压产生所述输出电压。
  6. 如权利要求1的信号产生电路，其特征在于，所述转换电路包括:
    模拟数字转换电路，耦接至所述多个处理电路中的每一个，其中所述模拟数字转换电路用于依据所述多个处理电路中的每一个的输出电压来产生数字输出电压。
  7. 如权利要求6的信号产生电路，其特征在于，所述转换电路还包括:
    特征撷取电路，耦接至模拟数字转换电路，其中所述特征撷取电路依据所述多个处理电路产生的输出电压产生分布趋势，以及依据所述分布趋势产生所述识别码。
  8. 如权利要求1的信号产生电路，其特征在于，所述多个处理电路包括多个比较电路，其中每一比较电路的输入端接收所述输入电压并于输出端输出所述输出电压。
  9. 如权利要求8的信号产生电路，其特征在于，所述多个比较电路包含第一组比较电路、第二组比较电路以及第三组比较电路，其中所述第一组比较电路中的每一比较电路的阈值大于第一阈值，所述第二组比较电路中的每一比较电路的阈值小于第二阈值，所述第三组比较电路中的每一比较电路的阈值大于所述第二阈值，并小于所述第一阈值，且第一阈值大于第二阈值。
  10. 如权利要求9的信号产生电路，其特征在于，所述第一阈值大于所述比较电路所产生的噪声强度，且所述第二阈值的绝对值大于所述比较电路所产生的所述噪声强度。
  11. 如权利要求9的信号产生电路，其特征在于，所述第三组比较电路中的每一比较电路的输出端耦接至特定电压。
  12. 如权利要求1-11任意一项的信号产生电路，其特征在于，所述转换电路包括:
    复用器，耦接于所述多个处理电路，其中所述复用器用于依序地将所述多个处理电路中的每一个的所述输出电压输出。
  13. 一种信号产生方法，用于产生识别码，其特征在于，包括:
    取得多个比较电路；
    依据所述多个比较电路中的每一个的制程偏移电压，将所述多个比较电路分为多组比较电路；
    设置所述多组比较电路中的至少一组比较电路，使所述至少一组比较电路的输出电压为特定电压；及
    读取所述多个比较电路中的每一个的输出电压。
  14. 如权利要求13的方法，其特征在于，所述依据所述多个比较电路中的每一个的制程偏移电压，将所述多个比较电路分为多组比较电路包括:
    依据所述多个比较电路中的每一个的制程偏移电压，将所述多个比较电路分为第一组比较电路、第二组比较电路以及第三组比较电路。
  15. 如权利要求14的方法，其特征在于，所述第一组比较电路中的每一比较电路的制程偏移电压大于第一阈值，所述第二组比较电路中的每一比较电路的制程偏移电压小于第二阈值，所述第三组比较电路中的每一比较电路的制程偏移电压大于所述第二阈值，并小于所述第一阈值，且第一阈值大于第二阈值。
  16. 如权利要求15的方法，其特征在于，所述第一阈值大于所述比较电路所产生的噪声强度，且所述第二阈值的绝对值大于所述比较电路所产生的所述噪声强度。
  17. 如权利要求15的方法，其特征在于，包括:
    将所述多个比较电路分别耦接至多个熔断器。
  18. 如权利要求17的方法，其特征在于，所述设置所述多组比较电路中的至少 一组比较电路，使所述至少一组比较电路的输出电压为特定电压包括:
    熔断所述至少一组比较电路对应的熔断器使所述至少一组比较电路的输出电压为特定电压。
  19. 如权利要求18的方法，其特征在于，所述熔断所述至少一组比较电路对应的熔断器包括:
    熔断所述第三组比较电路对应的熔断器。
  20. 如权利要求13的方法，另包括：
    依据所述多个比较电路中的每一个的输出电压来产生所述识别码。
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