WO2020098475A1 - 封装结构及其制造方法、半导体器件、电子设备 - Google Patents

封装结构及其制造方法、半导体器件、电子设备 Download PDF

Info

Publication number
WO2020098475A1
WO2020098475A1 PCT/CN2019/113881 CN2019113881W WO2020098475A1 WO 2020098475 A1 WO2020098475 A1 WO 2020098475A1 CN 2019113881 W CN2019113881 W CN 2019113881W WO 2020098475 A1 WO2020098475 A1 WO 2020098475A1
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
auxiliary
packaging structure
layer
structure according
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2019/113881
Other languages
English (en)
French (fr)
Inventor
杨清瑞
庞慰
孙晨
张孟伦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tianjin University
ROFS Microsystem Tianjin Co Ltd
Original Assignee
Tianjin University
ROFS Microsystem Tianjin Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tianjin University, ROFS Microsystem Tianjin Co Ltd filed Critical Tianjin University
Publication of WO2020098475A1 publication Critical patent/WO2020098475A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic elements; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/02007—Details of bulk acoustic wave devices
    • H03H9/02157—Dimensional parameters, e.g. ratio between two dimension parameters, length, width or thickness
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic elements; Electromechanical resonators
    • H03H9/02—Details
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic elements; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/02007—Details of bulk acoustic wave devices
    • H03H9/02047—Treatment of substrates
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic elements; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/05—Holders or supports
    • H03H9/10—Mounting in enclosures
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic elements; Electromechanical resonators
    • H03H9/02—Details
    • H03H9/05—Holders or supports
    • H03H9/10—Mounting in enclosures
    • H03H9/1007—Mounting in enclosures for bulk acoustic wave [BAW] devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic elements; Electromechanical resonators
    • H03H9/46—Filters
    • H03H9/54—Filters comprising resonators of piezoelectric or electrostrictive material

Definitions

  • Embodiments of the present invention relate to the field of semiconductors, and in particular, to a packaging structure for a semiconductor device and a manufacturing method thereof, a semiconductor device having the packaging structure, and an apparatus having the semiconductor device.
  • Thin film bulk wave resonators made by longitudinal resonance of piezoelectric thin films in the thickness direction have become a viable alternative to surface acoustic wave devices and quartz crystal resonators in wireless communication systems.
  • the working frequency of the thin film bulk acoustic resonator that usually constitutes the filter is usually at the GHz level, where the thickness of the core film layer is only micrometers or even nanometers, so the bare chip of the filter is extremely sensitive to the external environment, and the dust particles in the environment Water vapor, light and heat radiation, and mechanical shock can all cause the mechanical and electrical performance of the resonator to decline significantly. Therefore, isolating the filter from the outside world by constructing a certain protection structure is a necessary means to ensure the stable operation of the filter.
  • the substrate-level packaging structure is a commonly used packaging structure for protecting resonators.
  • the structure usually includes a functional substrate including a filter bare chip and a substrate packaging substrate for protecting the filter. In the packaging process, through the bonding process, the functional substrate and the packaging substrate are formed as a whole, thereby achieving the sealing protection of the filter bare chip.
  • Figures 1A-1E show a conventional package structure.
  • FIG. 1A is a schematic diagram of basic components of a conventional packaging structure.
  • the packaging structure includes a functional substrate F100 and a packaging substrate C100, wherein the top view of F100 is shown in FIG. 1B.
  • the main structure of the functional part shown in FIG. 1B includes an acoustic wave filter core part F201, a bonding layer part F203 (shaded part), and a base part F202.
  • the above structure is cut along the straight line AA 'to obtain a bonding cross-sectional structure as shown in FIG. 1C (this structure includes the package substrate C100).
  • FIG. 1C is the package cross-sectional structure shown in FIG. 1C
  • F212 is the base of the functional part
  • F211 is the filter core
  • F213 is the bonding layer metal
  • C111 is the package base
  • C111 has a protruding structure (gasket structure) on both sides, so that During packaging, a cavity C115 may be formed between the filter core and the packaging substrate.
  • FIG. 1D is an enlarged schematic view of the DT111 area in FIG. 1C.
  • C121 is a package substrate, C121 has a protruding structure C122; F312 is a functional substrate, the upper surface of which extends horizontally to both sides; the surface of the package substrate at the protrusion C122 and its vicinity is covered with a certain thickness of bonding layer metal BL121; The upper surface of F312 is also covered with a certain thickness of bonding metal layer BL122.
  • bonding the metal layers BL121 and BL122 are in contact with each other, and the metal atoms on the contact interface form metal bonds under the action of high temperature and high pressure so that the two layers of metal form a whole.
  • the problem with the conventional packaging structure shown in FIG. 1D is that the contact between the metal layer BL122 and the substrate F312 usually has a problem of insufficient strength due to defects formed by the process or adhesion of foreign particles in the environment, and the stress formed by some factors Under the influence, the BL122 part is easily peeled off from the substrate F312 (the P100 region shown in FIG. 1E) to form a gap (position shown by an arrow) in which water vapor and the like can invade.
  • the above-mentioned impurity particles and the surface defects of the substrate caused by the process may also exist, so that a plurality of tiny channels may be formed at the interface of the metal layer BL122 and the substrate in the area, and the external environment through these channels The water vapor can further enter the sealed cavity, which ultimately affects the performance of the resonator.
  • the present invention is proposed to alleviate or solve the deficiencies that still exist in the commonly used bonding package structure and improve the sealing effect of the package structure.
  • a bonding prevention auxiliary structure connected to the filter in the adhesion area of the substrate such as a stepped structure
  • the possibility of peeling of the adhesion layer from the substrate can be effectively reduced, thereby Improve the reliability of the package and improve the sealing effect.
  • a packaging structure for a semiconductor device includes a first substrate and a second substrate facing each other.
  • the packaging structure includes: suitable for being disposed on the first substrate Of the first adhesive layer, the first adhesive layer has a first adhesive area, the first adhesive area is adapted to be pressed to form a seal; and an anti-off auxiliary structure, the anti-off auxiliary structure is provided to the first substrate ,
  • the auxiliary anti-detachment structure is in contact with the edge of the substrate surface where the first adhesion area is located, and the surface roughness of at least a part of the auxiliary anti-detachment structure ranges from 10-80 nm, and the first adhesion layer is provided
  • the extension covers the at least a part of the anti-drop auxiliary structure.
  • the anti-falling auxiliary structure is formed with a stepped surface connected to the edge of the substrate surface corresponding to the adhesion area.
  • the range of the height of the stepped surface is 0.5-3.5 ⁇ m.
  • the stepped surface includes a vertical surface, and one side of the vertical surface is in contact with the corresponding base surface. Further optionally, the stepped surface further includes a horizontal plane, and the other side of the vertical plane is connected to the horizontal plane.
  • the stepped surface includes an inclined surface, and one side of the inclined surface is in contact with the corresponding base surface, and the inclined surface extends obliquely outward away from the corresponding base surface. Further optionally, the stepped surface further includes a horizontal plane, and the other side of the inclined plane is connected to the horizontal plane.
  • the angle formed by the inclined surface and the horizontal plane is in the range of 30 ° -80 °.
  • the width of the horizontal plane covered by the first adhesive layer has a value range of 10-50 ⁇ m.
  • the anti-detachment auxiliary structure is formed with a concave surface connected to the edge of the substrate surface where the adhesion area is located.
  • the concave surface includes a second inclined surface, a horizontal surface, and a first inclined surface that is in contact with the corresponding base surface, and the first inclined surface, the horizontal surface, and the second inclined surface are sequentially connected to form a cross section as A trapezoidal concave shape; or the concave surface includes a second inclined surface and a first inclined surface that is in contact with the corresponding base surface, and the first inclined surface and the second inclined surface are in contact to form a concave shape with a triangular cross-section; And the value range of the surface roughness of the first inclined surface is 10-80 nm.
  • the value range of the surface roughness of the second slope and / or the horizontal plane is 10-80 nm.
  • the surface of the substrate in the adhesion area that is in contact with the anti-detachment auxiliary structure has surface roughness, and the surface roughness has a value range of 10-80 nm.
  • the anti-off auxiliary structure has a first auxiliary inclined surface and a second auxiliary inclined surface which are respectively provided at two edges of the substrate surface where the first adhesion area is located; and the first auxiliary inclined surface has a surface roughness The surface of the base and the second auxiliary slope are successively connected to form a trapezoidal cross-section.
  • the thickness of the first adhesive layer covering the anti-detachment auxiliary structure has a value range of 0.5-1.5 ⁇ m.
  • the packaging structure further includes a second adhesive area adapted to be disposed on the second substrate, and the first adhesive area and the second adhesive area are adapted to be pressed against each other Bond to form a seal.
  • the second substrate is provided with a gasket structure protruding from the second substrate
  • the second adhesive layer is provided on the gasket structure
  • the first substrate is provided with the anti-off auxiliary structure and the The first adhesive layer is described.
  • the surface of the gasket structure opposite to the first adhesive layer is provided with a strip structure or a grid structure.
  • the cross section of the strip structure may have a trapezoidal shape with two sides oblique.
  • the substrate is made of single crystal silicon, gallium arsenide, sapphire, or quartz; the adhesion layer is made of gold, tungsten, molybdenum, platinum, ruthenium, iridium, germanium, copper, Titanium, titanium tungsten, aluminum, chromium, tin, arsenic doped gold, polydimethylsiloxane or polyurethane, or alloys or combinations thereof; and the adhesion layer is a bonding layer, the adhesion The area is a bonding area.
  • the packaging structure further includes an auxiliary bonding layer, and the auxiliary bonding layer is disposed between the substrate surface of the first substrate and the corresponding bonding layer.
  • the auxiliary bonding layer includes an aluminum nitride layer and a molybdenum layer that sequentially cover the surface of the substrate.
  • An embodiment of the present invention also relates to a method for manufacturing a packaging structure for a semiconductor device, the semiconductor device includes a first substrate and a second substrate facing each other, the method includes the steps of: forming an auxiliary anti-off structure on the first substrate , The anti-off auxiliary structure is in contact with the edge of the substrate surface where the first adhesion area on the first substrate is located, and the surface roughness of the bonded anti-off auxiliary structure takes a value of 10-80 nm; A first adhesive layer is provided on a substrate, the first adhesive layer extends to cover the first adhesive region and at least a part of the auxiliary auxiliary structure; and is pressed between the first substrate and the second substrate The first adhesion area to form a seal.
  • the method further includes the steps of: providing a second adhesive layer on the second substrate, the second adhesive layer having a second adhesive area suitable for bonding to the first adhesive area; and the step "Squeezing the first adhesion area between the first substrate and the second substrate to form a seal" includes squeezing the first adhesion area and the second adhesion area between the first substrate and the second substrate To form a seal.
  • the second substrate has a gasket structure protruding from the second substrate; the method further includes the step of providing a strip structure or a grid on the surface of the gasket structure facing the first substrate structure.
  • the cross section of the strip structure may have a trapezoidal shape with two sides oblique.
  • the anti-detachment auxiliary structure is formed with a stepped surface or a concave surface connected to the edge of the substrate surface where the first adhesion area is located.
  • the adhesion layer is a metal bonding layer
  • the adhesion area is a metal bonding area
  • An embodiment of the present invention also relates to a semiconductor device, including the above-mentioned packaging structure; a first substrate; a second substrate, which is arranged opposite to the first substrate, wherein: the packaging structure is provided on the first substrate and the first substrate Between the two substrates, the first substrate, the second substrate and the packaging structure enclose a receiving space.
  • the semiconductor device is a bulk acoustic wave filter.
  • Embodiments of the present invention also relate to an electronic device including the semiconductor device according to the above.
  • FIGS. 1A-1E are schematic diagrams of packaging structures in the prior art
  • FIG. 2 is a schematic diagram of a packaging structure according to an exemplary embodiment of the present invention.
  • FIG. 3 is a schematic diagram of a packaging structure according to another exemplary embodiment of the present invention.
  • FIG. 4 is a schematic diagram of a packaging structure according to still another exemplary embodiment of the present invention.
  • FIG. 5 is a schematic diagram of a packaging structure according to yet another exemplary embodiment of the present invention.
  • FIG. 6 is a schematic diagram of a packaging structure according to yet another exemplary embodiment of the present invention.
  • FIG. 7 is a schematic diagram of a packaging structure according to an exemplary embodiment of the present invention.
  • the embodiments of the present invention propose a packaging structure for semiconductor devices.
  • the semiconductor device includes opposing first substrate A200 and second substrate AC201
  • the packaging structure includes: a second bonding layer AL201 adapted to be disposed on the second substrate, the second bonding The layer has a second adhesion area S1; a first bonding layer AL202 adapted to be disposed on the first substrate, the first bonding layer has a first adhesion area S2, the second adhesion area and the first The adhesion areas are adapted to be bonded to each other to form a seal; and an anti-detachment auxiliary structure F provided to the first substrate A200, the anti-offset auxiliary structure F corresponding to the substrate surface S3 corresponding to the adhesion area
  • at least a part of the anti-detachment auxiliary structure has a surface roughness Ra, and the value range of Ra is 10-80 nm, and the corresponding bonding layer AL202 extends to cover the anti-detachment auxiliary
  • the surface roughness of the anti-detachment auxiliary structure may be 10 nm, 50 nm or 80 nm. At least a part of the anti-dropping auxiliary structure here means that not all anti-dropping auxiliary structures need to have a roughness in the range of 10-80 nm.
  • the roughness can be selected to be greater than 10 nm, and in order to reduce or prevent the formation of pores between the microscopic layer and the adhesive layer to reduce the contact area, the roughness can be selected to be less than 80nm.
  • AC200 is a packaging substrate or a packaging substrate
  • AC201 is a protrusion structure (gasket structure) on the packaging substrate.
  • the height of the protrusion structure is H201
  • the width is D202.
  • a bonding metal layer AL201 with a thickness of D201 is covered on the protrusion structure and the substrate near it.
  • H201 can be 8 ⁇ m, 15 ⁇ m, or 12 ⁇ m, H201 can range from 8-15 ⁇ m; D202 can be 25 ⁇ m, 32 ⁇ m, or 40 ⁇ m, and the range can be 25-40 ⁇ m; D201 can be 0.5 ⁇ m, 0.9 ⁇ m, or 1.5 ⁇ m, the range can be 0.5-1.5 ⁇ m.
  • AF200 is a functional substrate or a functional substrate on which an anti-off auxiliary structure F is provided; AF200 is covered with a bonding metal layer AL202 with a thickness of D200.
  • D200 may be 0.5 ⁇ m, 1.5 ⁇ m, 0.9 ⁇ m, and the range of D200 may be 0.5-1.5 ⁇ m.
  • the anti-off auxiliary structure F is formed with a stepped surface or a stepped structure connected to the edge of the substrate surface corresponding to the adhesion area.
  • the stepped surface includes a vertical surface, and one side of the vertical surface is in contact with the corresponding base surface S3. Further, the stepped surface may further include a horizontal plane, and the other side of the vertical plane is connected to the horizontal plane.
  • the width of the bonding layer covered on the horizontal plane is represented by D203, which can be 10 ⁇ m, 30 ⁇ m, or 50 ⁇ m, and its value range is 10-50 ⁇ m.
  • AC200 is a packaging substrate or a packaging substrate
  • AC201 is a protrusion structure (gasket structure) on the packaging substrate.
  • the height of the protrusion structure is H201
  • the width is D202.
  • a bonding metal layer AL201 with a thickness of D201 is covered on the protrusion structure and the substrate near it.
  • H201 is 8 ⁇ m, 15 ⁇ m or 12 ⁇ m, the range of H201 can be 8-15 ⁇ m; D202 can be 25 ⁇ m, 32 ⁇ m or 40 ⁇ m, the range can be 25-40 ⁇ m; D201 can be 0.5 ⁇ m, 0.9 ⁇ m or 1.5 ⁇ m, the range can be 0.5-1.5 ⁇ m.
  • AF200 is a functional substrate or a functional substrate, which has a stepped structure, and the height of the step, that is, the height of the vertical plane is H200;
  • H200 can be 0.5 ⁇ m, 2.0 ⁇ m or 3.5 ⁇ m, H200 can range from 0.5-3.5 ⁇ m;
  • D200 can be 0.5 ⁇ m, 1.5 ⁇ m or 0.9 ⁇ m, D200 can range from 0.5-1.5 ⁇ m.
  • the stepped structure or stepped surface or the later-mentioned recessed surface or recessed structure may be etched by reactive ion etching (RIE) process or deep silicon etching (DRIE) or wet etching using potassium hydroxide (KOH) aqueous solution Process formation.
  • RIE reactive ion etching
  • DRIE deep silicon etching
  • KOH potassium hydroxide
  • the ion reaction gases are C4F8 (flow rate range 100-600 sccm, preferably range 200-400 sccm) and SF6 (flow rate range 150-800 sccm, preferably range 400-500 sccm), and the reaction power is 50W-200W.
  • the vertical plane of the ladder is at right angles to the horizontal plane, and has a roughness Ra within the range of the shaded area shown in FIG. 3 (ie, the anti-off auxiliary structure F), and the value range of Ra is 10-80 nm.
  • the surface roughness of the anti-off auxiliary structure may be 10 nm, 50 nm or 80 nm.
  • the process of processing the stepped structure can increase the roughness of the processed surface so that the bonding layer material (gold, etc.) or the adhesion material layer can be better adhered On the surface of the functional substrate.
  • the stepped structure can provide a larger contact area with the bonding layer material or the adhesion layer material than the conventional straight structure.
  • AC300 is a packaging substrate or a packaging substrate
  • AC301 is a gasket structure or a protruding structure on the packaging substrate.
  • the height of the gasket structure is H301 and the width is D302
  • the bonding structure metal layer AL301 with a thickness of D301 is covered on the protrusion structure and the substrate nearby.
  • H301 is 8 ⁇ m, 15 ⁇ m or 12 ⁇ m, the range of H301 can be 8-15 ⁇ m; D302 can be 25 ⁇ m, 32 ⁇ m or 40 ⁇ m, the range can be 25-40 ⁇ m; D301 can be 0.5 ⁇ m, 1.5 ⁇ m or 0.9 ⁇ m, the range of D301 can be 0.5-1.5 ⁇ m.
  • the end surface of the washer structure AC301 further has a strip-shaped or mesh-shaped protrusion structure, and each strip-shaped protrusion has a trapezoid shape with two sides oblique.
  • the width of the trapezoidal median line is D305
  • the spacing between adjacent trapezoidal structures is D306.
  • D305 may be 1 ⁇ m, 2 ⁇ m or 3 ⁇ m
  • the value range may be 1-3 ⁇ m
  • D306 may be 1 ⁇ m, 2 ⁇ m or 3 ⁇ m
  • the value range may be 1-3 ⁇ m
  • the trapezoidal height is H302
  • H302 can be 1 ⁇ m, 2 ⁇ m or 3 ⁇ m, and its value range can be 1-3 ⁇ m.
  • AF300 is a functional substrate, which has a stepped structure, which constitutes an anti-off auxiliary structure F, with a step height of H300; AF300 is sequentially covered with an aluminum nitride layer AL304 with a thickness of D304, a molybdenum layer AL303 with a thickness of D303, and The gold layer AL302 with a thickness of D300.
  • H300 may be 0.5 ⁇ m, 2.0 ⁇ m, or 3.5 ⁇ m, and the range may be 0.5-3.5 ⁇ m; D304 may be or Its range can be D303 can be 0.1 ⁇ m, 0.6 ⁇ m or 0.8 ⁇ m, the range can be 0.1 ⁇ m-0.8 ⁇ m; D300 can be 0.5 ⁇ m, 1.5 ⁇ m or 0.9 ⁇ m, the range can be 0.5-1.5 ⁇ m.
  • the vertical structure of the stepped structure or the stepped surface is at right angles to the horizontal plane, and has a roughness Ra within the shaded area of the diagonal line shown in FIG. 4 (corresponding to the anti-offset auxiliary structure F).
  • the value range of Ra is 10- 80nm.
  • the surface roughness of the anti-off auxiliary structure may be 10 nm, 50 nm or 80 nm.
  • the width of the bonding layer covered on the horizontal plane is represented by D303, which can be 10 ⁇ m, 30 ⁇ m, or 50 ⁇ m, and the value range is 10-50 ⁇ m.
  • the material (such as gold) of the bonding layer located at the uppermost layer can more completely cover the side walls of the molybdenum layer and the aluminum nitride layer located below it.
  • AC400 is a packaging substrate or a packaging substrate
  • AC401 is a gasket structure on the packaging substrate
  • the height of the structure is H401
  • the width is D402
  • the bonding structure of the thickness D401 is covered on the gasket structure and the nearby substrate Metal layer AL401.
  • the range of H401 is 8-15 ⁇ m; the range of D402 is 25-40 ⁇ m; the range of D401 is 0.5-1.5 ⁇ m.
  • the value range of the above parameter is the same as or similar to the value or value range of the corresponding parameter in FIG. 4.
  • the end surface of the washer structure AC401 further has a strip-shaped or mesh-shaped protrusion structure, and each protrusion has a trapezoidal cross-sectional structure with two oblique sides.
  • the width of the trapezoidal median line is D405, and the spacing between adjacent trapezoidal structures is D406.
  • the range of D405 is 1-3 ⁇ m; the range of D406 is 1-3 ⁇ m; the trapezoid height is H402, and the value range of H402 is 1-3 ⁇ m.
  • the dimensions of the strip-like or mesh-like protrusion structure on the end surface of the washer structure AC401 are the same as or similar to the embodiment in FIG. 4.
  • AF400 is a functional substrate or a functional substrate, which has a stepped structure with a step height of H400; AF400 is sequentially covered with an aluminum nitride layer AL404 with a thickness of D404, a molybdenum layer AL403 with a thickness of D403 and a gold layer AL402 with a thickness of D400 .
  • the range of H400 is 0.5-3.5 ⁇ m; the range of D404 D403 range is 0.1 ⁇ m-0.8 ⁇ m; D400 range is 0.5-1.5 ⁇ m.
  • the value range of the above parameter is the same as or similar to the value or value range of the corresponding parameter in FIG. 4.
  • the inclined structure of the stepped structure or stepped surface is at an angle AG400 with the horizontal plane, and the value range of AG400 is 45 ° -80 °, furthermore, within the range of 50 ° -70 °;
  • the range of the shaded area (corresponding to the auxiliary structure for preventing detachment F) has roughness Ra, and the value range of Ra is 10-80 nm.
  • the surface roughness of the anti-off auxiliary structure may be 10 nm, 50 nm or 80 nm.
  • the anti-falling auxiliary structure F includes an inclined surface, one side of the inclined surface is in contact with the corresponding base surface S3, and the inclined surface extends obliquely outward away from the corresponding base surface.
  • the anti-drop auxiliary structure further includes a horizontal plane, and the other side of the inclined plane is connected to the horizontal plane.
  • the width of the bonding layer covered on the horizontal plane is represented by D403, and D403 may be 10 ⁇ m, 30 ⁇ m, or 50 ⁇ m, and its value range is 10-50 ⁇ m.
  • AC500 is a packaging substrate or a packaging substrate
  • AC501 is a gasket structure on the packaging substrate
  • the height of the gasket structure is H501
  • the width is D502
  • the bonding structure metal layer AL501 with a thickness of D501 is covered on the protrusion structure and the substrate nearby.
  • the range of H501 is 8-15 ⁇ m
  • the range of D502 is 25-40 ⁇ m
  • the range of D501 is 0.5-1.5 ⁇ m.
  • the value range of the above parameter is the same as or similar to the value or value range of the corresponding parameter in FIG. 4.
  • the end surface of the gasket structure AC501 further has a strip-shaped or mesh-shaped protrusion structure, and each protrusion has a trapezoidal cross-sectional structure with two oblique sides.
  • the width of the trapezoidal median line is D505, and the spacing between adjacent trapezoidal structures is D506.
  • the range of D505 is 1-3 ⁇ m; the range of D506 is 1-3 ⁇ m; the trapezoid height is H502, and the value range of H502 is 1-3 ⁇ m.
  • the dimensions of the strip-like or mesh-like protrusion structures on the end surface of the washer structure AC501 are the same as or similar to the embodiment in FIG. 4.
  • AF500 is a functional substrate or a functional substrate, as shown in FIG. 6, which has a groove structure or a concave surface, the structure has an inverted isosceles trapezoidal cross section, the height of the trapezoid is H500, the width of the bottom of the trapezoid is D507, the width of the upper bottom It is D508; AF500 is sequentially covered with an aluminum nitride layer AL504 with a thickness of D504, a molybdenum layer AL503 with a thickness of D503 and a gold layer AL502 with a thickness of D500.
  • the D504 range The range of D503 is 0.1 ⁇ m-0.8 ⁇ m; the range of D500 is 0.5-1.5 ⁇ m, the specific value is the same as or similar to the embodiment in FIG. 4.
  • H500 may be 0.5 ⁇ m, 2.0 ⁇ m or 3.5 ⁇ m, and its value range may be 0.5-3.5 ⁇ m.
  • D507 may be 2 ⁇ m, 5 ⁇ m, or 8 ⁇ m, and its value range may be 2-8 ⁇ m; D508 is greater than D507.
  • the surface roughness of the anti-off auxiliary structure may be 10 nm, 50 nm or 80 nm.
  • the detachment prevention auxiliary structure F is formed with a concave surface connected to the edge of the substrate surface S3 corresponding to the adhesion area.
  • the concave surface includes a second inclined surface, a horizontal surface, and a first inclined surface that is in contact with the corresponding substrate surface, and the first inclined surface, the horizontal surface, and the second inclined surface are sequentially connected to A concave shape with a trapezoidal cross section is formed.
  • the concave surface includes a second inclined surface and a first inclined surface that is in contact with the corresponding base surface, and the first inclined surface is in contact with the second inclined surface to form a concave shape with a substantially triangular cross-section.
  • the surface roughness of the first inclined surface is greater than the surface roughness of the surface of the corresponding substrate.
  • the surface roughness of the second slope and / or the horizontal plane is greater than the surface roughness of the corresponding bonding surface.
  • AC600 is a packaging substrate or a packaging substrate
  • AC601 is a gasket structure on the packaging substrate
  • the height of the gasket structure is H601
  • the width is D602
  • a bonding metal layer AL601 with a thickness of D601 is covered on the gasket structure and the substrate nearby .
  • the range of H601 is 8-15 ⁇ m
  • the range of D602 is 25-40 ⁇ m
  • the range of D601 is 0.5-1.5 ⁇ m.
  • the value range of the above parameter is the same as or similar to the value or value range of the corresponding parameter in FIG. 4.
  • the end surface of the washer structure AC601 further has a strip-shaped or mesh-shaped protrusion structure, each protrusion has a trapezoidal cross-sectional structure with two oblique sides.
  • the width of the trapezoidal median line is D605, and the spacing between adjacent trapezoidal structures is D606.
  • the range of D605 is 1-3 ⁇ m; the range of D606 is 1-3 ⁇ m; the trapezoid height is H602, and the value range of H602 is 1-3 ⁇ m.
  • the dimensions of the strip-like or mesh-like protrusion structure on the end surface of the washer structure AC601 are the same as or similar to the embodiment in FIG. 4.
  • AF600 is a functional substrate or a functional substrate, which has a groove structure with an inverted isosceles trapezoidal cross-section, the trapezoid height is H600, the trapezoid bottom width is D607, and the top bottom width is D608.
  • the AF600 is sequentially covered with an aluminum nitride layer AL604 having a thickness of D604, a molybdenum layer AL603 having a thickness of D603, and a gold layer AL602 having a thickness of D600.
  • the D604 range D603 range is 0.1 ⁇ m-0.8 ⁇ m; D600 range is 0.5-1.5 ⁇ m.
  • the value range of the above parameter is the same as or similar to the value or value range of the corresponding parameter in FIG. 4.
  • H600 may be 0.5 ⁇ m, 2.0 ⁇ m, or 3.5 ⁇ m, and the range may be 0.5-3.5 ⁇ m.
  • D607 is larger than D602, for example, about 8-15 ⁇ m; D608 is larger than D607.
  • the surface roughness of the anti-off auxiliary structure may be 10 nm, 50 nm or 80 nm.
  • the anti-off auxiliary structure F has a first auxiliary inclined surface and a second auxiliary inclined surface which are respectively provided at both edges of the substrate surface where the adhesion area is located; and the first auxiliary inclined surface 1.
  • the base surface with the surface roughness and the second auxiliary inclined surface are sequentially connected to form a trapezoidal cross section.
  • the base surface between the first auxiliary slope and the second auxiliary slope also has a corresponding surface roughness
  • the base surface between the two auxiliary slopes may not be provided with a corresponding Surface roughness
  • the substrate or the material of the substrate may be selected but not limited to: single crystal silicon (Si), gallium arsenide (GaAs), sapphire, quartz, etc.
  • the material of the metal bonding layer can be selected but not limited to: gold (Au), titanium, titanium tungsten, chromium, tin, lead, etc.
  • Au gold
  • Ti titanium
  • Ti tungsten titanium
  • chromium titanium
  • tin titanium
  • lead etc.
  • the process parameters of the package are mainly described in metal gold (Au). However, these process parameters can also be applied to other metals, such as tin and lead.
  • the above embodiment of forming a package seal by metal bonding has described the present invention, but the present invention is not limited to metal bonding.
  • the metal bonding layer in the above case may be an adhesive layer.
  • the adhesive layer Non-metal materials such as adhesives such as polydimethylsiloxane, benzocyclobutene (BCB) or polyurethane can also be used.
  • the adhesion layer may be gold, tungsten, molybdenum, platinum, ruthenium, iridium, germanium, copper, titanium, titanium tungsten, aluminum, chromium, tin, arsenic doped gold, polydimethylsiloxane or Made of polyurethane, or its alloy or combination
  • the bonding layer is provided on both the first substrate and the second substrate.
  • an adhesion layer or a bonding layer may also be provided on one substrate, and the anti-detachment auxiliary structure is provided on the one substrate.
  • the present invention proposes a packaging structure for a semiconductor device, the semiconductor device includes a first substrate and a second substrate facing each other, the packaging structure includes: a first adhesion suitable for being disposed on the first substrate Layer, the first adhesion layer has a first adhesion area, the first adhesion area is adapted to be pressed to form a seal; and an anti-off auxiliary structure provided to the first substrate, the anti-off The auxiliary structure is in contact with the edge of the substrate surface where the first adhesion area is located, and the surface roughness of at least a part of the auxiliary prevention structure ranges from 10-80 nm, and the first adhesion layer is provided to extend to cover the The at least a part of the anti-off auxiliary structure.
  • the first substrate and the second substrate are just numbers for the substrates, and do not limit which of the opposed substrates the anti-drop auxiliary structure is provided on.
  • the edge of the surface of the substrate where the first adhesion area is located means the edge or boundary on the corresponding substrate where the package sealing area is formed.
  • connection between the auxiliary auxiliary prevention structure and the “edge of the substrate surface where the first adhesion area is located” means that the auxiliary auxiliary prevention structure is directly connected to or adjacent to the edge, which is within the protection scope of the invention.
  • the anti-detachment auxiliary structure can prevent or reduce the risk of the bonding layer or the adhesive layer detaching from the substrate.
  • the present invention also proposes a method for manufacturing a packaging structure for a semiconductor device, the method includes the steps of: forming an auxiliary anti-off structure on the first substrate, and the auxiliary anti-off structure and the first substrate The edges of the substrate surface where the first adhesion area is located are in contact, and the surface roughness of the bonding prevention auxiliary structure ranges from 10-80 nm; a first adhesion layer is provided on the first substrate, The first adhesion layer extends to cover the first adhesion area and at least a part of the anti-detachment auxiliary structure; and the first adhesion area is pressed between the first substrate and the second substrate to form a seal .
  • the method further includes the steps of: providing a second adhesive layer on the second substrate, the second adhesive layer having a second adhesive area suitable for bonding to the first adhesive area; and the step "Squeezing the first adhesion area between the first substrate and the second substrate to form a seal" includes squeezing the first adhesion area and the second adhesion area between the first substrate and the second substrate To form a seal.
  • the second substrate has a gasket structure protruding from the second substrate; the method further includes the step of providing a strip structure or a grid on the surface of the gasket structure facing the first substrate structure.
  • the anti-detachment auxiliary structure is formed with a stepped surface or a concave surface connected to the edge of the substrate surface where the first adhesion area is located.
  • the adhesion layer is a metal bonding layer, and the adhesion area is a metal bonding area.
  • the packaging structure of the present invention can be applied to the packaging of semiconductor devices, for example, can be applied to the packaging of radio frequency filters, and can also be used in the packaging structure of other MEMS components.
  • the embodiments of the present invention also relate to a semiconductor device including the above-mentioned packaging structure; a first substrate; a second substrate, which is arranged opposite to the first substrate, wherein: the packaging structure is provided on the first Between the substrate and the second substrate, the first substrate, the second substrate and the packaging structure enclose a receiving space.
  • the semiconductor device is a bulk acoustic wave filter.
  • the embodiments of the present invention also relate to an electronic device including the above-mentioned semiconductor device.

Landscapes

  • Physics & Mathematics (AREA)
  • Acoustics & Sound (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Micromachines (AREA)

Abstract

一种半导体器件用封装结构及其制造方法，以及一种具有上述半导体器件的电子设备。所述半导体器件包括对置的第一晶圆与第二晶圆，所述封装结构包括：适于设置在第一晶圆上的第一键合层（AL202），第一键合层（AL202）具有第一键合区；适于设置在第二晶圆上的第二键合层（AL201），第二键合层（AL201）具有第二键合区，所述第一键合区与所述第二键合区适于彼此键合以形成密封；以及防脱辅助结构（F），所述防脱辅助结构（F）设置到第一晶圆和/或第二晶圆，所述防脱辅助结构（F）与键合区所在的晶圆表面的边缘相接，且所述防脱辅助结构（F）至少一部分的表面粗糙度的取值范围为10-80nm，对应的键合层延伸覆盖所述防脱辅助结构。

Description

封装结构及其制造方法、半导体器件、电子设备 技术领域
本发明的实施例涉及半导体领域，尤其涉及一种半导体器件用封装结构及其制造方法，一种具有该封装结构的半导体器件，以及一种具有该半导体器件的设备。
背景技术
近年来，基于硅材料的半导体器件、尤其是集成电路芯片取得了飞速的发展，已经牢牢占据了产业的主流地位。利用压电薄膜在厚度方向的纵向谐振所制成的薄膜体波谐振器，在无线通信系统中己成为声表面波器件和石英晶体谐振器的一个可行的替代。
通常构成滤波器的薄膜体声波谐振器的工作频率通常在GHz级别，其中核心膜层的厚度仅为微米甚至纳米级别，因此滤波器裸芯片对外界环境的影响极其敏感，环境中的尘埃颗粒，水汽，光热辐射，机械冲击都可能造成谐振器的机电性能大幅下滑。因此通过构建一定的保护结构将滤波器与外界进行隔离是确保滤波器稳定工作的必要手段。基底级封装结构是一种常用的用于保护谐振器的封装结构，该结构通常包含滤波器裸芯片在内的功能基底和用于保护滤波器的基底封装基底。在封装过程中通过键合工艺，使功能基底与封装基底形成一个整体，从而实现滤波器裸芯片的密封保护。
图1A-1E示出了传统的封装结构。
图1A为传统封装结构的基本组成部分示意图。如图1A所示，封装结构包含功能基底F100和封装基底C100，其中，F100的俯视图如图1B所示。图1B所示的功能部分的主要结构包含声波滤波器核心部分F201，键合层部分F203(阴影部分)，以及基底部分F202。沿着直线AA’将上述结构剖开，可得到如图1C所示的键合剖面结构(该结构包含了封装基底C100)。
图1C所示的封装剖面结构中，F212为功能部分的基底，F211为滤波器核心，F213为键合层金属，C111为封装基底，并且C111的两侧具有突起结构(垫圈结构)，从而在封装时可在滤波器核心和封装基底之间形成空腔C115。图1D为图1C中DT111区域的放大示意图。其中C121为封装基底，C121具有突起结构C122；F312为功能基底，其上表面水平向两侧延伸；在突起C122以及其附近的封装基底表面覆盖有一定厚度的键合层金属BL121；在功能基底F312上表面同样覆盖一定厚度的键合金属层BL122。进行键合时，金属层BL121和BL122相互接触，其接触界面上的金属原子之间在高温高压作用下形成金属键从而使两层金属形成一个整体。
但是，图1D所示的传统封装结构存在的问题是：金属层BL122与基底F312的接触通常会 因为工艺形成的缺陷或环境中的杂质微粒附着而存在强度不足的问题，在一些因素形成的应力影响下容易导致BL122部分从基底F312剥离(如图1E所示的P100区域)而形成可供水汽等侵入的间隙(箭头所示位置)。而在粘附区域P101内，上述杂质微粒和工艺造成的基底表面缺陷同样可能存在，这样就可能在该区域内的金属层BL122与基底的界面处形成多个微小的通道，通过这些通道外界环境的水汽可进一步进入密封腔，最终影响谐振器的性能。
目前常用的键合式封装结构中尚存在一些不足，这些问题通常会引起滤波器件封装可靠性下降。
发明内容
为缓解或解决目前常用的键合式封装结构中尚存在的不足，提高封装结构的密封效果，提出本发明。
在本发明的实施例中，通过在滤波器所在的基底的粘附区域构建与之相连的键合防脱辅助结构，例如阶梯类结构，可有效降低粘附层从基底剥落的可能性，从而提高封装的可靠性，提高了密封效果。
根据本发明的实施例的一个方面，提出了一种半导体器件用封装结构，所述半导体器件包括对置的第一基底与第二基底，所述封装结构包括：适于设置在第一基底上的第一粘附层，第一粘附层具有第一粘附区，第一粘附区适于被挤压以形成密封；以及防脱辅助结构，所述防脱辅助结构设置到第一基底，所述防脱辅助结构与第一粘附区所在的基底表面的边缘相接，且所述防脱辅助结构的至少一部分的表面粗糙度取值范围为10-80nm，第一粘附层设置成延伸覆盖所述防脱辅助结构的所述至少一部分。
在可选的实施例中，所述防脱辅助结构形成有与粘附区对应的基底表面的边缘相连的阶梯面。可选的，所述阶梯面的高度的取值范围为0.5-3.5μm。
可选的，所述阶梯面包括竖直面，所述竖直面的一侧与所述对应基底表面相接。进一步可选的，所述阶梯面还包括水平面，所述竖直面的另一侧与所述水平面相接。
可选的，所述阶梯面包括斜面，所述斜面的一侧与所述对应基底表面相接，所述斜面远离所述对应基底表面向外倾斜延伸。进一步可选的，所述阶梯面还包括水平面，所述斜面的另一侧与所述水平面相接。可选的，所述斜面与所述水平面所形成的角度在30°-80°的范围内。
在本发明中，可选的，所述水平面被第一粘附层覆盖的宽度的取值范围为10-50μm。
在另一可选的实施例中，所述防脱辅助结构形成有与粘附区所在的基底表面的边缘相连的凹陷面。
可选的，所述凹陷面包括第二斜面、水平面以及与所述对应基底表面相接的第一斜面，所述第一斜面、所述水平面与所述第二斜面依次相接以形成截面为梯形的凹陷形状；或者所述凹陷面包括第二斜面以及与所述对应基底表面相接的第一斜面，所述第一斜面与所述第二斜面相接以形成截面为三角形的凹陷形状；且所述第一斜面的表面粗糙度的取值范围为10-80nm。
进一步可选的，所述第二斜面和/或所述水平面的表面粗糙度的取值范围为10-80nm。
可选的，在上述封装结构中，位于粘附区域内的与所述防脱辅助结构相接的基底表面具有表面粗糙度，且表面粗糙度的取值范围为10-80nm。
进一步的，所述防脱辅助结构具有分别设置在第一粘附区所在的基底表面的两侧边缘处的第一辅助斜面和第二辅助斜面；且所述第一辅助斜面、具有表面粗糙度的所述基底表面、所述第二辅斜面依次相接以构成截面为梯形的形状。
可选的，上述封装结构中，覆盖所述防脱辅助结构的第一粘附层的厚度的取值范围为0.5-1.5μm。
可选的，上述封装结构中，所述封装结构还包括适于设置在第二基底上的第二粘附区，所述第一粘附区与所述第二粘附区适于彼此挤压粘接以形成密封。进一步的，所述第二基底设置有自第二基底凸出的垫圈结构，所述第二粘附层设置在所述垫圈结构上，所述第一基底设置有所述防脱辅助结构和所述第一粘附层。可选的，所述垫圈结构与所述第一粘附层相对的表面设置有条状结构或者网格状结构。所述条状结构的截面可具有两条边为斜边的梯形形状。
可选的，在上述封装结构中，所述基底由单晶硅、砷化镓、蓝宝石或石英制成；所述粘附层由金、钨、钼、铂、钌、铱、锗、铜、钛、钛钨、铝、铬、锡、砷掺金、聚二甲基硅氧烷或聚氨酯制成，或其合金或组合制成；且所述粘附层为键合层，所述粘附区为键合区。进一步的，所述封装结构还包括辅助键合层，所述辅助键合层设置在第一基底的所述基底表面与对应的键合层之间。可选的，所述辅助键合层包括依次覆盖在基底表面的氮化铝层和钼层。
本发明的实施例还涉及一种半导体器件用封装结构的制造方法，所述半导体器件包括对置的第一基底与第二基底，所述方法包括步骤：在第一基底上形成防脱辅助结构，防脱辅助结构与第一基底上的第一粘附区所在的基底表面的边缘相接，且所述键合防脱辅助结构的表面粗糙度的取值范围为为10-80nm；在第一基底上设置第一粘附层，所述第一粘附层延伸覆盖所述第一粘附区以及所述防脱辅助结构的至少一部分；和在第一基底与第二基底之间挤压所述第一粘附区以形成密封。
可选的，所述方法还包括步骤：在第二基底上设置第二粘附层，所述第二粘附层具有适于与第一粘附区粘接的第二粘附区；且步骤“在第一基底与第二基底之间挤压所述第一粘附区以形成 密封”包括在第一基底与第二基底之间挤压所述第一粘附区和第二粘接区以形成密封。
可选的，所述第二基底上具有自第二基底凸出的垫圈结构；所述方法还包括步骤：在所述垫圈结构的面对第一基底的表面上设置条状结构或者网格状结构。所述条状结构的截面可具有两条边为斜边的梯形形状。
可选的，所述防脱辅助结构形成有与第一粘附区所在的基底表面的边缘相连的阶梯面或者凹陷面。
可选的，所述粘附层为金属键合层，且所述粘附区为金属键合区。
本发明的实施例还涉及一种半导体器件，包括上述的封装结构；第一基底；第二基底，与第一基底相对布置，其中：所述封装结构设置在所述第一基底与所述第二基底之间，第一基底、第二基底与封装结构围合成容纳空间。可选的，所述半导体器件为体声波滤波器。
本发明的实施例也涉及一种电子设备，包括根据上述的半导体器件。
附图说明
以下描述与附图可以更好地帮助理解本发明所公布的各种实施例中的这些和其他特点、优点，图中相同的附图标记始终表示相同的部件，其中：
图1A-图1E为现有技术中封装结构的示意图；
图2为根据本发明的一个示例性实施例的封装结构的示意图；
图3为根据本发明的另一个示例性实施例的封装结构的示意图；
图4为根据本发明的还一个示例性实施例的封装结构的示意图；
图5为根据本发明的再一个示例性实施例的封装结构的示意图；
图6为根据本发明的又一个示例性实施例的封装结构的示意图；
图7为根据本发明的一个示例性实施例的封装结构的示意图。
具体实施方式
下面通过实施例，并结合附图，对本发明的技术方案作进一步具体的说明。在说明书中，相同或相似的附图标号指示相同或相似的部件。下述参照附图对本发明实施方式的说明旨在对本发明的总体发明构思进行解释，而不应当理解为对本发明的一种限制。
下面参照附图2-7以金属键合形成封装为例描述根据本发明的实施例的半导体器件用封装结构。
发明人发现，为了增强键合层与基底之间的附着力，避免或者减少图1E中的问题，防止或者减少键合层从基底脱落，可以通过刻蚀基底上与粘附区域相接的地方以增加该处的表面粗糙度。
基于此，本发明的实施例提出了一种半导体器件用封装结构。如图2所示，所述半导体器件包括对置的第一基底A200与第二基底AC201，所述封装结构包括：适于设置在第二基底上的第二键合层AL201，第二键合层具有第二粘附区S1；适于设置在第一基底上的第一键合层AL202，第一键合层具有第一粘附区S2，所述第二粘附区与所述第一粘附区适于彼此键合以形成密封；以及防脱辅助结构F，所述防脱辅助结构F设置到第一基底A200，所述防脱辅助结构F与粘附区对应的基底表面S3相接，且所述防脱辅助结构至少一部分具有表面粗糙度Ra，Ra的取值范围10-80nm，对应的键合层AL202延伸覆盖所述防脱辅助结构F。
在更具体的实施例中，所述防脱辅助结构的表面粗糙度可以为10nm，50nm或者80nm。这里的防脱辅助结构至少一部分表示并非所有的防脱辅助结构都需要具有10-80nm范围内的粗糙度。
为了在微观上提供足够的与粘附材料接触的面积，粗糙度可选择为大于10nm，而为了减少或者防止在微观上与粘附层之间形成孔隙而降低接触面积，粗糙度可选择为小于80nm。图2中，AC200为封装基底或者封装基底，AC201为封装基底上的突起结构(垫圈结构)。在可选的实施例中，该突起结构的高度为H201，宽度为D202。如图2所示，在突起结构和其附近的基底上覆盖有厚度为D201的键合金属层AL201。在可选的实施例中，H201可为8μm、15μm或12μm，H201的范围可是8-15μm；D202可为25μm、32μm或者40μm，范围可是25-40μm；D201可为0.5μm、0.9μm或1.5μm，其范围可为0.5-1.5μm。
AF200为功能基底或者功能基底，其上设置有防脱辅助结构F；AF200上覆盖有厚度为D200的键合金属层AL202。在可选的实施例中，D200可以为0.5μm、1.5μm、0.9μm，D200的范围可为0.5-1.5μm。
如图3-5所示，所述防脱辅助结构F形成有与粘附区对应的基底表面的边缘相连的阶梯面或者阶梯结构。
下面参照附图3描述根据本发明的一个示例性实施例。如图3所示，该阶梯面包括竖直面，所述竖直面的一侧与所述对应基底表面S3相接。进一步的，所述阶梯面还可包括水平面，所述竖直面的另一侧与所述水平面相接。该水平面上覆盖的键合层的宽度以D203表示，D203可以为10μm、30μm或者50μm，其取值范围为10-50μm。
图3中，AC200为封装基底或者封装基底，AC201为封装基底上的突起结构(垫圈结构)。在可选的实施例中，该突起结构的高度为H201，宽度为D202。如图3所示，在突起结构和其附近的基底上覆盖有厚度为D201的键合金属层AL201。在可选的实施例中，H201为8μm、15μm或12μm，H201的范围可为8-15μm；D202可为25μm、32μm或者40μm，范围可是25-40μm；D201可为0.5μm、0.9μm或1.5μm，其范围可为0.5-1.5μm。
AF200为功能基底或者功能基底，其上具有一阶梯结构，阶梯高度即竖直面的高度为H200；AF200上覆盖有厚度为D200的键合金属层AL202。在可选的实施例中，H200可以为0.5μm、2.0μm或3.5μm，H200的范围可为0.5-3.5μm；D200可以为0.5μm、1.5μm或0.9μm，D200的范围可为0.5-1.5μm。
在本发明中，阶梯结构或者阶梯面或者后面提到的凹陷面或凹陷结构可由反应离子刻蚀(RIE)工艺或深硅刻蚀(DRIE)或者采用氢氧化钾(KOH)水溶液湿法刻蚀工艺形成。例如，对于单晶硅基底，离子反应气体为C4F8(流量范围100-600sccm，优选范围200-400sccm)和SF6(流量范围150-800sccm，优选范围400-500sccm)，反应功率为50W-200W。
该阶梯的竖直面与水平面成直角，并在图3中所示的阴影区域范围(即防脱辅助结构F)内具有粗糙度Ra，Ra的取值范围10-80nm。所述防脱辅助结构的表面粗糙度可以为10nm，50nm或者80nm。
在本发明中，因为阶梯面或者阶梯结构的存在，使得：加工阶梯结构的工艺过程可增加被加工表面的粗糙度使键合层材料(金等)或者粘附材料层能够更好的粘附在功能基底表面。此外，阶梯结构相比于传统平直结构能够提供更大的与键合层材料或者粘附层材料的接触面积。
下面参照附图4描述根据本发明的一个示例性实施例。
本实施例包含的细节结构如图4所示。其中AC300为封装基底或封装基底，AC301为封装基底上的垫圈结构或者突起结构。在可选的实施例中，该垫圈结构的高度为H301，宽度为D302，在突起结构和其附近的基底上覆盖有厚度为D301的键合金属层AL301。在可选的实施例中，H301为8μm、15μm或12μm，H301的范围可为8-15μm；D302可为25μm、32μm或者40μm，范围可是25-40μm；D301可以为0.5μm、1.5μm或0.9μm，D301的范围可为0.5-1.5μm。
此外，如图4所示，在垫圈结构AC301的端面上进一步具有条状或网状突起结构，每个条状突起具有两条边为斜边的梯形形状。可选的，梯形中位线宽度为D305，相邻梯形结构间距D306。在进一步的实施例中，D305可为1μm、2μm或3μm，其取值范围可为1-3μm；D306可为1μm、2μm或3μm，其取值范围可为1-3μm；梯形高度为H302，H302可为1μm、2μm或3μm，其取值范围可为1-3μm。
AF300为功能基底，其上具有一阶梯结构，该阶梯结构构成防脱辅助结构F，阶梯高度为H300；AF300上依次覆盖有厚度为D304的氮化铝层AL304，厚度为D303的钼层AL303以及厚度为D300的金层AL302。在具体的实施例中，H300可为0.5μm、2.0μm或者3.5μm，其范围可为0.5-3.5μm；D304可为
Figure PCTCN2019113881-appb-000001
或者
Figure PCTCN2019113881-appb-000002
其范围可为
Figure PCTCN2019113881-appb-000003
D303可为0.1μm、0.6μm或者0.8μm，其范围可为0.1μm-0.8μm；D300可以为0.5μm、1.5μm或0.9μm，其范围可为 0.5-1.5μm。
该阶梯结构或者阶梯面的竖直面与水平面成直角，并在图4中所示的斜线阴影区域范围(对应于防脱辅助结构F)内具有粗糙度Ra，Ra的取值范围10-80nm。所述防脱辅助结构的表面粗糙度可以为10nm，50nm或者80nm。该水平面上覆盖的键合层的宽度以D303表示，D303可以为10μm、30μm或者50μm，其取值范围为10-50μm。
在本发明中，因为阶梯结构或者阶梯面的存在，使得位于最上层的键合层材质(如金)能够更彻底的覆盖位于其下方的钼层和氮化铝层侧壁。
下面参照附图5描述根据本发明的一个示例性实施例。
本实施例包含的细节结构如图5所示。在图5中，AC400为封装基底或者封装基底，AC401为封装基底上的垫圈结构，该结构的高度为H401，宽度为D402，在垫圈结构和其附近的基底上覆盖有厚度为D401的键合金属层AL401。
在具体的实施例中，H401的范围为8-15μm；D402范围25-40μm；D401的范围0.5-1.5μm。上述参数的取值范围与附图4中对应参数的取值或者取值范围相同或者相似。
在可选的具体实施例中，在垫圈结构AC401的端面上进一步具有条状或网状突起结构，每个突起具有两条边为斜边的梯形截面结构。在可选的实施例中，梯形中位线宽度为D405，相邻梯形结构间距D406。在进一步的实施例中，D405的范围为1-3μm；D406的范围为1-3μm；梯形高度为H402，H402的取值范围1-3μm。垫圈结构AC401的端面上的条状或网状突起结构的尺寸与图4中的实施例相同或者相似。
AF400为功能基底或者功能基底，其上具有一阶梯结构，阶梯高度为H400；AF400上依次覆盖有厚度为D404的氮化铝层AL404，厚度为D403的钼层AL403以及厚度为D400的金层AL402。
在具体的实施例中，H400的范围为0.5-3.5μm；D404范围
Figure PCTCN2019113881-appb-000004
D403范围0.1μm-0.8μm；D400范围0.5-1.5μm。上述参数的取值范围与附图4中对应参数的取值或者取值范围相同或者相似。
该阶梯结构或者阶梯面的斜面与水平面成角度AG400，AG400的取值范围为45°-80°，更进一步的，在50°-70°的范围内；同时在图5中所示的斜线阴影区域范围(对应于防脱辅助结构F)内具有粗糙度Ra，Ra的取值范围10-80nm。所述防脱辅助结构的表面粗糙度可以为10nm，50nm或者80nm。
如图5所示，防脱辅助结构F包括斜面，所述斜面的一侧与所述对应基底表面S3相接，所述斜面远离所述对应基底表面向外倾斜延伸。所述防脱辅助结构还包括水平面，所述斜面的另一侧与所述水平面相接。该水平面上覆盖的键合层的宽度以D403表示，D403可以为10μm、30μ m或者50μm，其取值范围为10-50μm。
下面参照附图6描述根据本发明的一个示例性实施例。
本实施例包含的细节结构如图6所示。AC500为封装基底或者封装基底，AC501为封装基底上的垫圈结构，该垫圈结构的高度为H501，宽度为D502，在突起结构和其附近的基底上覆盖有厚度为D501的键合金属层AL501。在具体的实施例中，H501的范围为8-15μm；D502范围25-40μm；D501的范围0.5-1.5μm。上述参数的取值范围与附图4中对应参数的取值或者取值范围相同或者相似。
此外在垫圈结构AC501的端面上进一步具有条状或网状突起结构，每个突起具有两条边为斜边的梯形截面结构。在可选的实施例中，梯形中位线宽度为D505，相邻梯形结构间距D506。D505的范围为1-3μm；D506的范围为1-3μm；梯形高度为H502，H502的取值范围1-3μm。垫圈结构AC501的端面上的条状或网状突起结构的尺寸与图4中的实施例相同或者相似。
AF500为功能基底或者功能基底，如图6所示，其上具有一凹槽结构或者凹陷面，该结构具有倒等腰梯形截面，该梯形高度为H500，梯形下底宽度为D507，上底宽度为D508；AF500上依次覆盖有厚度为D504的氮化铝层AL504，厚度为D503的钼层AL503以及厚度为D500的金层AL502。在具体的实施例中，D504范围
Figure PCTCN2019113881-appb-000005
D503范围0.1μm-0.8μm；D500范围0.5-1.5μm，具体的取值与与图4中的实施例相同或者相似。在可选的实施例中，H500可为0.5μm、2.0μm或3.5μm，其取值范围可为0.5-3.5μm。在可选的实施例中，D507可为2μm、5μm或者8μm，其取值范围可为2～8μm；D508大于D507。
在图6中所示的斜线阴影区域范围(对应于防脱辅助结构F)内具有粗糙度Ra，Ra的取值范围10-80nm。所述防脱辅助结构的表面粗糙度可以为10nm，50nm或者80nm。
基于以上，所述防脱辅助结构F形成有与粘附区对应的基底表面S3的边缘相连的凹陷面。在进一步的实施例中，所述凹陷面包括第二斜面、水平面以及与所述对应基底表面相接的第一斜面，所述第一斜面、所述水平面与所述第二斜面依次相接以形成截面为梯形的凹陷形状。
虽然没有示出，所述凹陷面包括第二斜面以及与所述对应基底表面相接的第一斜面，所述第一斜面与所述第二斜面相接以形成截面大致为三角形的凹陷形状。
明显的，所述第一斜面的表面粗糙度大于所述对应基底表面的表面粗糙度。
在更进一步的实施例中，所述第二斜面和/或所述水平面的表面粗糙度大于对应键合表面的表面粗糙度。
下面参照附图7描述根据本发明的一个示例性实施例。
本实施例包含的细节结构如图7所示。其中AC600为封装基底或者封装基底，AC601为封 装基底上的垫圈结构，该垫圈结构的高度为H601，宽度为D602，在垫圈结构和其附近的基底上覆盖有厚度为D601的键合金属层AL601。在具体的实施例中，H601的范围为8-15μm；D602的范围为25-40μm；D601的范围0.5-1.5μm。上述参数的取值范围与附图4中对应参数的取值或者取值范围相同或者相似。
在可选的实施例中，在垫圈结构AC601的端面上进一步具有条状或网状突起结构，每个突起具有两条边为斜边的梯形截面结构。在可选的实施例中，梯形中位线宽度为D605，相邻梯形结构间距D606。D605的范围为1-3μm；D606的范围为1-3μm；梯形高度为H602，H602的取值范围1-3μm。垫圈结构AC601的端面上的条状或网状突起结构的尺寸与图4中的实施例相同或者相似。
AF600为功能基底或者功能基底，其上具有一凹槽结构，该结构具有倒等腰梯形截面，该梯形高度为H600，梯形下底宽度为D607，上底宽度为D608。
在可选的实施例中，AF600上依次覆盖有厚度为D604的氮化铝层AL604，厚度为D603的钼层AL603以及厚度为D600的金层AL602。在进一步的实施例中，D604范围
Figure PCTCN2019113881-appb-000006
D603范围0.1μm-0.8μm；D600范围0.5-1.5μm。上述参数的取值范围与附图4中对应参数的取值或者取值范围相同或者相似。
在可选的实施例中，H600可为0.5μm、2.0μm或者3.5μm，其范围可为0.5-3.5μm。
在图7所示的实施例中，D607大于D602，例如约8-15μm；D608大于D607。
在图7中所示的斜线阴影区域范围(对应于防脱辅助结构F)内具有粗糙度Ra，Ra的取值范围10-80nm。所述防脱辅助结构的表面粗糙度可以为10nm，50nm或者80nm。
相应的，在本实施例中，所述防脱辅助结构F具有分别设置在粘附区域所在的基底表面的两侧边缘处的第一辅助斜面和第二辅助斜面；且所述第一辅助斜面、具有表面粗糙度的所述基底表面、所述第二辅斜面依次相接以构成截面为梯形的形状。
虽然在图7中，第一辅助斜面和第二辅助斜面之间的基底表面也具有相应的表面粗糙度，在另外的实施例中，处于两个辅助斜面之间的基底表面也可以不设置相应的表面粗糙度。
在图7示出的示例中，通过使得第一辅助斜面和第二辅助斜面之间的基底表面也具有相应的表面粗糙度，使得承受压力的键合层下方的基底表面或者基底表面的密封效果更好。
在本发明中，基底或者基底的材料可选择但不限于：单晶硅(Si)，砷化镓(GaAs)，蓝宝石，石英等。在本发明中，金属键合层的材料可选则但不限于：金(Au)、钛、钛钨、铬、锡、铅等。在本发明的附图2-7所给出的示例中，主要以金属金(Au)对于封装的工艺参数做了描述，不过，这些工艺参数也可以适用于其他金属，例如锡、铅等。
以上以金属键合形成封装密封的实施例说明了本发明，但是，本发明并不限于以金属键合的方式，上述案例中的金属键合层可以为粘附层，此时，粘附层的材料也可以使用粘合剂类的非金属材料如聚二甲基硅氧烷、苯并环丁烯(BCB)或聚氨酯等。在本发明中，所述粘附层可由金、钨、钼、铂、钌、铱、锗、铜、钛、钛钨、铝、铬、锡、砷掺金、聚二甲基硅氧烷或聚氨酯制成，或其合金或组合制成
还需要指出的是，在上述实施例中，第一基底与第二基底上均设置了键合层。不过，在可选的实施例中，也可以在一个基底上设置粘附层或者键合层，防脱辅助结构设置在所述一个基底上。
需要指出的是，在上述实施例中，仅一个基底上设置了防脱辅助结构，但是，在两个基底均设置粘附层或者键合层的情况下，也可以都设置基于本发明的防脱辅助结构。
基于以上，本发明提出了一种半导体器件用封装结构，所述半导体器件包括对置的第一基底与第二基底，所述封装结构包括：适于设置在第一基底上的第一粘附层，第一粘附层具有第一粘附区，第一粘附区适于被挤压以形成密封；以及防脱辅助结构，所述防脱辅助结构设置到第一基底，所述防脱辅助结构与第一粘附区所在的基底表面的边缘相接，且所述防脱辅助结构的至少一部分的表面粗糙度的取值范围为10-80nm，第一粘附层设置成延伸覆盖所述防脱辅助结构的所述至少一部分。这里的第一基底与第二基底，仅仅是对基底做一个编号，并不限制防脱辅助结构设置在对置基底中的哪一个基底上。
在本发明中，“第一粘附区所在的基底表面的边缘”表示对应基底上形成封装密封区域的边缘或者边界。
在本发明中，防脱辅助结构与“第一粘附区所在的基底表面的边缘”相接表示防脱辅助结构与该边缘直接相接或者邻近，均在本发明的保护范围之内。
在本发明中，防脱辅助结构可以防止或者降低键合层或者粘附层从基底上脱离的风险。
虽然没有示出，基于以上，本发明也提出了一种半导体器件用封装结构的制造方法，所述方法包括步骤：在第一基底上形成防脱辅助结构，防脱辅助结构与第一基底上的第一粘附区所在的基底表面的边缘相接，且所述键合防脱辅助结构的表面粗糙度的取值范围为为10-80nm；在第一基底上设置第一粘附层，所述第一粘附层延伸覆盖所述第一粘附区以及所述防脱辅助结构的至少一部分；和在第一基底与第二基底之间挤压所述第一粘附区以形成密封。
可选的，所述方法还包括步骤：在第二基底上设置第二粘附层，所述第二粘附层具有适于与第一粘附区粘接的第二粘附区；且步骤“在第一基底与第二基底之间挤压所述第一粘附区以形成密封”包括在第一基底与第二基底之间挤压所述第一粘附区和第二粘接区以形成密封。
可选的，所述第二基底上具有自第二基底凸出的垫圈结构；所述方法还包括步骤：在所述垫 圈结构的面对第一基底的表面上设置条状结构或者网格状结构。可选的，所述防脱辅助结构形成有与第一粘附区所在的基底表面的边缘相连的阶梯面或者凹陷面。可选的，所述粘附层为金属键合层，且所述粘附区为金属键合区。
本发明的封装结构可适用于半导体器件的封装，例如可适用于射频滤波器封装，也可用于其它MEMS元器件封装结构中。虽然没有示出，本发明的实施例也涉及一种半导体器件，包括上述的封装结构；第一基底；第二基底，与第一基底相对布置，其中：所述封装结构设置在所述第一基底与所述第二基底之间，第一基底、第二基底与封装结构围合成容纳空间。可选的，所述半导体器件为体声波滤波器。
虽然没有示出，本发明的实施例还涉及一种电子设备，包括上述的半导体器件。
尽管已经示出和描述了本发明的实施例，对于本领域的普通技术人员而言，可以理解在不脱离本发明的原理和精神的情况下可以对这些实施例进行变化，本发明的范围由所附权利要求及其等同物限定。

Claims (31)

  1. 一种半导体器件用封装结构，所述半导体器件包括对置的第一晶圆与第二基底，所述封装结构包括：
    适于设置在第一基底上的第一粘附层，第一粘附层具有第一粘附区，第一粘附区适于被挤压以形成密封；以及
    防脱辅助结构，所述防脱辅助结构设置到第一基底，所述防脱辅助结构与第一粘附区所在的基底表面的边缘相接，且所述防脱辅助结构的至少一部分的表面粗糙度的取值范围为10-80nm，第一粘附层设置成延伸覆盖所述防脱辅助结构的所述至少一部分。
  2. 根据权利要求1所述的封装结构，其中：
    所述防脱辅助结构形成有与第一粘附区所在的基底表面的边缘相连的阶梯面。
  3. 根据权利要求2所述的封装结构，其中：
    所述阶梯面的高度的取值范围为0.5-3.5μm。
  4. 根据权利要求2所述的封装结构，其中：
    所述阶梯面包括竖直面，所述竖直面的一侧与所述对应基底表面相接。
  5. 根据权利要求3所述的封装结构，其中：
    所述阶梯面还包括水平面，所述竖直面的另一侧与所述水平面相接。
  6. 根据权利要求2所述的封装结构，其中：
    所述阶梯面包括斜面，所述斜面的一侧与所述对应基底表面相接，所述斜面远离所述对应基底表面向外倾斜延伸。
  7. 根据权利要求6所述的封装结构，其中：
    所述阶梯面还包括水平面，所述斜面的另一侧与所述水平面相接。
  8. 根据权利要求5或7所述的封装结构，其中：
    所述水平面被第一粘附层覆盖的宽度的取值范围为10-50μm。
  9. 根据权利要求7所述的封装结构，其中：
    所述斜面与所述水平面所形成的角度在45°-80°的范围内。
  10. 根据权利要求1所述的封装结构，其中：
    所述防脱辅助结构形成有与第一粘附区所在的基底表面的边缘相连的凹陷面。
  11. 根据权利要求10所述的封装结构，其中：
    所述凹陷面包括第二斜面、水平面以及与所述对应基底表面相接的第一斜面，所述第一斜面、所述水平面与所述第二斜面依次相接以形成截面为梯形的凹陷形状；或者所述凹陷面包括第二斜 面以及与所述对应基底表面相接的第一斜面，所述第一斜面与所述第二斜面相接以形成截面为三角形的凹陷形状；且
    所述第一斜面的表面粗糙度的取值范围为10-80nm。
  12. 根据权利要求11所述的封装结构，其中：
    所述第二斜面和/或所述水平面的表面粗糙度的取值范围为10-80nm。
  13. 根据权利要求1-12中任一项所述的封装结构，其中：
    位于第一粘附区内的与所述防脱辅助结构相接的基底表面具有表面粗糙度，且表面粗糙度的取值范围为10-80nm。
  14. 根据权利要求13所述的封装结构，其中：
    所述防脱辅助结构具有分别设置在第一粘附区所在的基底表面的两侧边缘处的第一辅助斜面和第二辅助斜面；且
    所述第一辅助斜面、具有表面粗糙度的所述基底表面、所述第二辅斜面依次相接以构成截面为梯形的形状。
  15. 根据权利要求1-14中任一项所述的封装结构，其中：
    覆盖所述防脱辅助结构的第一粘附层的厚度的取值范围为0.5-1.5μm。
  16. 根据权利要求1-15中任一项所述的封装结构，其中：
    所述封装结构还包括适于设置在第二基底上的第二粘附区，所述第一粘附区与所述第二粘附区适于彼此挤压粘接以形成密封。
  17. 根据权利要求16所述的封装结构，其中：
    所述第二基底设置有自第二基底凸出的垫圈结构，所述第二粘附层设置在所述垫圈结构上，所述第一基底设置有所述防脱辅助结构和所述第一粘附层。
  18. 根据权利要求17所述的封装结构，其中：
    所述垫圈结构与所述第一粘附层相对的表面设置有条状结构或者网格状结构。
  19. 根据权利要求18所述的封装结构，其中：
    所述条状结构的截面具有两条边为斜边的梯形形状。
  20. 根据权利要求1-19中任一项所述的封装结构，其中：
    所述基底由单晶硅、砷化镓、蓝宝石或石英制成；
    所述粘附层由金、钨、钼、铂、钌、铱、锗、铜、钛、钛钨、铝、铬、锡、砷掺金、聚二甲基硅氧烷或聚氨酯制成，或其合金或组合制成；且
    所述粘附层为键合层，所述粘附区为键合区。
  21. 根据权利要求20所述的封装结构，还包括：
    辅助键合层，所述辅助键合层设置在第一基底的所述基底表面与对应的键合层之间。
  22. 根据权利要求21所述的封装结构，其中：
    所述辅助键合层包括依次覆盖在基底表面的氮化铝层和钼层。
  23. 一种半导体器件用封装结构的制造方法，所述半导体器件包括对置的第一基底与第二基底，所述方法包括步骤：
    在第一基底上形成防脱辅助结构，防脱辅助结构与第一基底上的第一粘附区所在的基底表面的边缘相接，且所述键合防脱辅助结构的表面粗糙度的取值范围为10-80nm；
    在第一基底上设置第一粘附层，所述第一粘附层延伸覆盖所述第一粘附区以及所述防脱辅助结构的至少一部分；和
    在第一基底与第二基底之间挤压所述第一粘附区以形成密封。
  24. 根据权利要求23所述的方法，其中：
    所述方法还包括步骤：在第二基底上设置第二粘附层，所述第二粘附层具有适于与第一粘附区粘接的第二粘附区；且
    步骤“在第一基底与第二基底之间挤压所述第一粘附区以形成密封”包括在第一基底与第二基底之间挤压所述第一粘附区和第二粘接区以形成密封。
  25. 根据权利要求24所述的方法，其中：
    所述第二基底上具有自第二基底凸出的垫圈结构；
    所述方法还包括步骤：在所述垫圈结构的面对第一基底的表面上设置条状结构或者网格状结构。
  26. 根据权利要求25所述的方法，其中：
    所述条状结构的截面具有两条边为斜边的梯形形状。
  27. 根据权利要求23-26中任一项所述的方法，其中：
    所述防脱辅助结构形成有与第一粘附区所在的基底表面的边缘相连的阶梯面或者凹陷面。
  28. 根据权利要求24-26中任一项所述的方法，其中：
    所述粘附层为金属键合层，且所述粘附区为金属键合区。
  29. 一种半导体器件，包括：
    根据权利要求1-22中任一项所述的封装结构；
    第一基底；
    第二基底，与第一基底相对布置，
    其中：
    所述封装结构设置在所述第一基底与所述第二基底之间，第一基底、第二基底与封装结构围合成容纳空间。
  30. 根据权利要求29所述的半导体器件，其中：
    所述半导体器件为体声波滤波器。
  31. 一种电子设备，包括根据权利要求29或30所述的半导体器件。
PCT/CN2019/113881 2018-11-14 2019-10-29 封装结构及其制造方法、半导体器件、电子设备 Ceased WO2020098475A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201811355048.9A CN111193487B (zh) 2018-11-14 2018-11-14 封装结构及其制造方法、半导体器件、电子设备
CN201811355048.9 2018-11-14

Publications (1)

Publication Number Publication Date
WO2020098475A1 true WO2020098475A1 (zh) 2020-05-22

Family

ID=70709077

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/113881 Ceased WO2020098475A1 (zh) 2018-11-14 2019-10-29 封装结构及其制造方法、半导体器件、电子设备

Country Status (2)

Country Link
CN (1) CN111193487B (zh)
WO (1) WO2020098475A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022217403A1 (zh) * 2021-04-12 2022-10-20 诺思(天津)微系统有限责任公司 Mems扬声器和电子设备

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102111116A (zh) * 2010-11-24 2011-06-29 张�浩 整合的晶圆级别封装体
US20120045618A1 (en) * 2010-08-19 2012-02-23 Seiko Epson Corporation Optical filter, method of manufacturing optical filter, and optical instrument
CN103217732A (zh) * 2012-01-18 2013-07-24 精工爱普生株式会社 干涉滤波器、光学模块以及电子设备
CN104241215A (zh) * 2013-06-14 2014-12-24 日月光半导体制造股份有限公司 半导体封装结构及半导体工艺
CN108365829A (zh) * 2017-03-24 2018-08-03 珠海晶讯聚震科技有限公司 单晶压电射频谐振器和滤波器的制备方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2848339B1 (fr) * 2002-12-05 2005-08-26 St Microelectronics Sa Procede d'adhesion de deux elements, en particulier d'un circuit integre, par exemple une encapsulation d'un resonateur, et circuit integre correspondant
JP4705748B2 (ja) * 2003-05-30 2011-06-22 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
CN102169845B (zh) * 2011-02-22 2013-08-14 中国科学院微电子研究所 一种用于三维封装的多层混合同步键合结构及方法
CN104362117B (zh) * 2014-11-24 2018-04-20 苏州晶方半导体科技股份有限公司 基底键合装置和键合方法
CN105355613B (zh) * 2015-10-27 2018-08-10 上海华虹宏力半导体制造有限公司 铝锗共晶键合的方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120045618A1 (en) * 2010-08-19 2012-02-23 Seiko Epson Corporation Optical filter, method of manufacturing optical filter, and optical instrument
CN102111116A (zh) * 2010-11-24 2011-06-29 张�浩 整合的晶圆级别封装体
CN103217732A (zh) * 2012-01-18 2013-07-24 精工爱普生株式会社 干涉滤波器、光学模块以及电子设备
CN104241215A (zh) * 2013-06-14 2014-12-24 日月光半导体制造股份有限公司 半导体封装结构及半导体工艺
CN108365829A (zh) * 2017-03-24 2018-08-03 珠海晶讯聚震科技有限公司 单晶压电射频谐振器和滤波器的制备方法

Also Published As

Publication number Publication date
CN111193487A (zh) 2020-05-22
CN111193487B (zh) 2023-10-24

Similar Documents

Publication Publication Date Title
US9496193B1 (en) Semiconductor chip with structured sidewalls
JP4401181B2 (ja) 半導体装置及びその製造方法
CN101673679B (zh) 薄型半导体晶片和减薄半导体晶片的方法
CN110116985B (zh) 用于制造薄层和具有薄层的微系统的方法
JPH03204954A (ja) 半導体装置の製造方法
CN104952794B (zh) 用于背面金属化的截口准备
US20140138833A1 (en) Semiconductor Device Assembly Including a Chip Carrier, Semiconductor Wafer and Method of Manufacturing a Semiconductor Device
TW201711097A (zh) 半導體裝置之製造方法
US20080233714A1 (en) Method for fabricating semiconductor device
US20250359209A1 (en) Semiconductor device and method of manufacturing the same
WO2020098475A1 (zh) 封装结构及其制造方法、半导体器件、电子设备
US7518240B2 (en) Deposition pattern for eliminating backside metal peeling during die separation in semiconductor device fabrication
CN106847717B (zh) 一种共晶键合方法和半导体器件
JP5228381B2 (ja) 半導体装置の製造方法
CN104465426B (zh) 凸块的制作方法
JP3501959B2 (ja) レーザー溶断方式半導体装置の製造方法および半導体装置
US10998231B2 (en) Method for increasing semiconductor device wafer strength
JP7095844B2 (ja) 半導体装置およびその製造方法
CN111606301A (zh) 器件结构及封装方法、滤波器、电子设备
CN113496963A (zh) 半导体装置及其制造方法
JP4522213B2 (ja) 半導体装置の製造方法
JPS63138794A (ja) 半導体レ−ザ素子ダイボンデイング方法
TWI899598B (zh) 半導體裝置及其製造方法
JPH05102300A (ja) 半導体装置
JP2958871B2 (ja) 半導体装置の製造方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19885397

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19885397

Country of ref document: EP

Kind code of ref document: A1