WO2020098045A1 - 一种显示面板、检测方法及显示装置 - Google Patents

一种显示面板、检测方法及显示装置 Download PDF

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Publication number
WO2020098045A1
WO2020098045A1 PCT/CN2018/121241 CN2018121241W WO2020098045A1 WO 2020098045 A1 WO2020098045 A1 WO 2020098045A1 CN 2018121241 W CN2018121241 W CN 2018121241W WO 2020098045 A1 WO2020098045 A1 WO 2020098045A1
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Prior art keywords
line
gate lines
display panel
line segment
reference voltage
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PCT/CN2018/121241
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English (en)
French (fr)
Inventor
吴川
Original Assignee
重庆先进光电显示技术研究院
重庆惠科金渝光电科技有限公司
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Priority to US17/272,601 priority Critical patent/US11966135B2/en
Publication of WO2020098045A1 publication Critical patent/WO2020098045A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/13629—Multilayer wirings
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136254—Checking; Testing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3607—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures

Definitions

  • the present application relates to the technical field of display panels, and in particular, to a display panel, a detection method, and a display device.
  • Matrix display panels are currently most commonly used in display devices.
  • the drive architecture of matrix display panels includes common active drive architectures and half-source drive architectures; the use of half-source drive architectures can reduce display panel The total number of data lines and gate lines can save a lot of plates and reduce the manufacturing cost of the display panel.
  • the timing pulse signals of wide and narrow phases cannot be recognized, and the display panel based on the half-source driving architecture cannot be normally detected, so that the display The short circuit and open circuit of the gate line or the reference voltage line of the panel cannot be detected, resulting in a decrease in the production yield of the display panel.
  • the purpose of the present application is to provide a liquid crystal display panel, a detection method and a liquid crystal display, including but not limited to, to solve the problem that the display panel based on the half-source driving architecture cannot be normally detected, so that the gate line or the reference voltage line of the display panel is short-circuited, The disconnection cannot be detected, resulting in a reduction in the production yield of the display panel.
  • a display panel provided by the embodiments of the present application includes a pixel array, multiple rows of gate lines and multiple columns of data lines, the gate lines and the data lines are perpendicular to each other, each Two gate lines correspond to a row of sub-pixels, and each data line corresponds to two columns of sub-pixels;
  • Each row of pixels corresponds to two gate lines and any two gate lines are parallel to each other;
  • the lengths of all odd-row gate lines are set to the first length; the lengths of all even-row gate lines are set to the second length; the first length is greater than the second length.
  • the lengths of all odd-row gate lines are set to a third length; the lengths of all even-row gate lines are set to a fourth length; the third length is greater than the fourth length.
  • the first part of each gate line connected to the sub-pixel of the display panel is arranged in a straight line, which is used for array detection.
  • the second part is arranged in a straight line or a broken line, wherein the first part and the second part form a Gate line.
  • the ends of the even-numbered gate lines are arranged in a broken line, and the broken line includes a first line segment and a second line segment;
  • the second line segments of the even-numbered gate lines and the adjacent odd-numbered gate lines are parallel to each other and the line spacing is the first distance.
  • the second line segment of the even-numbered gate lines is parallel to the adjacent two odd-row gate lines, and the second line segment is equal to the adjacent odd-numbered gate lines.
  • the ends of the odd-numbered gate lines are arranged in a broken line, and the broken line includes a third line segment and a fourth line segment;
  • the fourth line segment of the odd-numbered gate lines is parallel to the adjacent even-numbered gate lines, and the row spacing is the second distance.
  • the fourth line segment portion of the odd-numbered gate lines is parallel to two adjacent even-numbered gate lines, and the fourth line segment is equal to the adjacent even-numbered gate lines.
  • the display panel further includes a plurality of reference voltage lines, one reference voltage line is provided between two gate lines corresponding to pixels in each row, and each reference pixel line is correspondingly connected to one of the reference voltage lines;
  • the ends of the reference voltage lines are arranged in a zigzag line and the ends of the even-numbered gate lines are arranged in a zigzag line.
  • the zigzag lines of the reference voltage line include a fifth line segment and a sixth line segment, and the even-numbered lines
  • the broken line of the gate line includes a seventh line segment and an eighth line segment;
  • the sixth line segment of any one of the reference voltage lines and the eighth line segment of any of the even-numbered gate lines are parallel to each other, and both are parallel to the odd-numbered gate lines.
  • the row spacing between the sixth line segment of the reference voltage line and the adjacent odd-row gate line is a third distance
  • the sixth line segment of the reference voltage line is adjacent to the even-numbered row gate
  • the line spacing between the eighth line segments of the epipolar lines is a third distance
  • the line spacing between the eighth line segments of the even-line gate lines and the adjacent odd-line gate lines is the third distance.
  • the eighth line segment of the even-numbered gate lines and the sixth line segment of the reference voltage line and the odd-numbered gate lines are parallel to each other, and the sixth line segment of the reference voltage line is respectively parallel to the eighth line segment and the odd-numbered lines
  • the line spacing of the gate lines is equal.
  • the end of the reference voltage line is arranged in a zigzag line and the end of the odd-numbered gate line is arranged in a zigzag line.
  • the zigzag line of the reference voltage line includes a fifth line segment and a sixth line segment, and the odd-line gate
  • the polyline of the line includes the ninth line segment and the tenth line segment;
  • the sixth line segment of any one of the reference voltage lines is parallel to the tenth line segment of any odd-numbered gate lines, and both are parallel to the even-numbered gate lines.
  • the line spacing between the sixth line segment of the reference voltage line and the adjacent even-row gate lines is a fourth distance
  • the sixth line segment of the reference voltage line is adjacent to the adjacent odd-row gate
  • the line spacing between the tenth line segments of the epipolar lines is a fourth distance
  • the line spacing between the tenth line segments of the odd-line gate lines and the adjacent even-line gate lines is the fourth distance.
  • the tenth line segment of the odd-numbered gate lines is parallel to the sixth line segment of the reference voltage line and the even-numbered gate lines, and the sixth line segment of the reference voltage line is respectively parallel to the tenth line segment and the even-numbered gate lines
  • the line spacing is equal.
  • Another objective of this application is to provide a detection method, including:
  • the reference voltage line According to the third equally spaced timing pulse signal and the fourth equally spaced timing pulse signal, it is determined whether the reference voltage line has a fault.
  • Still another object of the present application is to provide a display device, including a display panel, wherein the display panel includes:
  • a pixel array multiple rows of gate lines and multiple columns of data lines, the gate lines and the data lines are perpendicular to each other, each two gate lines correspond to a row of sub-pixels, and each data line corresponds to two columns of sub-pixels;
  • Each row of pixels corresponds to two gate lines and any two gate lines are parallel to each other;
  • the detection method and the display device provided by the embodiments of the present application, by wiring the gates of the display panel, there is a preset length difference between the two adjacent gate lines, and the length of the adjacent gate lines is not Equal, so that the display panel is in a state where array detection can be performed, and when the gate line failure is detected, the short circuit or open circuit of the gate line can be detected, thereby improving the production yield of the display panel.
  • FIG. 1 is a schematic structural diagram of a display panel provided by an embodiment of the present application.
  • FIG. 2 is a specific structural schematic diagram of a display panel provided by an embodiment of the present application.
  • FIG. 3 is a schematic diagram of another specific structure of a display panel provided by an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of another display panel provided by an embodiment of the present application.
  • FIG. 5 is a schematic diagram of a specific structure of another display panel provided by an embodiment of the present application.
  • FIG. 6 is a schematic diagram of a specific structure of another display panel provided by an embodiment of the present application.
  • FIG. 7 is a schematic flowchart of an implementation of a method for detecting a display panel provided by an embodiment of the present application.
  • FIG. 8 is a schematic diagram of the display device provided in the embodiment of the application.
  • the thin film transistor TFT array substrate of the display panel of the active drive architecture includes: m parallel data lines D1 to Dm, n gate lines G1 to Gn parallel to each other and insulated from the data lines, and the semi-source drive architecture
  • the display panel doubles the number of gate lines and reduces the number of data lines by half.
  • Each row of sub-pixels corresponds to two gate lines, and each column of data lines corresponds to two columns of sub-pixels.
  • FIG. 1 a schematic structural diagram of a display panel provided by an embodiment of the present application. For convenience of description, only parts related to the embodiment of the present application are shown.
  • the display panel includes a pixel array 10, a plurality of gate lines 11 and a plurality of data lines 12, the gate lines and the data lines are perpendicular to each other, each two gate lines correspond to a row of sub-pixels, Each data line corresponds to two columns of sub-pixels; each row of pixels corresponds to two gate lines 11, and any two gate lines are parallel to each other; there is a preset length difference between the two adjacent gate lines;
  • the preset length can be set according to the actual needs of the specific size of the display panel, and setting the difference in the preset length puts the display panel in a detection state to realize array detection of the display panel.
  • Every two columns of sub-pixels are connected to one data line 12, and any two data lines are parallel to each other; as shown in Figure 1, 2n gate lines correspond to n rows of pixels, and m data lines correspond to 2m columns of sub-pixels; two adjacent rows
  • the gate lines are set to unequal lengths; where m ⁇ 1, n ⁇ 1 and m and n are both positive integers.
  • Each row of sub-pixels in the pixel array includes multiple groups of sub-pixels, and each group of sub-pixels includes sequentially arranged first-color sub-pixels, second-color sub-pixels, and third-color sub-pixels, and the colors of sub-pixels in the same column Similarly, at least one of the first color subpixel, the second color subpixel, and the third color subpixel is a red subpixel, at least one is a green subpixel, and at least one is a blue subpixel.
  • the lengths of all odd-row gate lines are set to the first length; the lengths of all even-row gate lines are set to the second length; the first length is greater than the second length.
  • the lengths of all odd-row gate lines are set to a third length; the lengths of all even-row gate lines are set to a fourth length; the third length is greater than the fourth length.
  • the lengths of all odd-row gate lines may be unequal, the lengths of all even-row gate lines may be unequal, and the lengths of the even-row gate lines and the odd-row gate lines are not equal.
  • the number of rows and columns of the pixel array can be set according to specific needs, and the size of the pixel array is not particularly limited.
  • a display panel based on a half-source driving architecture is used.
  • Each two gate lines corresponds to a row of sub-pixels.
  • the first interval between two gate lines connecting pixels in the same row is different from the phases connecting sub-pixels in different rows.
  • the second interval between the adjacent two lines of gate lines because the first interval and the second interval are not equal, it is impossible to detect the condition of the gate line path through a uniform pulse signal; by setting the gate lines to unequal lengths, A part of the gate lines at the end leading out of the gate lines for detection is provided.
  • the gate lines of different lengths it is convenient to set the gate lines used for the detection part to be parallel to each other at equal line spacings, so as to meet the conditions for detecting the path status.
  • the first part of each gate line connected to the sub-pixel of the display panel is arranged in a straight line, which is used for array detection.
  • the second part is arranged in a straight line or a broken line, wherein the first part and the second part form a complete Gate line.
  • the display panel may include M rows ⁇ N columns of sub-pixels, that is, the display panel includes a sub-pixel array of M ⁇ N sub-pixels, each column of sub-pixels includes multiple groups of sub-pixels, and each group of sub-pixels It includes a first color sub-pixel, a second color sub-pixel and a third color sub-pixel arranged in sequence; where N ⁇ 1, M ⁇ 1 and M, N are all positive integers.
  • the colors of the sub-pixels in the same column are the same, and the colors of the sub-pixels in the adjacent columns are different.
  • the first color sub-pixel, the second color sub-pixel, and the third color sub-pixel are any one of a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, and the first The colors of the color subpixel, the second color subpixel, and the third color subpixel are different.
  • FIG. 2 a specific structural schematic diagram of a display panel provided by an embodiment of the present application, for ease of description, only parts related to the embodiment of the present application are shown.
  • the second line segment of the even-numbered gate lines and the adjacent two odd-row gate lines are parallel to each other, and the second line segment and the adjacent odd-numbered gate lines have the same line spacing;
  • the second line segment portion of the row gate line and the gate line portion corresponding to the second line segment serve as an array detection portion, so that the condition of the gate line path can be detected by a detection signal with a uniform pulse width.
  • the ends of the odd-numbered gate lines are arranged in a broken line, and the broken line 30 includes a third line segment 31 and a fourth line segment 32 ;
  • the fourth line segment of the odd-numbered gate lines is parallel to the two adjacent even-line gate lines, and the fourth line segment is equal to the adjacent even-numbered gate lines;
  • the fourth line segment part of the odd-numbered gate lines and the even line gate line part corresponding to the fourth line segment serve as an array detection part, so that the condition of the gate line path can be detected by a detection signal with a uniform pulse width.
  • the width and width of the timing pulse signal can be used to control the gate line of the display panel.
  • the short circuit or open circuit is detected to improve the production yield of the display panel.
  • the embodiment of the present application provides a schematic structural diagram of another display panel. For ease of description, only parts related to the embodiment of the present application are shown.
  • the display panel includes a pixel array, multiple rows of gate lines, and multiple columns of data lines; each pixel includes three sub-pixels of red, green, and blue; each row of pixels corresponds to two gate lines, and any two The gate lines are parallel to each other; every two columns of subpixels are connected to one data line, and any two data lines are parallel to each other; for example: 2n gate lines correspond to n rows of pixels, m data lines correspond to 2m columns of subpixels; odd row gates The lengths of the polar lines are all equal, and the lengths of the even-numbered gate lines are all equal.
  • the display panel further includes a plurality of reference voltage lines 40, a reference voltage line 40 is provided between two gate lines corresponding to pixels in each row, and a reference voltage line 40 is connected to each row of pixels; the end of any reference voltage line is One gate line is parallel to each other, and the reference voltage line corresponding to each row of pixels is connected to one end of the liquid crystal capacitor of the same row of pixels and one end of the storage capacitor.
  • FIG. 5 a specific structural schematic diagram of another display panel provided by an embodiment of the present application, for ease of description, only parts related to the embodiment of the present application are shown.
  • the ends of the reference voltage lines are arranged in a zigzag line and the ends of the even-numbered gate lines are arranged in a zigzag line.
  • the zigzag line 500 of the reference voltage line includes a fifth line segment 501 and a sixth line segment 502, and the zigzag line 510 of the even-line gate line includes a seventh line segment 511 And the eighth line segment 512; the sixth line segment 502 of any reference voltage line is parallel to the eighth line segment 512 of any even-numbered gate line, and is parallel to the odd-numbered gate line.
  • the line spacing between the sixth line segment 502 of the reference voltage line and the adjacent odd-row gate lines is a third distance
  • the sixth line segment 502 of the reference voltage line and the eighth line segment of the adjacent even-row gate lines The line spacing between 512 is the third distance
  • the pixel pitch of the display panel of the 23.5-inch display device is 381.75 microns
  • the eighth line segment of the even-numbered gate lines and the sixth line segment of the reference voltage line and the odd-numbered gate lines are parallel to each other, and the sixth line segment of the reference voltage line is respectively parallel to the eighth line segment and the odd-numbered lines
  • the line spacing of the gate lines is equal; the sixth line segment, the eighth line segment, and the odd-numbered gate line parts corresponding to the sixth line segment are used as the array detection part, and the gate line path status is detected by a detection signal with a uniform pulse width.
  • FIG. 6 a specific structural schematic diagram of another display panel provided by an embodiment of the present application.
  • the end of the reference voltage line is arranged in a broken line and the end of the odd-numbered gate line is arranged in a broken line.
  • the broken line 500 of the reference voltage line includes a fifth line segment 501 and a sixth line segment 502, and the broken line 600 of the odd-numbered gate line includes a ninth line segment 601 and a Ten line segments 602; the sixth line segment 502 of any reference voltage line and the tenth line segment 602 of any odd-numbered gate line are parallel to each other, and are all parallel to the even-numbered gate lines.
  • the distance between the sixth line segment 502 of the reference voltage line and the adjacent even-row gate lines is the fourth distance, and the sixth line segment 502 of the reference voltage line and the tenth line segment 602 of the adjacent odd-row gate lines
  • the line spacing between them is the fourth distance
  • the pixel pitch of the display panel of the display device is 510.75 microns
  • the tenth line segment of the odd-numbered gate lines is parallel to the sixth line segment of the reference voltage line and the even-numbered gate lines
  • the sixth line segment of the reference voltage line is respectively parallel to the tenth line segment and the even-numbered gate lines
  • the line spacing of the lines is equal; the sixth line segment, the tenth line segment and the even-numbered gate line parts corresponding to the sixth line segment are used as the array detection part, and the gate line path status is detected by a detection signal with a uniform pulse width.
  • FIG. 7 a schematic flowchart of an implementation of a detection method of a display panel provided by an embodiment of the present application.
  • the detection method is applied to the above-mentioned array detection of a display panel to improve the production yield of the display panel.
  • the detection method may include the following steps:
  • Step S301 output the first equally spaced timing pulse signal to the gate line of the display panel
  • Step S302 Obtain a second equally spaced timing pulse signal output by the gate line
  • Step S303 Determine whether the gate line is faulty according to the first equally spaced timing pulse signal and the second equally spaced timing pulse signal;
  • Step S304 output a third equally spaced timing pulse signal to the reference voltage line of the display panel
  • Step S305 Acquire a fourth equally spaced timing pulse signal output by the reference voltage line
  • Step S306 Determine whether the reference voltage line is faulty according to the third equally spaced timing pulse signal and the fourth equally spaced timing pulse signal.
  • the corresponding engineering inspection is performed to check the array of the display panel. Detection of short circuit or open circuit inspection, non-contact inspection can be used; the pulse signal generating device scans the end of the gate line at a uniform speed, outputs an equally spaced timing pulse signal to the gate line, receives the feedback of the equally spaced timing pulse signal, and According to the sent timing pulse signal and the received timing pulse signal, it is determined whether the gate line or the reference voltage line is short-circuited or broken.
  • the array scanning inspection of the gate line can also be an electron beam signal sent from the detection device to the gate line.
  • the received signal can be a secondary electronic signal.
  • the strength of the secondary electronic signal is determined by the voltage on the pixel and the detection device. The voltage difference between them determines that the change in the amount of secondary electrons reflects the voltage change on the pixel. The defect and the normal voltage value are completely different. That is, whether the gate line, the reference voltage line or the pixel electrode is short-circuited can be determined according to the change of the voltage signal Or open circuit.
  • the even-numbered gate lines and the odd-numbered gate lines are set to have different lengths, so that there is a preset length difference between the gate lines, which is convenient for setting the end of the gate lines into the odd-numbered gate lines and the even-numbered lines
  • the line spacing of the end of the gate line of the same is equal
  • the line spacing between the end of the reference voltage line and the end of the even line gate line is equal to the line spacing between the end of the reference voltage line and the end of the odd line gate line, so that the display panel is in a
  • the failure detection of the gate line and the reference voltage line can save the detection time, save the cost of consumables, and have no damage to the surface of the display panel, thereby improving The production yield of the display panel.
  • FIG. 8 is a schematic diagram of a display device provided by an embodiment of the present application, for ease of description, only parts related to the embodiment of the present application are shown.
  • the display device 200 includes a display panel 201, wherein the display panel includes:
  • a pixel array multiple rows of gate lines and multiple columns of data lines, the gate lines and the data lines are perpendicular to each other, each two gate lines correspond to a row of sub-pixels, and each data line corresponds to two columns of sub-pixels;
  • Each row of pixels corresponds to two gate lines and any two gate lines are parallel to each other;
  • the display panel may be any type of display panel, for example, a liquid crystal display panel based on LCD (Liquid Crystal) display technology, or an organic light based on OLED (Organic Electroluminesence Display) technology Laser display panel, quantum dot light emitting diode display panel or curved display panel based on QLED (Quantum Dot Light Emitting Diodes) technology.
  • LCD Liquid Crystal
  • OLED Organic Electroluminesence Display
  • Laser display panel quantum dot light emitting diode display panel or curved display panel based on QLED (Quantum Dot Light Emitting Diodes) technology.
  • the storage medium may be a magnetic disk, an optical disk, a read-only memory (Read-Only Memory, ROM) or a random access memory (Random Access Memory, RAM), etc.

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  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

一种显示面板（201），包括像素阵列（10）、多行栅极线（11）和多列数据线（12），栅极线（11）和数据线（12）相互垂直，每两条栅极线（11）对应连接一行子像素，每条数据线（12）对应连接两列子像素；每行像素对应连接两条栅极线（11）且任意两条栅极线（11）相互平行；相邻两行栅极线（11）存在预设长度差异；便于对显示面板的布线进行阵列检测，提高显示面板（201）的生产良率。

Description

一种显示面板、检测方法及显示装置
本申请要求于2018年11月12日提交中国专利局，申请号为201811339326.1，发明名称为“一种显示面板、检测方法及显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示面板技术领域，尤其涉及一种显示面板、检测方法及显示装置。
背景技术
这里的陈述仅提供与本申请有关的背景信息,而不必然地构成现有技术。矩阵式的显示面板目前最常应用于显示装置，矩阵式显示面板的驱动架构包括普通有源驱动架构以及半源驱动架构；采用半源驱动架构相对于普通有源驱动架构，可以减少显示面板的数据线以及栅极线的总数，能够节省大量板材，降低显示面板的制造成本。
然而，基于半源驱动架构的显示面板的结构特征，在对显示面板栅极线进行阵列检测时，无法识别宽窄相间的时序脉冲信号，便无法正常检测基于半源驱动架构的显示面板，使得显示面板的栅极线或基准电压线的短路、断路情况不能被检出，从而导致显示面板的生产良率降低。
申请内容
本申请的目的在于提供一种液晶显示面板、检测方法及液晶显示器，包括但不限于，解决无法正常检测基于半源驱动架构的显示面板，使得显示面板的 栅极线或基准电压线的短路、断路情况不能被检出，导致显示面板的生产良率降低。
本申请实施例采用的技术方案是：本申请实施例提供的一种显示面板，包括像素阵列、多行栅极线和多列数据线，所述栅极线和所述数据线相互垂直，每两条栅极线对应连接一行子像素，每条数据线对应连接两列子像素；
每行所述像素对应连接两条所述栅极线且任意两条所述栅极线相互平行；
相邻两行所述栅极线存在预设长度差异。
在一个实施例中，所有奇数行栅极线的长度设置为第一长度；所有偶数行栅极线的长度设置为第二长度；第一长度大于第二长度。
在一个实施例中，所有奇数行栅极线的长度设置为第三长度；所有偶数行栅极线的长度设置为第四长度；第三长度大于第四长度。
在一个实施例中，显示面板的每条栅极线与子像素连接的第一部分，呈直线设置，用于阵列检测第二部分呈直线或折线设置，其中第一部分与第二部分组成一条完整的栅极线。
在一个实施例中，所述偶数行栅极线的末端呈折线布置，所述折线包括第一线段和第二线段；
所述偶数行栅极线的第二线段与相邻的奇数行栅极线相互平行且行间距为第一距离。
在一个实施例中，偶数行栅极线的第二线段部分与相邻两条奇数行栅极线相互平行，所述第二线段部分与相邻奇数行栅极线的行间距相等。
在一个实施例中，所述奇数行栅极线的末端呈折线布置，所述折线包括第三线段和第四线段；
所述奇数行栅极线的第四线段与相邻的偶数行栅极线相互平行，行间距为 第二距离。
在一个实施例中，奇数行栅极线的第四线段部分与其相邻的两条偶数行栅极线相互平行，所述第四线段部分与相邻偶数行栅极线的行间距相等。
在一个实施例中，显示面板还包括多条基准电压线，每行像素对应的两条栅极线之间设置一条所述基准电压线，每行像素对应连接一条所述基准电压线；
任一条所述基准电压线的末端与任一条所述栅极线相互平行。
在一个实施例中，所述基准电压线的末端呈折线布置且所述偶数行栅极线的末端呈折线布置，所述基准电压线的折线包括第五线段和第六线段，所述偶数行栅极线的折线包括第七线段和第八线段；
任一条所述基准电压线的第六线段与任一条偶数行栅极线的第八线段相互平行，且均与奇数行栅极线平行。
在一个实施例中，所述基准电压线的第六线段与相邻的奇数行栅极线之间的行间距为第三距离，所述基准电压线的第六线段与相邻的偶数行栅极线的第八线段之间的行间距为第三距离，所述偶数行栅极线的第八线段与相邻的奇数行栅极线之间的行间距为第三距离。
在一个实施例中，偶数行栅极线的第八线段与基准电压线的第六线段以及奇数行栅极线之间相互平行，且基准电压线的第六线段分别与第八线段、奇数行栅极线的行间距相等。
在一个实施例中，所述基准电压线末端呈折线布置且所述奇数行栅极线末端呈折线布置，所述基准电压线的折线包括第五线段和第六线段，所述奇数行栅极线的折线包括第九线段和第十线段；
任一条所述基准电压线的第六线段与任一条奇数行栅极线的第十线段相 互平行，且均与偶数行的栅极线平行。
在一个实施例中，所述基准电压线的第六线段与相邻的偶数行栅极线之间的行间距为第四距离，所述基准电压线的第六线段与相邻的奇数行栅极线的第十线段之间的行间距为第四距离，所述奇数行栅极线的第十线段与相邻的偶数行栅极线之间的行间距为第四距离。
在一个实施例中，奇数行栅极线的第十线段与基准电压线的第六线段以及偶数行栅极线相互平行，且基准电压线的第六线段分别与第十线段、偶数行栅极线的行间距相等。
本申请的另一目的在于提供一种检测方法，包括：
输出第一等间隔时序脉冲信号至显示面板的栅极线；
获取所述栅极线输出的第二等间隔时序脉冲信号；
根据所述第一等间隔时序脉冲信号和所述第二等间隔时序脉冲信号，判断所述栅极线是否发生故障；
输出第三等间隔时序脉冲信号至显示面板的基准电压线；
获取所述基准电压线输出的第四等间隔时序脉冲信号；
根据所述第三等间隔时序脉冲信号和所述第四等间隔时序脉冲信号，判断所述基准电压线是否发生故障。
本申请的再一目的在于提供一种显示装置，包括显示面板，其中，所述显示面板包括：
像素阵列、多行栅极线和多列数据线，所述栅极线和所述数据线相互垂直，每两条栅极线对应连接一行子像素，每条数据线对应连接两列子像素；
每行所述像素对应连接两条所述栅极线且任意两条所述栅极线相互平行；
相邻两行所述栅极线存在预设长度差异。
本申请实施例提供的显示面板、检测方法及显示装置，通过对显示面板的栅极进行布线设置，相邻两行所述栅极线存在预设长度差异，将相邻栅极线的长度不相等，使显示面板处于可以进行阵列检测状态，在进行栅极线故障检测时，可以检测出栅极线的短路或断路情况，从而提高了显示面板的生产良率。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图。
图1是本申请实施例提供的显示面板的结构示意图；
图2是本申请实施例提供的显示面板具体的结构示意图；
图3是本申请实施例提供的显示面板另一种具体的结构的示意图；
图4是本申请实施例提供的另一显示面板的结构示意图；
图5是本申请实施例提供的另一显示面板的具体结构示意图；
图6是本申请实施例提供的另一显示面板的具体结构示意图；
图7是本申请实施例提供的显示面板的检测方法的实现流程示意图；
图8是申请实施例里提供的显示装置的示意图。
具体实施方式
为了使本申请的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本申请进行进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
需说明的是，当部件被称为“固定于”或“设置于”另一个部件，它可以 直接在另一个部件上或者间接在该另一个部件上。当一个部件被称为是“连接于”另一个部件，它可以是直接或者间接连接至该另一个部件上。术语“上”、“下”、“左”、“右”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本专利的限制，对于本领域的普通技术人员而言，可以根据具体情况理解上述术语的具体含义。术语“第一”、“第二”仅用于便于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明技术特征的数量。“多个”的含义是两个或两个以上，除非另有明确具体的限定。
为了说明本申请所述的技术方案，以下结合具体附图及实施例进行详细说明。
有源驱动架构的显示面板的薄膜晶体管TFT阵列基板包括：m条相互平行的数据线D1～Dm，n条相互平行且与数据线绝缘相交的栅极线G1～Gn，而半源驱动架构的显示面板则增加了一倍的栅极线，减少了一半的数据线，每行子像素对应两条栅极线，每列数据线对应两列子像素。
如图1所示，本申请实施例提供的显示面板的结构示意图，为了便于说明，仅示出了与本申请实施例相关的部分。
如图所示，显示面板包括像素阵列10、多条栅极线11及多条数据线12，所述栅极线和所述数据线相互垂直，每两条栅极线对应连接一行子像素，每条数据线对应连接两列子像素；每行像素对应连接两条栅极线11，且任意两条栅极线相互平行；相邻两行所述栅极线存在预设长度差异；所述的预设长度可以根据显示面板的具体尺寸的实际需求进行设置，设置预设长度差异使显示面板处于检测状态，实现对显示面板的阵列检测。每两列子像素连接在一条数据 线12上，且任意两条数据线相互平行；如图1所示，2n条栅极线对应n行像素，m条数据线对应2m列子像素；相邻两行所述栅极线设置为不等长度；其中，m≥1，n≥1且m和n均为正整数。
像素阵列中的每行子像素均包括多组子像素，每组子像素均包括依次排列的第一颜色子像素、第二颜色子像素和第三颜色子像素，位于同一列的子像素的颜色相同，第一颜色子像素、第二颜色子像素和第三颜色子像素中至少有一个为红色子像素、至少有一个为绿色子像素且至少有一个为蓝色子像素。
在一个实施例中，所有奇数行栅极线的长度设置为为第一长度；所有偶数行栅极线的长度设置为为第二长度；第一长度大于第二长度。
在一个实施例中，所有奇数行栅极线的长度设置为第三长度；所有偶数行栅极线的长度设置为第四长度；第三长度大于第四长度。
在一个实施例中，所有奇数行栅极线的长度可以分别不相等，所有偶数行栅极线的长度可以分别不相等，且偶数行栅极线与奇数行栅极线长度不相等。
在一个实施例中，像素阵列的行数和列数可以根据具体需要进行设定，不对像素阵列的大小作特别限定。
本实施例采用基于半源驱动架构的显示面板，每两条栅极线对应连接一行子像素，连接同一行像素的两条栅极线之间的第一间隔，与连接不同行子像素的相邻两行栅极线之间的第二间隔，由于第一间隔与第二间隔不相等，从而无法通过均匀脉冲信号进行栅极线通路状况的检测；通过将栅极线设置成不等长度，引出栅极线用于检测的一端的部分栅极线，根据不同长度的栅极线，便于对用于检测部分的栅极线设置为相互平行等行间距，满足对通路状况检测的条件。
在一个实施例中，显示面板的每条栅极线与子像素连接的第一部分，呈直 线设置，用于阵列检测第二部分呈直线或折线设置，其中第一部分与第二部分组成一条完整的栅极线。
在一个实施例中，显示面板可以包括M行×N列子像素，即显示面板包括一个子像素个数为M×N的子像素阵列，每列子像素均包括多组子像素，每组子像素均包括依次排列的第一颜色子像素、第二颜色子像素和第三颜色子像素；其中N≥1，M≥1且M，N均为正整数。
在一个实施例中，上述像素阵列中，位于同一列的子像素的颜色相同，相邻列的子像素的颜色不同。
在一个实施例中，第一颜色子像素、第二颜色子像素和第三颜色子像素分别为红色子像素、绿色子像素、蓝色子像素和白色子像素中的任一种，并且第一颜色子像素、第二颜色子像素和第三颜色子像素的颜色各不相同。
如图2所示，本申请实施例提供的显示面板具体的结构示意图，为了便于说明，仅示出了与本申请实施例相关的部分。
如图所示，偶数行栅极线的末端呈折线布置，折线20包括第一线段21和第二线段22；偶数行栅极线的第二线段22与相邻的奇数行栅极线相互平行且行间距为第一距离，即y1＝y2；例如：对于23.5寸的显示装置的显示面板的像素间距为381.75微米，将其显示面板的栅极线末端的行间距设置成y1＝y2＝190.875微米。
在一个实施例中，偶数行栅极线的第二线段部分与相邻两条奇数行栅极线相互平行，所述第二线段部分与相邻奇数行栅极线的行间距相等；将偶数行栅极线的第二线段部分以及与第二线段对应的栅极线部分作为阵列检测部分，从而可以通过脉冲宽度均匀的检测信号对栅极线通路状况进行检测。
在一个实施例中，如图3所示的本申请实施例提供的显示面板另一具体的 结构示意图，奇数行栅极线的末端呈折线布置，折线30包括第三线段31和第四线段32；奇数行栅极线的第四线段32与相邻的偶数行栅极线相互平行，行间距为第二距离，即y3＝y4；例如：对于32寸的显示装置的显示面板的像素间距为510.75微米，则将其显示面板的栅极线末端的行间距设置成y3＝y4＝255.375微米。
在一个实施例中，奇数行栅极线的第四线段部分与其相邻的两条偶数行栅极线相互平行，所述第四线段部分与相邻偶数行栅极线的行间距相等；将奇数行栅极线的第四线段部分以及与第四线段对应的偶数行栅极线部分作为阵列检测部分，从而可以通过脉冲宽度均匀的检测信号对栅极线通路状况进行检测。
本申请实施例，通过使显示面板的所有栅极线的末端均保持相等的行间距，以便于在对面板进行阵列检测时，可以通过宽窄相等的时序脉冲信号，对显示面板的栅极线的短路或断路实现检测，提高显示面板的生产良率。
如图4所示，本申请实施例提供了另一显示面板的结构示意图，为了便于说明，仅示出了与本申请实施例相关的部分。
如图所示，显示面板包括像素阵列、多行栅极线以及多列数据线；每个像素包括红、绿、蓝三个子像素；每行像素对应连接两条栅极线，且任意两条栅极线相互平行；每两列子像素连接在一条数据线上，且任意两条数据线相互平行；例如：2n条栅极线对应n行像素，m条数据线对应2m列子像素；奇数行栅极线的长度均相等，偶数行栅极线的长度均相等。显示面板还包括多条基准电压线40，每行像素对应的两条栅极线之间设置一条基准电压线40，每行像素对应连接一条基准电压线40；任一条基准电压线的末端与任一条栅极线相互平行，每一行像素对应的基准电压线与同一行像素液晶电容一端、存储电容 的一端均连接。
如图5所示，本申请实施例提供的另一显示面板的具体结构示意图，为了便于说明，仅示出了与本申请实施例相关的部分。基准电压线的末端呈折线布置且偶数行栅极线的末端呈折线布置，基准电压线的折线500包括第五线段501和第六线段502，偶数行栅极线的折线510包括第七线段511和第八线段512；任一条基准电压线的第六线段502与任一条偶数行栅极线的第八线段512相互平行，且均与奇数行栅极线平行。其中，基准电压线的第六线段502与相邻的奇数行栅极线之间的行间距为第三距离，基准电压线的第六线段502与相邻的偶数行栅极线的第八线段512之间的行间距为第三距离，偶数行栅极线的第六线段502与相邻的奇数行栅极线之间的行间距为第三距离，即x1＝x2＝x3；例如：对于23.5寸的显示装置的显示面板的像素间距为381.75微米，将其显示面板的栅极线末端的行间距设置成x1＝x2＝x3＝127.25微米。
在一个实施例中，偶数行栅极线的第八线段与基准电压线的第六线段以及奇数行栅极线之间相互平行，且基准电压线的第六线段分别与第八线段、奇数行栅极线的行间距相等；将第六线段、第八线段以及与第六线段对应的奇数行栅极线部分作为阵列检测部分，通过脉冲宽度均匀的检测信号对栅极线通路状况进行检测。
如图6所示，本申请实施例提供的另一显示面板的具体结构示意图，为了便于说明，仅示出了与本申请实施例相关的部分。基准电压线末端呈折线布置且奇数行栅极线末端呈折线布置，基准电压线的折线500包括第五线段501和第六线段502，奇数行栅极线的折线600包括第九线段601和第十线段602；任一条基准电压线的第六线段502与任一条奇数行栅极线的第十线段602相互平行，且均与偶数行的栅极线平行。基准电压线的第六线段502与相邻的偶数 行栅极线之间的行间距为第四距离，基准电压线的第六线段502与相邻的奇数行栅极线的第十线段602之间的行间距为第四距离，奇数行栅极线的第十线段602与相邻的偶数行栅极线之间的行间距为第四距离，即x4＝x5＝x6；例如：对于32寸的显示装置的显示面板的像素间距为510.75微米，则将其显示面板的栅极线末端的行间距设置成x4＝x5＝x6＝170.25微米。
在一个实施例中，奇数行栅极线的第十线段与基准电压线的第六线段以及偶数行栅极线相互平行，且基准电压线的第六线段分别与第十线段、偶数行栅极线的行间距相等；将第六线段、第十线段以及与第六线段对应的偶数行栅极线部分作为阵列检测部分，通过脉冲宽度均匀的检测信号对栅极线通路状况进行检测。
本申请实施例，通过将显示面板的基准电压线的末端、奇数行栅极线末端之间的行间距与基准电压线的末端、偶数行栅极线末端之间的行间距设置为相等，在对面板进行阵列检测时，根据均匀的时序脉冲信号实现对显示面板的栅极线以及基准电压线的短路或断路检测，提高显示面板的生产良率。
如图7所示，本申请实施例提供的显示面板的检测方法的实现流程示意图，该检测方法应用于对上述显示面板的阵列检测，以提高显示面板的生产良率。所述检测方法可以包括以下步骤：
步骤S301，输出第一等间隔时序脉冲信号至显示面板的栅极线；
步骤S302，获取所述栅极线输出的第二等间隔时序脉冲信号；
步骤S303，根据所述第一等间隔时序脉冲信号和所述第二等间隔时序脉冲信号，判断所述栅极线是否发生故障；
步骤S304，输出第三等间隔时序脉冲信号至显示面板的基准电压线；
步骤S305，获取所述基准电压线输出的第四等间隔时序脉冲信号；
步骤S306，根据所述第三等间隔时序脉冲信号和所述第四等间隔时序脉冲信号，判断所述基准电压线是否发生故障。
在本实施例中，为了保证显示面板的整个工艺过程的结果都在管控范围之内，避免不合格产品的出现，在完成面板像素阵列的布线工艺后进行相应的工程检查，对显示面板的阵列检测有短路或断路检查，可以采用非接触式的检查；通过脉冲信号发生装置匀速扫描栅极线的末端，输出等间隔时序脉冲信号至栅极线，接收反馈的等间隔的时序脉冲信号，并根据发出的时序脉冲信号以及接收的时序脉冲信号，判断栅极线或基准电压线是否发生短路或断路。对栅极线的阵列扫描检查也可以是由检测装置发出电子束信号至栅极线，所接收的信号可以是二次电子信号，二次电子信号的强弱由像素上的电压与检测装置之间的电压差决定，二次电子量变化反应了像素上的电压变化，存在缺陷和正常的电压值完全不同，即可以根据电压信号的变化确定栅极线、基准电压线或像素电极是否发生短路或断路。
本申请实施例将偶数行栅极线与奇数行栅极线设置成不等的长度，使栅极线存在预设长度差异，便于将栅极线末端设置成奇数行栅极线末端与偶数行的栅极线末端的行间距相等，基准电压线末端、偶数行栅极线末端之间的行间距与基准电压线末端、奇数行栅极线末端之间的行间距相等，使显示面板处于能够进行阵列检测的状态，通过匀速扫描栅极线以及基准电压线的末端，对栅极线以及基准电压线进行故障检测，节省检测时间，节约消耗品成本，且对显示面板表面无损害，进而提高了显示面板的生产良率。
应理解，上述实施例中各步骤的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本申请实施例的实施过程构成任何限定。
参见图8，是本申请实施例提供的显示装置的示意图，为了便于说明，仅示出了与本申请实施例相关的部分。
所述显示装置200包括显示面板201，其中，所述显示面板包括：
像素阵列、多行栅极线和多列数据线，所述栅极线和所述数据线相互垂直，每两条栅极线对应连接一行子像素，每条数据线对应连接两列子像素；
每行所述像素对应连接两条所述栅极线且任意两条所述栅极线相互平行；
相邻两行所述栅极线存在预设长度差异。
在本实施例中，显示面板可以为任意类型的显示面板，例如基于LCD(Liquid Crystal Display，液晶显示装置)技术的液晶显示面板、基于OLED(Organic Electroluminesence Display，有机电激光显示)技术的有机电激光显示面板、基于QLED(Quantum Dot Light Emitting Diodes，量子点发光二极管)技术的量子点发光二极管显示面板或曲面显示面板等。
本领域普通技术人员可以理解实现上述实施例方法中的全部或部分流程，是可以通过计算机程序来指令相关的硬件来完成，所述的程序可存储于一计算机可读取存储介质中，该程序在执行时，可包括如上述各方法的实施例的流程。其中，所述的存储介质可为磁碟、光盘、只读存储记忆体(Read-Only Memory，ROM)或随机存储记忆体(Random Access Memory，RAM)等。
以上所述仅为本申请的较佳实施例而已，并不用以限制本申请，凡在本申请的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本申请的保护范围之内。

Claims (18)

  1. 一种显示面板，包括像素阵列、多行栅极线和多列数据线，所述栅极线和所述数据线相互垂直，每两条栅极线对应连接一行子像素，每条数据线对应连接两列子像素；
    每行所述像素对应连接两条所述栅极线且任意两条所述栅极线相互平行；
    相邻两行所述栅极线存在预设长度差异。
  2. 根据权利要求1所述的显示面板，其中，所有奇数行栅极线的长度设置为第一长度；所有偶数行栅极线的长度设置为第二长度；第一长度大于第二长度。
  3. 根据权利要求1所述的显示面板，其中，所有奇数行栅极线的长度设置为第三长度；所有偶数行栅极线的长度设置为第四长度；第三长度大于第四长度。
  4. 根据权利要求1所述的显示面板，其中，将栅极线用于检测的一端设置为相互平行且等行间距。
  5. 根据权利要求1所述的显示面板，其中，显示面板的每条栅极线与子像素连接的第一部分，呈直线设置，用于阵列检测第二部分呈直线或折线设置，其中第一部分与第二部分组成一条完整的栅极线。
  6. 根据权利要求1所述的显示面板，其中，所述偶数行栅极线的末端呈折线布置，所述折线包括第一线段和第二线段；
    所述偶数行栅极线的第二线段与相邻的奇数行栅极线相互平行且行间距为第一距离。
  7. 根据权利要求6所述的显示面板，其中，偶数行栅极线的第二线段部分与相邻两条奇数行栅极线相互平行，所述第二线段部分与相邻奇数行栅极线 的行间距相等。
  8. 根据权利要求1所述的显示面板，其中，所述奇数行栅极线的末端呈折线布置，所述折线包括第三线段和第四线段；
    所述奇数行栅极线的第四线段与相邻的偶数行栅极线相互平行且行间距为第二距离。
  9. 根据权利要求8所述的显示面板，其中，奇数行栅极线的第四线段部分与其相邻的两条偶数行栅极线相互平行，所述第四线段部分与相邻偶数行栅极线的行间距相等。
  10. 根据权利要求1所述的显示面板，其中，还包括多条基准电压线，每行像素对应的两条栅极线之间设置一条所述基准电压线，每行像素对应连接一条所述基准电压线；
    任一条所述基准电压线的末端与任一条所述栅极线相互平行。
  11. 根据权利要求10所述的显示面板，其中，所述基准电压线的末端呈折线布置且所述偶数行栅极线的末端呈折线布置，所述基准电压线的折线包括第五线段和第六线段，所述偶数行栅极线的折线包括第七线段和第八线段；
    任一条所述基准电压线的第六线段与任一条偶数行栅极线的第八线段相互平行，且均与奇数行栅极线平行。
  12. 根据权利要求11所述的显示面板，其中，所述基准电压线的第六线段与相邻的奇数行栅极线之间的行间距为第三距离，所述基准电压线的第六线段与相邻的偶数行栅极线的第八线段之间的行间距为第三距离，所述偶数行栅极线的第八线段与相邻的奇数行栅极线之间的行间距为第三距离。
  13. 根据权利要求12所述的显示面板，其中，偶数行栅极线的第八线段与基准电压线的第六线段以及奇数行栅极线之间相互平行，且基准电压线的第 六线段分别与第八线段、奇数行栅极线的行间距相等。
  14. 根据权利要求10所述的显示面板，其中，所述基准电压线末端呈折线布置且所述奇数行栅极线末端呈折线布置，所述基准电压线的折线包括第五线段和第六线段，所述奇数行栅极线的折线包括第九线段和第十线段；
    任一条所述基准电压线的第六线段与任一条奇数行栅极线的第十线段相互平行，且均与偶数行的栅极线平行。
  15. 根据权利要求14所述的显示面板，其中，所述基准电压线的第六线段与相邻的偶数行栅极线之间的行间距为第四距离，所述基准电压线的第六线段与相邻的奇数行栅极线的第十线段之间的行间距为第四距离，所述奇数行栅极线的第十线段与相邻的偶数行栅极线之间的行间距为第四距离。
  16. 根据权利要求15所述的显示面板，其中，奇数行栅极线的第十线段与基准电压线的第六线段以及偶数行栅极线相互平行，且基准电压线的第六线段分别与第十线段、偶数行栅极线的行间距相等。
  17. 一种检测方法，包括：
    输出第一等间隔时序脉冲信号至显示面板的栅极线；
    获取所述栅极线输出的第二等间隔时序脉冲信号；
    根据所述第一等间隔时序脉冲信号和所述第二等间隔时序脉冲信号，判断所述栅极线是否发生故障；
    输出第三等间隔时序脉冲信号至显示面板的基准电压线；
    获取所述基准电压线输出的第四等间隔时序脉冲信号；
    根据所述第三等间隔时序脉冲信号和所述第四等间隔时序脉冲信号，判断所述基准电压线是否发生故障。
  18. 一种显示装置，包括显示面板，其中，所述显示面板包括：
    像素阵列、多行栅极线和多列数据线，所述栅极线和所述数据线相互垂直，每两条栅极线对应连接一行子像素，每条数据线对应连接两列子像素；
    每行所述像素对应连接两条所述栅极线且任意两条所述栅极线相互平行；
    相邻两行所述栅极线存在预设长度差异。
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Families Citing this family (2)

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CN109188743A (zh) * 2018-11-14 2019-01-11 惠科股份有限公司 显示面板的制作方法及显示装置
CN114822014B (zh) * 2021-01-19 2023-11-03 北京隐空科技有限公司 基于柔性轨道进路式点阵结构的区域检测系统及方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5546013A (en) * 1993-03-05 1996-08-13 International Business Machines Corporation Array tester for determining contact quality and line integrity in a TFT/LCD
CN102236231A (zh) * 2011-04-12 2011-11-09 友达光电股份有限公司 半源驱动显示面板
CN102194399B (zh) * 2010-11-12 2014-03-19 友达光电股份有限公司 半源显示装置的驱动方法
CN106547128A (zh) * 2015-09-22 2017-03-29 三星显示有限公司 显示装置
CN105096786B (zh) * 2015-08-19 2017-08-29 京东方科技集团股份有限公司 阵列检测可靠性判断方法、有机发光背板检测方法及装置
CN103163683B (zh) * 2011-12-14 2018-09-11 三菱电机株式会社 双画面显示装置

Family Cites Families (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7724920B2 (en) * 1995-05-08 2010-05-25 Digimarc Corporation Digital authentication with analog documents
US6069464A (en) * 1998-10-01 2000-05-30 Umax Data Systems Inc. Driving apparatus for an image processing system
KR20050118059A (ko) * 2004-05-31 2005-12-15 엘지.필립스 엘시디 주식회사 구동 회로가 내장된 액정 표시 패널
CN101449202B (zh) * 2006-08-31 2011-02-09 夏普株式会社 显示面板和包括该显示面板的显示装置
JP5214601B2 (ja) * 2007-06-12 2013-06-19 シャープ株式会社 液晶表示装置、液晶表示装置の駆動方法、及びテレビジョン受像機
WO2008155889A1 (ja) * 2007-06-18 2008-12-24 Panasonic Corporation 映像表示装置
TWI377383B (en) * 2008-05-05 2012-11-21 Au Optronics Corp Pixel, display and the driving method thereof
US8345211B2 (en) * 2008-08-20 2013-01-01 Sharp Kabushiki Kaisha Display apparatus and manufacturing method therefor, and active matrix substrate
JP5218222B2 (ja) * 2009-03-31 2013-06-26 カシオ計算機株式会社 画素駆動装置、発光装置及び発光装置の駆動制御方法
JP5299407B2 (ja) * 2010-11-16 2013-09-25 株式会社ジャパンディスプレイ 液晶表示装置
KR101778650B1 (ko) * 2011-02-23 2017-09-15 삼성디스플레이 주식회사 표시 패널 및 이를 포함하는 표시 장치
KR101840220B1 (ko) * 2011-10-10 2018-03-21 삼성디스플레이 주식회사 터치 표시 패널의 구동 방법 및 이에 적합한 터치 표시 장치
CN102332245A (zh) * 2011-10-14 2012-01-25 深圳市华星光电技术有限公司 液晶显示装置及其驱动方法
CN103513808B (zh) * 2012-06-29 2016-09-07 上海天马微电子有限公司 触摸面板、触摸显示面板、触摸检测及显示方法
JP5984306B2 (ja) * 2012-08-22 2016-09-06 富士フイルム株式会社 放射線撮影システムおよびこれに用いられる信号中継装置
JP2015045726A (ja) * 2013-08-28 2015-03-12 シナプティクス・ディスプレイ・デバイス株式会社 表示駆動装置及び表示装置
US10147371B2 (en) * 2014-06-27 2018-12-04 Lg Display Co., Ltd. Display device having pixels with shared data lines
CN104167177A (zh) * 2014-08-15 2014-11-26 合肥鑫晟光电科技有限公司 像素电路、有机电致发光显示面板及显示装置
KR102243210B1 (ko) * 2014-08-19 2021-04-23 삼성디스플레이 주식회사 표시 장치
CN104361877B (zh) * 2014-12-09 2016-08-17 京东方科技集团股份有限公司 一种显示面板的驱动方法、其驱动装置及显示装置
CN104464587B (zh) * 2014-12-31 2017-04-19 深圳市华星光电技术有限公司 一种阵列基板及其检测电路
KR20160087459A (ko) * 2015-01-13 2016-07-22 삼성디스플레이 주식회사 표시 장치 및 그 구동방법
JP6399936B2 (ja) * 2015-01-14 2018-10-03 キヤノン株式会社 電子機器、電子機器の制御方法、プログラム、及び記憶媒体
CN105047115B (zh) * 2015-08-10 2018-03-27 武汉华星光电技术有限公司 检测驱动电路、检测驱动装置及检测方法
KR102400302B1 (ko) * 2015-09-08 2022-05-23 삼성디스플레이 주식회사 표시 패널 및 이의 점등 검사선 형성 방법
CN205487263U (zh) * 2015-12-31 2016-08-17 上海天马微电子有限公司 一种阵列基板、显示装置及用于检测阵列基板的电路
CN106201107B (zh) * 2016-07-29 2019-01-22 厦门天马微电子有限公司 一种触控显示面板及其驱动方法、触控显示装置
CN106125438B (zh) * 2016-09-05 2019-07-23 京东方科技集团股份有限公司 一种阵列基板、显示装置及其驱动方法
CN106200181A (zh) * 2016-09-07 2016-12-07 深圳市华星光电技术有限公司 一种液晶显示面板测试线路及液晶显示面板
CN106292110A (zh) * 2016-09-23 2017-01-04 京东方科技集团股份有限公司 一种阵列基板、显示面板、显示装置
CN106409257B (zh) * 2016-11-08 2019-03-15 京东方科技集团股份有限公司 一种显示面板的驱动方法及其驱动电路
TWI613640B (zh) * 2017-02-24 2018-02-01 友達光電股份有限公司 觸控顯示裝置
KR102356588B1 (ko) * 2017-04-06 2022-01-28 삼성디스플레이 주식회사 표시 장치 및 이의 구동 방법
CN107315502B (zh) * 2017-06-30 2020-05-19 上海天马微电子有限公司 显示面板、显示装置和压力检测方法
CN107749282A (zh) * 2017-11-03 2018-03-02 惠科股份有限公司 一种显示面板及显示装置
CN107862998B (zh) * 2017-11-09 2020-05-19 深圳市华星光电半导体显示技术有限公司 一种柔性goa显示面板及其制作方法
CN108364567B (zh) * 2018-01-30 2020-06-05 厦门天马微电子有限公司 显示面板和显示装置
CN108447439B (zh) * 2018-05-14 2019-07-02 昆山国显光电有限公司 阵列基板、显示屏及显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5546013A (en) * 1993-03-05 1996-08-13 International Business Machines Corporation Array tester for determining contact quality and line integrity in a TFT/LCD
CN102194399B (zh) * 2010-11-12 2014-03-19 友达光电股份有限公司 半源显示装置的驱动方法
CN102236231A (zh) * 2011-04-12 2011-11-09 友达光电股份有限公司 半源驱动显示面板
CN103163683B (zh) * 2011-12-14 2018-09-11 三菱电机株式会社 双画面显示装置
CN105096786B (zh) * 2015-08-19 2017-08-29 京东方科技集团股份有限公司 阵列检测可靠性判断方法、有机发光背板检测方法及装置
CN106547128A (zh) * 2015-09-22 2017-03-29 三星显示有限公司 显示装置

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