WO2020097991A1 - 显示面板的驱动方法和驱动电路 - Google Patents

显示面板的驱动方法和驱动电路 Download PDF

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Publication number
WO2020097991A1
WO2020097991A1 PCT/CN2018/118047 CN2018118047W WO2020097991A1 WO 2020097991 A1 WO2020097991 A1 WO 2020097991A1 CN 2018118047 W CN2018118047 W CN 2018118047W WO 2020097991 A1 WO2020097991 A1 WO 2020097991A1
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WIPO (PCT)
Prior art keywords
active switch
resistor
circuit
display panel
driving
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PCT/CN2018/118047
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English (en)
French (fr)
Inventor
邱彬
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惠科股份有限公司
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Application filed by 惠科股份有限公司 filed Critical 惠科股份有限公司
Priority to US16/319,483 priority Critical patent/US11488525B2/en
Publication of WO2020097991A1 publication Critical patent/WO2020097991A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0814—Several active elements per pixel in active matrix panels used for selection purposes, e.g. logical AND for partial update
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/027—Arrangements or methods related to powering off a display

Definitions

  • the present application relates to the field of display technology, and in particular to a driving method and driving circuit of a display panel.
  • Flat panel displays have become the mainstream products of the display due to the hot spots such as thin body, power saving and low radiation, which have been widely used.
  • Flat panel displays include thin film transistor liquid crystal displays (Thin Film Transistor-Liquid Crystal Display, TFT-LCD).
  • TFT-LCD Thin Film Transistor-Liquid Crystal Display
  • the driving circuit splits the original gate driving chip into two parts, one part is a boosting chip arranged on a driving circuit board, and the other part a shift register is arranged on a panel.
  • the boost chip sends signals to the shift register to complete the drive, which can compress the length of the frame.
  • the present application provides a driving method and driving circuit for a display panel to ensure that the display panel is normally closed.
  • the present application provides a driving method of a display panel, including the steps of:
  • the step of outputting the shutdown signal includes: outputting the shutdown signal when the power supply voltage drops to a preset value.
  • the step of turning on the active switch corresponding to the pixel includes: switching a low-level signal driving the active switch into a high-level signal through a switching circuit, and turning on the active switch corresponding to the pixel.
  • the step of closing the display panel includes the display panel receiving a shutdown signal and closing the display panel.
  • This application also discloses a driving method of a display panel, including the steps of:
  • the low-level signal driving the active switch is switched to a high-level signal, and the corresponding active switch corresponding to the pixel is turned on;
  • the present application also discloses a driving circuit for a display panel, including: a power supply circuit that outputs a shutdown signal; a pixel control circuit that turns on an active switch corresponding to the pixel; a shutdown circuit that turns off the display panel.
  • the power supply circuit includes a power supply.
  • a control signal is output through the power supply circuit.
  • the circuit control signal includes a high-level signal, a low-level signal, and a circuit switching signal.
  • the active switch corresponding to the pixel is turned on by the circuit control signal.
  • the pixel control circuit includes: a first logic circuit configured to output a first control signal to close the active switch; a second logic circuit configured to output a second control signal to open the active switch; switching The circuit is set to switch between the first logic circuit and the second logic circuit; when the display panel is closed, the switching circuit controls the second logic circuit to open, and controls the active switch to open.
  • the first logic circuit includes a first resistor, a second resistor, and a first active switch, wherein the first resistor is connected to a second resistor, the second resistor is connected to the switching circuit, and the first The drain of the active switch is connected to the control end of the active switch, the gate of the first active switch is connected between the first resistor and the second resistor, and the first active switch is connected to the power circuit .
  • the switching circuit includes a third active switch, and a source of the third active switch is connected to the second resistor.
  • the second logic circuit includes a third resistor, a fourth resistor, and a second active switch, wherein the third resistor and the fourth resistor are connected, the fourth resistor is connected to the switching circuit, the The gate of the second active switch is connected between the third resistor and the fourth resistor, and the drain of the second active switch is connected to the control terminal of the active switch.
  • the switching circuit includes a fourth active switch, and a source of the fourth active switch is connected to the fourth resistor.
  • the switching circuit includes a third active switch, a fourth active switch, and a logic power supply; the drain of the third active switch is connected to the logic power supply, and the source of the third active switch is connected to the The first logic circuit is connected; the source of the fourth active switch is connected to the second logic circuit.
  • the first logic circuit includes a first resistor, a second resistor, and a first active switch, wherein the first resistor is connected to the second resistor, and the drain of the first active switch is connected to the active switch
  • the control terminal of the first active switch is connected between the first resistor and the second resistor, the first active switch is connected to the power circuit
  • the second logic circuit includes a third A resistor, a fourth resistor and a second active switch, wherein the third resistor and the fourth resistor are connected, the gate of the second active switch is connected between the third resistor and the fourth resistor, the second
  • the drain of the active switch is connected to the control end of the active switch
  • the switching circuit includes a third active switch, a fourth active switch, and a logic power supply; the drain of the third active switch is connected to the logic power supply.
  • the source of the third active switch is connected to the second resistor; the source of the fourth active switch is connected to the fourth resistor.
  • this application uses a new peripheral drive circuit to switch the low-level signal to a high-level signal when the display panel is closed, turn on all active switches corresponding to the pixels, and The output channels are all open, and the charge stored in the panel will be quickly released to ensure that the display panel is normally closed.
  • FIG. 1 is a schematic diagram of an exemplary driving circuit of a display panel
  • FIG. 2 is a schematic diagram of an exemplary shift register driving circuit
  • FIG. 3 is a schematic flowchart of a driving method according to an embodiment of the present application.
  • FIG. 4 is a schematic flowchart of a driving method according to another embodiment of the present application.
  • FIG. 5 is a schematic diagram of a driving circuit according to another embodiment of the present application.
  • FIG. 6 is a schematic diagram of a voltage signal of a driving circuit according to another embodiment of the present application.
  • the features defined as “first” and “second” may explicitly or implicitly include one or more features.
  • the meaning of “plurality” is two or more.
  • the term “comprising” and any variations thereof are intended to cover non-exclusive inclusions.
  • connection should be understood in a broad sense, for example, it can be fixed connection or detachable Connected, or connected integrally; either mechanically or electrically; directly connected, or indirectly connected through an intermediary, or internally connected between two components.
  • installation should be understood in a broad sense, for example, it can be fixed connection or detachable Connected, or connected integrally; either mechanically or electrically; directly connected, or indirectly connected through an intermediary, or internally connected between two components.
  • FIG. 1 is a new gateless driver (GDL) drive architecture, which divides the gate driver chip (Gate IC) into two parts: a boost chip 110 and a shift register 210.
  • the pressure chip is disposed on the driving circuit board 100, the shift register 310 is disposed on the side of the panel display area 200, and the driving signal is transmitted to the shift register through the boost chip 110 to complete the driving.
  • GDL gateless driver
  • FIG. 2 is the drive circuit of the shift register, where T11, T21, T31 and T41 are MOS (Metal, Oxide, Semiconductor, MOS) tubes, the output signal of the previous line pulls the potential of Q point high through T11, and the CK / XCK signal is equivalent to Forcibly charge G (N), and finally when G (N + 1) output is high, turn on T31 and T41, the potentials of Q point and G (N) point are both pulled down, and the G (N) line is completed at this time Charging and shutting down process.
  • the CK / XCK voltage is directly pulled high, but this approach cannot guarantee that all output channels are turned on, which affects the normal closing of the display panel.
  • an embodiment of the present application discloses a driving method, and the steps include:
  • the new gateless driver (Gate driverless, GDL) architecture is increasingly used in the narrow border design of TVs.
  • the gateless driver circuit splits the original gate driver chip into a boost chip and a shift register .
  • This method cannot open all the output channels corresponding to the pixels, and cannot discharge the charge stored in the panel as soon as possible, which affects the closing of the display panel screen.
  • This application uses a new driving method. When receiving the shutdown signal, all active switches corresponding to the pixels are turned on. At this time, all output channels are turned on, and the charge stored in the panel will be quickly released to ensure that the display panel is normally closed.
  • S41 when the power supply voltage drops to a preset value, output a shutdown signal of the display panel.
  • the power supply voltage is generally 12V.
  • a preset value is set for the power supply voltage.
  • the power supply voltage value falls to the preset value, it is judged that the display panel is now turned off and a shutdown signal is output.
  • preset values generally set to 8-9V.
  • S42 Switch the low-level signal driving the active switch to a high-level signal through a switching circuit, and turn on the corresponding active switch of the pixel.
  • the circuit when the circuit outputs a shutdown signal, the low-level signal that drives the active switch is switched to a high-level signal through a switching circuit. At this time, the active switches corresponding to the pixels are all turned on, and all output channels when the display panel is closed All open, the charge release speed in the panel is accelerated.
  • the step of closing the display panel includes: the display panel receives the shutdown signal and closes the display panel.
  • the display panel closes the display panel to ensure that the display panel is normally closed.
  • a driving method is disclosed, and the steps include:
  • S42 Switch the low-level signal driving the active switch to a high-level signal through the switching circuit, and turn on the corresponding active switch of the pixel;
  • the preset value is first set when the display panel is closed, and the preset value is set.
  • the power supply voltage reaches the preset value, it is determined that the display panel is closed, and a shutdown signal is output at this time.
  • the output signal is switched through the switching circuit, the original low-level signal is switched to the high-level signal, the active switch corresponding to the pixel is turned on, all output channels are opened, and the charge stored in the panel is quickly released to ensure that the display panel is normally closed .
  • a driving circuit including: a power supply circuit 300 configured to output a shutdown signal; a pixel control circuit 400 configured to turn on an active switch corresponding to a pixel; a shutdown circuit , Set to close the display panel.
  • the driving circuit includes a power supply circuit 300, a pixel control circuit 400, and a shutdown circuit, where the pixel control circuit 400 is the core of the driving circuit.
  • the active switch corresponding to the pixel can be turned on to ensure that the charge in the panel is quickly discharged, thereby ensuring that the display panel is normally closed.
  • the power supply circuit 300 includes a power supply, and outputs a control signal through the power supply.
  • the internal voltage is distributed to each circuit by the power supply, and the circuit control signal output by the power supply controls the entire circuit of the display panel.
  • the circuit control signal includes a high level signal, a low level signal, and a circuit switching signal.
  • the drive circuit switches the high-level signal and the low-level signal to ensure the normal shutdown of the display panel.
  • the active switch corresponding to the pixel is turned on by the circuit control signal.
  • the circuit control signal is actually an on / off signal of the active switch corresponding to the pixel, and the active switch corresponding to the pixel is turned on or off by the circuit control signal.
  • the pixel control circuit 400 includes: a first logic circuit 410 configured to output a first control signal that closes the active switch, the first logic circuit is a low level path, and the output first control signal is low Level signal; the second logic circuit 420 is set to output a second control signal that turns on the active switch, the second logic circuit is a high level circuit, and the output second control signal is a high level signal; the switching circuit 430 is set to The first logic circuit 410 and the second logic circuit 420 are switched; when the display panel is closed, the switching circuit 430 controls the second logic circuit 430 to turn on, and the active switch is turned on.
  • the power circuit 300 when the power circuit 300 detects that the voltage has dropped to a preset value, it considers that it is in the state of closing the display panel at this time, and sends a shutdown signal.
  • the first logic circuit 410 is switched to the second logic circuit 430 through the switching circuit 430, the second logic circuit 430 is controlled to be turned on, and a high-level signal, that is, a VGH signal is output. With the output of the high-level signal, the active switch opens.
  • the first logic circuit 410 includes a first resistor R1, a second resistor R2, and a first active switch 411, wherein the first resistor R1 is connected to the second resistor R2, and the second resistor R2 is connected to the switching circuit 430, The drain of the first active switch 411 is connected to the active switch control terminal 500, the gate of the first active switch 411 is connected between the first resistor R1 and the second resistor R2, and the first active switch 411 is connected to the power circuit 300.
  • the first active switch 411 of the first logic circuit 410 is an N-type MOS (Metal, Oxide, Semiconductor, MOS) tube, wherein the drain of the first active switch 411 is connected to the active switch control terminal 500, and the first resistor R1 and The wire between the second resistor R2 is connected to the gate of the first active switch 411, the voltage between the first resistor R1 and the second resistor R2 is V1, when the switching circuit 430 is at a low level, V1 is greater than the low level voltage, The first active switch 411 is turned on and outputs a low-level signal; when the switching circuit 430 is at a high level, V1 is equal to the low-level voltage. At this time, the first active switch 411 is turned off and cannot output a low-level signal.
  • MOS Metal, Oxide, Semiconductor, MOS
  • the switching circuit 430 includes a third active switch 431 whose source is connected to the second resistor R2.
  • the second resistor R2 in the first logic circuit 410 is connected to the switching circuit 430, in fact, the second resistor R2 is connected to the source of the third active switch 431.
  • the second logic circuit 420 includes a third resistor R3, a fourth resistor R4, and a second active switch 421, wherein the third resistor R3 and the fourth resistor R4 are connected, and the fourth resistor R4 is connected to the switching circuit 430,
  • the gate of the second active switch 421 is connected between the third resistor R3 and the fourth resistor R4, and the drain of the second active switch 421 is connected to the active switch control terminal 500.
  • the second active switch 421 of the second logic circuit 420 is a P-type MOS (Metal, Oxide, Semiconductor, MOS) tube. Similar to the first active switch 411, the gate of the second active switch 421 is connected to the first The voltage between the third resistor R3 and the fourth resistor R4, and the voltage between the third resistor R3 and the fourth resistor R4 is V2.
  • MOS Metal, Oxide, Semiconductor, MOS
  • V2 When the switching circuit 430 is at a low level, V2 is equal to a high-level voltage, and the second active switch 421 is turned off, and a high-level signal cannot be output; when the switching circuit 430 is at a high level, V2 is less than the high-level voltage, and the second active switch 421 When it is turned on, it outputs a high-level signal. At this time, the active switch is turned on and all output channels are turned on.
  • the switching circuit 430 includes a fourth active switch 432 whose source is connected to the fourth resistor R4.
  • the fourth resistor R4 in the second logic circuit 410 is connected to the switching circuit 430, in fact, the fourth resistor R4 is connected to the source of the fourth active switch 432.
  • the switching circuit 430 includes a third active switch 431, a fourth active switch 432, and a logic power supply VDD; the drain of the third active switch 431 is connected to the logic power supply VDD, and the source of the third active switch 431 is connected to the first A logic circuit 410 is connected; the source of the fourth active switch 432 is connected to the second logic circuit 420.
  • the third active switch 431 in the switching circuit is a P-type MOS (Metal, Oxide, Semiconductor, MOS) tube
  • the fourth active switch 432 is an N-type MOS (Metal, Oxide, Semiconductor, MOS) tube
  • the third active switch 431 The gate is connected to the gate of the fourth active switch 432.
  • the logic power supply VDD is 3.3V, and the working voltage of the logic circuit in the general chip is adopted.
  • the third active switch 431 and the fourth active switch 432 are respectively connected to corresponding circuits.
  • the first logic circuit 410 includes a first resistor R1, a second resistor R2, and a first active switch 411, wherein the first resistor R1 is connected to the second resistor R2, and the drain of the first active switch 411 is connected to the active
  • the switch control terminal 500 is connected, the gate of the first active switch 411 is connected between the first resistor R1 and the second resistor R2, the first active switch 411 is connected to the power circuit 300
  • the second logic circuit 420 includes a third resistor R3, The fourth resistor R4 and the second active switch 421, wherein the third resistor R3 and the fourth resistor R4 are connected, the gate of the second active switch 421 is connected between the third resistor R3 and the fourth resistor R4, the second active switch 421 Is connected to the active switch control terminal 500
  • the switching circuit 430 includes a third active switch 431, a fourth active switch 432, and a logic power supply VDD; the drain of the third active switch 431 is connected to the logic power supply VDD, and the third active switch
  • the first active switch 411 and the fourth active switch 432 are N-type MOS (Metal) Oxide Semiconductor (MOS) tubes, and the second active switch 421 and the third active switch 431 are P-type MOS (Metal Oxide Semiconductor). tube.
  • MOS Metal Oxide Semiconductor
  • the switching circuit 430 is at a low level.
  • the third active switch 431 is turned on, and the fourth active switch 432 is turned off.
  • the logic power supply VDD passes through the third active switch 431 and the first resistor R1, the second resistor R2 communicate with the first logic circuit 410, the intermediate voltage V1 of the first resistor R1 and the second resistor R2 is greater than the low level voltage, causing the first active switch 411 to turn on, and the low level signal to pass the first active switch 411 output, the fourth active switch 432 is turned off, the intermediate voltage V2 of the third resistor and the fourth resistor R4 is equal to the high level voltage, the third active switch 431 is also turned off, and the high level signal cannot be output; when the switching circuit 430 is high level , The third active switch 431 is turned off, the fourth active switch 432 is turned on, at this time V1 is equal to the low level voltage, the low level signal cannot be output, and at the same time, the fourth active switch 432 is turned on, V2 is less than the high level voltage, The second active switch 421 is turned on and outputs a high-level signal.
  • the original low-level signal is switched to
  • FIG. 6 is a voltage change diagram when the driving circuit of the present application closes the display panel, where T1 is the moment when the display panel is turned off, IP (Input Power, IP) is the input power supply voltage, and OP (Output, OP) is the output For the signal voltage, XON is the signal output by the switching circuit 430, VGL is the low-level signal voltage, and VGH is the high-level signal voltage.
  • IP Input Power, IP
  • OP Output, OP
  • XON is the signal output by the switching circuit 430
  • VGL is the low-level signal voltage
  • VGH is the high-level signal voltage.
  • the IP When starting to close the display panel, the IP begins to fall, when it reaches the preset value, the XON signal switches from low level to high level, and the circuit output is also converted from VGL to VGH, to ensure the maximum voltage drop until it drops to 0V , All charges in the panel are completely discharged, and the display panel is closed.
  • the technical solution of the present application can be widely used in various display panels, such as TN type display panel (full name Twisted Nematic, namely twisted nematic panel), IPS type display panel (In-Plane Switching, plane switching), VA type display
  • TN type display panel full name Twisted Nematic, namely twisted nematic panel
  • IPS type display panel In-Plane Switching, plane switching
  • the panel Multi-domain Vertica Alignment, multi-quadrant vertical alignment technology
  • OLED display panel organic light emitting diode

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Abstract

一种显示面板的驱动方法和驱动电路，驱动电路包括：电源电路(300)，输出关机信号；像素控制电路(400)，打开像素对应的主动开关；关机电路，关闭显示面板；其中像素控制电路(400)包括：第一逻辑电路(410)，输出关闭主动开关的第一控制信号；第二逻辑电路(420)，设置为输出打开主动开关的第二控制信号；切换电路(430)，设置为第一逻辑电路(410)和第二逻辑电路(420)切换；关闭显示面板时，打开像素对应的主动开关。

Description

显示面板的驱动方法和驱动电路
本申请要求于2018年11月14日提交中国专利局，申请号为CN201811350600.5，发明名称为“一种显示面板的驱动方法和驱动电路”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，尤其涉及一种显示面板的驱动方法和驱动电路。
背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然地构成现有技术。
随着科技的发展和进步，平板显示器由于具备机身薄、省电和辐射低等热点而成为显示器的主流产品，得到了广泛应用。平板显示器包括薄膜晶体管液晶显示器(Thin Film Transistor-Liquid Crystal Display，TFT-LCD)。人们对电视窄边框的需求越来越强烈，与之应运而生的无门(Gate driver less，GDL)驱动越来越受到欢迎。该驱动电路将原有的门驱动芯片拆分为两部分，一部分为升压芯片设置在驱动电路板上，另一部分移位寄存器设置在面板上。通过升压芯片输送信号到移位寄存器完成驱动，可以压缩边框长度。
关闭显示面板时无法保证所有输出通道都处于打开状态，面板存储的电荷无法快速释放，可能影响关闭显示面板时间甚至造成画面异常。
技术解决方案
本申请提供一种显示面板的驱动方法和驱动电路，保证正常关闭显示面板。
为实现上述目的，本申请提供了一种显示面板的驱动方法，包括步骤：
输出显示面板的关机信号；
打开像素对应的主动开关；
关闭显示面板。
可选的，所述输出关机信号的步骤包括：电源电压降低到预设值时，输出所述关机信号。
可选的，所述打开像素对应的主动开关的步骤包括：通过切换电路，将驱动所述主 动开关的低电平信号切换成高电平信号，打开像素对应主动开关。
可选的，所述关闭显示面板的步骤包括：显示面板接收关机信号，关闭显示面板。
本申请还公开了一种显示面板的驱动方法，包括步骤：
电源电压降低到预设值时，输出显示面板的关机信号；
通过切换电路，将驱动所述主动开关的低电平信号切换成高电平信号，打开像素对应主动开关；
关闭显示面板。
本申请还公开了一种显示面板的驱动电路，包括：电源电路，输出关机信号；像素控制电路，打开像素对应的主动开关；关机电路，关闭显示面板。
可选的，所述电源电路包括电源。
可选的，通过所述电源输出电路控制信号。
可选的，所述电路控制信号包括高电平信号、低电平信号和电路切换信号。
可选的，通过电路控制信号，打开像素对应的主动开关。
可选的，所述像素控制电路包括：第一逻辑电路，设置为输出关闭所述主动开关的第一控制信号；第二逻辑电路，设置为输出打开所述主动开关的第二控制信号；切换电路，设置为第一逻辑电路和第二逻辑电路切换；关闭显示面板时，所述切换电路控制第二逻辑电路打开,控制所述主动开关打开。
可选的，所述第一逻辑电路包括第一电阻、第二电阻和第一主动开关，其中所述第一电阻与第二电阻连接，第二电阻和所述切换电路连接，所述第一主动开关的漏极与所述主动开关的控制端连接，所述第一主动开关的栅极连接在所述第一电阻与第二电阻之间，所述第一主动开关与所述电源电路连接。
可选的，所述切换电路包括第三主动开关，所述第三主动开关的源极与所述第二电阻连接。
可选的，所述第二逻辑电路包括第三电阻、第四电阻和第二主动开关，其中所述第三电阻和第四电阻连接，所述第四电阻与所述切换电路连接，所述第二主动开关的栅极连接在所述第三电阻与第四电阻之间，所述第二主动开关的漏极与所述主动开关的控制 端连接。
可选的，所述切换电路包括第四主动开关，所述第四主动开关的源极与所述第四电阻连接。
可选的，所述切换电路包括第三主动开关、第四主动开关和逻辑电源；所述第三主动开关的漏极与所述逻辑电源连接，所述第三主动开关的源极与所述第一逻辑电路连接；所述第四主动开关的源极与所述第二逻辑电路连接。
可选的，所述第一逻辑电路包括第一电阻、第二电阻和第一主动开关，其中所述第一电阻与第二电阻连接，所述第一主动开关的漏极与所述主动开关的控制端连接，所述第一主动开关的栅极连接在所述第一电阻与第二电阻之间，所述第一主动开关与所述电源电路连接；所述第二逻辑电路包括第三电阻、第四电阻和第二主动开关，其中所述第三电阻和第四电阻连接，所述第二主动开关的栅极连接在所述第三电阻与第四电阻之间，所述第二主动开关的漏极与所述主动开关的控制端连接；所述切换电路包括第三主动开关、第四主动开关和逻辑电源；所述第三主动开关的漏极与所述逻辑电源连接，所述第三主动开关的源极与所述第二电阻连接；所述第四主动开关的源极与所述第四电阻连接。
相对于将输出点位电压直接拉高的方案来说，本申请采用新的外围驱动电路，关闭显示面板时将低电平信号切换为高电平信号，打开像素对应的所有主动开关，将所有输出通道都打开，面板存储的电荷会快速释放，保证正常关闭显示面板。
附图说明
所包括的附图用来提供对本申请实施例的的理解，其构成了说明书的一部分，进行例示本申请的实施方式，并与文字描述一起来阐释本申请的原理。显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。在附图中：
图1是一种范例性的显示面板的驱动电路示意图；
图2是一种范例性的移位寄存器驱动电路的示意图；
图3是本申请的一实施例的一种驱动方法的流程示意图；
图4是本申请的另一实施例的一种驱动方法的流程示意图；
图5是本申请的另一实施例的一种驱动电路的示意图；
图6是本申请的另一实施例的一种驱动电路电压信号的示意图。
具体实施方式
这里所公开的具体结构和功能细节仅仅是代表性的，并且是进行描述本申请的示例性实施例的目的。但是本申请可以通过许多替换形式来具体实现，并且不应当被解释成仅仅受限于这里所阐述的实施例。
在本申请的描述中，需要理解的是，术语“中心”、“横向”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。此外，术语“第一”、“第二”仅描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个特征。在本申请的描述中，除非另有说明，“多个”的含义是两个或两个以上。另外，术语“包括”及其任何变形，意图在于覆盖不排他的包含。
在本申请的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本申请中的具体含义。
这里所使用的术语仅仅是为了描述具体实施例而不意图限制示例性实施例。除非上下文明确地另有所指，否则这里所使用的单数形式“一个”、“一项”还意图包括复数。还应当理解的是，这里所使用的术语“包括”和/或“包含”规定所陈述的特征、整数、步骤、操作、单元和/或组件的存在，而不排除存在或添加一个或更多其他特征、整数、步骤、操作、单元、组件和/或其组合。
如图1和图2所示，图1为新型的无门(Gate driver less，GDL)驱动架构，将门驱 动芯片(Gate IC)拆分为升压芯片110和移位寄存器210两部分，其中升压芯片设置在驱动电路板100上，移位寄存器310设置在面板显示区200侧边，通过升压芯片110输送驱动信号到移位寄存器完成驱动，这样的驱动架构可以缩短显示器边框长度。
图2为移位寄存器的驱动电路，其中T11、T21、T31和T41为MOS(Metal Oxide Semiconductor,MOS)管，上一行输出信号通过T11将Q点电位拉高，CK/XCK信号通过T21对当强行G(N)进行充电，最后当G(N+1)输出为高电平时，将T31和T41打开，Q点和G(N)点电位均被拉低，此时完成G(N)行的充电和关闭过程。关闭显示面板时，直接将CK/XCK电压直接拉高，但这种做法无法保证所有输出通道都打开，影响正常关闭显示面板。
下面参考附图和可选的实施例对本申请作进一步说明。
如图3至图4所示，本申请实施例公开了一种驱动方法，步骤包括：
S31:输出显示面板的关机信号；
S32:打开像素对应的主动开关；
S33:关闭显示面板。
本方案中，新型的无门驱动(Gate driver less，GDL)架构越来越多的应用在电视窄边框设计中，无门驱动电路将原来的门驱动芯片拆分成升压芯片和移位寄存器。关闭显示面板时将CK/XCK直接拉高，但是这种方式无法把像素对应的所有输出通道都处于打开状态，无法尽快将面板存储的电荷释放掉，影响关闭显示面板画面。本申请采用新的驱动方法，接收到关机信号时，打开像素对应的所有主动开关，此时所有输出通道都打开，面板存储的电荷会快速释放，保证正常关闭显示面板。
在一实施例中，S41：电源电压降低到预设值时，输出显示面板的关机信号。
本方案中，一般输入电源电压时12V，这里对电源电压设定预设值，当电源电压值下降到预设值时，判断此刻处于关闭显示面板状态，输出关机信号。在实际应用中，并没有预设值的明确标准，一般设置为8-9V。
在一实施例中，S42：通过切换电路，将驱动主动开关的低电平信号切换成高电平信号，打开像素对应主动开关。
本方案中，当电路输出关机信号时，通过切换电路，将驱动所述主动开关的低电平信号切换成高电平信号，此时像素对应的主动开关全部打开，关闭显示面板时所有输出通道全部打开，面板中电荷释放速度加快。
在一实施例中，关闭显示面板的步骤包括：显示面板接收关机信号，关闭显示面板。
本方案中，显示面板接收到给关机信号后，关闭显示面板，保证显示面板正常关闭。
如图4所示，作为本申请的另一实施例，公开了一种驱动方法，步骤包括：
S41:电源电压降低到预设值时，输出显示面板的关机信号；
S42:通过切换电路，将驱动主动开关的低电平信号切换成高电平信号，打开像素对应主动开关；
S43:关闭显示面板。
本方案中，首先对关闭显示面板时预设值进行设定，设定预设值，当电源电压达到预设值时判定为关闭显示面板状态，此时输出关机信号。接着通过切换电路对输出信号进行切换，将原有的低电平信号切换为高电平信号，打开像素对应的主动开关，所有输出通道打开，面板内存储的电荷快速释放，保证正常关闭显示面板。
如图5所示，作为本申请的另一实施例，公开了一种驱动电路，包括：电源电路300，设置为输出关机信号；像素控制电路400，设置为打开像素对应的主动开关；关机电路，设置为关闭显示面板。
本方案中，驱动电路包括电源电路300、像素控制电路400和关机电路，其中像素控制电路400为本驱动电路的核心。通过像素驱动电路400，可以打开像素对应的主动开关，保证面板中电荷快速释放，从而保证正常关闭显示面板。
在一实施例中，电源电路300包括电源，通过电源输出电路控制信号。
本方案中，通过电源将内部电压分散到各个电路，电源输出的电路控制信号对显示面板整体电路进行控制。
在一实施例中，电路控制信号包括高电平信号、低电平信号和电路切换信号。
本方案中，通过驱动电路对高电平信号、低电平信号进行切换，保证显示面板的正常关闭。
在一实施例中，通过电路控制信号，打开像素对应的主动开关。
本方案中，电路控制信号实际上就是像素对应的主动开关的开启关闭信号，通过电路控制信号，打开或关闭像素对应的主动开关。
在一实施例中，像素控制电路400包括：第一逻辑电路410，设置为输出关闭所述主动开关的第一控制信号，第一逻辑电路为低电平路，输出的第一控制信号为低电平信号；第二逻辑电路420，设置为输出打开主动开关的第二控制信号，第二逻辑电路为高电平电路，输出的第二控制信号为高电平信号；切换电路430，设置为第一逻辑电路410和第二逻辑电路420切换；关闭显示面板时，切换电路430控制第二逻辑电路430打开,主动开关打开。
本方案中，当电源电路300侦测到电压下降到预设值时，认为此时处于关闭显示面板状态，发出关机信号。通过切换电路430将第一逻辑电路410切换为第二逻辑电路430，控制第二逻辑电路430导通，输出高电平信号，即VGH信号。随着高电平信号的输出，主动开关打开。
在一实施例中，第一逻辑电路410包括第一电阻R1、第二电阻R2和第一主动开关411，其中第一电阻R1与第二电阻R2连接，第二电阻R2和切换电路430连接，第一主动开关411的漏极与主动开关控制端500连接，第一主动开关411的栅极连接在第一电阻R1与第二电阻R2之间，第一主动开关411与电源电路300连接。
本方案中，第一逻辑电路410的第一主动开关411为N型MOS(Metal Oxide Semiconductor,MOS)管,其中第一主动开关411的漏极与主动开关控制端500连接，第一电阻R1和第二电阻R2之间的导线连接到第一主动开关411的栅极，第一电阻R1和第二电阻R2中间的电压为V1,当切换电路430为低电平时，V1大于低电平电压，第一主动开关411导通，输出低电平信号；当切换电路430为高电平时，V1等于低电平电压，此时第一主动开关411截止，无法输出低电平信号。
在一实施例中，切换电路430包括第三主动开关431，所述第三主动开关431的源极与第二电阻连接R2。
本方案中，第一逻辑电路410中第二电阻R2和切换电路430连接，实际上是第二 电阻R2与第三主动开关431的源极连接。
在一实施例中，第二逻辑电路420包括第三电阻R3、第四电阻R4和第二主动开关421，其中第三电阻R3和第四电阻R4连接，第四电阻R4与切换电路430连接，第二主动开关421的栅极连接在第三电阻R3与第四电阻R4之间，第二主动开关421的漏极与主动开关控制端连接500。
本方案中，第二逻辑电路420的第二主动开关421为P型MOS(Metal Oxide Semiconductor,MOS)管，与第一主动开关411相似之处是，第二主动开关421的栅极连在第三电阻R3和第四电阻R4中间，第三电阻R3和第四电阻R4中间的电压为V2。切换电路430为低电平时，V2等于高电平电压，第二主动开关421截止，无法输出高电平信号；当切换电路430为高电平时，V2小于高电平电压，第二主动开关421打开，输出高电平信号，此时主动开关打开，所有输出通道打开。
在一实施例中，切换电路430包括第四主动开关432，第四主动开关432的源极与所述第四电阻R4连接。
本方案中，第二逻辑电路410中第四电阻R4和切换电路430连接，实际上是第四电阻R4与第四主动开关432的源极连接。
在一实施例中，切换电路430包括第三主动开关431、第四主动开关432和逻辑电源VDD；第三主动开关431的漏极与逻辑电源VDD连接，第三主动开关431的源极与第一逻辑电路410连接；第四主动开关432的源极与第二逻辑电路420连接。
本方案中，切换电路中的第三主动开关431为P型MOS(Metal Oxide Semiconductor,MOS)管，第四主动开关432为N型MOS(Metal Oxide Semiconductor,MOS)管，第三主动开关431的栅极与第四主动开关432的栅极连接。逻辑电源VDD为3.3V，采用通用芯片中逻辑电路的工作电压。第三主动开关431和第四主动开关432分别与对应的电路连接。
在一实施例中，第一逻辑电路410包括第一电阻R1、第二电阻R2和第一主动开关411，其中第一电阻R1与第二电阻R2连接，第一主动开关411的漏极与主动开关控制端500连接，第一主动开关411的栅极连接在第一电阻R1与第二电阻R2之间，第一主 动开关411与电源电路300连接；第二逻辑电路420包括第三电阻R3、第四电阻R4和第二主动开关421，其中第三电阻R3和第四电阻R4连接，第二主动开关421的栅极连接在第三电阻R3与第四电阻R4之间，第二主动开关421的漏极与主动开关控制端500连接；切换电路430包括第三主动开关431、第四主动开关432和逻辑电源VDD；第三主动开关431的漏极与逻辑电源VDD连接，第三主动开关431的源极与第二电阻R2连接；第四主动开关432的源极与第四电阻R4连接。
本方案中，第一主动开关411和第四主动开关432为N型MOS(Metal Oxide Semiconductor,MOS)管，第二主动开关421和第三主动开关431为P型MOS(Metal Oxide Semiconductor,MOS)管。在本电路运行时，正常状态下，切换电路430为低电平，此时第三主动开关431导通，第四主动开关432截止，此时逻辑电源VDD通过第三主动开关431、第一电阻R1、第二电阻R2与第一逻辑电路410连通，第一电阻R1和第二电阻R2中间电压V1大于低电平电压，导致第一主动开关411导通，低电平信号通过第一主动开关411输出，第四主动开关432截止，第三电阻和第四电阻R4中间电压V2等于高电平电压，第三主动开关431同样截止，无法输出高电平信号；当切换电路430为高电平时，第三主动开关431截止，第四主动开关432导通，此时V1等于低电平电压，低电平信号无法输出，与此同时第四主动开关432导通，V2小于高电平电压，第二主动开关421导通，输出高电平信号，原有的低电平信号切换为高电平信号，打开像素对应的主动开关，加速电荷快速释放。
如图6所示，图6为本申请驱动电路关闭显示面板时电压变化图，其中T1为开始关闭显示面板时刻，IP(Input Power,IP)为输入电源电压，OP(Output,OP)为输出信号电压，XON为切换电路430输出的信号，VGL为低电平信号电压，VGH为高电平信号电压。当开始关闭显示面板时，IP开始下降，达到预设值时，XON信号由低电平切换为高电平，电路输出也由VGL转换为VGH，最大限度的保证电压的下降，直至降至0V，面板中所有电荷完全释放，完成关闭显示面板。
需要说明的是，本方案中涉及到的各步骤的限定，在不影响具体方案实施的前提下，并不认定为对步骤先后顺序做出限定，写在前面的步骤可以是在先执行的，也可以是在 后执行的，甚至也可以是同时执行的，只要能实施本方案，都应当视为属于本申请的保护范围。
本申请的技术方案可以广泛使用在各种显示面板，如TN型显示面板(全称为Twisted Nematic，即扭曲向列型面板)、IPS型显示面板(In-Plane Switching，平面转换)、VA型显示面板(Multi-domain Vertica Alignment，多象限垂直配向技术)，当然，也可以是其他类型的显示面板，如有机发光显示面板(organic light emitting diode，简称OLED显示面板)，均可适用上述方案。
以上内容是结合具体的可选实施方式对本申请所作的进一步详细说明，不能认定本申请的具体实施只局限于这些说明。对于本申请所属技术领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干简单推演或替换，都应当视为属于本申请的保护范围。

Claims (17)

  1. 一种显示面板的驱动方法，包括步骤：
    输出显示面板的关机信号；
    打开像素对应的主动开关；
    关闭显示面板。
  2. 如权利要求1所述的一种显示面板的驱动方法，其中，所述输出关机信号的步骤包括：
    电源电压降低到预设值时，输出所述关机信号。
  3. 如权利要求1所述的一种显示面板的驱动方法，其中，所述打开像素对应的主动开关的步骤包括：
    通过切换电路，将驱动所述主动开关的低电平信号切换成高电平信号，打开像素对应的主动开关。
  4. 如权利要求1所述的一种显示面板的驱动方法，其中，所述关闭显示面板的步骤包括：
    显示面板接收关机信号，关闭显示面板。
  5. 一种显示面板的驱动方法，包括步骤：
    电源电压降低到预设值时，输出显示面板的关机信号；
    通过切换电路，将驱动所述主动开关的低电平信号切换成高电平信号，打开像素对应主动开关；以及
    关闭显示面板。
  6. 一种显示面板的驱动电路，包括：
    电源电路，输出关机信号；
    像素控制电路，打开像素对应的主动开关；以及
    关机电路，关闭显示面板。
  7. 如权利要求6所述的一种显示面板的驱动电路，其中，所述电源电路包括电源。
  8. 如权利要求7所述的一种显示面板的驱动电路，其中，通过所述电源输出电路 控制信号。
  9. 如权利要求8所述的一种显示面板的驱动电路，其中，所述电路控制信号包括高电平信号、低电平信号和电路切换信号。
  10. 如权利要求8所述的一种显示面板的驱动电路，其中，通过电路控制信号，打开像素对应的主动开关。
  11. 如权利要求6所述的一种显示面板的驱动电路，其中，所述像素控制电路包括：
    第一逻辑电路，输出关闭所述主动开关的第一控制信号；
    第二逻辑电路，输出打开所述主动开关的第二控制信号；以及
    切换电路，切换所述第一逻辑电路和第二逻辑电路；
    关闭显示面板时，所述切换电路控制第二逻辑电路打开,控制所述主动开关打开。
  12. 如权利要求11所述的一种显示面板的驱动电路，其中，所述第一逻辑电路包括第一电阻、第二电阻和第一主动开关，其中所述第一电阻与所述第二电阻连接，所述第二电阻和所述切换电路连接，所述第一主动开关的漏极与所述主动开关的控制端连接，所述第一主动开关的栅极连接在所述第一电阻与所述第二电阻之间，所述第一主动开关与所述电源电路连接。
  13. 如权利要求12所述的一种显示面板的驱动电路，其中，所述切换电路包括第三主动开关，所述第三主动开关源极与所述第二电阻连接。
  14. 如权利要求11所述的一种显示面板的驱动电路，其中，所述第二逻辑电路包括第三电阻、第四电阻和第二主动开关，其中所述第三电阻和所述第四电阻连接，所述第四电阻与所述切换电路连接，所述第二主动开关栅极连接在所述第三电阻与所述第四电阻之间，所述第二主动开关的漏极与所述主动开关的控制端连接。
  15. 如权利要求14所述的一种显示面板的驱动电路，其中，所述切换电路包括第四主动开关，所述第四主动开关的源极与所述第四电阻连接。
  16. 如权利要求11所述的一种显示面板的驱动电路，其中，所述切换电路包括第三主动开关、第四主动开关和逻辑电源；所述第三主动开关漏极与所述逻辑电源连接，所述第三主动开关源极与所述第一逻辑电路连接；所述第四主动开关源极与所述第二逻 辑电路连接。
  17. 如权利要求11所述的一种显示面板的驱动电路，其中，所述第一逻辑电路包括第一电阻、第二电阻和第一主动开关，其中所述第一电阻与所述第二电阻连接，所述第一主动开关漏极与所述主动开关的控制端连接，所述第一主动开关栅极连接在所述第一电阻与所述第二电阻之间，所述第一主动开关与所述电源电路连接；所述第二逻辑电路包括第三电阻、第四电阻和第二主动开关，其中所述第三电阻和所述第四电阻连接，所述第二主动开关栅极连接在所述第三电阻与所述第四电阻之间，所述第二主动开关漏极与所述主动开关的控制端连接；所述切换电路包括第三主动开关、第四主动开关和逻辑电源；所述第三主动开关的漏极与所述逻辑电源连接，所述第三主动开关的源极与所述第二电阻连接；所述第四主动开关的源极与所述第四电阻连接。
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