WO2020097816A1 - 移位寄存器单元及驱动方法、栅极驱动电路、显示装置 - Google Patents

移位寄存器单元及驱动方法、栅极驱动电路、显示装置 Download PDF

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Publication number
WO2020097816A1
WO2020097816A1 PCT/CN2018/115370 CN2018115370W WO2020097816A1 WO 2020097816 A1 WO2020097816 A1 WO 2020097816A1 CN 2018115370 W CN2018115370 W CN 2018115370W WO 2020097816 A1 WO2020097816 A1 WO 2020097816A1
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Prior art keywords
node
clock signal
control
circuit
transistor
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Application number
PCT/CN2018/115370
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English (en)
French (fr)
Inventor
王迎
李蒙
李红敏
Original Assignee
京东方科技集团股份有限公司
合肥京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 合肥京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/634,394 priority Critical patent/US10971102B2/en
Priority to EP18926381.7A priority patent/EP3882901A4/en
Priority to PCT/CN2018/115370 priority patent/WO2020097816A1/zh
Priority to CN201880002061.8A priority patent/CN111937067B/zh
Publication of WO2020097816A1 publication Critical patent/WO2020097816A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the embodiments of the present disclosure relate to a shift register unit and a driving method, a gate driving circuit, and a display device.
  • a pixel array of a liquid crystal display panel or an organic light emitting diode (Organic Light Emitting Diode, OLED) display panel generally includes multiple rows of gate lines and multiple columns of data lines interleaved therewith.
  • the driving of the gate line can be realized by the integrated driving circuit bound.
  • the gate line driver circuit can also be directly integrated on the thin film transistor array substrate to form a GOA (Gate Driver On Array) to drive the gate line .
  • GOA Gate Driver On Array
  • a GOA composed of a plurality of cascaded shift register units can be used to provide a switch-state voltage signal (scanning signal) for the multi-row gate lines of the pixel array, so as to control, for example, the multi-row gate lines to be sequentially turned on, and simultaneously
  • the line provides data signals to the pixel units of the corresponding row in the pixel array to form the gray voltages required for each gray level of the display image in each pixel unit, thereby displaying a frame of image.
  • Current display panels increasingly use GOA technology to drive gate lines. GOA technology helps to realize the narrow bezel design of the display panel, and can reduce the production cost of the display panel.
  • At least one embodiment of the present disclosure provides a shift register unit including an input circuit, an output circuit, a first node control circuit, and a second node control circuit.
  • the input circuit is connected to the first node and is configured to provide an input signal to the first node in response to the first control signal;
  • the output circuit is connected to the first node and the output terminal and is configured to be Under the control of the level of the first node, output an output signal at the output terminal;
  • the first node control circuit is connected to the first node and the second node, and is configured to be at the second node Under the control of the level, the first node is reset;
  • the second node control circuit is connected to the second node and is configured to provide a third control signal to the second node in response to the second control signal A node to control the level of the second node.
  • the input circuit includes a first transistor.
  • the gate of the first transistor is connected to the first clock signal terminal to receive the first clock signal as the first control signal, and the first electrode of the first transistor is connected to the input terminal to receive the input signal.
  • the second electrode of the first transistor is connected to the first node.
  • the second node control circuit includes a first control sub-circuit and a second control sub-circuit.
  • the first control sub-circuit is connected to a third node, and is configured to control the level of the third node in response to a second clock signal as the second control signal; the second control sub-circuit and all
  • the second node is connected to the third node, and is configured to output a third control signal to the second node under the control of the level of the third node.
  • the third control signal includes a third clock signal.
  • the first control sub-circuit includes a second transistor.
  • the gate and the first electrode of the second transistor are electrically connected to each other, and are respectively configured to be connected to a second clock signal terminal to receive the second clock signal as the second control signal.
  • the second pole is connected to the third node.
  • the second control sub-circuit includes a third transistor and a first capacitor.
  • the gate of the third transistor is connected to the third node, the first electrode of the third transistor is connected to the third clock signal terminal to receive the third clock signal as the third control signal, the The second electrode of the third transistor is connected to the second node; the first end of the first capacitor is connected to the second node, and the second end of the first capacitor is connected to the third node.
  • the second node control circuit further includes a third node reset sub-circuit.
  • the third node reset subcircuit is connected to the third node, and is configured to reset the third node in response to a reset signal.
  • the third node reset sub-circuit includes a fourth transistor.
  • the gate of the fourth transistor is connected to the reset terminal to receive the reset signal
  • the first electrode of the fourth transistor is connected to the third node
  • the second electrode of the fourth transistor is connected to the reference voltage terminal To receive the reference voltage.
  • the output circuit uses the second clock signal as the output signal at the output terminal under the control of the level of the first node Output.
  • the output terminal includes a shift output terminal and at least one scan signal output terminal.
  • the output circuit includes a fifth transistor, a sixth transistor, and a second capacitor.
  • the gate of the fifth transistor is connected to the first node, the first electrode of the fifth transistor is connected to the second clock signal terminal to receive the second clock signal as the output signal, the fifth The second electrode of the transistor is connected to the shift output terminal;
  • the gate of the sixth transistor is connected to the first node, and the first electrode of the sixth transistor is connected to the second clock signal terminal to receive
  • the second clock signal is used as the output signal, and the second electrode of the sixth transistor is connected to the scan signal output terminal;
  • the first terminal of the second capacitor is connected to the first node, and the first The second terminal of the two capacitors is connected to the shift output terminal or the scan signal output terminal.
  • the first node control circuit includes a seventh transistor.
  • the gate of the seventh transistor is connected to the second node, the first electrode of the seventh transistor is connected to the first node, and the second electrode of the seventh transistor is connected to the reference voltage terminal to receive a reference Voltage.
  • the shift register unit provided by an embodiment of the present disclosure further includes an output noise reduction circuit.
  • the output noise reduction circuit is connected to the second node and the output terminal, and is configured to perform noise reduction on the output terminal under the control of the level of the second node.
  • the shift register unit provided by an embodiment of the present disclosure further includes a general reset circuit.
  • the general reset circuit is connected to the first node, and is configured to reset the first node under the control of a reset signal.
  • At least one embodiment of the present disclosure further provides a gate driving circuit, including a plurality of cascaded shift register units provided by any embodiment of the present disclosure.
  • the gate driving circuit provided by an embodiment of the present disclosure further includes a first clock signal line, a second clock signal line, and a third clock signal line
  • the shift register unit further includes a first clock signal terminal, a second The clock signal terminal and the third clock signal terminal.
  • the first clock signal terminal of the 3N + 1 stage shift register unit is connected to the first clock signal line, the second clock signal terminal is connected to the second clock signal line, and the third clock signal terminal is connected to the third Clock signal line connection;
  • the first clock signal terminal of the 3N + 2 stage shift register unit is connected to the second clock signal line, the second clock signal terminal is connected to the third clock signal line, and the third clock signal terminal Connected to the first clock signal line;
  • the first clock signal terminal of the 3N + 3 stage shift register unit is connected to the third clock signal line, and the second clock signal terminal is connected to the first clock signal line,
  • the third clock signal terminal is connected to the second clock signal line;
  • N is an integer greater than or equal to 0.
  • At least one embodiment of the present disclosure also provides a display device including the gate driving circuit provided by any embodiment of the present disclosure.
  • At least one embodiment of the present disclosure also provides a method for driving a shift register unit, including: in response to the first control signal, the input circuit provides the input signal to the first node; Under the control of the level of a node, the output circuit outputs the output signal at the output terminal; in response to the second control signal, the second node control circuit provides the third control signal to The second node to control the level of the second node; under the control of the level of the second node, the first node control circuit resets the first node.
  • the second node control circuit includes a first control sub-circuit and a second control sub-circuit
  • the driving method further includes: in response to the second control signal Two clock signals, the first control sub-circuit controls the level of the third node; under the control of the level of the third node, the second control sub-circuit uses the third clock signal as the first Three control signals are output to the second node.
  • the output circuit under the control of the level of the first node, the output circuit outputs the second clock signal as the output signal.
  • 1 is a schematic diagram of a circuit structure of a shift register unit
  • FIG. 2 is a schematic diagram of a shift register unit provided by an embodiment of the present disclosure
  • FIG. 3 shows a schematic diagram of an example of the second node control circuit shown in FIG. 2;
  • FIG. 4 is a schematic diagram of another shift register unit provided by an embodiment of the present disclosure.
  • FIG. 5 is a schematic diagram of yet another shift register unit provided by an embodiment of the present disclosure.
  • FIG. 6 is a circuit schematic diagram of a specific implementation example of the shift register unit shown in FIG. 5;
  • FIG. 7 is a schematic diagram of a gate driving circuit provided by an embodiment of the present disclosure.
  • FIG. 8 is a signal timing diagram corresponding to an example of the operation of the gate driving circuit shown in FIG. 7;
  • FIG. 9 is a schematic diagram of a display device provided by an embodiment of the present disclosure.
  • GOA technology In order to reduce the cost of the display device and improve its manufacturing process level, more and more display devices use GOA technology. However, due to the complicated circuit design (such as a large number of clock signals and transistors), the traditional GOA technology has obvious noise and high power consumption.
  • FIG. 1 is a schematic diagram of a circuit structure of a shift register unit.
  • a plurality of such shift register units may be cascaded to form a gate driving circuit for driving, for example, a liquid crystal display panel or an organic light emitting diode display panel.
  • the shift register unit 11 includes a pull-up node PU and a pull-down node PD. Gates of the pull-down transistors T11 and T13 are connected to the pull-down node PD and are controlled by the level of the pull-down node PD. As shown in FIG.
  • the pull-down node PD in a frame display, the pull-down node PD is low level only when the scan signal is output (that is, the pull-up node PU is high level), and is in the high level state for the rest of the time. Because the pull-down node PD is at a high level for a long time, the pull-down transistors T11 and T13 connected to the pull-down node PD are subject to positive bias stress for a long time, and the positive drift of the threshold voltage is likely to occur, especially the transistor with an oxide structure , Prone to positive drift phenomenon. If the positive drift range of the threshold voltage of the transistor is too large, it is easy to cause an abnormal output of the gate drive circuit, thereby causing a display abnormal phenomenon in the display panel.
  • At least one embodiment of the present disclosure provides a shift register unit including an input circuit, an output circuit, a first node control circuit, and a second node control circuit.
  • the input circuit is connected to the first node and is configured to provide the input signal to the first node in response to the first control signal;
  • the output circuit is connected to the first node and is configured to output under the control of the level of the first node The signal is output at the output;
  • the first node control circuit is connected to the first node and the second node, and is configured to reset the first node under the control of the level of the second node;
  • the nodes are connected and configured to provide a third control signal to the second node in response to the second control signal to control the level of the second node.
  • Embodiments of the present disclosure also provide a gate driving circuit, a display device, and a driving method corresponding to the above shift register unit.
  • the shift register unit provided by the above embodiment of the present disclosure can prevent the second node from being in an effective level state for a long time, thereby avoiding the positive voltage of the threshold voltage caused by the transistor connected to the second node due to the positive bias stress
  • the drift phenomenon improves the stability and reliability of the gate drive circuit composed of shift register units, and improves the display quality of the display panel.
  • FIG. 2 is a schematic diagram of a shift register unit provided by an embodiment of the present disclosure.
  • the shift register unit 100 includes an input circuit 110, an output circuit 120, a first node control circuit 130 and a second node control circuit 140.
  • a gate drive circuit can be obtained by cascading a plurality of the shift register units 100.
  • the gate drive circuit is used to drive a display panel such as a liquid crystal display panel and an organic light-emitting diode display panel, which is a sequence of multiple gate lines of the display panel Provides a scan signal to perform progressive or interlaced scanning while the display panel is displaying a frame of pictures.
  • the input circuit 110 is connected to a first node Q1 (for example, a pull-up node here), and is configured to input an input signal to the first node Q1 in response to the first control signal to connect the first node Q1 Charge it.
  • a first node Q1 for example, a pull-up node here
  • the input circuit 110 is connected to the first clock signal terminal CLK1, the input terminal INT, and the first node Q1, and is configured to be turned on under the control of the first clock signal received by the first clock signal terminal CLK1, so that
  • the input signal terminal INT or a separately provided voltage terminal (for example, a high voltage terminal) is connected to the first node Q1, so that the input signal provided by the input signal terminal INT or the high-level signal provided by the separately provided voltage terminal is input to the first A node Q1 charges (eg, pulls up) the potential of the first node Q1 to the working potential (effective level).
  • the first clock signal is used as the first control signal.
  • the embodiments of the present disclosure do not limit this, and may be other suitable control signals.
  • the output circuit 120 is connected to the first node Q1 and the output terminal OUT, and is configured to output an output signal at the output terminal OUT under the control of the level of the first node Q1.
  • the output circuit 120 is connected to the second clock signal terminal CLK2, the first node Q1, and the output terminal OUT, and is configured to be turned on under the control of the level of the first node Q1 to connect the second clock signal
  • the second clock signal provided by the terminal CLK2 is transmitted to the output terminal OUT and output as an output signal at the output terminal OUT.
  • the first node control circuit 130 is connected to the first node Q1 and the second node Q2 (for example, when the first node Q1 is a pull-up node, it is a pull-down node), and is configured to control the level of the second node Q2 Next, the first node Q1 is reset.
  • the first node control circuit 120 may be connected to the first node Q1, the reference voltage terminal VGL (for example, providing a low level) or a separately provided voltage terminal (for example, a low voltage terminal), and the second node Q2, so that Under the control of the level of the second node Q2, the first node Q1 is electrically connected to the reference voltage terminal VGL or a voltage terminal provided separately to perform pull-down reset on the first node Q1.
  • the second node control circuit 140 is connected to the second node Q2, and is configured to provide a third control signal to the second node Q2 in response to the second control signal to control the level of the second node Q2.
  • the second node control circuit 140 may be connected to the second clock signal terminal CLK2 and the third clock signal terminal CLK3, and configured to respond to the second clock signal provided by the second clock signal terminal CLK2 to connect the third clock signal terminal
  • the third clock signal provided by CLK3 is output to the second node Q2, so that the level of the second node Q2 and the third clock signal remain the same, thereby avoiding that the second node Q2 is always at a high level in the non-output stage, to avoid being The positive drift of the threshold voltage of the transistor in the circuit controlled by the second node Q2 (for example, the first node control circuit 130).
  • the second clock signal CLK2 serves as the second control signal
  • the third clock signal CLK3 serves as the third control signal, which is not limited in the embodiments of the present
  • the shift register unit provided by the above embodiment of the present disclosure can prevent the second node from being in an effective level state for a long time, thereby avoiding the positive voltage of the threshold voltage caused by the transistor connected to the second node due to the positive bias stress
  • the drift phenomenon improves the stability and reliability of the gate drive circuit composed of shift register units, and improves the display quality of the display panel.
  • FIG. 3 shows a schematic diagram of an example of the second node control circuit shown in FIG. 2.
  • the second node control circuit 140 includes a first control sub-circuit 141 and a second control sub-circuit 142.
  • the first control sub-circuit 141 is connected to the third node Q3, and is configured to control the level of the third node Q3 in response to the second clock signal CLK2 as the second control signal.
  • the first control sub-circuit 141 is connected to the second clock signal terminal CLK2 and the third node Q3, and is configured to be turned on under the control of the second clock signal provided by the second clock signal terminal CLK2 to perform the third node Q3 Precharge.
  • the second control signal includes a second clock signal.
  • the second control sub-circuit 142 is connected to the second node Q2 and the third node Q3, and is configured to output the third control signal to the second node Q2 under the control of the level of the third node Q3.
  • the second control sub-circuit 142 is connected to the third clock signal terminal CLK3, the second node Q2, and the third node Q3, and is configured to be turned on under the control of the level of the third node Q3, thereby turning the third clock signal
  • the third clock signal provided by the terminal CLK3 is output to the second node Q2, so that the level of the second node Q2 is consistent with the third clock signal, thereby avoiding that the second node Q2 is always at a high level during the non-output stage, to avoid The positive drift of the threshold voltage of the transistor in the circuit controlled by the second node Q2 (for example, the first node control circuit 130).
  • the third control signal includes a third clock signal.
  • the second node control circuit 140 further includes a third node reset sub-circuit 143.
  • the third node reset sub-circuit 143 is connected to the third node Q3, and is configured to reset the third node Q3 in response to the reset signal.
  • the third node reset sub-circuit 143 is connected to the reset terminal T_RST, the reference voltage terminal VGL or a separately provided voltage terminal (for example, providing a low level), and the third node Q3, and is configured to be reset at the reset terminal T_RST Under the control of the signal, the third node Q3 is connected to the reference voltage terminal VGL or a voltage terminal provided separately, thereby resetting the third node Q3.
  • the reset signal is a global reset signal, which simultaneously resets the third node Q3 of all cascaded shift register units at the beginning or end of one frame display, thereby ensuring the display quality of the display panel.
  • FIG. 4 is a schematic block diagram of another shift register unit provided by an embodiment of the present disclosure. As shown in FIG. 4, based on the shift register unit shown in FIG. 3, the shift register unit 100 further includes an output noise reduction circuit 150. It should be noted that other circuit structures of the shift register unit 100 shown in FIG. 4 are basically the same as those of the shift register unit 100 shown in FIG. 3, and repeated descriptions are not repeated here.
  • the output noise reduction circuit 150 is configured to perform noise reduction on the output terminal OUT under the control of the level of the second node Q2.
  • the output noise reduction circuit 150 is connected to the second node Q2, the output terminal OUT, and the reference voltage terminal VGL or a separately provided voltage terminal (for example, a low voltage terminal), and is configured to conduct when the second node Q2 is at a high level, for example
  • the output terminal OUT is connected to the reference voltage terminal VGL or a voltage terminal provided separately to achieve noise reduction on the output terminal OUT.
  • FIG. 5 is a schematic block diagram of yet another shift register unit provided by an embodiment of the present disclosure. As shown in FIG. 5, on the basis of the shift register unit shown in FIG. 4, the shift register unit 100 further includes a total reset circuit 160. It should be noted that other circuit structures of the shift register unit 100 shown in FIG. 5 are basically the same as those of the shift register unit 100 shown in FIG. 4, and repeated descriptions are not repeated here.
  • the general reset circuit 160 is connected to the first node Q1 and is configured to reset the first node Q1 under the control of a reset signal.
  • the total reset circuit 160 is connected to the reset terminal T_RST, the first node Q1 and the reference voltage terminal VGL or a separately provided voltage terminal (for example, a low voltage terminal), and is configured to conduct under the control of the reset signal provided by the reset terminal T_RST
  • the first node Q1 is electrically connected to the reference voltage terminal VGL or a voltage terminal (eg, a low voltage terminal) provided separately, thereby resetting the first node Q1.
  • the connection line corresponding to the reset terminal T_RST connection is omitted in the figure.
  • the reference voltage terminal VGL is configured to provide a low-level DC signal (for example, a low-level part that is lower than or equal to the clock signal), such as ground.
  • a low-level DC signal for example, a low-level part that is lower than or equal to the clock signal
  • the low-level DC signal is referred to as a reference voltage. This is the same and will not be repeated here.
  • the “active level” of the shift register unit refers to a level that enables the operated transistor included therein to be turned on, and accordingly the “inactive level” refers to the level that cannot be enabled. It includes the level at which the operated transistor is turned on (ie, the transistor is turned off). Depending on factors such as the type of transistor (N-type or P-type) in the circuit structure of the shift register unit, the effective level may be higher or lower than the invalid level.
  • the square wave pulse signal used by the shift register unit during operation the effective level corresponds to the level of the square wave pulse part of the square wave pulse signal, and the invalid level corresponds to the level of the non-square wave pulse part .
  • FIG. 6 is a circuit diagram of a specific implementation example of the shift register unit of the embodiment shown in FIG. 5, and the shift register unit of the embodiments shown in other figures may be implemented in the same or similar manner.
  • the shift register unit 100 includes first to tenth transistors M1-M10, and further includes a first capacitor C1 and a second capacitor C2.
  • each transistor is an N-type transistor as an example for description, but this does not constitute a limitation on the embodiments of the present disclosure.
  • the input circuit 110 may be implemented as the first transistor M1.
  • the gate of the first transistor M1 is connected to the first clock signal terminal CLK1 to receive the first clock signal as the first control signal
  • the first electrode of the first transistor M1 is connected to the input terminal INT to receive the input signal
  • the first transistor M1 The second pole is connected to the first node Q1, so that when the first transistor M1 is turned on in response to the effective level (eg, high level signal) of the first clock signal provided by the first clock signal terminal CLK1, the input terminal is used
  • the input signal received by INT charges the first node Q1 to be at a high level.
  • the first control sub-circuit 141 may be implemented as a second transistor M2.
  • the gate and the first electrode of the second transistor M2 are electrically connected to each other, and are respectively configured to be connected to the second clock signal terminal CLK2 to receive the second clock signal as the second control signal, the second electrode and the third electrode of the second transistor M2
  • the node Q3 is connected so that when the second transistor M2 is turned on in response to the second clock signal (eg, high level) provided by the second clock signal terminal CLK2, the second clock signal is used to charge the third node Q3 so that It is at a high level.
  • the second control sub-circuit 142 may be implemented as a third transistor M3 and a first capacitor C1.
  • the gate of the third transistor M3 is connected to the third node Q3, the first pole of the third transistor M3 is connected to the third clock signal terminal CLK3 to receive the third clock signal as the third control signal, and the second pole of the third transistor M3 Connected to the second node Q2.
  • the first terminal of the first capacitor C1 is connected to the second node Q2, and the second terminal of the first capacitor C1 is connected to the third node Q3.
  • the third transistor M3 When the third node Q3 is at an effective level (for example, a high level), the third transistor M3 is turned on, and the second node Q2 is connected to the third clock signal terminal CLK3, so that the level of the second node Q2 and the third clock
  • the third clock signal provided by the signal terminal CLK3 has the same level.
  • the second node Q2 when the third clock signal provided by the third clock signal terminal CLK3 is high, the second node Q2 is high; when the third clock signal is low, the second node Q2 is low, so it can be Avoid that the second node Q2 is always at a high level in the non-output stage, so that the transistors controlled by the second node Q2 (for example, the seventh transistor M7, the ninth transistor M9, and the tenth transistor M10) can be prevented from being positively biased for a long time The positive drift of the threshold voltage occurs under the effect of stress.
  • the third node reset sub-circuit 143 includes a fourth transistor M4.
  • the gate of the fourth transistor M4 is connected to the reset terminal T_RST to receive the reset signal
  • the first electrode of the fourth transistor M4 is connected to the third node Q3
  • the second electrode of the fourth transistor M4 is connected to the reference voltage terminal VGL to receive the reference voltage .
  • the fourth transistor M4 is turned on, so that the third node Q3 and the reference voltage terminal VGL Connected so that the third node Q3 can be reset.
  • the output terminal OUT includes a shift output terminal CR and at least one scan signal output terminal, so as to output an output signal such as a second clock signal provided by the second clock signal terminal CLK2 to the shift output terminal CR, respectively And the scan signal output terminal OUT1 to improve the driving capability of the shift register unit 100.
  • at least one scan signal output terminal includes a scan signal output terminal OUT1.
  • the shift output terminal CR is used to provide an input signal for the shift register unit 100 of the next stage
  • the scan signal output terminal OUT1 is used to provide a drive signal for a pixel circuit of a row of pixel units in the display panel.
  • the shift output terminal CR and the scan signal output terminal OUT1 output the same output signal. It should be noted that, in other examples, when multiple scan signal output terminals are included, each scan signal output terminal may also output different output signals. The specific setting depends on the actual situation, and the embodiments of the present disclosure do not make this limit.
  • the output circuit 120 may be implemented as a fifth transistor M5, a sixth transistor M6, and a second capacitor C2.
  • the gate of the fifth transistor M5 is connected to the first node Q1, the first pole of the fifth transistor M5 is connected to the second clock signal terminal CLK2 to receive the second clock signal as an output signal, and the second pole of the fifth transistor M5 is shifted Bit output terminal CR is connected.
  • the gate of the sixth transistor M6 is connected to the first node Q1, the first electrode of the sixth transistor M6 is connected to the second clock signal terminal CLK2 to receive the second clock signal as an output signal, and the second electrode of the sixth transistor M6 and the scan The signal output OUT1 is connected.
  • the first terminal of the second capacitor C2 is connected to the first node Q1, and the second terminal of the second capacitor C2 is connected to the shift output terminal CR or the scan signal output terminal OUT1. It should be noted that, not limited to this, the shift register unit may also include more output signals and scan signal output terminals corresponding thereto.
  • the first node control circuit 130 may be implemented as a seventh transistor M7.
  • the gate of the seventh transistor M7 is connected to the second node Q2, the first electrode of the seventh transistor M7 is connected to the first node Q1, and the second electrode of the seventh transistor M7 is connected to the reference voltage terminal VGL to receive the reference voltage.
  • the seventh transistor T7 is turned on, so that the first node Q1 is connected to the reference voltage terminal VGL to receive the reference voltage, so that the first node Q1 can be reset.
  • the output noise reduction circuit 150 may be implemented as a ninth transistor M9 and a tenth transistor M10.
  • the gate of the ninth transistor M9 is connected to the second node Q2, the first electrode is connected to the shift output terminal CR, and the second electrode is connected to the reference voltage terminal VGL to receive the reference voltage.
  • the gate of the tenth transistor M10 is connected to the second node Q2, the first electrode of the tenth transistor M10 is connected to the first scan signal output terminal OUT1, and the second electrode of the tenth transistor M10 is connected to the reference voltage terminal VGL to receive the reference voltage .
  • both the ninth transistor M9 and the tenth transistor M10 are turned on, so that the shift output terminal CR and the scan signal output terminal OUT1 are both connected to the reference voltage terminal VGL is electrically connected to reduce noise at the shift output terminal CR and the scan signal output terminal OUT1.
  • the output noise reduction circuit 150 when the shift output terminal CR and the scan signal output terminal OUT1 respectively include more than one, the output noise reduction circuit 150 also includes a plurality of shift output terminals and / Or Transistor corresponding to the output of the scan signal to reduce noise.
  • the total reset circuit 160 may be implemented as an eighth transistor M8.
  • the gate of the eighth transistor M8 is connected to the reset terminal T_RST to receive a reset signal
  • the first electrode of the eighth transistor M8 is connected to the first node Q1
  • the second electrode of the eighth transistor M8 is connected to the reference voltage terminal VGL to receive Reference voltage.
  • the eighth transistor M8 is turned on, so that the first node Q1 and the reference voltage terminal VGL Connected so that the first node Q1 can be reset.
  • circuit structure of the shift register unit shown in FIG. 2 to FIG. 4 is similar to the circuit structure of the shift register unit shown in FIG. 6 shown in FIG. 6, and details are not repeated here.
  • pulse-up means charging a node or an electrode of a transistor so that the level of the node or the electrode is absolute The value is increased to achieve the operation of the corresponding transistor (for example, conduction); “pull down” means that a node or an electrode of a transistor is discharged, so that the absolute value of the level of the node or the electrode is reduced, so as to achieve the corresponding Operation of the transistor (for example, off).
  • pulse-up means discharging a node or an electrode of a transistor, so that the absolute value of the level of the node or the electrode is reduced, thereby implementing the corresponding transistor Operation (for example, turn-on);
  • pulse-down means to charge a node or an electrode of a transistor, so that the absolute value of the level of the node or the electrode is increased, so as to achieve the operation of the corresponding transistor (for example, off) .
  • first node Q1, the second node Q2, and the third node Q3 do not represent actual components, but represent the junction of related electrical connections in the circuit diagram.
  • all the transistors used in the embodiments of the present disclosure may be thin film transistors, field effect transistors, or other switching devices having the same characteristics.
  • the thin film transistors are used as examples for description.
  • the source and drain of the transistor used here may be symmetrical in structure, so the source and drain may be indistinguishable in structure.
  • one pole is described as the first pole and the other pole is the second pole.
  • the transistors in the embodiments of the present disclosure are all described using N-type transistors as an example.
  • the first electrode of the transistor is the drain and the second electrode is the source.
  • this disclosure includes but is not limited to this.
  • one or more transistors in the shift register unit 100 provided by the embodiments of the present disclosure may also use P-type transistors.
  • the first pole of the transistor is the source and the second pole is the drain.
  • the poles of a certain type of transistor refer to the poles of the corresponding transistors in the embodiments of the present disclosure, and connect the corresponding poles, and make the corresponding voltage terminals provide corresponding high or low voltages.
  • indium gallium zinc oxide Indium Gallium Zinc Oxide, IGZO
  • LTPS Low Temperature Polysilicon
  • amorphous silicon such as hydrogenated non-crystalline Crystalline silicon
  • An embodiment of the present disclosure also provides a gate driving circuit.
  • 7 is a schematic diagram of a gate driving circuit provided by an embodiment of the present disclosure.
  • the gate driving circuit 10 includes a plurality of cascaded shift register units 100, wherein any one or more shift register units 100 may adopt the shift register unit 100 provided by any embodiment of the present disclosure
  • the shift register unit 100 shown in FIG. 6 may be adopted for the structure or its modification.
  • the gate driving circuit 10 may be directly integrated on the array substrate of the display device using the same semiconductor manufacturing process as the thin film transistor to achieve the progressive or interlaced scanning driving function.
  • the input terminals INT of the shift register units of the remaining stages are connected to the shift output terminal CR of the shift register unit of the upper stage.
  • the shift register unit provided by the embodiment of the present disclosure can control the first node control circuit 130 and the output noise reduction circuit 150 to be turned on under the control of the level of the second node Q2 to realize the reset and the first node Q1.
  • the noise reduction of the output terminal OUT eliminates the need to set a separate reset circuit to reset the first node Q1 of the shift register unit of the current stage. Therefore, in this gate drive circuit 10, the shift register units at all stages (except the last shift register unit) need not be connected to the shift output terminal CR of the shift register unit at the lower stage for the current stage
  • the first node Q1 of the shift register unit is reset, so that the gate driving circuit provided by the embodiment of the present disclosure can reduce the complexity of wiring and improve the stability of the gate driving circuit.
  • the gate driving circuit 10 further includes a first clock signal line CLKA, a second clock signal line CLKB, and a third clock signal line CLKC.
  • the first clock signal line CLKA, the second clock signal line CLKB, and the third clock signal line CLKC are respectively connected to clock signal terminals of a plurality of cascaded shift register units to provide clock signals.
  • the gate driving circuit 10 may further include four, six, eight, or more clock signal lines. The number of clock signal lines depends on specific situations, and the embodiments of the present disclosure are not limited herein.
  • each of the shift register units further includes a first clock signal terminal CLK1, a second clock signal terminal CLK2, and a third clock signal terminal CLK3, and are respectively configured to be connected to the first clock signal line CLKA 2.
  • the second clock signal line CLKB or the third clock signal line CLKC is connected to receive the clock signal.
  • the first clock signal terminal CLK1 of the 3N + 1 (N is an integer greater than or equal to 0) stage shift register unit is connected to the first clock signal line CLKA, the second clock signal terminal CLK2 is connected to the second clock signal line CLKB,
  • the three clock signal terminal CLK3 is connected to the third clock signal line CLKC;
  • the first clock signal terminal CLK1 of the 3N + 2 stage shift register unit is connected to the second clock signal line CLKB, and the second clock signal terminal CLK2 is connected to the third clock signal
  • the line CLKC is connected, the third clock signal terminal CLK3 is connected to the first clock signal line CLKA;
  • the first clock signal terminal CLK1 of the 3N + 3 stage shift register unit is connected to the third clock signal line CLKC, and the second clock signal terminal CLK2 It is connected to the first clock signal line CLKA, and the third clock signal terminal CLK3 is connected to the second clock signal line CLKB.
  • the embodiments of the present disclosure include but are not limited to the above-mentioned connection manners
  • the gate driving circuit 10 further includes a reset signal line T_RST1, each of the shift register units further includes a reset terminal T_RST, and is configured to be connected to the reset signal line T_RST1 to receive a reset signal.
  • OUT1_3N + 1 shown in FIG. 7 represents the scan signal output terminal of the 3N + 1 stage shift register unit
  • OUT1_3N + 2 represents the scan signal output terminal of the 3N + 2 stage shift register unit
  • OUT1_3N +3 represents the scan signal output terminal of the 3N + 3th stage shift register unit, and so on ...
  • CR_3N + 1 represents the shift output terminal of the 3N + 1th stage shift register unit
  • CR_3N + 2 represents the 3N +
  • the shift output of the 2nd stage shift register unit, CR_3N + 3 represents the shift output of the 3N + 3th stage shift register unit, and so on.
  • the reference symbols in the following embodiments are similar to this, and will not be repeated here.
  • the input terminal INT of the shift register unit of the first stage may be configured to receive the trigger signal STV, which is not shown in FIG. 7 for simplicity.
  • the gate driving circuit 10 may further include a timing controller 200.
  • the timing controller 200 may be configured to be connected to the first clock signal line CLKA, the second clock signal line CLKB, and the third clock signal line CLKC to provide clock signals to the shift register units; the timing controller 200 It may also be configured to be connected to a reset signal line T_RST1 and a reference voltage line (not shown in the figure) to provide a reset signal and a reference voltage to each shift register unit 100, respectively.
  • the timing controller 300 may also be configured to provide the trigger signal STV. It should be noted that the phase relationship between the multiple clock signals provided by the timing controller 200 may be determined according to actual requirements.
  • the clock signal timing provided by the first clock signal line CLKA, the second clock signal line CLKB, and the third clock signal line CLKC may adopt the signal timing shown in FIG. 8 to realize the gate driving circuit 10 outputting the gates row by row The function of scanning signals.
  • the level of the potential in the signal timing chart shown in FIG. 8 is only schematic, and does not represent the true potential value or relative ratio.
  • the high level signal corresponds to the turn-on signal of the N-type transistor.
  • the low-level signal corresponds to the N-type transistor being an off signal.
  • the operation principle of the first-stage shift register unit of the gate driving circuit 10 shown in FIG. 7 is described below in conjunction with the signal timing chart shown in FIG. 8.
  • Q1 ⁇ 1>, Q2 ⁇ 1>, and Q3 ⁇ 1> respectively represent the first node, the second node, and the third node in the first-stage shift register unit in the gate drive circuit 10;
  • OUT1_1, OUT1_2 represents the scan signal output terminals of the first-stage and second-stage shift register units in the gate driving circuit 210, respectively.
  • the first-stage shift register unit may adopt the circuit structure shown in FIG. 6, and the working principle of the shift register unit 100 is:
  • the reset signal line T_RST1 provides a high level. Since the reset terminals T_RST of the shift register units at all levels are connected to the reset signal line T_RST1, at this stage, all levels The total reset circuit 160 and the third node reset sub-circuit 143 of the shift register unit are both turned on, so that the first node Q1 and the third node Q3 are both connected to the reference voltage terminal VGL, so that the first The node Q1 and the third node Q3 are reset. It should be noted that the level of the potential in the signal timing diagram shown in FIG. 8 is only schematic, and does not represent the true potential value or relative ratio. Corresponding to the above example, the high level signal corresponds to the turn-on signal of the N-type transistor , And the low-level signal corresponds to the N-type transistor is an off signal.
  • the input terminal INT provides a high level
  • the first clock signal line CLKA provides a high level
  • the first clock signal terminal CLK1 of the first-stage shift register unit 100 Since the first clock signal terminal CLK1 of the first-stage shift register unit 100 is connected to the first clock signal line CLKA, Therefore, at this stage, the first clock signal terminal CLK1 of the first-stage shift register unit 100 inputs a high level, and the input circuit 110 is turned on under the control of the high level provided by the first clock signal terminal CLK1, so that the input terminal INT
  • the provided high level charges the first node Q1 ⁇ 1>, and the first node Q1 ⁇ 1> is charged to the first high level; meanwhile, the second clock signal line CLKB provides a low level due to the shift of the first stage
  • the second clock signal terminal CLK2 of the bit register unit 100 is connected to the second clock signal line CLKB, so at this stage, the second clock signal terminal CLK2 of the first-stage shift register unit 100 inputs a low level, so at the first
  • the second clock signal line CLKB provides a high level, so the second clock signal terminal CLK2 of the first-stage shift register unit 100 inputs a high level, and the first node Q1 ⁇ 1> due to the bootstrap of the capacitor The effect is further charged to the second high level, so under the control of the second high level of the first node Q1 ⁇ 1>, the high level input from the second clock signal terminal CLK2 is output to the shift register of the first stage
  • the node Q3 ⁇ 1> is charged, and the third node Q3 ⁇ 1> is charged to the first high level; meanwhile, the third clock signal line CLKC provides a low level due to the third clock of the shift register unit 100 of the first stage
  • the signal terminal CLK3 is connected to the third
  • the third clock signal line CLKC provides a low level. Since the second clock signal terminal CLK2 of the second-stage shift register unit 100 is connected to the third clock signal line CLKC, the second-stage shift at this stage The second clock signal terminal CLK2 of the bit register unit 100 inputs a low level, and the high level output by the first output terminal OUT1_1 of the first-stage shift register unit 100 is used as the input signal of the second-stage shift register unit 100 , The first node Q1 of the second-stage shift register unit 100 is pulled up to the first high level by the input signal. Therefore, the first high-level node of the first node Q1 of the second-stage shift register unit 100 Under the control of, the low level input from the second clock signal terminal CLK2 of the second-stage shift register unit 100 is output to the output terminal OUT1_2.
  • the third clock signal line CLKC provides a high level, so the third clock signal terminal CLK3 of the first-stage shift register unit 100 inputs a high level, and the third node Q3 ⁇ 1> is due to the bootstrap of the capacitor The effect is further charged to the second high level, so under the control of the second high level of the third node Q3 ⁇ 1>, the high level input from the third clock signal terminal CLK3 is output to the shift register of the first stage
  • the second node Q2 ⁇ 1> of the cell 100 so that the first node control circuit 130 and the output noise reduction circuit 150 are turned on under the control of the level of the second node Q2 ⁇ 1>, so that the first node Q1 ⁇ 1>,
  • the shift output terminal CR_1 and the scan signal output terminal OUT1_1 are connected to the reference voltage terminal VGL to achieve noise reduction; meanwhile, at this stage, since the third clock signal line CLKC provides a high level, the second-stage shift register unit 100
  • the third clock signal line CLKC provides a low level, and therefore, the third clock signal terminal CLK3 of the shift register unit of the first stage inputs a low level. Since the second control sub-circuit 142 is turned on in response to the high level of the third node Q3 ⁇ 1>, the low level input from the third clock signal terminal CLK3 is output to the second level of the shift register unit 100 of the first stage Node Q2 ⁇ 1>, therefore, at this stage, the second node Q2 ⁇ 1> is discharged to a low level, so that the level of the second node Q2 ⁇ 1> and the third clock provided by the third clock signal terminal CLK3
  • the level of the signal is consistent, so it can avoid that the second node Q2 ⁇ 1> is always at a high level in the non-output stage (ie, excluding the third stage t3), so that it can be avoided by the second node Q2 ⁇ 1>
  • the transistors for example, the seventh transistor M7, the ninth transistor M9
  • the working principles of the shift register units of the remaining stages are similar to the working principles of the shift register unit of the first stage, and will not be repeated here. The difference is that except for the shift register unit of the first stage, the remaining stages The shift register unit does not include the first stage t1, that is, the global reset at the beginning of the display of one frame.
  • the reset signal line T_RST1 provides a high level. Since the reset terminal T_RST of the shift register units at all levels is connected to the reset signal line T_RST1, at this stage, all levels of shift
  • the total reset circuit 160 and the third node reset sub-circuit 143 of the bit register unit are both turned on, so that the first node Q1 and the third node Q3 are both connected to the reference voltage terminal VGL, thereby the first node of the shift register unit at each level Q1 and the third node Q3 are reset to avoid erroneous output of the shift register unit and improve the display quality.
  • the level of the potential in the signal timing diagram shown in FIG. 8 is only schematic, and does not represent the true potential value or relative ratio.
  • the high level signal corresponds to the turn-on signal of the N-type transistor
  • the low-level signal corresponds to the N-type transistor is an off signal.
  • the gate driving circuit 10 may be disposed on one side of the display panel.
  • the display panel includes multiple rows of gate lines, and the second output terminals of the voltage conversion circuits of each stage in the gate driving circuit 10 may be configured to be sequentially connected to the multiple rows of gate lines for outputting gate scan signals.
  • the gate driving circuit 10 may also be provided on both sides of the display panel to achieve bilateral driving. The embodiment of the present disclosure does not limit the manner of setting the gate driving circuit 10.
  • the display device 1 includes the gate driving circuit 10 provided by the above-described embodiment of the present disclosure.
  • the display device 1 further includes a display panel 40 that includes an array of multiple sub-pixel units 410.
  • the display device 1 may further include a data driving circuit 30.
  • the data driving circuit 30 is used to provide a data signal to the pixel array;
  • the gate driving circuit 10 is used to provide a driving signal to the pixel array.
  • the driving signal can drive the scanning transistor and the sensing transistor in the sub-pixel unit 410.
  • the data driving circuit 30 is electrically connected to the sub-pixel unit 410 through the data line DL, and the gate driving circuit 10 is electrically connected to the sub-pixel unit 410 through the gate line GL.
  • the display device 1 in this embodiment may be any of a liquid crystal panel, an LCD TV, a display, an OLED panel, an OLED TV, an electronic paper display device, a mobile phone, a tablet computer, a notebook computer, a digital photo frame, a navigator, etc. Products or parts with display function.
  • the display device 1 may further include other conventional components such as a display panel, which is not limited in the embodiments of the present disclosure.
  • An embodiment of the present disclosure also provides a driving method that can be used to drive the shift register unit 100 provided by the embodiment of the present disclosure.
  • the driving method includes: in response to a first control signal, an input circuit 110 provides the input signal to the first node Q1; under the control of the level of the first node Q1, the output circuit 120 outputs the output signal at the output terminal OUT; in response to the second control signal, the second node control circuit 140 Three control signals are provided to the second node Q2 to control the level of the second node Q2; under the control of the level of the second node Q2, the first node control circuit resets the first node Q1.
  • the second node control circuit 140 includes a first control sub-circuit 141 and a second control sub-circuit 142
  • the driving method further includes: in response to the second clock signal as the second control signal, the first The control sub-circuit 141 controls the level of the third node Q3; under the control of the level of the third node Q3, the second control sub-circuit 142 outputs the third clock signal as the third control signal to the second node Q2.
  • the output circuit 120 outputs a second clock signal as an output signal.

Abstract

一种移位寄存器单元(100)、栅极驱动电路(10)、显示装置(1)及驱动方法。该移位寄存器单元(100)包括输入电路(110)、输出电路(120)、第一节点控制电路(130)和第二节点控制电路(140)。输入电路(110)与第一节点(Q1)连接，且配置为响应于第一控制信号将输入信号提供至第一节点(Q1)；输出电路(120)与第一节点(Q1)和输出端(OUT)连接，且配置为在第一节点(Q1)的电平的控制下，将输出信号在输出端(OUT)输出；第一节点控制电路(130)与第一节点(Q1)和第二节点(Q2)连接，且配置为在第二节点(Q2)的电平的控制下对第一节点(Q1)进行复位；第二节点控制电路(140)与第二节点(Q2)连接，且配置为响应于第二控制信号将第三控制信号提供至第二节点(Q2)以对第二节点(Q2)的电平进行控制。该移位寄存器单元(100)可避免第二节点(Q2)长时间处于有效电平状态，以避免与该第二节点(Q2)连接的晶体管正漂。

Description

移位寄存器单元及驱动方法、栅极驱动电路、显示装置 技术领域
本公开的实施例涉及一种移位寄存器单元及驱动方法、栅极驱动电路、显示装置。
背景技术
在显示技术领域，例如液晶显示面板或有机发光二极管(Organic Light Emitting Diode,OLED)显示面板的像素阵列通常包括多行栅线和与之交错的多列数据线。对栅线的驱动可以通过绑定的集成驱动电路实现。近几年随着非晶硅薄膜晶体管或氧化物薄膜晶体管制备工艺的不断提高，也可以将栅线驱动电路直接集成在薄膜晶体管阵列基板上构成GOA(Gate driver On Array)来对栅线进行驱动。例如，可以采用由多个级联的移位寄存器单元构成的GOA为像素阵列的多行栅线提供开关态电压信号(扫描信号)，从而例如控制多行栅线依序打开，并且同时由数据线向像素阵列中对应行的像素单元提供数据信号，以在各像素单元形成显示图像的各灰阶所需要的灰度电压，进而显示一帧图像。目前的显示面板越来越多地采用GOA技术来对栅线进行驱动。GOA技术有助于实现显示面板的窄边框设计，并且可以降低显示面板的生产成本。
发明内容
本公开至少一实施例提供一种移位寄存器单元，包括输入电路、输出电路、第一节点控制电路和第二节点控制电路。所述输入电路与第一节点连接，且配置为响应于第一控制信号将输入信号提供至所述第一节点；所述输出电路与所述第一节点和输出端连接，且配置为在所述第一节点的电平的控制下，将输出信号在所述输出端输出；所述第一节点控制电路与所述第一节点和第二节点连接，且配置为在所述第二节点的电平的控制下，对所述第一节点进行复位；所述第二节点控制电路与所述第二节点连接，且配置为响应于第二控制信号将第三控制信号提供至所述第二节点，以对所述第二节点的电平进 行控制。
例如，在本公开一实施例提供的移位寄存器单元中，所述输入电路包括第一晶体管。所述第一晶体管的栅极和第一时钟信号端连接以接收第一时钟信号作为所述第一控制信号，所述第一晶体管的第一极和输入端连接以接收所述输入信号，所述第一晶体管的第二极和所述第一节点连接。
例如，在本公开一实施例提供的移位寄存器单元中，所述第二节点控制电路包括第一控制子电路和第二控制子电路。所述第一控制子电路与第三节点连接，且配置为响应于作为所述第二控制信号的第二时钟信号，控制所述第三节点的电平；所述第二控制子电路与所述第二节点和所述第三节点连接，且配置为在所述第三节点的电平的控制下，将第三控制信号输出至所述第二节点。
例如，在本公开一实施例提供的移位寄存器单元中，所述第三控制信号包括第三时钟信号。
例如，在本公开一实施例提供的移位寄存器单元中，所述第一控制子电路包括第二晶体管。所述第二晶体管的栅极和第一极彼此电连接，且分别配置为与第二时钟信号端连接以接收所述第二时钟信号作为所述第二控制信号，所述第二晶体管的第二极和所述第三节点连接。
例如，在本公开一实施例提供的移位寄存器单元中，所述第二控制子电路包括第三晶体管和第一电容。所述第三晶体管的栅极和所述第三节点连接，所述第三晶体管的第一极和第三时钟信号端连接以接收所述第三时钟信号作为所述第三控制信号，所述第三晶体管的第二极与所述第二节点连接；所述第一电容的第一端与所述第二节点连接，所述第一电容的第二端与所述第三节点连接。
例如，在本公开一实施例提供的移位寄存器单元中，所述第二节点控制电路还包括第三节点复位子电路。所述第三节点复位子电路与所述第三节点连接，且配置为响应于复位信号对所述第三节点进行复位。
例如，在本公开一实施例提供的移位寄存器单元中，所述第三节点复位子电路包括第四晶体管。所述第四晶体管的栅极和复位端连接以接收所述复位信号，所述第四晶体管的第一极和所述第三节点连接，所述第四晶体管的第二极和参考电压端连接以接收参考电压。
例如，在本公开一实施例提供的移位寄存器单元中，所述输出电路在所述第一节点的电平的控制下，将所述第二时钟信号作为所述输出信号在所述输出端输出。
例如，在本公开一实施例提供的移位寄存器单元中，所述输出端包括移位输出端和至少一个扫描信号输出端。
例如，在本公开一实施例提供的移位寄存器单元中，所述输出电路包括第五晶体管、第六晶体管和第二电容。所述第五晶体管的栅极和所述第一节点连接，所述第五晶体管的第一极和第二时钟信号端连接以接收所述第二时钟信号作为所述输出信号，所述第五晶体管的第二极和所述移位输出端连接；所述第六晶体管的栅极和所述第一节点连接，所述第六晶体管的第一极和所述第二时钟信号端连接以接收所述第二时钟信号作为所述输出信号，所述第六晶体管的第二极和所述扫描信号输出端连接；所述第二电容的第一端和所述第一节点连接，所述第二电容的第二端和所述移位输出端连接或者所述扫描信号输出端连接。
例如，在本公开一实施例提供的移位寄存器单元中，所述第一节点控制电路包括第七晶体管。所述第七晶体管的栅极和所述第二节点连接，所述第七晶体管的第一极和所述第一节点连接，所述第七晶体管的第二极和参考电压端连接以接收参考电压。
例如，本公开一实施例提供的移位寄存器单元还包括输出降噪电路。所述输出降噪电路与所述第二节点和所述输出端连接，且配置为在所述第二节点的电平的控制下，对所述输出端进行降噪。
例如，本公开一实施例提供的移位寄存器单元还包括总复位电路。所述总复位电路与所述第一节点连接，且配置为在复位信号的控制对所述第一节点进行复位。
本公开至少一实施例还提供一种栅极驱动电路，包括多个级联的本公开任一实施例提供的移位寄存器单元。
例如，本公开一实施例提供的栅极驱动电路，还包括第一时钟信号线、第二时钟信号线和第三时钟信号线，所述移位寄存器单元还包括第一时钟信号端、第二时钟信号端和第三时钟信号端。第3N+1级移位寄存器单元的第一时钟信号端和所述第一时钟信号线连接，第二时钟信号端和所述第二时钟 信号线连接，第三时钟信号端和所述第三时钟信号线连接；第3N+2级移位寄存器单元的第一时钟信号端和所述第二时钟信号线连接，第二时钟信号端和所述第三时钟信号线连接，第三时钟信号端和所述第一时钟信号线连接；第3N+3级移位寄存器单元的第一时钟信号端和所述第三时钟信号线连接，第二时钟信号端和所述第一时钟信号线连接，第三时钟信号端和所述第二时钟信号线连接；N为大于等于0的整数。
本公开至少一实施例还提供一种显示装置，包括本公开任一实施例提供的栅极驱动电路。
本公开至少一实施例还提供一种移位寄存器单元的驱动方法，包括：响应于所述第一控制信号，所述输入电路将所述输入信号提供至所述第一节点；在所述第一节点的电平的控制下，所述输出电路将所述输出信号在所述输出端输出；响应于所述第二控制信号，所述第二节点控制电路将所述第三控制信号提供至所述第二节点，以对所述第二节点的电平进行控制；在所述第二节点的电平的控制下，所述第一节点控制电路对所述第一节点进行复位。
例如，本公开一实施例提供的驱动方法，所述第二节点控制电路包括第一控制子电路和第二控制子电路，所述驱动方法还包括：响应于作为所述第二控制信号的第二时钟信号，所述第一控制子电路对第三节点的电平进行控制；在所述第三节点的电平的控制下，所述第二控制子电路将第三时钟信号作为所述第三控制信号输出至所述第二节点。
例如，在本公开一实施例提供的驱动方法中，在所述第一节点的电平的控制下，所述输出电路输出所述第二时钟信号作为所述输出信号。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为一种移位寄存器单元的电路结构示意图；
图2为本公开一实施例提供的一种移位寄存器单元的示意图；
图3示出了图2中所示的第二节点控制电路一个示例的示意图；
图4为本公开一实施例提供的另一种移位寄存器单元的示意图；
图5为本公开一实施例提供的又一种移位寄存器单元的示意图；
图6为图5中所示的移位寄存器单元的一种具体实现示例的电路示意图；
图7为本公开一实施例提供的一种栅极驱动电路的示意图；
图8为对应于图7中所示的栅极驱动电路工作时的一种示例的信号时序图；以及
图9为本公开一实施例提供的一种显示装置的示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
下面通过几个具体的实施例对本公开进行说明。为了保持本公开实施例的以下说明清楚且简明，可省略已知功能和已知部件的详细说明。当本公开实施例的任一部件在一个以上的附图中出现时，该部件在每个附图中由相同或类似的参考标号表示。
为了降低显示装置的成本以及提高其制造工艺水平，越来越多的显示装置采用了GOA技术。然而，传统的GOA技术由于电路设计复杂(例如时钟 信号和晶体管数量较多)，均存在噪声明显、功耗高等现象。
例如，图1为一种移位寄存器单元的电路结构示意图。可以多个这样的移位寄存器单元级联来构成栅极驱动电路，用于驱动例如液晶显示面板、有机发光二极管显示面板。如图1所示，该移位寄存器单元11包括上拉节点PU和下拉节点PD，下拉晶体管T11和T13的栅极与下拉节点PD连接，受到下拉节点PD的电平控制。如图1所示，在一帧显示中，下拉节点PD只有在输出扫描信号时(即上拉节点PU为高电平)为低电平，其余时间均处于高电平状态。由于下拉节点PD长时间处于高电平，会使得与下拉节点PD连接的下拉晶体管T11和T13由于长时间受正偏压应力作用，容易发生阈值电压的正漂，尤其是具有氧化物结构的晶体管，更容易出现正漂现象。如果晶体管的阈值电压的正漂范围过大，则容易造成栅极驱动电路的输出异常，从而导致显示面板出现显示异常的现象。
本公开至少一实施例提供了一种移位寄存器单元，包括输入电路、输出电路、第一节点控制电路和第二节点控制电路。输入电路与第一节点连接，且配置为响应于第一控制信号将输入信号提供至第一节点；输出电路与第一节点连接，且配置为在第一节点的电平的控制下，将输出信号在输出端输出；第一节点控制电路与第一节点和第二节点连接，且配置为在第二节点的电平的控制下，对第一节点进行复位；第二节点控制电路与第二节点连接，且配置为响应于第二控制信号将第三控制信号提供至第二节点，以对第二节点的电平进行控制。本公开的实施例还提供对应于上述移位寄存器单元的栅极驱动电路、显示装置及驱动方法。
本公开上述实施例提供的移位寄存器单元，可以避免第二节点长时间处于有效电平状态，从而避免了与该第二节点连接的晶体管因长时间受正偏压应力而发生阈值电压的正漂的现象，提高了移位寄存器单元组成的栅极驱动电路的稳定性和信赖性，提高显示面板的显示质量。
下面结合附图对本公开的实施例及其示例进行详细说明。
图2为本公开一实施例提供的一种移位寄存器单元的示意图。如图2所示，该移位寄存器单元100包括输入电路110、输出电路120、第一节点控制电路130和第二节点控制电路140。通过级联多个该移位寄存器单元100可以得到栅极驱动电路，该栅极驱动电路用于驱动例如液晶显示面板、有机发 光二极管显示面板的显示面板，为显示面板的多条栅线依序提供扫描信号，从而在显示面板显示一帧画面的期间进行逐行或隔行扫描等。
如图2所示，输入电路110与第一节点Q1(例如，这里为上拉节点)连接，且配置为响应于第一控制信号将输入信号输入至第一节点Q1，以对第一节点Q1进行充电。例如，在一些示例中，输入电路110与第一时钟信号端CLK1、输入端INT和第一节点Q1连接，配置为在第一时钟信号端CLK1接收的第一时钟信号的控制下导通，使输入信号端INT或另行提供的电压端(例如，高电压端)和第一节点Q1连接，从而使输入信号端INT提供的输入信号或另行提供的电压端提供的高电平信号被输入到第一节点Q1，将第一节点Q1的电位充电(例如上拉)到工作电位(有效电平)。例如，在该示例中，第一时钟信号作为第一控制信号，当然，本公开的实施例对此不作限制，还可以是其他合适的控制信号。
例如，输出电路120与第一节点Q1和输出端OUT连接，且配置为在第一节点Q1的电平的控制下，将输出信号在输出端OUT输出。例如，在一些示例中，输出电路120与第二时钟信号端CLK2、第一节点Q1以及输出端OUT连接，且配置为在第一节点Q1的电平的控制下导通，将第二时钟信号端CLK2提供的第二时钟信号传输至输出端OUT，并作为输出信号在输出端OUT输出。
第一节点控制电路130与第一节点Q1和第二节点Q2(例如，当第一节点Q1为上拉节点时，其为下拉节点)连接，且配置为在第二节点Q2的电平的控制下，对第一节点Q1进行复位。例如，该第一节点控制电路120可以和第一节点Q1、参考电压端VGL(例如，提供低电平)或另行提供的电压端(例如，低电压端)以及第二节点Q2连接，从而可以在第二节点Q2的电平的控制下，使得第一节点Q1和参考电压端VGL或另行提供的电压端电连接，以对第一节点Q1进行下拉复位。
第二节点控制电路140与第二节点Q2连接，且配置为响应于第二控制信号将第三控制信号提供至第二节点Q2，以对第二节点Q2的电平进行控制。例如，该第二节点控制电路140可以与第二时钟信号端CLK2和第三时钟信号端CLK3连接，且配置为响应于第二时钟信号端CLK2提供的第二时钟信号，将第三时钟信号端CLK3提供的第三时钟信号输出至第二节点Q2，以使 得第二节点Q2的电平和第三时钟信号保持一致，从而可以避免第二节点Q2在非输出阶段一直处于高电平，以避免被第二节点Q2控制的电路(例如，第一节点控制电路130)中晶体管的阈值电压的正漂。例如，在一个示例中，该第二时钟信号CLK2作为第二控制信号，第三时钟信号CLK3作为第三控制信号，本公开的实施例对此不作限制。
本公开上述实施例提供的移位寄存器单元，可以避免第二节点长时间处于有效电平状态，从而避免了与该第二节点连接的晶体管因长时间受正偏压应力而发生阈值电压的正漂的现象，提高了移位寄存器单元组成的栅极驱动电路的稳定性和信赖性，提高显示面板的显示质量。
图3示出了图2中所示的第二节点控制电路的一个示例的示意图。如图3所示，在一个示例中，第二节点控制电路140包括第一控制子电路141和第二控制子电路142。
例如，第一控制子电路141与第三节点Q3连接，且配置为响应于作为第二控制信号的第二时钟信号CLK2，控制第三节点Q3的电平。例如，第一控制子电路141与第二时钟信号端CLK2和第三节点Q3连接，且配置为在第二时钟信号端CLK2提供的第二时钟信号的控制下导通，对第三节点Q3进行预充电。例如，在该示例中，第二控制信号包括第二时钟信号。
例如，第二控制子电路142与第二节点Q2和第三节点Q3连接，且配置为在第三节点Q3的电平的控制下，将第三控制信号输出至第二节点Q2。例如，第二控制子电路142与第三时钟信号端CLK3、第二节点Q2和第三节点Q3连接，且配置为在第三节点Q3的电平的控制下导通，从而将第三时钟信号端CLK3提供的第三时钟信号输出至第二节点Q2，以使得第二节点Q2的电平和第三时钟信号保持一致，从而可以避免第二节点Q2在非输出阶段一直处于高电平，以避免被第二节点Q2控制的电路(例如，第一节点控制电路130)中晶体管的阈值电压的正漂。例如，在该示例中，第三控制信号包括第三时钟信号。
如图3所示，在另一个示例中，该第二节点控制电路140还包括第三节点复位子电路143。例如，第三节点复位子电路143与第三节点Q3连接，且配置为响应于复位信号对第三节点Q3进行复位。例如，第三节点复位子电路143与复位端T_RST、参考电压端VGL或另行提供的电压端(例如，提 供低电平)连接以及第三节点Q3连接，且配置为在复位端T_RST提供的复位信号的控制下，使得第三节点Q3与参考电压端VGL或另行提供的电压端连接，从而对第三节点Q3的复位。例如，该复位信号为全局复位信号，在一帧显示的开始阶段或结束阶段，对所有级联的移位寄存器单元的第三节点Q3同时复位，从而保证显示面板的显示质量。
图4为本公开一实施例提供的另一种移位寄存器单元的示意框图。如图4所示，在图3所示的移位寄存器单元的基础上，该移位寄存器单元100还包括输出降噪电路150。需要说明的是，图4所示的移位寄存器单元100的其他电路结构与图3中所示的移位寄存器单元100基本上相同，在此重复之处不再赘述。
例如，该输出降噪电路150配置为在第二节点Q2的电平的控制下，对输出端OUT进行降噪。例如，输出降噪电路150与第二节点Q2、输出端OUT以及参考电压端VGL或另行提供的电压端(例如，低电压端)连接，且配置为在第二节点Q2例如为高电平时导通，使得输出端OUT与参考电压端VGL或另行提供的电压端连接，以实现对输出端OUT降噪。
图5为本公开一实施例提供的又一种移位寄存器单元的示意框图。如图5所示，在图4所示的移位寄存器单元的基础上，该移位寄存器单元100还包括总复位电路160。需要说明的是，图5所示的移位寄存器单元100的其他电路结构与图4中所示的移位寄存器单元100基本上相同，在此重复之处不再赘述。
例如，总复位电路160与第一节点Q1连接，且配置为在复位信号的控制对第一节点Q1进行复位。例如，总复位电路160与复位端T_RST、第一节点Q1和参考电压端VGL或另行提供的电压端(例如，低电压端)连接，且配置为在复位端T_RST提供的复位信号的控制下导通，使第一节点Q1与参考电压端VGL或另行提供的电压端(例如，低电压端)电连接，从而对第一节点Q1复位。例如，图中省略了与复位端T_RST连接对应的连接线。
例如，参考电压端VGL配置为提供直流低电平信号(例如低于或等于时钟信号的低电平部分)，例如接地，这里将该直流低电平信号称为参考电压，以下各实施例与此相同，不再赘述。
请注意，本公开实施例中提供的移位寄存器单元的“有效电平”指的是 能够使得其包括的被操作晶体管被导通的电平，相应地“无效电平”指的是不能使得其包括的被操作晶体管被导通(即，该晶体管被截止)的电平。根据移位寄存器单元的电路结构中的晶体管的类型(N型或P型)等因素，有效电平可以比无效电平高或者低。通常，移位寄存器单元在工作期间使用的方波脉冲信号，有效电平对应于该方波脉冲信号的方波脉冲部分的电平，而无效电平则对应于非方波脉冲部分的电平。
图6为图5中所示实施例的移位寄存器单元的一种具体实现示例的电路图，而其他图中所示实施例的移位寄存器单元可以相同或相似的方式实现。如图6所示，该移位寄存器单元100包括第一晶体管至第十晶体管M1-M10，以及还包括第一电容C1和第二电容C2。需要注意的是，在下面的说明中以各晶体管为N型晶体管为例进行说明，但这并不构成对本公开实施例的限制。
如图6所示，输入电路110可以实现为第一晶体管M1。第一晶体管M1的栅极和第一时钟信号端CLK1连接以接收第一时钟信号作为第一控制信号，第一晶体管M1的第一极和输入端INT连接以接收输入信号，第一晶体管M1的第二极和第一节点Q1连接，从而当第一晶体管M1响应于第一时钟信号端CLK1提供的第一时钟信号的有效电平(例如，高电平信号)而导通时，使用输入端INT接收到的输入信号对第一节点Q1进行充电，使其处于高电平。
如图6所示，第一控制子电路141可以实现为第二晶体管M2。第二晶体管M2的栅极和第一极彼此电连接，且分别配置为与第二时钟信号端CLK2连接以接收第二时钟信号作为第二控制信号，第二晶体管M2的第二极和第三节点Q3连接，从而当第二晶体管M2响应于第二时钟信号端CLK2提供的第二时钟信号(例如，高电平)导通时，使用该第二时钟信号对第三节点Q3进行充电，使其处于高电平。
第二控制子电路142可以实现为第三晶体管M3和第一电容C1。第三晶体管M3的栅极和第三节点Q3连接，第三晶体管M3的第一极和第三时钟信号端CLK3连接以接收第三时钟信号作为第三控制信号，第三晶体管M3的第二极与第二节点Q2连接。第一电容C1的第一端与第二节点Q2连接，第一电容C1的第二端与第三节点Q3连接。当第三节点Q3为有效电平(例如，高电平)时，第三晶体管M3导通，第二节点Q2与第三时钟信号端CLK3 连接，使得第二节点Q2的电平与第三时钟信号端CLK3提供的第三时钟信号的电平一致。例如，当第三时钟信号端CLK3提供的第三时钟信号为高电平时，第二节点Q2为高电平；当第三时钟信号为低电平时，第二节点Q2为低电平，因此可以避免第二节点Q2在非输出阶段一直处于高电平，从而可以避免通过第二节点Q2控制的晶体管(例如，第七晶体管M7、第九晶体管M9和第十晶体管M10)长时间处于正偏压应力的作用下而发生阈值电压的正漂。
如图6所示，第三节点复位子电路143包括第四晶体管M4。第四晶体管M4的栅极和复位端T_RST连接以接收复位信号，第四晶体管M4的第一极和第三节点Q3连接，第四晶体管M4的第二极和参考电压端VGL连接以接收参考电压。例如，在一帧显示的开始或结束时，当复位端T_RST提供的复位信号为有效电平(例如，高电平)时，第四晶体管M4导通，使得第三节点Q3和参考电压端VGL连接，从而可以对第三节点Q3进行复位。
例如，如图6所示，输出端OUT包括移位输出端CR和至少一个扫描信号输出端，从而将输出信号例如第二时钟信号端CLK2提供的第二时钟信号分别输出至移位输出端CR和扫描信号输出端OUT1，以提高该移位寄存器单元100的驱动能力。例如，至少一个扫描信号输出端包括一个扫描信号输出端OUT1。例如，移位输出端CR用于为下一级移位寄存器单元100提供输入信号，扫描信号输出端OUT1用于为显示面板中一行像素单元的像素电路提供驱动信号。例如，移位输出端CR和该扫描信号输出端OUT1输出相同的输出信号。需要注意的是，在其他示例中，当包括多个扫描信号输出端时，各个扫描信号输出端也可以输出不同的输出信号，具体的设置根据实际情况而定，本公开的实施例对此不作限制。
例如，输出电路120可以实现为第五晶体管M5、第六晶体管M6和第二电容C2。第五晶体管M5的栅极和第一节点Q1连接，第五晶体管M5的第一极和第二时钟信号端CLK2连接以接收第二时钟信号作为输出信号，第五晶体管M5的第二极和移位输出端CR连接。第六晶体管M6的栅极和第一节点Q1连接，第六晶体管M6的第一极和第二时钟信号端CLK2连接以接收第二时钟信号作为输出信号，第六晶体管M6的第二极和扫描信号输出端OUT1连接。第二电容C2的第一端和第一节点Q1连接，第二电容C2的 第二端和移位输出端CR连接或者扫描信号输出端OUT1连接。需要注意的是，不限于此，移位寄存器单元还可以包括更多的输出信号，以及与其对应的扫描信号输出端。
如图6所示，第一节点控制电路130可以实现为第七晶体管M7。例如，第七晶体管M7的栅极和第二节点Q2连接，第七晶体管M7的第一极和第一节点Q1连接，第七晶体管M7的第二极和参考电压端VGL连接以接收参考电压。例如，当第二节点Q2为高电平时，第七晶体管T7导通，使得第一节点Q1与参考电压端VGL连接以接收参考电压，从而可以对第一节点Q1进行复位。
例如，在至少一个扫描信号输出端包括一个扫描信号输出端，例如，扫描信号输出端OUT1时，例如，输出降噪电路150可以实现为第九晶体管M9和第十晶体管M10。第九晶体管M9的栅极和第二节点Q2连接，第一极和移位输出端CR连接，第二极和参考电压端VGL连接以接收参考电压。第十晶体管M10的栅极和第二节点Q2连接，第十晶体管M10的第一极和第一扫描信号输出端OUT1连接，第十晶体管M10的第二极和参考电压端VGL连接以接收参考电压。
例如，当第二节点Q2为有效电平(例如，高电平)时，第九晶体管M9和第十晶体管M10均导通，使移位输出端CR和扫描信号输出端OUT1均与参考电压端VGL电连接，从而对移位输出端CR和扫描信号输出端OUT1降噪。
需要说明的是，在本公开的各实施例中，当移位输出端CR和扫描信号输出端OUT1分别包括更多个时，输出降噪电路150也相应地包括多个与移位输出端和/或扫描信号输出端对应连接的晶体管，以对其进行降噪。
例如，总复位电路160可以实现为第八晶体管M8。例如，第八晶体管M8的栅极和复位端T_RST连接以接收复位信号，第八晶体管M8的第一极和第一节点Q1连接，第八晶体管M8的第二极和参考电压端VGL连接以接收参考电压。例如，在一帧显示的开始或结束时，当复位端T_RST提供的复位信号为有效电平(例如，高电平)时，第八晶体管M8导通，使得第一节点Q1和参考电压端VGL连接，从而可以对第一节点Q1进行复位。
需要注意的是，图2-图4中所示的移位寄存器单元的电路结构和图6中 所示的图5中所示的移位寄存器单元的电路结构类似，在此不再赘述。
在本公开的实施例中，例如，当各个电路实现为N型晶体管时，术语“上拉”表示对一个节点或一个晶体管的一个电极进行充电，以使得该节点或该电极的电平的绝对值升高，从而实现相应晶体管的操作(例如导通)；“下拉”表示对一个节点或一个晶体管的一个电极进行放电，以使得该节点或该电极的电平的绝对值降低，从而实现相应晶体管的操作(例如截止)。
又例如，当各个电路实现为P型晶体管时，术语“上拉”表示对一个节点或一个晶体管的一个电极进行放电，以使得该节点或该电极的电平的绝对值降低，从而实现相应晶体管的操作(例如导通)；“下拉”表示对一个节点或一个晶体管的一个电极进行充电，以使得该节点或该电极的电平的绝对值升高，从而实现相应晶体管的操作(例如截止)。
需要注意的是，在本公开的各个实施例的说明中，第一节点Q1、第二节点Q2和第三节点Q3并非表示实际存在的部件，而是表示电路图中相关电连接的汇合点。
需要说明的是，本公开的实施例中采用的晶体管均可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件，本公开的实施例中均以薄膜晶体管为例进行说明。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管除栅极之外的两极，直接描述了其中一极为第一极，另一极为第二极。
另外，在本公开的实施例中的晶体管均以N型晶体管为例进行说明，此时，晶体管的第一极是漏极，第二极是源极。需要说明的是，本公开包括但不限于此。例如，本公开的实施例提供的移位寄存器单元100中的一个或多个晶体管也可以采用P型晶体管，此时，晶体管第一极是源极，第二极是漏极，只需将选定类型的晶体管的各极参照本公开的实施例中的相应晶体管的各极相应连接，并且使相应的电压端提供对应的高电压或低电压即可。当采用N型晶体管时，可以采用氧化铟镓锌(Indium Gallium Zinc Oxide，IGZO)作为薄膜晶体管的有源层，相对于采用低温多晶硅(Low Temperature Poly Silicon，LTPS)或非晶硅(例如氢化非晶硅)作为薄膜晶体管的有源层，可以有效减小晶体管的尺寸以及防止漏电流。
本公开一个实施例还提供一种栅极驱动电路。图7为本公开一实施例提供的一种栅极驱动电路的示意图。如图7所示，该栅极驱动电路10包括多个级联的移位寄存器单元100，其中任意一个或多个移位寄存器单元100可以采用本公开任一实施例提供的移位寄存器单元100的结构或其变型，例如，可以采用图6中所示的移位寄存器单元100。例如，该栅极驱动电路10可以采用与薄膜晶体管同样半导体制程的工艺直接集成在显示装置的阵列基板上，以实现逐行或隔行扫描驱动功能。
除第1级移位寄存器单元外，其余各级移位寄存器单元的输入端INT和其上级移位寄存器单元的移位输出端CR连接。
本公开实施例提供的移位寄存器单元，由于可以在第二节点Q2的电平的控制下，控制第一节点控制电路130和输出降噪电路150导通，实现对第一节点Q1的复位和对输出端OUT的降噪，从而无需设置单独的复位电路对当前级移位寄存器单元的第一节点Q1进行复位。因此，在该栅极驱动电路10中，各级移位寄存器单元(除最后1级移位寄存器单元外)也无需和其下级移位寄存器单元的移位输出端CR连接以用于对当前级移位寄存器单元的第一节点Q1进行复位，从而本公开实施例提供的栅极驱动电路可以降低布线的复杂度，提高栅极驱动电路的稳定性。
如图7所示，栅极驱动电路10还包括第一时钟信号线CLKA、第二时钟信号线CLKB和第三时钟信号线CLKC。例如，该第一时钟信号线CLKA、第二时钟信号线CLKB和第三时钟信号线CLKC分别与多个级联的移位寄存器单元的时钟信号端连接以提供时钟信号。需要注意的是，该栅极驱动电路10还可以包括四条、六条或八条以及更多的时钟信号线，时钟信号线的条数视具体情况而定，本公开的实施例在此不作限定。
例如，如图7所示，该移位寄存器单元的每个还包括第一时钟信号端CLK1、第二时钟信号端CLK2和第三时钟信号端CLK3，且分别配置为和第一时钟信号线CLKA、第二时钟信号线CLKB或第三时钟信号线CLKC连接以接收时钟信号。第3N+1(N为大于等于0的整数)级移位寄存器单元的第一时钟信号端CLK1和第一时钟信号线CLKA连接，第二时钟信号端CLK2和第二时钟信号线CLKB连接，第三时钟信号端CLK3和第三时钟信号线CLKC连接；第3N+2级移位寄存器单元的第一时钟信号端CLK1和第二时 钟信号线CLKB连接，第二时钟信号端CLK2和第三时钟信号线CLKC连接，第三时钟信号端CLK3和第一时钟信号线CLKA连接；第3N+3级移位寄存器单元的第一时钟信号端CLK1和第三时钟信号线CLKC连接，第二时钟信号端CLK2和第一时钟信号线CLKA连接，第三时钟信号端CLK3和第二时钟信号线CLKB连接。需要说明的是，本公开的实施例包括但不限于上述连接方式。
如图7所示，栅极驱动电路10还包括复位信号线T_RST1，该移位寄存器单元的每个还包括复位端T_RST，且配置为和复位信号线T_RST1连接以接收复位信号。
需要说明的是，图7中所示的OUT1_3N+1表示第3N+1级移位寄存器单元的扫描信号输出端，OUT1_3N+2表示第3N+2级移位寄存器单元的扫描信号输出端，OUT1_3N+3表示第3N+3级移位寄存器单元的扫描信号输出端，以此类推……；CR_3N+1表示第3N+1级移位寄存器单元的移位输出端，CR_3N+2表示第3N+2级移位寄存器单元的移位输出端，CR_3N+3表示第3N+3级移位寄存器单元的移位输出端，以此类推……。以下各实施例中的附图标记与此类似，不再赘述。
例如，第1级移位寄存器单元的输入端INT可以被配置为接收触发信号STV，为简洁起见触发信号STV在图7中未示出。
例如，如图7所示，该栅极驱动电路10还可以包括时序控制器200。例如，该时序控制器200可以被配置为和第一时钟信号线CLKA、第二时钟信号线CLKB和第三时钟信号线CLKC连接，以向各移位寄存器单元提供时钟信号；该时序控制器200还可以被配置为与复位信号线T_RST1和参考电压线(图中未示出)连接，以向各移位寄存器单元100分别提供复位信号和参考电压。例如，时序控制器300还可以被配置为提供触发信号STV。需要说明的是，时序控制器200提供的多个时钟信号彼此之间的相位关系可以根据实际需求而定。
例如，第一时钟信号线CLKA、第二时钟信号线CLKB和第三时钟信号线CLKC提供的时钟信号时序可以采用图8中所示的信号时序，以实现栅极驱动电路10逐行输出栅极扫描信号的功能。需要说明的是，图8所示的信号时序图的电位的高低仅是示意性的，不代表真实电位值或相对比例，对应于 上述示例，高电平信号对应于N型晶体管的开启信号，而低电平信号对应于N型晶体管为截止信号。
例如，在一个示例中，下面结合图8所示的信号时序图，对图7中所示的栅极驱动电路10的第1级移位寄存器单元的工作原理进行说明。
如图8所示，Q1<1>、Q2<1>和Q3<1>分别表示栅极驱动电路10中第一级移位寄存器单元中第一节点、第二节点和第三节点；OUT1_1、OUT1_2分别表示栅极驱动电路210中的第一级、第二级移位寄存器单元中扫描信号输出端。例如，第1级移位寄存器单元可以采用图6所示的电路结构，该移位寄存器单元100的工作原理为：
在第一阶段t1(即一帧开始的阶段)，复位信号线T_RST1提供高电平，由于各级移位寄存器单元的复位端T_RST均与复位信号线T_RST1连接，因此，在此阶段，各级移位寄存器单元的总复位电路160和第三节点复位子电路143均导通，使得第一节点Q1和第三节点Q3均与参考电压端VGL连接，从而对各级移位寄存器单元的第一节点Q1和第三节点Q3进行复位。需要说明的是，图8中所示的信号时序图的电位的高低仅是示意性的，不代表真实电位值或相对比例，对应于上述示例，高电平信号对应于N型晶体管的开启信号，而低电平信号对应于N型晶体管为截止信号。
在第二阶段t2，输入端INT提供高电平，第一时钟信号线CLKA提供高电平，由于第1级移位寄存器单元100的第一时钟信号端CLK1和第一时钟信号线CLKA连接，所以在此阶段，第1级移位寄存器单元100的第一时钟信号端CLK1输入高电平，输入电路110在第一时钟信号端CLK1提供的高电平的控制下导通，使得输入端INT提供的高电平对第一节点Q1<1>进行充电，第一节点Q1<1>被充电至第一高电平；同时，第二时钟信号线CLKB提供低电平，由于第1级移位寄存器单元100的第二时钟信号端CLK2和第二时钟信号线CLKB连接，所以在此阶段，第1级移位寄存器单元100的第二时钟信号端CLK2输入低电平，所以在第一节点Q1<1>的第一高电平的控制下，第二时钟信号端CLK2输入的低电平输出至第1级移位寄存器单元100的输出端OUT1_1。
在第三阶段t3，第二时钟信号线CLKB提供高电平，所以第1级移位寄存器单元100的第二时钟信号端CLK2输入高电平，第一节点Q1<1>由于电 容的自举效应被进一步充电至第二高电平，所以在第一节点Q1<1>的第二高电平的控制下，第二时钟信号端CLK2输入的高电平被输出至第1级移位寄存器单元100的扫描信号输出端OUT1_1；同时，第一控制子电路141在第二时钟信号端CLK2输入的高电平的控制下导通，使得第二时钟信号端CLK2输入的高电平对第三节点Q3<1>进行充电，第三节点Q3<1>被充电至第一高电平；同时，第三时钟信号线CLKC提供低电平，由于第1级移位寄存器单元100的第三时钟信号端CLK3和第三时钟信号线CLKC连接，所以在此阶段，第1级移位寄存器单元100的第三时钟信号端CLK3输入低电平，所以在第三节点Q3<1>的第一高电平的控制下，第三时钟信号端CLK3输入的低电平输出至第1级移位寄存器单元100的第二节点Q2<1>。而且，在此阶段，第三时钟信号线CLKC提供低电平，由于第2级移位寄存器单元100的第二时钟信号端CLK2和第三时钟信号线CLKC连接，所以在此阶段第2级移位寄存器单元100的第二时钟信号端CLK2输入低电平，且由于该第1级移位寄存器单元100的第一输出端OUT1_1输出的高电平作为第2级移位寄存器单元100的输入信号，从而第2级移位寄存器单元100的第一节点Q1被该输入信号上拉至第一高电平，所以，在第2级移位寄存器单元100的第一节点Q1的第一高电平的控制下，第2级移位寄存器单元100的第二时钟信号端CLK2输入的低电平输出至输出端OUT1_2。
在第四阶段t4，第三时钟信号线CLKC提供高电平，所以第1级移位寄存器单元100的第三时钟信号端CLK3输入高电平，第三节点Q3<1>由于电容的自举效应被进一步充电至第二高电平，所以在第三节点Q3<1>的第二高电平的控制下，第三时钟信号端CLK3输入的高电平被输出至第1级移位寄存器单元100的第二节点Q2<1>，从而第一节点控制电路130和输出降噪电路150在第二节点Q2<1>的电平的控制下导通，使得第一节点Q1<1>、移位输出端CR_1和扫描信号输出端OUT1_1与参考电压端VGL连接，实现降噪；同时，在此阶段，由于第三时钟信号线CLKC提供高电平，所以第2级移位寄存器单元100的第二时钟信号端CLK2输入高电平，第2级移位寄存器单元100的第一节点Q1由于电容的自举效应被进一步充电至第二高电平，所以在第一节点Q1的第二高电平的控制下，第2级移位寄存器单元100的第二时钟信号端CLK2输入的高电平输出至第2级移位寄存器单元100的输出 端OUT1_2。
在第五阶段t5，第三时钟信号线CLKC提供低电平，因此，第1级移位寄存器单元的第三时钟信号端CLK3输入低电平。由于第二控制子电路142响应于第三节点Q3<1>的高电平而导通，所以第三时钟信号端CLK3输入的低电平被输出至第1级移位寄存器单元100的第二节点Q2<1>，因此，在此阶段，第二节点Q2<1>被放电至低电平，从而使得第二节点Q2<1>的电平与第三时钟信号端CLK3提供的第三时钟信号的电平一致，因此可以避免第二节点Q2<1>在非输出阶段(即除去第三阶段t3的各个阶段)一直处于高电平，从而可以避免被第二节点Q2<1>控制的晶体管(例如，第七晶体管M7、第九晶体管M9和第十晶体管M10)长时间处于正偏压应力的作用下而发生阈值电压的正漂。在此阶段，当第二节点Q2<1>被放电至低电平时，由于电容的耦合作用，第三节点Q3<1>也被下拉，例如，被下拉至第一高电平。
需要注意的是，其余各级移位寄存器单元的工作原理与第1级移位寄存器单元的工作原理类似，在此不再赘述，区别在于：除第1级移位寄存器单元外，其余各级移位寄存器单元不包括第1阶段t1，即在一帧显示开始时的全局复位。
在一帧结束时，即在第六阶段t6，复位信号线T_RST1提供高电平，由于各级移位寄存器单元的复位端T_RST均与复位信号线T_RST1连接，因此，在此阶段，各级移位寄存器单元的总复位电路160和第三节点复位子电路143均导通，使得第一节点Q1和第三节点Q3均与参考电压端VGL连接，从而对各级移位寄存器单元的第一节点Q1和第三节点Q3进行复位，以避免移位寄存器单元的误输出，提高显示质量。
需要说明的是，图8中所示的信号时序图的电位的高低仅是示意性的，不代表真实电位值或相对比例，对应于上述示例，高电平信号对应于N型晶体管的开启信号，而低电平信号对应于N型晶体管为截止信号。
需要说明的是，当采用本公开的实施例提供的栅极驱动电路10驱动一显示面板时，可以将该栅极驱动电路10设置于显示面板的一侧。例如，该显示面板包括多行栅线，栅极驱动电路10中的各级电压转换电路的第二输出端可以配置为依序和该多行栅线连接，以用于输出栅极扫描信号。需要说明的是，还可以分别在显示面板的两侧设置该栅极驱动电路10，以实现双边驱动，本 公开的实施例对栅极驱动电路10的设置方式不作限定。
本公开的实施例还提供一种显示装置1，如图9所示，该显示装置1包括本公开上述实施例提供的栅极驱动电路10。该显示装置1还包括显示面板40，显示面板40包括由多个子像素单元410构成的阵列。例如，该显示装置1还可以包括数据驱动电路30。数据驱动电路30用于提供数据信号给像素阵列；栅极驱动电路10用于提供驱动信号给像素阵列，例如该驱动信号可以驱动子像素单元410中的扫描晶体管和感测晶体管。数据驱动电路30通过数据线DL与子像素单元410电连接，栅极驱动电路10通过栅线GL与子像素单元410电连接。
需要说明的是，本实施例中的显示装置1可以为：液晶面板、液晶电视、显示器、OLED面板、OLED电视、电子纸显示装置、手机、平板电脑、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。该显示装置1还可以包括显示面板等其他常规部件，本公开的实施例对此不作限定。
本公开的实施例提供的显示装置1的技术效果可以参考上述实施例中关于栅极驱动电路10的相应描述，这里不再赘述。
需要说明的是，为表示清楚、简洁，并没有给出该显示装置1的全部结构。为实现显示装置的必要功能，本领域技术人员可以根据具体应用场景进行设置其他未示出的结构，本公开的实施例对此不做限制。
本公开的实施例还提供一种驱动方法，可以用于驱动本公开的实施例提供的移位寄存器单元100，例如，在一个示例中，该驱动方法包括：响应于第一控制信号，输入电路110将输入信号提供至第一节点Q1；在第一节点Q1的电平的控制下，输出电路120将输出信号在输出端OUT输出；响应于第二控制信号，第二节点控制电路140将第三控制信号提供至第二节点Q2，以对第二节点Q2的电平进行控制；在第二节点Q2的电平的控制下，第一节点控制电路对第一节点Q1进行复位。
例如，在另一个示例中，第二节点控制电路140包括第一控制子电路141和第二控制子电路142，该驱动方法还包括：响应于作为第二控制信号的第二时钟信号，第一控制子电路141对第三节点Q3的电平进行控制；在第三节点Q3的电平的控制下，第二控制子电路142将第三时钟信号作为第三控制信号输出至第二节点Q2。例如，在该示例中，在第一节点Q1的电平的控 制下，输出电路120输出第二时钟信号作为输出信号。
本公开的实施例提供的栅极驱动电路10的驱动方法的技术效果可以参考上述实施例中关于栅极驱动电路10的相应描述，这里不再赘述。
有以下几点需要说明：
(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，本公开的保护范围由所附的权利要求确定。

Claims (20)

  1. 一种移位寄存器单元，包括输入电路、输出电路、第一节点控制电路和第二节点控制电路；其中，
    所述输入电路与第一节点连接，且配置为响应于第一控制信号将输入信号提供至所述第一节点；
    所述输出电路与所述第一节点和输出端连接，且配置为在所述第一节点的电平的控制下，将输出信号在所述输出端输出；
    所述第一节点控制电路与所述第一节点和第二节点连接，且配置为在所述第二节点的电平的控制下，对所述第一节点进行复位；
    所述第二节点控制电路与所述第二节点连接，且配置为响应于第二控制信号将第三控制信号提供至所述第二节点，以对所述第二节点的电平进行控制。
  2. 根据权利要求1所述的移位寄存器单元，其中，所述输入电路包括第一晶体管；
    其中，所述第一晶体管的栅极和第一时钟信号端连接以接收第一时钟信号作为所述第一控制信号，所述第一晶体管的第一极和输入端连接以接收所述输入信号，所述第一晶体管的第二极和所述第一节点连接。
  3. 根据权利要求1或2所述的移位寄存器单元，其中，所述第二节点控制电路包括第一控制子电路和第二控制子电路；其中，
    所述第一控制子电路与第三节点连接，且配置为响应于作为所述第二控制信号的第二时钟信号，控制所述第三节点的电平；
    所述第二控制子电路与所述第二节点和所述第三节点连接，且配置为在所述第三节点的电平的控制下，将第三控制信号输出至所述第二节点。
  4. 根据权利要求3所述的移位寄存器单元，其中，所述第三控制信号包括第三时钟信号。
  5. 根据权利要求3或4所述的移位寄存器单元，其中，所述第一控制子电路包括第二晶体管；其中，
    所述第二晶体管的栅极和第一极彼此电连接，且分别配置为与第二时钟信号端连接以接收所述第二时钟信号作为所述第二控制信号，所述第二晶体 管的第二极和所述第三节点连接。
  6. 根据权利要求4所述的移位寄存器单元，其中，所述第二控制子电路包括第三晶体管和第一电容；其中，
    所述第三晶体管的栅极和所述第三节点连接，所述第三晶体管的第一极和第三时钟信号端连接以接收所述第三时钟信号作为所述第三控制信号，所述第三晶体管的第二极与所述第二节点连接；
    所述第一电容的第一端与所述第二节点连接，所述第一电容的第二端与所述第三节点连接。
  7. 根据权利要求3-6任一所述的移位寄存器单元，其中，所述第二节点控制电路还包括第三节点复位子电路，其中，
    所述第三节点复位子电路与所述第三节点连接，且配置为响应于复位信号对所述第三节点进行复位。
  8. 根据权利要求7所述的移位寄存器单元，其中，所述第三节点复位子电路包括第四晶体管；
    其中，所述第四晶体管的栅极和复位端连接以接收所述复位信号，所述第四晶体管的第一极和所述第三节点连接，所述第四晶体管的第二极和参考电压端连接以接收参考电压。
  9. 根据权利要求3-8任一所述的移位寄存器单元，其中，所述输出电路在所述第一节点的电平的控制下，将所述第二时钟信号作为所述输出信号在所述输出端输出。
  10. 根据权利要求9所述的移位寄存器单元，其中，所述输出端包括移位输出端和至少一个扫描信号输出端。
  11. 根据权利要求10所述的移位寄存器单元，其中，所述输出电路包括第五晶体管、第六晶体管和第二电容；其中，
    所述第五晶体管的栅极和所述第一节点连接，所述第五晶体管的第一极和第二时钟信号端连接以接收所述第二时钟信号作为所述输出信号，所述第五晶体管的第二极和所述移位输出端连接；
    所述第六晶体管的栅极和所述第一节点连接，所述第六晶体管的第一极和所述第二时钟信号端连接以接收所述第二时钟信号作为所述输出信号，所述第六晶体管的第二极和所述扫描信号输出端连接；
    所述第二电容的第一端和所述第一节点连接，所述第二电容的第二端和所述移位输出端连接或者所述扫描信号输出端连接。
  12. 根据权利要求1-11任一所述的移位寄存器单元，其中，所述第一节点控制电路包括第七晶体管；
    其中，所述第七晶体管的栅极和所述第二节点连接，所述第七晶体管的第一极和所述第一节点连接，所述第七晶体管的第二极和参考电压端连接以接收参考电压。
  13. 根据权利要求1-12任一所述的移位寄存器单元，还包括输出降噪电路；
    其中，所述输出降噪电路与所述第二节点和所述输出端连接，且配置为在所述第二节点的电平的控制下，对所述输出端进行降噪。
  14. 根据权利要求1-13任一所述的移位寄存器单元，还包括总复位电路；
    其中，所述总复位电路与所述第一节点连接，且配置为在复位信号的控制对所述第一节点进行复位。
  15. 一种栅极驱动电路，包括多个级联的如权利要求1-14任一所述的移位寄存器单元。
  16. 根据权利要求14所述的栅极驱动电路，还包括第一时钟信号线、第二时钟信号线和第三时钟信号线，所述移位寄存器单元还包括第一时钟信号端、第二时钟信号端和第三时钟信号端；其中，
    第3N+1级移位寄存器单元的第一时钟信号端和所述第一时钟信号线连接，第二时钟信号端和所述第二时钟信号线连接，第三时钟信号端和所述第三时钟信号线连接；
    第3N+2级移位寄存器单元的第一时钟信号端和所述第二时钟信号线连接，第二时钟信号端和所述第三时钟信号线连接，第三时钟信号端和所述第一时钟信号线连接；
    第3N+3级移位寄存器单元的第一时钟信号端和所述第三时钟信号线连接，第二时钟信号端和所述第一时钟信号线连接，第三时钟信号端和所述第二时钟信号线连接；
    N为大于等于0的整数。
  17. 一种显示装置，包括如权利要求15或16所述的栅极驱动电路。
  18. 一种如权利要求1所述的移位寄存器单元的驱动方法，包括：
    响应于所述第一控制信号，所述输入电路将所述输入信号提供至所述第一节点；
    在所述第一节点的电平的控制下，所述输出电路将所述输出信号在所述输出端输出；
    响应于所述第二控制信号，所述第二节点控制电路将所述第三控制信号提供至所述第二节点，以对所述第二节点的电平进行控制；
    在所述第二节点的电平的控制下，所述第一节点控制电路对所述第一节点进行复位。
  19. 根据权利要求18所述的驱动方法，所述第二节点控制电路包括第一控制子电路和第二控制子电路，所述驱动方法还包括：
    响应于作为所述第二控制信号的第二时钟信号，所述第一控制子电路对第三节点的电平进行控制；
    在所述第三节点的电平的控制下，所述第二控制子电路将第三时钟信号作为所述第三控制信号输出至所述第二节点。
  20. 根据权利要求19所述的驱动方法，其中，
    在所述第一节点的电平的控制下，所述输出电路输出所述第二时钟信号作为所述输出信号。
PCT/CN2018/115370 2018-11-14 2018-11-14 移位寄存器单元及驱动方法、栅极驱动电路、显示装置 WO2020097816A1 (zh)

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