WO2020088432A1 - 显示基板及其制造方法、显示装置 - Google Patents

显示基板及其制造方法、显示装置 Download PDF

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Publication number
WO2020088432A1
WO2020088432A1 PCT/CN2019/113888 CN2019113888W WO2020088432A1 WO 2020088432 A1 WO2020088432 A1 WO 2020088432A1 CN 2019113888 W CN2019113888 W CN 2019113888W WO 2020088432 A1 WO2020088432 A1 WO 2020088432A1
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Prior art keywords
signal line
power signal
base substrate
electrode
layer
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PCT/CN2019/113888
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English (en)
French (fr)
Inventor
张子予
张嵩
周伟峰
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京东方科技集团股份有限公司
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Priority to US16/766,310 priority Critical patent/US20200373373A1/en
Publication of WO2020088432A1 publication Critical patent/WO2020088432A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H10K50/844—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/873—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/10—Deposition of organic active material
    • H10K71/12—Deposition of organic active material using liquid deposition, e.g. spin coating
    • H10K71/13—Deposition of organic active material using liquid deposition, e.g. spin coating using printing techniques, e.g. ink-jet printing or screen printing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display substrate, a manufacturing method thereof, and a display device.
  • thin film packaging Thin Film Encapsulation, TFE
  • TFE Thin Film Encapsulation
  • the principle of thin-film encapsulation is to use a dense thin-film encapsulation layer to block water and oxygen (hereinafter abbreviated as water-oxygen), so as to prevent sensitive materials such as metal materials and luminescent materials inside the flexible display device from being corroded by water and oxygen.
  • water-oxygen water and oxygen
  • the present disclosure provides a display substrate, a manufacturing method thereof, and a display device.
  • the technical solution is as follows:
  • a display substrate includes:
  • the base substrate has a package area, an orthographic projection of the power signal line on the base substrate extends from the package area to the outside of the package area, and the electrode block is on the base substrate The orthographic projection of and there is a coincident area with the packaging area.
  • the electrode block covers both sides of the power signal line.
  • the electrode block includes a first portion, a second portion, a third portion, a fourth portion, and a fifth portion that are sequentially adjacent to each other, and the first portion and the fifth portion are both located on the base substrate
  • the second part and the fourth part are respectively attached to one side of the power signal line
  • the third part covers the side of the power signal line away from the base substrate.
  • the distance from the end of the first part far away from the power signal line to the power signal line is 2 to 20 microns, and the end of the fifth part far away from the power signal line to the power signal
  • the distance of the line ranges from 2 to 20 microns.
  • the front projection of the electrode block on the base substrate completely covers the front projection of the power signal line on the base substrate.
  • the electrode block covers one side of the power signal line, and the electrode block is coated on both sides of the power signal line.
  • the electrode block has a zigzag shape, and the electrode block includes a sixth portion, a seventh portion, and an eighth portion that are adjacent to each other in sequence, and the sixth portion overlaps the power signal line away from the backing On one side of the base substrate, the seventh portion is attached to the target side of the power signal line, the eighth portion is located on the base substrate, and the target side is on both sides of the power signal line Side.
  • the distance from the end of the sixth portion away from the target side to the target side is 2 to 20 microns
  • the distance from the end of the eighth portion away from the target side to the target side It is 2 to 20 microns.
  • the display substrate further includes a thin film transistor on the base substrate, and the power signal line and the source and drain patterns in the thin film transistor are in the same layer and the same material.
  • the display substrate further includes a light emitting device located on a side of the thin film transistor away from the base substrate, the light emitting device includes a first electrode stacked in a direction away from the base substrate, and emitting light Layer and second electrode, the electrode block and the first electrode are in the same layer and the same material.
  • the display substrate includes a first power signal line and a second power signal line insulated from each other;
  • the first power signal line is connected to the first electrode, and the second power signal line is connected to the second electrode.
  • the power signal line includes a first metal layer, a second metal layer, and a third metal layer stacked in a direction away from the base substrate, the material of the second metal layer and the first metal layer The materials of the metal layer and the third metal layer are different.
  • the metal activity of the second metal layer is greater than the metal activity of the first metal layer and the third metal layer.
  • the thin film transistor is one of a thin film transistor with a top gate structure and a thin film transistor with a bottom gate structure.
  • the display substrate further includes a thin film transistor on the base substrate, and the power signal line and the source and drain patterns in the thin film transistor are in the same layer and the same material;
  • the display substrate further includes a light emitting device on a side of the thin film transistor away from the base substrate, the light emitting device includes a first electrode, a light emitting layer, and a second layer stacked in a direction away from the base substrate
  • An electrode, the electrode block and the first electrode have the same layer and the same material
  • the power signal line includes a first metal layer, a second metal layer, and a third metal layer stacked in a direction away from the base substrate, the metal activity of the second metal layer is greater than that of the first metal layer And the metal activity of the third metal layer.
  • a display device comprising: the display substrate according to any one of the aspects.
  • a method for manufacturing a display substrate includes:
  • the substrate substrate having a packaging area
  • the forming an electrode block on the base substrate on which the power signal line is formed includes:
  • the electrode block and the first electrode in the light emitting device are formed in the same layer on the base substrate on which the power signal line is formed.
  • the method further includes:
  • a second electrode in the light-emitting device is formed on the base substrate on which the light-emitting layer is formed.
  • forming the electrode block and the first electrode in the light emitting device in the same layer on the base substrate on which the power signal line is formed includes:
  • the photoresist is stripped to obtain the first electrode and the electrode block.
  • FIG. 1 is a schematic plan view of a flexible display device in the related art
  • FIG. 2 is a schematic cross-sectional view of the flexible display device shown in FIG. 1 at AA 'position;
  • FIG. 3 is a schematic cross-sectional view of the flexible display device shown in FIG. 1 at the BB 'position;
  • FIG. 4 is a schematic structural view of a top view of a display substrate provided by an embodiment of the present disclosure
  • FIG. 5 is a schematic cross-sectional view of the display substrate shown in FIG. 4 at the position of CC ';
  • FIG. 6 is a schematic cross-sectional view of the display substrate shown in FIG. 4 at the DD 'position;
  • FIG. 7 is a schematic structural diagram of an electrode block provided by an embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram of another electrode block provided by an embodiment of the present disclosure.
  • FIG. 9 is a flowchart of a method for manufacturing a display substrate provided by an embodiment of the present disclosure.
  • FIG. 10 is a flowchart of another method for manufacturing a display substrate provided by an embodiment of the present disclosure.
  • FIG. 11 is a flowchart of a method for forming an electrode block and a first electrode in a light emitting device on the same layer on a base substrate formed with a power signal line according to an embodiment of the present disclosure.
  • Current flexible display devices generally include a base substrate, a thin film transistor (TFT), a light emitting device, and a thin film encapsulation layer that are sequentially disposed on the base substrate in a direction away from the base substrate.
  • the TFT includes a gate pattern, a gate insulating layer, an active layer, and a source-drain pattern that are stacked.
  • the source-drain pattern includes source and drain electrodes located in the display area and power signal lines located in the non-display area. That is, the power signal line is prepared in the same layer as the source and drain.
  • the light-emitting device includes an anode, a light-emitting layer, and a cathode stacked in a direction away from the base substrate.
  • FIG. 1 is a schematic plan view of a flexible display device in the related art.
  • the flexible display device 10 has a display area M (area within a dotted frame) and a non-display area N (area outside a dotted frame).
  • a plurality of sub-pixels W are arranged in the display area M in an array.
  • the power signal line 101 is located in the non-display area N.
  • the area where the thin film encapsulation layer (not marked in the figure) is the encapsulation area K of the flexible display device.
  • the display area M is located in the package area K, and the edge of the package area K is located in the non-display area N.
  • the power signal line 101 located in the non-display area N extends from the inside of the packaging area K to the outside of the packaging area K to be connected to an external control circuit (not shown in the figure).
  • the external control circuit supplies a power signal to the cathode and / or anode (not shown in the figure) of the light emitting device through the power signal line 101.
  • the power signal line 101 includes a first power signal line 1011 and a second power signal line 1012.
  • the first power signal line 1011 and the second power signal line 1012 are one of the VDD signal line and the VSS signal line, respectively.
  • the power signal line 101 is composed of a first metal layer 101 a, a second metal layer 101 b, and a third metal layer 101 c stacked in a direction away from the base substrate 103.
  • the activity of the second metal layer also called metal activity
  • the conductive material for example, aluminum metal is used as the preparation material of the source and drain pattern .
  • metal materials with high activity are susceptible to oxidation, at present, in order to avoid the oxidation of metal materials with higher activity, which affects their electrical conductivity, metal materials with lower activity are usually used to protect the metal material with higher activity.
  • metal titanium is used to form a protective layer on the upper and lower surfaces of the metal aluminum layer. Therefore, the current source-drain pattern usually has a three-layer structure.
  • FIG. 3 is a schematic cross-sectional view of the flexible display device shown in FIG. 1 at the BB 'position.
  • the slit L formed inside the power signal line 101 becomes an intrusion channel for water and oxygen, causing external water and oxygen to enter the display area of the flexible display device through the slit L, causing erosion to the light emitting device and affecting the light emitting device Luminous performance. Therefore, the reliability of packaging for flexible display devices is currently low.
  • FIG. 4 is a schematic top view of a display substrate provided by an embodiment of the present disclosure.
  • the display substrate 20 has a display area M (area within a dotted frame) and a non-display area N located around the display area M.
  • the display area M is provided with a plurality of sub-pixels W arranged in an array.
  • the display substrate 20 includes a base substrate 201, and a thin film transistor 202, a light emitting device 203, and a packaging structure 204 that are sequentially disposed on the base substrate 201 in a direction away from the base substrate 201.
  • the thin film transistor includes a gate pattern, a gate insulating layer, an active layer, and a source-drain pattern.
  • the thin film transistor is a thin film transistor with a top gate structure or a thin film transistor with a bottom gate structure.
  • FIG. 5 takes a thin film transistor with a top gate structure as an example for description.
  • the thin film transistor 202 includes an active layer 21, a first gate insulating layer 22, a gate pattern 23, a second gate insulating layer 24, and a source-drain pattern 25 stacked in a direction away from the base substrate 201.
  • the source-drain pattern 25 includes a source 251 and a drain 252 located in the display area.
  • a barrier layer, a buffer layer, etc. may be further included between the base substrate 201 and the active layer 21.
  • the thin-film transistor with a bottom gate structure includes a gate pattern, a gate insulating layer, an active layer, and a source-drain pattern stacked in a direction away from the base substrate.
  • the embodiments of the present disclosure will not be repeated here.
  • the light emitting device 203 includes a first electrode 31, a light emitting layer 32 and a second electrode 33 stacked in a direction away from the base substrate 201.
  • the light emitting layer includes a first carrier injection layer, a first carrier transport layer, a light emitting material layer, a second carrier transport layer, and a second carrier injection layer that are stacked.
  • the first carrier is a hole and the second carrier is an electron
  • the first electrode is an anode and the second electrode is a cathode.
  • the first electrode is a cathode and the second electrode is an anode.
  • the first carrier injection layer, the first carrier transport layer, the second carrier transport layer, and the second carrier injection layer all have a full-layer structure, then in the process of preparing the display substrate, The first carrier injection layer, the first carrier transport layer, the second carrier transport layer, and the second carrier injection layer can be prepared in whole layers to simplify the manufacturing process of the light emitting device.
  • the light emitting device may be a quantum dot light emitting diode (Quantum Dot Light Emitting Diodes, QLED) device or an organic light emitting diode (Organic Light-Emitting Diode, OLED) device, which is not limited in the embodiments of the present disclosure.
  • QLED Quantum Dot Light Emitting Diodes
  • OLED Organic Light-Emitting Diode
  • the display substrate 20 includes a base substrate 201, and power signal lines 253 and electrode blocks 26 on the base substrate 201.
  • the electrode block 26 covers at least one side of the power signal line 253.
  • the electrode block covers at least one side of the power signal line, that is, the electrode block covers at least one side of the power signal line.
  • the side of the power signal line is parallel to the extending direction of the power signal line and the angle with the base substrate is not 0.
  • the side of the power signal line and the side of the power signal line may refer to the end surface of the power signal line close to the packaging structure.
  • the base substrate has a packaging area K
  • the display area M is located in the packaging area K where the packaging structure is located
  • the edge of the packaging area K is located in the non-display area N.
  • the orthographic projection of the power signal line 253 on the base substrate extends from the inside of the package area K to the outside of the package area K.
  • the power signal line 253 is usually located in the non-display area N.
  • the orthographic projection of the electrode block 26 on the base substrate coincides with the packaging area K.
  • the packaging area of the base substrate is the packaging area of the display substrate.
  • the packaging area on the base substrate 201 in FIG. 6 is an orthographic area of the packaging structure 204 on the base substrate 201.
  • the power signal line and the source-drain pattern in the thin film transistor are prepared in the same layer, that is, the power signal line and the source-drain pattern in the thin film transistor are in the same layer and the same material.
  • the display substrate 20 includes a first power signal line 253a and a second power signal line 253b (collectively referred to as power signal lines 253) insulated from each other.
  • the first power signal line 253a is electrically connected to the first electrode in the light emitting device
  • the second power signal line 253b is electrically connected to the second electrode in the light emitting device.
  • the electrode block 26 and the first electrode 31 in the light emitting device are prepared in the same layer, that is, the electrode block 26 and the first electrode 31 in the light emitting device are in the same layer and the same material. There is no need to add a new process to prepare the electrode block, and the realization is high.
  • the first power signal line is a VDD signal line
  • the second power signal line is a VSS signal line
  • the first power signal line is a VSS signal line
  • the second power signal line is a VDD signal line
  • the second electrode may be provided in a whole layer, and the first electrode is electrically connected to the first power signal line through the thin film transistor.
  • the thin film transistor is used to control the loading voltage on the first electrode.
  • the width of the power signal line ranges from 50 microns to 2000 microns.
  • the display substrate provided by the embodiment of the present disclosure, because the electrode block covers at least one side of the power signal line, and the orthographic projection of the electrode block on the base substrate and the packaging area have overlapping areas, the wet method is used When the electrode in the light-emitting device is prepared by the etching process, drilling can be avoided on the side of the power supply signal line covered with the electrode block.
  • the packaging structure is provided on the side of the light emitting device away from the base substrate, the side of the power signal line covered with the electrode block will not form a water and oxygen intrusion channel, so the water and oxygen intrusion can be suppressed to a certain extent, thereby improving display Packaging reliability of the substrate.
  • the power signal line includes a first metal layer a, a second metal layer b, and a third metal layer c stacked in a direction away from the base substrate, that is, the power signal line is Three-tier structure.
  • the material of the second metal layer is different from the material of the first metal layer and the third metal layer.
  • the metal activity of the second metal layer is greater than the metal activity of the first metal layer and the third metal layer.
  • the encapsulation structure provided by the embodiments of the present disclosure may be composed of a stacked organic encapsulation layer and an inorganic encapsulation layer.
  • the encapsulation structure 204 may include a first inorganic encapsulation layer 41, an organic encapsulation layer 42 and a second inorganic encapsulation layer 43 that are stacked.
  • the first inorganic encapsulation layer and the second inorganic encapsulation layer can play a role in blocking water and oxygen
  • the organic encapsulation layer can play a role in regional planarization and stress relief.
  • the organic encapsulation layer is usually located in the display area.
  • the orthographic projection of the inorganic encapsulation layer ie, the second inorganic encapsulation layer 43 in FIG. 5 on the side of the organic encapsulation layer away from the base substrate completely covers the organic encapsulation layer In order to prevent external water and oxygen from invading into the light emitting device through the organic encapsulation layer.
  • the first inorganic encapsulation layer 41 and the second inorganic encapsulation layer 43 in the encapsulation structure 204 cover the power signal line 253 located in the encapsulation area. Since the first inorganic encapsulation layer and the second inorganic encapsulation layer are used to encapsulate the display area, and both the first inorganic encapsulation layer and the second inorganic encapsulation layer extend from the display area to the non-display area, when the first inorganic When the encapsulation layer and the second inorganic encapsulation layer can form a seal ring, the display area can be hermetically sealed.
  • the display substrate 20 further includes a flat layer 205 between the thin film transistor 202 and the light emitting device 203.
  • the flat layer can be made of an organic insulating material.
  • forming a flat layer on the side of the thin film transistor away from the base substrate can provide a flat preparation environment for the preparation of the light emitting device, and isolate the interference of the electrical signal in the thin film transistor on the light emitting device to improve the light emitting device Preparation yield.
  • the light emitting device 203 further includes a pixel definition layer 34.
  • the pixel definition layer 34 is located between the first electrode 31 and the light-emitting layer 32.
  • the light emitting device 203 further includes an isolation column 35.
  • the isolation column 35 is located on the side of the pixel definition layer 34 away from the base substrate 201.
  • the pixel definition layer is used to limit the contact area of the light emitting layer and the first electrode, that is, the actual light emitting area of the pixel.
  • the film layer in the light-emitting device is generally prepared by evaporation, and the isolation column is used to support the high-precision metal mask in the process of using the high-precision metal mask (FMM) evaporation film material Function to ensure the reliability of preparation.
  • FMM high-precision metal mask
  • one side of the power signal line is covered with an electrode block; or, both sides of the power signal line are covered with an electrode block.
  • the embodiments of the present disclosure are described by taking an example in which both sides of the power signal line in the display substrate are covered with electrode blocks.
  • the packaging structure can realize the hermetic packaging of the light-emitting device, which further improves the packaging reliability of the display substrate.
  • the structure of the electrode block provided in the embodiments of the present disclosure may have various structures, and the following two structures are used as examples for description.
  • the structure of the first electrode block is shown in FIG. 7.
  • the electrode block 26 covers both sides of the power signal line 253, that is, the electrode block 26 covering both sides of the power signal line 253 is an integrated structure.
  • the electrode block 26 includes a first portion 261 a, a second portion 262 a, a third portion 263 a, a fourth portion 264 a, and a fifth portion 265 a that are sequentially adjacent. Both the first portion 261a and the fifth portion 265a are located on the base substrate 201. The second portion 262a and the fourth portion 264a are attached to one side of the power signal line 253, respectively. The third portion 263a covers the side of the power signal line 253 away from the base substrate 201.
  • the distance D from the end of the first portion 261a away from the power signal line 253 to the power signal line 253 is 2 to 20 microns.
  • the distance D between the end of the fifth portion 265a away from the power signal line 253 and the power signal line 253 is 2 to 20 microns.
  • the electrode block with the integrated structure covers the upper surface and the side surfaces of the power signal line, which can prevent the power signal line from being drilled, thereby preventing the internal slit of the power signal line.
  • the packaging structure After the packaging structure is provided on the side of the light-emitting device away from the base substrate, the packaging structure can realize the hermetic packaging of the light-emitting device, blocking the invasion channel of water and oxygen, thus improving the packaging reliability of the display substrate.
  • the integrated structure of the electrode block can cover both sides of the power signal line at the same time, the preparation process is simple, and the realization is high.
  • the orthographic projection of the electrode block 26 in FIG. 7 on the base substrate 201 completely covers the orthographic projection of the power signal line 253 on the base substrate 201. That is, the electrode block 26 may be connected in parallel with the power signal line 253 to reduce the resistance of the power signal line to some extent.
  • the structure of the second electrode block is shown in FIG. 8.
  • the electrode block 26 covers one side of the power signal line 253, and the two sides of the power signal line 253 are covered with one electrode block 26, that is, both sides of the power signal line 253 They are covered by different electrode blocks 26, respectively.
  • the orthographic projection of the electrode block 26 on the base substrate 201 coincides with the orthographic projection of the power signal line 253 on the base substrate 201.
  • the electrode block 26 has a zigzag shape.
  • the electrode block 26 includes a sixth portion 261b, a seventh portion 262b, and an eighth portion 263b that are sequentially adjacent.
  • the sixth portion 261b overlaps the side of the power signal line 253 away from the base substrate 201.
  • the seventh portion 262b is attached to the target side P of the power signal line 253.
  • the target side is one of the two sides of the power signal line.
  • the eighth portion 263b is located on the base substrate 201.
  • the distance D 'from the end of the sixth portion 261b away from the target side P to the target side P is 2 to 20 microns.
  • the distance range D "of the end of the eighth portion 263b away from the target side P to the target side P is 2 to 20 microns.
  • the packaging structure can realize the hermetic packaging of the light-emitting device, blocking the invasion channel of water and oxygen, thus improving the packaging reliability of the display substrate.
  • the display substrate provided by the embodiment of the present disclosure, because the electrode block covers at least one side of the power signal line, and the orthographic projection of the electrode block on the base substrate and the packaging area have overlapping areas, the wet method is used When the electrode in the light-emitting device is prepared by the etching process, drilling can be avoided on the side of the power signal line covered with the electrode block.
  • the side of the power signal line covered with the electrode block will not form a water and oxygen intrusion channel, so to a certain extent, it can suppress the intrusion of water and oxygen, thereby improving the display substrate Package reliability.
  • the packaging structure can realize the hermetic packaging of the light emitting device, which further improves the packaging reliability of the display substrate.
  • FIG. 9 is a flowchart of a method for manufacturing a display substrate provided by an embodiment of the present disclosure. As shown in FIG. 9, the method may include the following working process:
  • step 301 a base substrate is provided, the base substrate having a package area.
  • step 302 a power signal line is formed on the base substrate, and an orthographic projection of the power signal line on the base substrate extends from within the package area to outside the package area.
  • an electrode block is formed on the base substrate on which the thin film transistor is formed, the electrode block covers at least one side of the power signal line, and the orthographic projection of the electrode block on the base substrate and the packaging area have a coincident area .
  • the above working process further includes: forming a light emitting device on the base substrate on which the electrode block is formed.
  • the method for manufacturing the display substrate uses the electrode block to cover at least one side of the power signal line. Since the orthographic projection of the electrode block on the base substrate and the packaging area have overlapping areas, the When the electrode in the light-emitting device is prepared by the wet etching process, the side of the power signal line covered with the electrode block can be prevented from being drilled. After the packaging structure is provided on the side of the light emitting device away from the base substrate, the side of the power signal line covered with the electrode block will not form a water and oxygen intrusion channel, so the water and oxygen intrusion can be suppressed to a certain extent, thereby improving display Packaging reliability of the substrate.
  • FIG. 10 is a flowchart of another method for manufacturing a display substrate provided by an embodiment of the present disclosure. As shown in FIG. 10, the method may include the following working process:
  • step 401 a base substrate is provided, the base substrate having a package area.
  • the base substrate may be a flexible base substrate.
  • the base substrate can be made of polyimide (Polyimide, PI).
  • the base substrate may be a rigid base substrate.
  • the base substrate may be made of materials such as glass, silicon wafer, quartz, or plastic. The embodiments of the present disclosure do not limit the material of the base substrate.
  • step 402 a thin film transistor and a power signal line are formed on the base substrate.
  • the power signal line and the source-drain pattern in the thin film transistor are prepared in the same layer.
  • the source-drain pattern includes a source and a drain located in the display area, and the power signal line is usually located in the non-display area.
  • the thin film transistor may be a thin film transistor with a top gate structure.
  • the thin film transistor includes a barrier layer, a buffer layer, an active layer, a first gate insulating layer, a gate pattern, a second gate insulating layer, and a source-drain pattern stacked in a direction away from the base substrate.
  • the thin film transistor may be a thin film transistor with a bottom gate structure.
  • the thin film transistor includes a gate pattern, a gate insulating layer, an active layer, and a source-drain pattern stacked in a direction away from the base substrate.
  • a thin-film transistor with a bottom gate structure is taken as an example to introduce a manufacturing process of the thin-film transistor. The manufacturing process is as follows:
  • the gate pattern may be prepared from metal molybdenum (Mo), and then a metal molybdenum layer may be formed on the base substrate by means of deposition, and then the gate pattern is formed through a patterning process.
  • the gate insulating layer can be prepared from silicon dioxide (SiO2), silicon nitride (SiN) or aluminum oxide (Al2O3), for example, silicon dioxide can be formed on the base substrate with the gate pattern formed by deposition The film layer is then patterned to form a gate insulating layer.
  • the active layer can be made of Indium Gallium Zinc Oxide (Indium Gallium Zinc Oxide, IGZO), Monocrystalline Silicon (a-Si), Low Temperature Polycrystalline Silicon (Low Temperature Poly-silicon, LTPS) or Low Temperature Polycrystalline Oxide (Low Temperature Temperature PolyPolycrystalline Oxide) , LTPO) is prepared, for example, an indium gallium zinc oxide layer can be formed on the base substrate on which the gate insulating layer is formed by deposition, and then an active layer is formed through a patterning process.
  • Indium Gallium Zinc Oxide Indium Gallium Zinc Oxide, IGZO
  • Monocrystalline Silicon a-Si
  • Low Temperature Polycrystalline Silicon Low Temperature Poly-silicon
  • LTPO Low Temperature Polycrystalline Oxide
  • an indium gallium zinc oxide layer can be formed on the base substrate on which the gate insulating layer is formed by deposition, and then an active layer is formed through a patterning process.
  • the source-drain pattern can be prepared from metal titanium and metal aluminum, and then a metal titanium layer, a metal aluminum layer, and a metal titanium layer can be sequentially formed on the base substrate on which the active layer is formed by deposition, and then formed through a patterning process Source-drain pattern.
  • the patterning process may include: photoresist coating, exposure, development, etching, and photoresist stripping.
  • the embodiments of the present disclosure do not limit the materials and preparation processes of each layer structure in the TFT.
  • step 403 an electrode block and a first electrode in the light emitting device are formed in the same layer on the base substrate on which the power signal line is formed.
  • the electrode block covers at least one side of the power signal line, and the orthographic projection of the electrode block on the base substrate coincides with the packaging area.
  • the first electrode is located in the display area, and the electrode block is usually located in the non-display area.
  • the electrode block may cover both sides of the power signal line.
  • one electrode block covers one side of the power signal line.
  • FIG. 11 is a flowchart of a method for forming an electrode block and a first electrode in a light-emitting device in the same layer on a base substrate formed with a power signal line according to an embodiment of the present disclosure.
  • the implementation process includes:
  • step 4031 a metal layer is formed on the base substrate on which the thin film transistor is formed.
  • the metal layer may be prepared from indium tin oxide (Indium Tin Oxide, ITO), lithium fluoride, or aluminum.
  • ITO Indium Tin Oxide
  • the metal layer can be formed by depositing ITO.
  • the metal layer is made of lithium fluoride or aluminum, the metal layer can be formed by vapor deposition.
  • the embodiments of the present disclosure do not limit the preparation materials and preparation methods of the metal layer.
  • step 4032 a photoresist is coated on the side of the metal layer away from the base substrate, and the photoresist is sequentially exposed and developed.
  • the composition of the photoresist includes polymethyl methacrylate (PolyMethyl MethAcrylate, PMMA).
  • PMMA PolyMethyl MethAcrylate
  • step 4033 the metal layer is etched using a wet etching process.
  • wet etching is to use an etching solution to chemically react with the metal layer for etching.
  • the etching solution may be hydrochloric acid (HCl).
  • HCl hydrochloric acid
  • a dry etching process may also be used to etch the metal layer.
  • the embodiment of the present disclosure does not limit the etching process of the metal layer.
  • step 4034 the photoresist is stripped to obtain the first electrode and the electrode block.
  • the photoresist can be stripped through a wet stripping process.
  • the wet stripping is to use a specific chemical to dissolve the photoresist.
  • the photoresist can be stripped through a dry stripping process.
  • the dry stripping is to strip the photoresist by ashing components (for example, oxygen in a plasma state). The embodiment of the present disclosure does not limit the process of stripping the photoresist.
  • step 404 a light emitting layer is formed on the base substrate on which the first electrode is formed.
  • the light emitting layer includes a first carrier injection layer, a first carrier transport layer, a light emitting material layer, a second carrier transport layer and a second carrier injection layer.
  • the first carrier and the second carrier are one of electrons and holes, respectively.
  • the first carrier injection layer, the first carrier transport layer, the second carrier transport layer, and the second carrier injection layer can all be prepared in one layer to simplify the manufacturing process of the light emitting device.
  • the hole injection layer may be prepared from a thermoplastic polymer PEDOT: PSS (3,4-ethylenedioxythiophene / polystyrene sulfonate).
  • the hole transport layer can be prepared from 1,2,4,5-Tetrakis (trifluoromethyl) Benzene (1,2,4,5-Tetrakis (trifluoromethyl) Benzene (TFB), can be used inkjet printing process respectively
  • the hole injection layer and the hole transport layer are prepared.
  • the embodiments of the present disclosure do not limit the preparation materials and preparation methods of the hole injection layer and the hole transport layer.
  • the light emitting material layer may be a quantum dot material layer, and then the flexible light emitting device is a QLED device.
  • the light-emitting material layer may also be an organic light-emitting material layer, and the flexible light-emitting device is an OLED device.
  • the luminescent material layer can be formed by printing. The embodiments of the present disclosure do not limit the preparation materials and preparation methods of the luminescent material layer.
  • the electron transport layer may be prepared from zinc oxide, and the electron transport layer may be formed by printing or sputtering.
  • the electron injection layer can be formed by printing or sputtering.
  • the embodiments of the present disclosure do not limit the preparation materials and preparation methods of the electron transport layer and the electron injection layer.
  • step 405 the second electrode in the light emitting device is formed on the base substrate on which the light emitting layer is formed.
  • the second electrode may be prepared by ITO, lithium fluoride, or aluminum.
  • a metal layer may be formed by depositing ITO.
  • the second electrode is made of lithium fluoride or aluminum, the metal layer can be formed by vapor deposition.
  • the embodiments of the present disclosure do not limit the preparation materials and preparation methods of the second electrode.
  • step 406 a package structure is formed on the base substrate on which the light emitting device is formed.
  • the orthographic projection of the packaging structure on the base substrate coincides with the packaging area of the base substrate, that is, the area where the packaging structure is located is the packaging area of the display substrate.
  • the electrode block located in the package area It can ensure that there is no drilling in the covered area, and can block the water and oxygen invasion channel inside the power signal line. Furthermore, after the packaging structure is formed, the display area can be isolated from the outside world to ensure packaging reliability.
  • the encapsulation structure provided by the embodiments of the present disclosure may be composed of a stacked organic encapsulation layer and an inorganic encapsulation layer.
  • the organic encapsulation layer can be prepared from PMMA material, and the organic encapsulation layer can be prepared by an inkjet printing process.
  • the inorganic encapsulation layer may be prepared from silicon oxide, silicon nitride, silicon oxynitride, or aluminum oxide, and may be prepared by a chemical vapor deposition (Chemical Vapor Deposition, CVD) or atomic layer deposition (Atomic Layer Deposition, ALD) process.
  • the organic encapsulation layer is usually located in the display area.
  • the orthographic projection of the inorganic encapsulation layer on the organic encapsulation layer completely covers the organic encapsulation layer, and both the first inorganic encapsulation layer and the second inorganic encapsulation layer extend from the display area to the non-display area.
  • the display area can be hermetically sealed.
  • the method for manufacturing the display substrate uses the electrode block to cover at least one side of the power signal line. Since the orthographic projection of the electrode block on the base substrate and the packaging area have overlapping areas, the When the electrode in the light-emitting device is prepared by the wet etching process, the side of the power signal line covered with the electrode block can be prevented from being drilled. After the packaging structure is provided on the side of the light emitting device away from the base substrate, the invasion of water and oxygen can be suppressed to a certain extent, and the packaging reliability of the display substrate is improved.
  • the packaging structure can realize the hermetic packaging of the light emitting device, which further improves the packaging reliability of the display substrate.
  • An embodiment of the present disclosure also provides a display device including the display substrate as shown in any one of FIGS. 4 to 6.
  • the display device may be any product or component with a display function such as electronic paper, mobile phone, tablet computer, television, display, notebook computer, digital photo frame, and navigator.
  • a display function such as electronic paper, mobile phone, tablet computer, television, display, notebook computer, digital photo frame, and navigator.

Abstract

公开了一种显示基板及其制造方法、显示装置，属于显示技术领域。显示基板包括：衬底基板，以及位于衬底基板上的电源信号线和电极块，该电极块包覆电源信号线的至少一侧。该衬底基板具有封装区域，电源信号线在衬底基板上的正投影从封装区域内延伸至封装区域外，且电极块在衬底基板上的正投影与封装区域存在重合区域。本公开通过在电源信号线位于封装区域内的一侧包覆电极块，可以避免电源信号线中包覆有电极块的一侧发生钻刻，提高了显示基板的封装可靠性。摘要附图为图6。

Description

显示基板及其制造方法、显示装置
本公开要求于2018年10月30日提交的申请号为201811275484.5、发明名称为“显示基板及其制造方法、显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及显示技术领域，特别涉及一种显示基板及其制造方法、显示装置。
背景技术
目前，柔性显示器件通常采用薄膜封装(Thin Film Encapsulation，TFE)的方式进行封装。薄膜封装的原理是利用致密的薄膜封装层阻隔水和氧气(以下简称为水氧)，以避免柔性显示器件内部的金属材料和发光材料等敏感材料受到水氧的侵蚀。
发明内容
本公开提供了一种显示基板及其制造方法、显示装置。所述技术方案如下：
一方面，提供了一种显示基板，所述显示基板包括：
衬底基板，以及位于所述衬底基板上的电源信号线和电极块，所述电极块包覆所述电源信号线的至少一侧；
所述衬底基板具有封装区域，所述电源信号线在所述衬底基板上的正投影从所述封装区域内延伸至所述封装区域外，且所述电极块在所述衬底基板上的正投影与所述封装区域存在重合区域。
可选地，所述电极块包覆所述电源信号线的两侧。
可选地，所述电极块包括依次邻接的第一部、第二部、第三部、第四部和第五部，所述第一部和所述第五部均位于所述衬底基板上，所述第二部和所述第四部分别贴附于所述电源信号线的一侧，所述第三部覆盖所述电源信号线远离所述衬底基板的一面。
可选地，所述第一部远离所述电源信号线的一端到所述电源信号线的距离 范围为2至20微米，所述第五部远离所述电源信号线的一端到所述电源信号线的距离范围为2至20微米。
可选地，所述电极块在所述衬底基板上的正投影完全覆盖所述电源信号线在所述衬底基板上的正投影。
可选地，所述电极块包覆所述电源信号线的一侧，所述电源信号线的两侧分别包覆有一个所述电极块。
可选地，所述电极块呈Z字型，所述电极块包括依次邻接的第六部、第七部和第八部，所述第六部搭接在所述电源信号线远离所述衬底基板的一面上，所述第七部贴附于所述电源信号线的目标侧，所述第八部位于所述衬底基板上，所述目标侧为所述电源信号线的两侧中的一侧。
可选地，所述第六部远离所述目标侧的一端到所述目标侧的距离范围为2至20微米，所述第八部远离所述目标侧的一端到所述目标侧的距离范围为2至20微米。
可选地，所述显示基板还包括位于所述衬底基板上的薄膜晶体管，所述电源信号线与所述薄膜晶体管中的源漏极图案同层同材料。
可选地，所述显示基板还包括位于所述薄膜晶体管远离所述衬底基板的一侧的发光器件，所述发光器件包括沿远离所述衬底基板的方向层叠设置的第一电极、发光层和第二电极，所述电极块与所述第一电极同层同材料。
可选地，所述显示基板中包括相互绝缘的第一电源信号线和第二电源信号线；
所述第一电源信号线与所述第一电极连接，所述第二电源信号线与所述第二电极连接。
可选地，所述电源信号线包括沿远离所述衬底基板的方向层叠设置的第一金属层、第二金属层和第三金属层，所述第二金属层的材质与所述第一金属层以及所述第三金属层的材质不同。
可选地，所述第二金属层的金属活泼性大于所述第一金属层和所述第三金属层的金属活泼性。
可选地，所述薄膜晶体管为顶栅结构的薄膜晶体管和底栅结构的薄膜晶体管中的一种。
可选地，所述显示基板还包括位于所述衬底基板上的薄膜晶体管，所述电源信号线与所述薄膜晶体管中的源漏极图案同层同材料；
所述显示基板还包括位于所述薄膜晶体管远离所述衬底基板的一侧的发光器件，所述发光器件包括沿远离所述衬底基板的方向层叠设置的第一电极、发光层和第二电极，所述电极块与所述第一电极同层同材料；
所述电源信号线包括沿远离所述衬底基板的方向层叠设置的第一金属层、第二金属层和第三金属层，所述第二金属层的金属活泼性大于所述第一金属层和所述第三金属层的金属活泼性。
另一方面，提供了一种显示装置，包括：如一方面任一所述的显示基板。
又一方面，提供了一种显示基板的制造方法，所述方法包括：
提供衬底基板，所述衬底基板具有封装区域；
在所述衬底基板上形成电源信号线，所述电源信号线在所述衬底基板上的正投影从所述封装区域内延伸至所述封装区域外；
在形成有所述电源信号线的衬底基板上形成电极块，所述电极块包覆所述电源信号线的至少一侧，且所述电极块在所述衬底基板上的正投影与所述封装区域存在重合区域。
可选地，所述在形成有所述电源信号线的衬底基板上形成电极块，包括：
在形成有所述电源信号线的衬底基板上同层形成所述电极块以及发光器件中的第一电极。
可选地，在形成有所述电源信号线的衬底基板上同层形成所述电极块以及发光器件中的第一电极之后，所述方法还包括：
在形成有所述第一电极的衬底基板上形成发光层；
在形成有所述发光层的衬底基板上形成所述发光器件中的第二电极。
可选地，所述在形成有所述电源信号线的衬底基板上同层形成所述电极块以及发光器件中的第一电极，包括：
在形成有所述电源信号线的衬底基板上形成金属层；
在所述金属层远离所述衬底基板的一侧涂覆光刻胶，并对所述光刻胶依次进行曝光处理和显影处理；
采用湿法刻蚀的工艺对所述金属层进行刻蚀；
剥离所述光刻胶，得到所述第一电极和所述电极块。
附图说明
图1是相关技术中的一种柔性显示器件的俯视结构示意图；
图2是图1所示的柔性显示器件在AA’位置的截面示意图；
图3是图1所示的柔性显示器件在BB’位置的截面示意图；
图4是本公开实施例提供的一种显示基板的俯视结构示意图；
图5是图4所示的显示基板在CC’位置的截面示意图；
图6是图4所示的显示基板在DD’位置的截面示意图；
图7是本公开实施例提供的一种电极块的结构示意图；
图8是本公开实施例提供的另一种电极块的结构示意图；
图9是本公开实施例提供的一种显示基板的制造方法流程图；
图10是本公开实施例提供的另一种显示基板的制造方法流程图；
图11是本公开实施例提供的一种在形成有电源信号线的衬底基板上同层形成电极块以及发光器件中的第一电极的方法流程图。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚，下面将结合附图对本公开实施方式作进一步地详细描述。
目前的柔性显示器件通常包括：衬底基板，以及沿远离衬底基板的方向依次设置在该衬底基板上的薄膜晶体管(Thin Film Transistor，TFT)、发光器件和薄膜封装层。其中，TFT包括层叠设置的栅极图案、栅绝缘层、有源层和源漏极图案。源漏极图案包括位于显示区域内的源极和漏极，以及位于非显示区域内的电源信号线。也即是，电源信号线与源极、漏极同层制备。发光器件包括沿远离衬底基板的方向层叠设置的阳极、发光层和阴极。
图1是相关技术中的一种柔性显示器件的俯视结构示意图。如图1所示，柔性显示器件10具有显示区域M(虚线框内的区域)和非显示区域N(虚线框外的区域)。多个子像素W阵列排布在显示区域M内。电源信号线101位于非显示区域N内。其中，薄膜封装层(图中未标出)所在区域为柔性显示器件的封装区K。显示区域M位于封装区K内，且封装区K的边缘位于非显示区域N内。位于非显示区域N内的电源信号线101从封装区K内延伸至封装区K外，以与外部控制电路(图中未画出)连接。外部控制电路通过电源信号线101向发光器件中的阴极和/或阳极(图中未画出)提供电源信号。参见图1，电源信号线101包括第一电源信号线1011和第二电源信号线1012。第一电源信号线1011和第二电源信号线1012分别为VDD信号线和VSS信号线中的一个。
图2是图1所示的柔性显示器件在AA’位置的截面示意图。如图2所示，电源信号线101由沿远离衬底基板103的方向层叠设置的第一金属层101a、第二金属层101b和第三金属层101c构成。其中，第二金属层的活泼性(也称金属活泼性)大于第一金属层和第三金属层的活泼性。在制备源漏极图案时，为了保证源极、漏极以及电源信号线的良好导电性，一般采用具有较高活泼性的金属材料作为导电材料，例如采用金属铝作为源漏极图案的制备材料。但是，由于活泼性高的金属材料易发生氧化，因此目前为了避免活泼性较高的金属材料氧化后影响其导电性能，通常采用活泼性较低的金属材料保护该活泼性较高的金属材料。例如，在金属铝层的上下表面分别采用金属钛形成保护层。因此目前的源漏极图案通常具有三层结构。
在制备如图1所示的柔性显示器件的过程中，当采用湿法刻蚀工艺制备发光器件中的阳极(图中未画出)时，由于电源信号线中的第二金属层的活泼性大于第一金属层和第三金属层的活泼性，因此刻蚀液对第二金属层的刻蚀速度大于对第一金属层和第三金属层的刻蚀速度，会导致电源信号线发生钻刻。其中，钻刻指光刻掩膜之下的侧向刻蚀。如图2所示，发生钻刻的电源信号线101内部会形成狭缝L。在完成发光器件的制备后进行薄膜封装时，薄膜封装层102无法完全填充电源信号线101内部形成的狭缝L。图3是图1所示的柔性显示器件在BB’位置的截面示意图。如图3所示，电源信号线101内部形成的狭缝L成为水氧入侵通道，导致外部的水氧能够通过狭缝L进入柔性显示器件的显示区域，对发光器件造成侵蚀，影响发光器件的发光性能。因此目前对柔性显示器件的封装可靠性较低。
图4是本公开实施例提供的一种显示基板的俯视结构示意图。如图4所示，显示基板20具有显示区域M(虚线框内的区域)以及位于显示区域M周围的非显示区域N。显示区域M内设置有阵列排布的多个子像素W。
图5是图4所示的显示基板在CC’位置的截面示意图。如图5所示，显示基板20包括：衬底基板201，以及沿远离衬底基板201的方向依次设置在衬底基板201上的薄膜晶体管202、发光器件203和封装结构204。其中，薄膜晶体管包括栅极图案、栅绝缘层、有源层和源漏极图案。
可选地，薄膜晶体管为顶栅结构的薄膜晶体管或底栅结构的薄膜晶体管。
示例地，图5中以顶栅结构的薄膜晶体管为例进行说明。参见图5，薄膜晶 体管202包括沿远离衬底基板201的方向层叠设置的有源层21、第一栅绝缘层22、栅极图案23、第二栅绝缘层24和源漏极图案25。源漏极图案25包括位于显示区域内的源极251和漏极252。可选地，衬底基板201和有源层21之间还可以包括层叠设置的阻挡层和缓冲层等(图中未画出)。
可选地，底栅结构的薄膜晶体管包括沿远离衬底基板的方向层叠设置的栅极图案、栅绝缘层、有源层和源漏极图案，本公开实施例在此不做赘述。
可选地，请继续参见图5，发光器件203包括沿远离衬底基板201的方向层叠设置的第一电极31、发光层32和第二电极33。其中，发光层包括层叠设置的第一载流子注入层、第一载流子传输层、发光材料层、第二载流子传输层和第二载流子注入层。当第一载流子为空穴，第二载流子为电子时，第一电极为阳极，第二电极为阴极。当第一载流子为电子，第二载流子为空穴时，第一电极为阴极，第二电极为阳极。可选地，第一载流子注入层、第一载流子传输层、第二载流子传输层和第二载流子注入层均为整层结构，则在制备显示基板的过程中，可以整层制备第一载流子注入层、第一载流子传输层、第二载流子传输层和第二载流子注入层，以简化发光器件的制备工艺。
可选地，发光器件可以是量子点发光二极管(Quantum Dot Light Emitting Diodes，QLED)器件或有机发光二极管(Organic Light-Emitting Diode，OLED)器件，本公开实施例对此不做限定。
图6是图4所示的显示基板在DD’位置的截面示意图。如图6所示，该显示基板20包括：衬底基板201，以及位于衬底基板201上的电源信号线253和电极块26。电极块26包覆电源信号线253的至少一侧。电极块包覆电源信号线的至少一侧，即电极块包覆电源信号线的至少一个侧面。电源信号线的侧面平行于电源信号线的延伸方向且与衬底基板的夹角不为0。本公开实施例中，电源信号线的侧面以及电源信号线的一侧可以指电源信号线靠近封装结构的端面。
请继续参见图4，衬底基板具有封装区域K，显示区域M位于封装结构所在的封装区域K内，且封装区域K的边缘位于非显示区域N内。电源信号线253在衬底基板上的正投影从封装区域K内延伸至封装区域K外，电源信号线253通常位于非显示区域N内。电极块26在衬底基板上的正投影与封装区域K存在重合区域。衬底基板的封装区域即显示基板的封装区域。图6中衬底基板201上的封装区域为封装结构204在衬底基板201上的正投影区域。
可选地，电源信号线与薄膜晶体管中的源漏极图案同层制备得到，即电源 信号线与薄膜晶体管中的源漏极图案同层同材料。
可选地，请继续参见图4，显示基板20包括相互绝缘的第一电源信号线253a和第二电源信号线253b(统称为电源信号线253)。第一电源信号线253a与发光器件中的第一电极电连接，第二电源信号线253b与发光器件中的第二电极电连接。
可选地，电极块26与发光器件中的第一电极31同层制备得到，即电极块26与发光器件中的第一电极31同层同材料。无需增加新的工艺流程制备电极块，可实现性高。
可选地，当第一电极为阳极，第二电极为阴极时，第一电源信号线为VDD信号线，第二电源信号线为VSS信号线；当第一电极为阴极，第二电极为阳极时，第一电源信号线为VSS信号线，第二电源信号线为VDD信号线。其中，第二电极可以整层设置，第一电极通过薄膜晶体管与第一电源信号线电连接。薄膜晶体管用于控制第一电极上的加载电压。
可选地，电源信号线的宽度范围为50微米至2000微米。
综上所述，本公开实施例提供的显示基板，由于电极块包覆电源信号线的至少一侧，且电极块在衬底基板上的正投影与封装区域存在重合区域，因此在采用湿法刻蚀工艺制备发光器件中的电极时，可以避免电源信号线包覆有电极块的一侧发生钻刻。在发光器件远离衬底基板的一侧设置封装结构后，电源信号线包覆有电极块的一侧不会形成水氧入侵通道，因此在一定程度上可以抑制水氧的入侵，进而提高了显示基板的封装可靠性。
可选地，请继续参见图6，电源信号线包括沿远离衬底基板的方向层叠设置的第一金属层a、第二金属层b和第三金属层c，也即是，电源信号线为三层结构。第二金属层的材质与第一金属层以及第三金属层的材质不同。可选地，第二金属层的金属活泼性大于第一金属层和第三金属层的金属活泼性。
可选地，本公开实施例提供的封装结构可以由层叠设置的有机封装层和无机封装层构成。示例地，如图5所示，封装结构204可以包括层叠设置的第一无机封装层41、有机封装层42和第二无机封装层43。
需要说明的是，第一无机封装层和第二无机封装层可以起到阻隔水氧的作用，有机封装层可以起到区域平坦化和应力释放的作用。有机封装层通常位于显示区域内，位于有机封装层远离衬底基板的一侧的无机封装层(即图5中的第二无机封装层43)在有机封装层上的正投影完全覆盖有机封装层，以防止外 部水氧通过有机封装层入侵至发光器件内部。
示例地，参见图6，封装结构204中的第一无机封装层41和第二无机封装层43覆盖位于封装区域内的电源信号线253。由于第一无机封装层和第二无机封装层用于封装显示区域，且第一无机封装层和第二无机封装层均从显示区域延伸至非显示区域，当位于非显示区域内的第一无机封装层和第二无机封装层能够形成密封圈时，即可实现对显示区域的密闭封装。
可选地，如图5所示，显示基板20还包括位于薄膜晶体管202和发光器件203之间的平坦层205。其中，平坦层可以由有机绝缘材料制备得到。
需要说明的是，在薄膜晶体管远离衬底基板的一侧形成平坦层，可以为发光器件的制备提供平坦的制备环境，并隔绝薄膜晶体管内的电信号对发光器件的干扰，以提高发光器件的制备良率。
可选地，请继续参见图5，发光器件203还包括像素定义层34。像素定义层34位于第一电极31和发光层32之间。
可选地，请继续参见图5，发光器件203还包括隔离柱35。隔离柱35位于像素定义层34远离衬底基板201的一侧。
需要说明的是，像素定义层用于限制发光层和第一电极的接触区域，即限制像素的实际发光区域。发光器件中的膜层一般采用蒸镀的方式制备，隔离柱用于在使用高精度金属掩膜板(Fine Metal Mask，FMM)蒸镀膜层材料的过程中对高精度金属掩膜板起到支撑作用，以保证制备可靠性。
可选地，在本公开实施例中，电源信号线的一侧包覆有电极块；或者，电源信号线的两侧均包覆有电极块。本公开实施例以显示基板中电源信号线的两侧均包覆有电极块为例进行说明。
需要说明的是，当电源信号线的两侧均包覆有电极块，电源信号线的内部不会出现因钻刻导致的狭缝，即电源信号线的内部不存在水氧入侵通道，在发光器件远离衬底基板的一侧设置封装结构后，封装结构可以实现对发光器件的密闭封装，进一步提高了显示基板的封装可靠性。
可选地，本公开实施例提供的电极块的结构可以有多种，在此以以下两种结构为例进行说明。
第一种电极块的结构如图7所示，电极块26包覆电源信号线253的两侧，即包覆电源信号线253两侧的电极块26为一体结构。
示例地，参见图7，电极块26包括依次邻接的第一部261a、第二部262a、 第三部263a、第四部264a和第五部265a。第一部261a和第五部265a均位于衬底基板201上。第二部262a和第四部264a分别贴附于电源信号线253的一侧。第三部263a覆盖电源信号线253远离衬底基板201的一面。
可选地，第一部261a远离电源信号线253的一端到电源信号线253的距离范围D为2至20微米。第五部265a远离电源信号线253的一端到电源信号线253的距离范围D为2至20微米。
需要说明的是，一体结构的电极块包覆电源信号线的上表面和侧面，可以避免电源信号线发生钻刻，进而避免电源信号线内部产生狭缝。在发光器件远离衬底基板的一侧设置封装结构后，封装结构可以实现对发光器件的密闭封装，阻断了水氧的入侵通道，因此提高了显示基板的封装可靠性。另外，一体结构的电极块能够同时覆盖电源信号线的两侧，制备工艺简单，可实现性高。
可选地，图7中的电极块26在衬底基板201上的正投影完全覆盖电源信号线253在衬底基板201上的正投影。也即是，电极块26可以与电源信号线253并联，以在一定程度上减小电源信号线的电阻。
第二种电极块的结构如图8所示，电极块26包覆电源信号线253的一侧，电源信号线253的两侧分别包覆有一个电极块26，即电源信号线253的两侧分别由不同的电极块26包覆。电极块26在衬底基板201上的正投影与电源信号线253在衬底基板201上的正投影部分重合。
示例地，参见图8，电极块26呈Z字型。电极块26包括依次邻接的第六部261b、第七部262b和第八部263b。第六部261b搭接在电源信号线253远离衬底基板201的一面上。第七部262b贴附于电源信号线253的目标侧P贴合。该目标侧为电源信号线的两侧中的一侧。第八部263b位于衬底基板201上。
可选地，第六部261b远离目标侧P的一端到目标侧P的距离范围D’为2至20微米。第八部263b远离目标侧P的一端到目标侧P的距离范围D”为2至20微米。
需要说明的是，由于电极块包覆电源信号线的侧面，可以避免电源信号线发生钻刻，避免电源信号线内部产生狭缝。在发光器件远离衬底基板的一侧设置封装结构后，封装结构可以实现对发光器件的密闭封装，阻断了水氧的入侵通道，因此提高了显示基板的封装可靠性。
综上所述，本公开实施例提供的显示基板，由于电极块包覆电源信号线的至少一侧，且电极块在衬底基板上的正投影与封装区域存在重合区域，因此在 采用湿法刻蚀工艺制备发光器件中的电极时，可以避免电源信号线中包覆有电极块的一侧发生钻刻。在发光器件远离衬底基板的一侧设置封装结构后，电源信号线包覆有电极块的侧面不会形成水氧入侵通道，因此在一定程度上可以抑制水氧的入侵，进而提高了显示基板的封装可靠性。当电源信号线的两侧均包覆有电极块，电源信号线的内部不会出现狭缝，即电源信号线的内部不存在水氧入侵通道，在发光器件远离衬底基板的一侧设置封装结构后，封装结构可以实现对发光器件的密闭封装，进一步提高了显示基板的封装可靠性。
图9是本公开实施例提供的一种显示基板的制造方法流程图。如图9所示，该方法可以包括以下工作过程：
在步骤301中，提供衬底基板，该衬底基板具有封装区域。
在步骤302中，在衬底基板上形成电源信号线，该电源信号线在衬底基板上的正投影从封装区域内延伸至封装区域外。
在步骤303中，在形成有薄膜晶体管的衬底基板上形成电极块，该电极块包覆电源信号线的至少一侧，且该电极块在衬底基板上的正投影与封装区域存在重合区域。
在步骤303之后，上述工作过程还包括：在形成有电极块的衬底基板上形成发光器件。
综上所述，本公开实施例提供的显示基板的制造方法，采用电极块包覆电源信号线的至少一侧，由于电极块在衬底基板上的正投影与封装区域存在重合区域，因此在采用湿法刻蚀工艺制备发光器件中的电极时，可以避免电源信号线中包覆有电极块的一侧发生钻刻。在发光器件远离衬底基板的一侧设置封装结构后，电源信号线包覆有电极块的一侧不会形成水氧入侵通道，因此在一定程度上可以抑制水氧的入侵，进而提高了显示基板的封装可靠性。
图10是本公开实施例提供的另一种显示基板的制造方法流程图。如图10所示，该方法可以包括以下工作过程：
在步骤401中，提供衬底基板，该衬底基板具有封装区域。
可选地，衬底基板可以为柔性衬底基板。例如衬底基板可以由聚酰亚胺(Polyimide，PI)制备得到。或者，衬底基板可以为刚性衬底基板。例如衬底基板可以由玻璃、硅片、石英或塑料等材料制成，本公开实施例对衬底基板的 材料不做限定。
在步骤402中，在衬底基板上形成薄膜晶体管和电源信号线。
可选地，电源信号线与薄膜晶体管中的源漏极图案同层制备。源漏极图案包括位于显示区域内的源极和漏极，电源信号线通常位于非显示区域内。
可选地，薄膜晶体管可以是顶栅结构的薄膜晶体管。该薄膜晶体管包括沿远离衬底基板的方向层叠设置的阻挡层、缓冲层、有源层、第一栅绝缘层、栅极图案、第二栅绝缘层和源漏极图案。或者，薄膜晶体管也可以是底栅结构的薄膜晶体管。该薄膜晶体管包括沿远离衬底基板的方向层叠设置的栅极图案、栅绝缘层、有源层和源漏极图案。本公开实施例以底栅结构的薄膜晶体管为例来介绍薄膜晶体管的制备过程，其制备过程如下：
可选地，栅极图案可以由金属钼(Mo)制备得到，则可以采用沉积的方式在衬底基板上形成金属钼层，再通过构图工艺形成栅极图案。栅绝缘层可以由二氧化硅(SiO2)、氮化硅(SiN)或三氧化二铝(Al2O3)制备得到，例如可以采用沉积的方式在形成有栅极图案的衬底基板上形成二氧化硅膜层，再通过构图工艺形成栅绝缘层。有源层可以由铟镓锌氧化物(Indium Gallium Zinc Oxide，IGZO)、单晶硅(a-Si)、低温多晶硅(Low Temperature Poly-silicon，LTPS)或低温多晶氧化物(Low Temperature Polycrystalline Oxide，LTPO)制备得到，例如可以采用沉积的方式在形成有栅绝缘层的衬底基板上形成铟镓锌氧化物层，再通过构图工艺形成有源层。源漏极图案可以由金属钛和金属铝制备得到，则可以采用沉积的方式在形成有有源层的衬底基板上依次形成金属钛层、金属铝层和金属钛层，再通过构图工艺形成源漏极图案。其中，构图工艺可以包括：光刻胶涂覆、曝光、显影、刻蚀和光刻胶剥离。本公开实施例对TFT中各层级结构的材质和制备工艺均不做限定。
在步骤403中，在形成有电源信号线的衬底基板上同层形成电极块以及发光器件中的第一电极。
其中，电极块包覆电源信号线的至少一侧，且该电极块在衬底基板上的正投影与封装区域存在重合区域。第一电极位于显示区域内，电极块通常位于非显示区域内。示例地，参见图7，电极块可以包覆电源信号线的两侧。又示例地，参见图8，一个电极块包覆电源信号线的一侧。
可选地，图11是本公开实施例提供的一种在形成有电源信号线的衬底基板上同层形成电极块以及发光器件中的第一电极的方法流程图。如图11所示，该 实现过程包括：
在步骤4031中，在形成有薄膜晶体管的衬底基板上形成金属层。
可选地，金属层可以由氧化铟锡(Indium Tin Oxide，ITO)、氟化锂或铝制备得到。当金属层由ITO制备得到时，可采用沉积ITO的方式形成金属层。当金属层由氟化锂或铝制备得到时，可采用蒸镀的方式形成金属层。本公开实施例对金属层的制备材料和制备方式均不做限定。
在步骤4032中，在金属层远离衬底基板的一侧涂覆光刻胶，并对光刻胶依次进行曝光处理和显影处理。
可选地，光刻胶的组成成分包括聚甲基丙烯酸甲酯(PolyMethyl MethAcrylate，PMMA)，本公开实施例对光刻胶的组成成分不做限定。
在步骤4033中，采用湿法刻蚀的工艺对金属层进行刻蚀。
可选地，湿法刻蚀是利用刻蚀液与金属层发生化学反应进行刻蚀。刻蚀液可为盐酸(HCl)，本公开实施例对刻蚀液的成分不做限定。
可替代地，也可以采用干刻工艺对金属层进行刻蚀，本公开实施例对金属层的刻蚀工艺不做限定。
在步骤4034中，剥离光刻胶，得到第一电极和电极块。
可选地，可以通过湿法剥离工艺剥离光刻胶。其中，湿法剥离是通过使用特定的化学药品，使光刻胶溶解。或者，也可以通过干法剥离工艺剥离光刻胶。其中，干法剥离是通过灰化成分(例如，处于等离子状态的氧气)剥离光刻胶。本公开实施例对剥离光刻胶的工艺不做限定。
在步骤404中，在形成有第一电极的衬底基板上形成发光层。
其中，发光层包括第一载流子注入层、第一载流子传输层、发光材料层、第二载流子传输层和第二载流子注入层。第一载流子和第二载流子分别为电子和空穴中的一种。第一载流子注入层、第一载流子传输层、第二载流子传输层和第二载流子注入层均可整层制备得到，以简化发光器件的制备工艺。
可选地，空穴注入层可以由热塑聚合物PEDOT:PSS(3，4-乙烯二氧噻吩/聚苯乙烯磺酸盐)制备得到。空穴传输层可以由1，2，4，5-四(三氟甲基)苯(1,2,4,5-Tetrakis(trifluoromethyl)Benzene，TFB)制备得到，可采用喷墨打印的工艺分别制备得到空穴注入层和空穴传输层。本公开实施例对空穴注入层和空穴传输层的制备材料和制备方式均不做限定。
可选地，发光材料层可以为量子点材料层，则该柔性发光器件为QLED器 件。或者，发光材料层也可以为有机发光材料层，则该柔性发光器件为OLED器件。可采用打印的方式形成发光材料层。本公开实施例对发光材料层的制备材料和制备方式均不做限定。
可选地，电子传输层可以由氧化锌制备得到，可采用打印或溅射的方式形成电子传输层。电子注入层可采用打印或溅射的方式形成。本公开实施例对电子传输层和电子注入层的制备材料和制备方式均不做限定。
在步骤405中，在形成有发光层的衬底基板上形成发光器件中的第二电极。
可选地，第二电极可以ITO、氟化锂或铝制备得到，当第二电极由ITO制备得到时，可采用沉积ITO的方式形成金属层。当第二电极由氟化锂或铝制备得到时，可采用蒸镀的方式形成金属层。本公开实施例对第二电极的制备材料和制备方式均不做限定。当第一载流子为空穴，第二载流子为电子时，第一电极为阳极，第二电极为阴极。当第一载流子为电子，第二载流子为空穴时，第一电极为阴极，第二电极为阳极。
在步骤406中，在形成有发光器件的衬底基板上形成封装结构。
该封装结构在衬底基板上的正投影与衬底基板的封装区域重合，即封装结构所在区域为显示基板的封装区域。
本公开实施例中，由于电极块在衬底基板上的正投影与封装区域存在重合区域，因此即使电源信号线未包覆有电极块的部分区域发生钻刻，位于封装区域内的电极块也能保证包覆的区域不发生钻刻，可以阻断电源信号线内部的水氧入侵通道。进而在形成封装结构后，可以使显示区域与外界隔离，保证封装可靠性。
可选地，本公开实施例提供的封装结构可以由层叠设置的有机封装层和无机封装层构成。有机封装层可以由PMMA材料制备得到，可采用喷墨打印的工艺制备得到有机封装层。无机封装层可以由氧化硅、氮化硅、氮氧化硅或氧化铝制备得到，可以采用化学气相沉积(Chemical Vapor Deposition，CVD)或原子层沉积(Atomic Layer Deposition，ALD)的工艺制备得到。有机封装层通常位于显示区域内，无机封装层在有机封装层上的正投影完全覆盖有机封装层，且第一无机封装层和第二无机封装层均从显示区域延伸至非显示区域，当位于非显示区域内的第一无机封装层和第二无机封装层能够形成密封圈时，即可实现对显示区域的密闭封装。
需要说明的是，本公开实施例提供的显示基板的制造方法的步骤的先后顺 序可以进行适当调整，步骤也可以根据情况进行相应增减，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化的方法，都应涵盖在本公开的保护范围之内，因此不再赘述。
综上所述，本公开实施例提供的显示基板的制造方法，采用电极块包覆电源信号线的至少一侧，由于电极块在衬底基板上的正投影与封装区域存在重合区域，因此在采用湿法刻蚀工艺制备发光器件中的电极时，可以避免电源信号线中包覆有电极块的一侧发生钻刻。在发光器件远离衬底基板的一侧设置封装结构后，在一定程度上可以抑制水氧的入侵，提高了显示基板的封装可靠性。当电源信号线的两侧均包覆有电极块，电源信号线的内部不会出现狭缝，即电源信号线的内部不存在水氧入侵通道，在发光器件远离衬底基板的一侧设置封装结构后，封装结构可以实现对发光器件的密闭封装，进一步提高了显示基板的封装可靠性。
关于上述方法实施例中的结构，其中显示基板的结构以及材质已经在装置侧实施例中进行了详细描述，此处将不做详细阐述说明。
本公开实施例还提供了一种显示装置，该显示装置包括如图4至图6任一所示的显示基板。
可选地，本公开实施例提供的显示装置可以为电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框和导航仪等任何具有显示功能的产品或部件。
本申请中术语“和/或”，仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。另外，本文中字符“/”，一般表示前后关联对象是一种“或”的关系。
以上所述仅为本公开的可选实施例，并不用以限制本公开，凡在本公开的构思和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (20)

  1. 一种显示基板，所述显示基板包括：
    衬底基板(201)，以及位于所述衬底基板(201)上的电源信号线(253)和电极块(26)，所述电极块(26)包覆所述电源信号线(253)的至少一侧；
    所述衬底基板(201)具有封装区域，所述电源信号线(253)在所述衬底基板(201)上的正投影从所述封装区域内延伸至所述封装区域外，且所述电极块(26)在所述衬底基板(201)上的正投影与所述封装区域存在重合区域。
  2. 根据权利要求1所述的显示基板，所述电极块(26)包覆所述电源信号线(253)的两侧。
  3. 根据权利要求2所述的显示基板，所述电极块(26)包括依次邻接的第一部、第二部、第三部、第四部和第五部，所述第一部和所述第五部均位于所述衬底基板(201)上，所述第二部和所述第四部分别贴附于所述电源信号线(253)的一侧，所述第三部覆盖所述电源信号线(253)远离所述衬底基板(201)的一面。
  4. 根据权利要求3所述的显示基板，所述第一部远离所述电源信号线(253)的一端到所述电源信号线(253)的距离范围为2至20微米，所述第五部远离所述电源信号线(253)的一端到所述电源信号线(253)的距离范围为2至20微米。
  5. 根据权利要求2至4任一所述的显示基板，所述电极块(26)在所述衬底基板(201)上的正投影完全覆盖所述电源信号线(253)在所述衬底基板(201)上的正投影。
  6. 根据权利要求1所述的显示基板，所述电极块(26)包覆所述电源信号线(253)的一侧，所述电源信号线(253)的两侧分别包覆有一个所述电极块(26)。
  7. 根据权利要求6所述的显示基板，所述电极块(26)呈Z字型，所述电极块(26)包括依次邻接的第六部、第七部和第八部，所述第六部搭接在所述电源信号线(253)远离所述衬底基板(201)的一面上，所述第七部贴附于所述电源信号线(253)的目标侧，所述第八部位于所述衬底基板(201)上，所述目标侧为所述电源信号线(253)的两侧中的一侧。
  8. 根据权利要求7所述的显示基板，所述第六部远离所述目标侧的一端到所述目标侧的距离范围为2至20微米，所述第八部远离所述目标侧的一端到所述目标侧的距离范围为2至20微米。
  9. 根据权利要求1至8任一所述的显示基板，所述显示基板还包括位于所述衬底基板(201)上的薄膜晶体管(202)，所述电源信号线(253)与所述薄膜晶体管(202)中的源漏极图案同层同材料。
  10. 根据权利要求9所述的显示基板，所述显示基板还包括位于所述薄膜晶体管(201)远离所述衬底基板的一侧的发光器件(203)，所述发光器件(203)包括沿远离所述衬底基板(201)的方向层叠设置的第一电极(31)、发光层(32)和第二电极(33)，所述电极块(26)与所述第一电极(31)同层同材料。
  11. 根据权利要求10所述的显示基板，所述显示基板中包括相互绝缘的第一电源信号线和第二电源信号线；
    所述第一电源信号线与所述第一电极(31)连接，所述第二电源信号线与所述第二电极(33)连接。
  12. 根据权利要求1至11任一所述的显示基板，所述电源信号线(253)包括沿远离所述衬底基板(201)的方向层叠设置的第一金属层、第二金属层和第三金属层，所述第二金属层的材质与所述第一金属层以及所述第三金属层的材质不同。
  13. 根据权利要求12所述的显示基板，所述第二金属层的金属活泼性大于 所述第一金属层和所述第三金属层的金属活泼性。
  14. 根据权利要求9至11任一所述的显示基板，所述薄膜晶体管(202)为顶栅结构的薄膜晶体管和底栅结构的薄膜晶体管中的一种。
  15. 根据权利要求4或8所述的显示基板，所述显示基板还包括位于所述衬底基板(201)上的薄膜晶体管(202)，所述电源信号线(253)与所述薄膜晶体管(202)中的源漏极图案同层同材料；
    所述显示基板还包括位于所述薄膜晶体管(202)远离所述衬底基板(201)的一侧的发光器件(203)，所述发光器件(203)包括沿远离所述衬底基板(201)的方向层叠设置的第一电极(31)、发光层(32)和第二电极(33)，所述电极块(26)与所述第一电极(31)同层同材料；
    所述电源信号线(253)包括沿远离所述衬底基板(201)的方向层叠设置的第一金属层、第二金属层和第三金属层，所述第二金属层的金属活泼性大于所述第一金属层和所述第三金属层的金属活泼性。
  16. 一种显示装置，包括：如权利要求1至15任一所述的显示基板。
  17. 一种显示基板的制造方法，所述方法包括：
    提供衬底基板，所述衬底基板具有封装区域；
    在所述衬底基板上形成电源信号线，所述电源信号线在所述衬底基板上的正投影从所述封装区域内延伸至所述封装区域外；
    在形成有所述电源信号线的衬底基板上形成电极块，所述电极块包覆所述电源信号线的至少一侧，且所述电极块在所述衬底基板上的正投影与所述封装区域存在重合区域。
  18. 根据权利要求17所述的方法，所述在形成有所述电源信号线的衬底基板上形成电极块，包括：
    在形成有所述电源信号线的衬底基板上同层形成所述电极块以及发光器件中的第一电极。
  19. 根据权利要求18所述的方法，在形成有所述电源信号线的衬底基板上同层形成所述电极块以及发光器件中的第一电极之后，所述方法还包括：
    在形成有所述第一电极的衬底基板上形成发光层；
    在形成有所述发光层的衬底基板上形成所述发光器件中的第二电极。
  20. 根据权利要求18或19所述的方法，所述在形成有所述电源信号线的衬底基板上同层形成所述电极块以及发光器件中的第一电极，包括：
    在形成有所述电源信号线的衬底基板上形成金属层；
    在所述金属层远离所述衬底基板的一侧涂覆光刻胶，并对所述光刻胶依次进行曝光处理和显影处理；
    采用湿法刻蚀的工艺对所述金属层进行刻蚀；
    剥离所述光刻胶，得到所述第一电极和所述电极块。
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