WO2020078326A1 - 阵列基板、驱动方法、有机发光显示面板及显示装置 - Google Patents

阵列基板、驱动方法、有机发光显示面板及显示装置 Download PDF

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Publication number
WO2020078326A1
WO2020078326A1 PCT/CN2019/111072 CN2019111072W WO2020078326A1 WO 2020078326 A1 WO2020078326 A1 WO 2020078326A1 CN 2019111072 W CN2019111072 W CN 2019111072W WO 2020078326 A1 WO2020078326 A1 WO 2020078326A1
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Prior art keywords
light
switching transistor
driving
transistor
array substrate
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PCT/CN2019/111072
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English (en)
French (fr)
Inventor
杨盛际
董学
陈小川
王辉
李胜男
郑增强
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京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to EP19861298.8A priority Critical patent/EP3869491A4/en
Priority to JP2020571763A priority patent/JP2022503421A/ja
Priority to US16/650,601 priority patent/US11462592B2/en
Publication of WO2020078326A1 publication Critical patent/WO2020078326A1/zh

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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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Definitions

  • the present disclosure relates to the field of display technology, and in particular, to an array substrate, a driving method, an organic light-emitting display panel, and a display device.
  • Organic light emitting diode (Organic Light Emitting Diode, OLED) display panel is one of the hotspots in the field of flat panel display research today. Compared with liquid crystal display (Liquid Crystal) display, OLED display has low energy consumption, low production cost, self-luminous, The advantages of wide viewing angle and fast response speed.
  • the existing OLED display panel includes a plurality of pixel units, each pixel unit includes a plurality of sub-pixels, and each sub-pixel includes: one OLED and a pixel circuit configured to drive the OLED to emit light.
  • the pixel circuit generally includes a plurality of transistors and capacitors.
  • the pixel circuit will occupy a larger area in the sub-pixel, which is not conducive to the realization of high PPI OLED display panels. Especially when the OLED is set to Micro-OLED or Mini-OLED, the larger area of the sub-pixel occupied by the pixel circuit has a significant effect on the OLED display panel with high PPI.
  • Embodiments of the present disclosure provide an array substrate, a driving method, an organic light-emitting display panel, and a display device, which are used to reduce the occupied area of a pixel circuit, which is beneficial to realize a high PPI display panel.
  • An embodiment of the present disclosure provides an array substrate, including:
  • a plurality of light emitting devices the plurality of light emitting devices being located in the display area;
  • a pixel circuit the pixel circuit is located in the display area and is coupled to each of the light emitting devices, and the pixel circuit includes a driving transistor;
  • a plurality of voltage control circuits are located in a non-display area; at least two of the pixel circuits share a voltage control circuit, and in the pixel circuit, the first electrode of each of the driving transistors and the common The voltage control circuit is coupled, and the second electrode of each driving transistor is coupled to the corresponding light emitting device.
  • the array substrate further includes: a plurality of pixel units located in the display area, each pixel unit includes a plurality of sub-pixels; each of the sub-pixels includes: one of the light-emitting devices and One of the pixel circuits.
  • the pixel circuits are arranged in multiple rows, and pixel circuits in at least two adjacent sub-pixels in the same row share one voltage control circuit.
  • all the pixel circuits in the same row share one voltage control circuit.
  • the voltage control circuit includes: a first switching transistor
  • the gate of the first switching transistor is configured to receive the reset control signal
  • the first pole of the first switching transistor is configured to receive the initialization signal
  • the second pole of the first switching transistor corresponds to The first electrode of the driving transistor is coupled.
  • the voltage control circuit further includes: a second switching transistor
  • the gate of the second switching transistor is configured to receive a light emission control signal
  • the first pole of the second switching transistor is configured to receive the first power signal
  • the second pole of the second switching transistor corresponds to The first electrode of the driving transistor is coupled.
  • the pixel circuit further includes: a third switching transistor and a storage capacitor;
  • the gate of the third switching transistor is configured to receive the first gate scan signal and is coupled to the first gate driving circuit, and the first pole of the third switching transistor is configured to receive the data signal.
  • the second pole of the three-switch transistor is coupled to the gate of the driving transistor;
  • the first end of the storage capacitor is coupled to the gate of the driving transistor, and the second end of the storage capacitor is coupled to the ground.
  • the pixel circuit further includes: a fourth switching transistor; wherein, the type of the fourth switching transistor and the third switching transistor are different;
  • the gate of the fourth switching transistor is configured to receive a second gate scan signal and is coupled to a second gate driving circuit, and the first pole of the fourth switching transistor is configured to receive the data signal.
  • the second electrode of the fourth switching transistor is coupled to the gate of the driving transistor.
  • the pixel circuit further includes: a fifth switching transistor; wherein, the second electrode of the driving transistor is coupled to the corresponding light emitting device through the fifth switching transistor;
  • the gate of the fifth switching transistor is coupled to the reference signal terminal, the first pole of the fifth switching transistor is coupled to the second pole of the driving transistor, and the second pole of the fifth switching transistor corresponds to The light emitting device is coupled.
  • the fifth switching transistor is a P-type transistor, and the reference signal terminal is a ground terminal.
  • the array substrate further includes a plurality of lighting control signal lines, and a lighting control circuit electrically connected to each of the lighting control signal lines; wherein, one of the lighting control signal lines is The voltage control circuits electrically connected to the pixel circuits of one row are electrically connected, and are configured to input the light emission control signal to the electrically connected voltage control circuits.
  • the lighting control circuit includes a plurality of cascading lighting shift registers, and each of the lighting shift registers is correspondingly electrically connected to one of the lighting control signal lines.
  • the array substrate further includes: a first power signal line; wherein the first power signal line is electrically connected to all the voltage control circuits and is configured to The voltage control circuit inputs the first power signal; or,
  • the array substrate further includes: a plurality of first power signal lines; wherein one of the light emission control signal lines is electrically connected to the voltage control circuit electrically connected to the row of the pixel circuits, and is configured to electrically connect the The voltage control circuit inputs the first power signal.
  • the embodiments of the present disclosure also provide an organic light emitting display panel, including the array substrate provided by the embodiments of the present disclosure.
  • an embodiment of the present disclosure also provides a display device, including the organic light emitting display panel provided by the embodiment of the present disclosure.
  • an embodiment of the present disclosure also provides a driving method of an array substrate configured as an embodiment of the present disclosure, including: controlling the voltage control circuit and the pixel circuit within a frame display time to drive The light emitting device works;
  • the voltage control circuit In the reset phase, the voltage control circuit outputs an initialization signal to the first pole of the driving transistor in response to the reset control signal to control the corresponding light emitting device to reset;
  • the voltage control circuit In the light-emission phase, the voltage control circuit outputs a first power signal to the first pole of the drive transistor in response to the light-emission control signal to drive the light-emitting device to emit light.
  • the operation of driving a row of light-emitting devices further includes: a non-light-emitting stage;
  • the voltage control circuit disconnects the first power signal from the first electrode of the driving transistor in response to the light emitting control signal, and controls the corresponding pixel circuit to drive the connected light emitting device to stop emitting light.
  • the non-light-emitting phase that drives each row of light-emitting devices to work is turned on at the same time; or,
  • the non-light-emitting phase that drives each row of light-emitting devices to work is turned on row by row.
  • the operation of driving a row of light-emitting devices further includes: a dimming stage; the dimming stage includes: at least one non-light-emitting stage and at least one light-emitting stage; Wherein the non-light-emitting phase and the light-emitting phase are alternately arranged in sequence;
  • the voltage control circuit disconnects the first power signal from the first electrode of the driving transistor in response to the light emitting control signal, and controls the corresponding pixel circuit to drive the connected light emitting device to stop emitting light;
  • the voltage control circuit In the light-emission phase, the voltage control circuit outputs a first power signal to the first pole of the driving transistor in response to the light-emission control signal, and controls the corresponding pixel circuit to drive the connected light-emitting device to emit light.
  • the dimming phase that drives the operation of each row of light emitting devices is turned on at the same time; or,
  • the dimming phase that drives each row of light-emitting devices to work is turned on row by row.
  • the array substrate, driving method, organic light-emitting display panel and display device provided by the embodiments of the present disclosure include: a pixel circuit in which a plurality of light-emitting devices in the display area are connected to each light-emitting device, and a plurality of voltages in the non-display area Control circuit; wherein, at least two pixel circuits share a voltage control circuit, so that the structure of each pixel circuit in the display area can be simplified, and the occupation area of the pixel circuit in the display area can be reduced, so that more pixel circuits and Light emitting device, realize high PPI organic light emitting display panel.
  • the initialization signal is output to the first pole of the driving transistor to control the corresponding light-emitting device to reset, thereby avoiding the voltage applied to the light-emitting device when the previous frame emits light to the next frame The effect of luminescence, thereby improving the afterimage phenomenon.
  • FIG. 1 is a schematic structural diagram of an array substrate provided by an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of another array substrate provided by an embodiment of the present disclosure.
  • 3a is a schematic structural diagram of another array substrate provided by an embodiment of the present disclosure.
  • 3b is a schematic structural diagram of another array substrate provided by an embodiment of the present disclosure.
  • FIG. 4 is a schematic diagram of a specific structure of an array substrate provided by an embodiment of the present disclosure.
  • FIG. 5 is a schematic diagram of a specific structure of another array substrate provided by an embodiment of the present disclosure.
  • FIG. 6 is a flowchart of a driving method provided by an embodiment of the present disclosure.
  • FIG. 8 is another circuit timing diagram provided by an embodiment of the present disclosure.
  • FIG. 11 is another circuit timing diagram provided by an embodiment of the present disclosure.
  • FIG 13 is another circuit timing diagram provided by an embodiment of the present disclosure.
  • An embodiment of the present disclosure provides an array substrate. As shown in FIG. 1, it may include:
  • Multiple light emitting devices L multiple light emitting devices L are located in the display area AA;
  • the pixel circuit 10 is located in the display area AA and is coupled to each light emitting device L. Specifically, one pixel driving circuit 10 may be correspondingly coupled to one light emitting device L, and each pixel driving circuit 10 corresponds to the light emitting device L
  • the pixel circuit 10 includes a driving transistor;
  • a plurality of voltage control circuits 20, the plurality of voltage control circuits 20 are located in a non-display area (an area other than the display area AA in the array substrate); at least two pixel circuits 10 share a voltage control circuit 20, and the pixel circuit 10 is driven
  • the first pole of the transistor is coupled to the common voltage control circuit 20, and the second pole of each driving transistor is coupled to the corresponding light emitting device L.
  • the voltage control circuit 20 is configured to output the initialization signal Vinit to the first electrode of the driving transistor in response to the reset control signal RE, to control the reset of the corresponding light emitting device L; and to output the first power signal VDD in response to the light emission control signal EM To the first electrode of the driving transistor to drive the light emitting device L to emit light.
  • the above-mentioned array substrate includes: a plurality of light emitting devices located in a display area and pixel circuits connected to each light emitting device, and a plurality of voltage control circuits located in a non-display area; wherein at least two pixel circuits Sharing a voltage control circuit can simplify the structure of each pixel circuit in the display area and reduce the occupied area of the pixel circuit in the display area, so that more pixel circuits and light-emitting devices can be provided in the display area to realize high PPI organic light-emitting display panel.
  • the initialization signal is output to the first pole of the driving transistor to control the corresponding light-emitting device to reset, thereby avoiding the voltage applied to the light-emitting device when the previous frame emits light to the next frame The effect of luminescence, thereby improving the afterimage phenomenon.
  • the array substrate may further include: a plurality of pixel units PX located in the display area AA, each pixel unit PX includes a plurality of sub-pixels 40; each sub-pixel 40 respectively include: a light emitting device L and a pixel circuit 10.
  • the pixel unit PX may include three sub-pixels 40 of different colors.
  • the three sub-pixels 40 may be a red sub-pixel, a green sub-pixel, and a blue sub-pixel, respectively.
  • the pixel unit may also include 4, 5 or more sub-pixels, which need to be designed and determined according to the actual application environment, and are not limited herein.
  • the pixel circuits are arranged in multiple rows, so that the pixel circuits in at least two adjacent sub-pixels in the same row share one voltage control circuit.
  • the first electrode of the driving transistor in the row of pixel circuits 10 is coupled to the common voltage control circuit 20.
  • all pixel circuits 10 in the same row can share one voltage control circuit 20.
  • two or three adjacent sub-pixels or more pixel circuits in the same row may share a voltage control circuit, which is not limited herein. In this way, the shared voltage control circuit can reduce the occupied area of the pixel circuit in the display area.
  • the array substrate may further include a plurality of light emission control signal lines SEM, and a light emission control circuit 30 electrically connected to each light emission control signal line SEM;
  • the light emission control signal line SEM is electrically connected to a voltage control circuit electrically connected to a row of pixel circuits, and is configured to input a light emission control signal to the electrically connected voltage control circuit.
  • one light emission control signal line SEM is electrically connected to the gate of the second switching transistor M2 electrically connected to a row of pixel circuits in the display area AA.
  • the light emission control circuit 30 may include multiple cascaded light emission shift registers EOA, each light emission shift register EOA and a light emission control signal
  • the line SEM corresponds to the electrical connection.
  • the light-emitting input signal terminal of the first-level light-emitting shift register EOA is configured to receive a frame light-emitting trigger signal, and the light-emitting input signal terminals of the remaining light-emitting shift registers EOA are respectively adjacent to the previous-level light-emitting shift register
  • the light output terminal of the EOA is electrically connected to realize the function of inputting the light control signal to the light control signal line SEM.
  • the structure of the light-emitting shift register is the same as the existing structure, and will not be repeated here.
  • the array substrate may further include: a first power signal line SVDD; wherein, the first power signal line SVDD is electrically connected to all voltage control circuits , Configured to input a first power signal to each voltage control circuit.
  • the first power signal line SVDD is electrically connected to the first electrodes of all second switching transistors M2.
  • the first power signal line SVDD may be disposed in the non-display area, which further reduces the number of traces provided in the display area AA, so that a high-PPI organic light-emitting display panel can be realized.
  • the driving transistor M0 may be an N-type transistor.
  • the first terminal S is its source
  • the second terminal D is its drain.
  • the light emitting device L may include an OLED.
  • the anode of the OLED is electrically connected to the second terminal D of the driving transistor M0
  • the cathode of the OLED is electrically connected to the second power terminal VSS.
  • the voltage of the second power supply terminal VSS is generally a negative voltage or a ground voltage V GND (generally 0V), and the voltage of the initialization signal may also be set to the ground voltage V GND, which is not limited herein.
  • OLED can be set to Micro-OLED or Mini-OLED, which is further conducive to the realization of high PPI organic light-emitting display panels.
  • the voltage control circuit may include: a first switching transistor; the gate of the first switching transistor is configured to receive a reset control signal, the first pole of the first switching transistor is configured to receive an initialization signal, and the first switching transistor Is coupled to the first pole of the corresponding driving transistor.
  • the voltage control circuit may further include: a second switching transistor; the gate of the second switching transistor is configured to receive the light emission control signal, the first pole of the second switching transistor is configured to receive the first power signal, and the second switch The second electrode of the transistor is coupled to the first electrode of the corresponding driving transistor.
  • the voltage control circuit includes a first switching transistor and a second switching transistor for specific description below: As shown in FIGS.
  • the voltage control circuit 20 may include: a first Switching transistor M1 and second switching transistor M2; wherein, the gate of the first switching transistor M1 is configured to receive the reset control signal RE, the first pole of the first switching transistor M1 is configured to receive the initialization signal Vinit, the first switching transistor The second pole of M1 is coupled to the first pole S of the corresponding driving transistor M0.
  • the gate of the second switching transistor M2 is configured to receive the light emission control signal EM, the first pole of the second switching transistor M2 is configured to receive the first power signal VDD, the second pole of the second switching transistor M2 and the corresponding driving transistor The first pole S of M0 is coupled.
  • the types of the first switching transistor M1 and the second switching transistor M2 may be different.
  • the first switching transistor M1 is an N-type transistor
  • the second switching transistor M2 is a P-type transistor
  • the first switching transistor is a P-type transistor
  • the second switching transistor is an N-type transistor.
  • the types of the first switching transistor M1 and the second switching transistor M2 may be the same. In practical applications, the types of the first switching transistor and the second switching transistor need to be designed according to the actual application environment, which is not limited herein.
  • the pixel circuit 10 may further include: a third switching transistor M3 and a storage capacitor Cst; wherein, the gate of the third switching transistor M3 is configured To receive the first gate scan signal S1, coupled to the first gate driving circuit, the first pole of the third switching transistor M3 is configured to receive the data signal DA, the second pole of the third switching transistor M3 and the driving transistor M0
  • the gate G is coupled.
  • the first end of the storage capacitor Cst is coupled to the gate G of the driving transistor M0, and the second end of the storage capacitor Cst is coupled to the ground terminal GND.
  • the pixel circuit 10 may further include: a fourth switching transistor M4; wherein, the gate of the fourth switching transistor M4 is configured as Receiving the second gate scan signal S2, coupled to the second gate driving circuit, the first pole of the fourth switching transistor M4 is configured to receive the data signal DA, the second pole of the fourth switching transistor M4 and the driving transistor M0
  • the gate G is coupled.
  • the types of the fourth switching transistor M4 and the third switching transistor M3 are different.
  • the third switching transistor M3 is an N-type transistor
  • the fourth switching transistor M4 is a P-type transistor
  • the fourth switching transistor M4 is an N-type transistor.
  • the pixel circuit 10 may further include: a fifth switching transistor M5; wherein, the second pole D of the driving transistor M0 passes through the fifth switching transistor M5 and the corresponding The light emitting device L is coupled. Moreover, the gate of the fifth switching transistor M5 is coupled to the reference signal terminal, the first pole of the fifth switching transistor M5 is coupled to the second pole D of the driving transistor M0, and the second pole of the fifth switching transistor M5 is corresponding to The light emitting device L is coupled. Further, the fifth switching transistor M5 may be set as a P-type transistor, and the reference signal terminal is set as the ground terminal GND.
  • the P-type transistor is turned off under the action of the high-level signal and turned on under the action of the low-level signal; the N-type transistor is turned on under the action of the high-level signal and is on the low level Cut off under the action of the signal.
  • the above switching transistor may be a thin film transistor (TFT, Thin Film Transistor) or a metal oxide semiconductor field effect transistor (MOS, Metal Oxide Scmiconductor), which is not limited herein.
  • TFT Thin Film Transistor
  • MOS Metal Oxide Scmiconductor
  • the first electrode of the above switching transistor can be used as its source and the second electrode as its drain; or, the second electrode can be used as its source and the first electrode can be used as its drain, which is not limited herein.
  • an embodiment of the present disclosure also provides a driving method of an array substrate provided by an embodiment of the present disclosure, which may include: controlling a voltage control circuit and a pixel circuit within a frame display time to drive the light emitting device to work.
  • driving a row of light-emitting devices to work may include the following steps:
  • the voltage control circuit In the reset phase, the voltage control circuit outputs an initialization signal to the first pole of the driving transistor in response to the reset control signal, and controls the corresponding light emitting device to reset;
  • the voltage control circuit outputs the first power signal to the first pole of the drive transistor in response to the light-emission control signal to drive the light-emitting device to emit light.
  • Driving a row of light-emitting devices to work may include: a reset phase T1, a data writing phase T2, and a light-emitting phase T3.
  • the gate G of the driving transistor M0 stores the data signal of low gray level through the storage capacitor Cst during the display of the previous frame (that is, the low gray level is displayed)
  • the voltage of the first electrode S of the driving transistor M0 is reset to The ground voltage V GND
  • the current flows from the second electrode D of the driving transistor M0 to its first electrode S, so that the voltage of the second electrode D and the positive electrode of the light emitting device L can be reset to V GND -V th .
  • V th represents the threshold voltage of the driving transistor M0. In this way, the influence of the voltage applied to the light-emitting device when the previous frame emits light on the next frame can be avoided, thereby improving the afterimage phenomenon.
  • the turned-on third and fourth switching transistors M3 and M4 can provide the data signal DA to the gate G of the driving transistor M0, so that the gate G of the driving transistor M0 is the voltage VDA of the data signal and is stored by The capacitor Cst is used for storage.
  • the data signal DA when the voltage of the data signal DA is the voltage corresponding to the high gray level, the data signal DA is transmitted to the gate G of the driving transistor M0 through the P-type fourth switching transistor M4 to be turned on to avoid the data signal
  • the voltage of DA is affected by the threshold voltage V th (M3) of the N-type third switching transistor M3.
  • the N-type third switching transistor M3 When the voltage of the data signal DA is a voltage corresponding to the low gray level, the N-type third switching transistor M3 is turned on to transmit the data signal DA to the gate G of the driving transistor M0, which can prevent the voltage of the data signal DA from being affected by P
  • the effect of the threshold voltage V th (M4) of the fourth switching transistor M4 of the type This can increase the voltage range input to the gate G of the driving transistor M0.
  • V D of the second electrode D of the driving transistor M0 may be approximated as V DA -V th , but actually V D ⁇ V DA -V th .
  • the voltage of V D can be changed, thereby changing the voltage difference between the two electrodes of the light emitting device L, and thereby changing the light emission of the light emitting device L.
  • driving a row of light-emitting devices may further include: a non-light-emitting phase T4; wherein, in the non-light-emitting phase T4, the voltage control circuit responds to the light-emitting control signal EM, The first power signal is disconnected from the first electrode of the driving transistor, and the corresponding pixel circuit is controlled to drive the connected light emitting device to stop emitting light.
  • Driving a row of light-emitting devices to work may include: a reset phase T1, a data writing phase T2, a light-emitting phase T3, and a non-light-emitting phase T4.
  • the reset phase T1, the data writing phase T2, and the light-emitting phase T3 can refer to the first embodiment, and will not be repeated here.
  • the non-light-emission phase T4 that drives the operation of each row of light-emitting devices may be turned on at the same time t0 within a frame display time F (ie, Frame).
  • the general array substrate may include K rows of pixel units, and K is a positive integer.
  • G_k (1 ⁇ k ⁇ K, and an integer) represents each signal that drives the pixel circuit in the pixel unit of the k-th row.
  • the pixel circuit can be driven by row-by-row driving mode. After driving the light emitting devices in the first row of pixel units to the last row of pixel units to emit light, the light emitting devices in each row of pixel units can be controlled simultaneously. Stop glowing.
  • the non-light-emitting phase T4 can be occupied for 2 ms, and the remaining 9.1 ms is the duration for driving the pixel circuits in the pixel units of the first row to the last row.
  • the non-light-emitting phase T4 driving each row of light-emitting devices to work is turned on row by row.
  • the pixel circuits in driving the pixel units in the first row to the pixel units in the last row can be operated sequentially in a row-by-row driving manner.
  • the non-light-emitting stage T4 is turned on at time t_1, and the second switching transistor electrically connected to the first row of pixel circuits is controlled to turn off to control the first row of pixel units
  • the light emitting device in stops emitting light.
  • the non-light-emitting stage T4 is turned on, and the second switching transistor electrically connected to the second row of pixel circuits is controlled to turn off to control the light emission in the second row of pixel units The device stops emitting light.
  • the light emitting device in the pixel unit of the Kth row After driving the light emitting device in the pixel unit of the Kth row to emit light, it is turned on at the time t_K to enter the non-light emitting stage T4, and the second switching transistor electrically connected to the pixel circuit of the Kth row is controlled to be turned off to control the light emission in the pixel unit of the Kth row
  • the device stops emitting light. The rest can be deduced by analogy.
  • FIG. 4 The structural schematic diagram of the array substrate corresponding to this embodiment is shown in FIG. 4, which is modified for the implementation in the first embodiment. The following only describes the differences between this embodiment and the first embodiment, and the similarities are not repeated here.
  • driving a row of light-emitting devices may further include: a dimming phase TS.
  • the light-emitting stages TS2_y are alternately arranged in sequence. Among them, X can be set to 1, 2, 3, etc., Y can be set to 1, 2, 3, etc.
  • X can be set to 1, 2, 3, etc.
  • Y can be set to 1, 2, 3, etc.
  • the specific implementation of the number of stages and light-emitting stages can be designed and determined according to the actual application environment, and is not limited herein.
  • the voltage control circuit disconnects the first power signal from the first electrode of the driving transistor in response to the light-emission control signal, and controls the corresponding pixel circuit to drive the connected light-emitting device to stop emitting light;
  • the voltage control circuit outputs the first power signal to the first electrode of the driving transistor in response to the light-emitting control signal, and controls the corresponding pixel circuit to drive the connected light-emitting device to emit light. In this way, by setting the dimming stage, the brightness of the light emitting device can be effectively controlled.
  • the dimming stage TS may include: a non-lighting stage TS1_1, a light emitting stage TS2_1, a non-lighting stage TS1_2, and a light emitting stage TS2_2 that are sequentially set.
  • the dimming stage may also include a non-lighting stage, a light-emitting stage, and a non-lighting stage that are sequentially set. Not limited here.
  • the dimming phase TS driving each row of light-emitting devices to work is turned on at the same time ts0.
  • the pixel circuit can be driven by row-by-row driving mode. After driving the light-emitting devices in the first row of pixel units to the last row of pixel units to emit light, the pixels in each row can be controlled. The light emitting device simultaneously enters the dimming phase TS at time ts0.
  • the dimming phase TS driving each row of light emitting devices to work is turned on row by row.
  • the pixel circuits in driving the pixel units in the first row to the pixel units in the last row can be sequentially operated in a row-by-row driving manner. Specifically, after driving the light emitting devices in the pixel units in the first row to emit light, the light dimming stage TS is turned on at time ts_1. After driving the light emitting devices in the pixel units in the second row to emit light, it turns on and enters the dimming stage TS at time ts_2. After driving the light emitting device in the pixel unit of the Kth row to emit light, it turns on and enters the dimming stage TS at time t_K. The rest can be deduced by analogy.
  • the structure of the array substrate shown in FIG. 5 is that only a P-type fifth switching transistor M5 is provided between the second electrode D of the driving transistor M0 and the positive electrode of the light emitting device L.
  • the fifth switching transistor M0 can function as a contrast clamper.
  • the fifth switch The transistor M5 may be turned on under the control of the voltage of the ground terminal GND and the voltage of the second electrode D of the driving transistor M0, so that V DA -V th is applied to the positive electrode of the light emitting device L, so that Brightness will not be affected.
  • the gate of the fifth switching transistor M5 is connected to the ground GND, so that the fifth switching transistor M5 is insufficient Conducted under the control of the voltage of the ground terminal GND and the voltage of the second pole D of the driving transistor M0, so that the current flowing through the fifth switching transistor M5 can be very small, which can be equivalent to the second pole D of the driving transistor M0 Open circuit with the light-emitting device L, so that the brightness of the light-emitting device L will reach a super low level.
  • the contrast of the light-emitting device L is the lowest in this mode.
  • embodiments of the present disclosure also provide an organic light-emitting display panel, including the array substrate provided by the embodiments of the present disclosure.
  • the principle of the organic light-emitting display panel to solve the problem is similar to that of the aforementioned array substrate. Therefore, for the implementation of the organic light-emitting display panel, please refer to the implementation of the aforementioned array substrate, and the repetition is not repeated here.
  • embodiments of the present disclosure also provide a display device including the above-mentioned organic light-emitting display panel provided by the embodiments of the present disclosure.
  • the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • the other indispensable components of the display device should be understood by those of ordinary skill in the art, and will not be repeated here, nor should it be used as a limitation to the present disclosure.
  • the array substrate, driving method, organic light-emitting display panel and display device provided by the embodiments of the present disclosure include: a pixel circuit in which a plurality of light-emitting devices in the display area are connected to each light-emitting device, and a plurality of voltages in the non-display area Control circuit; wherein, at least two pixel circuits in a row share a voltage control circuit, so that the structure of each pixel circuit in the display area can be simplified, and the occupation area of the pixel circuit in the display area can be reduced, so that more pixels can be set in the display area Circuits and light-emitting devices to achieve high PPI organic light-emitting display panels.
  • the initialization signal is output to the first pole of the driving transistor to control the corresponding light-emitting device to reset, thereby avoiding the voltage applied to the light-emitting device when the previous frame emits light to the next frame The effect of luminescence, thereby improving the afterimage phenomenon.

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Abstract

一种阵列基板、驱动方法、有机发光显示面板及显示装置，包括：位于显示区（AA）中的多个发光器件（L）与各发光器件（L）连接的像素电路（10），以及位于非显示区中的多个电压控制电路（20）；其中，一行中至少两个像素电路（10）共用一个电压控制电路（20），从而可以简化显示区（AA）中各像素电路（10）的结构，降低显示区（AA）中像素电路（10）的占用面积，从而可以使显示区（AA）设置更多的像素电路（10）和发光器件（L），实现高PPI的有机发光显示面板。并且，通过电压控制电路（20）在复位控制信号（RE）的控制下，将初始化信号（Vinit）输出至驱动晶体管（M0）的第一极（S），控制对应的发光器件（L）复位，从而可以避免上一帧发光时加载于发光器件（L）上电压对下一帧发光的影响，进而改善残影现象。

Description

阵列基板、驱动方法、有机发光显示面板及显示装置
相关申请的交叉引用
本申请要求在2018年10月18日提交中国专利局、申请号为201811215357.6、申请名称为“阵列基板、驱动方法、有机发光显示面板及显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，特别涉及一种阵列基板、驱动方法、有机发光显示面板及显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，OLED)显示面板是当今平板显示器研究领域的热点之一，与液晶显示器(Liquid Crystal Display，LCD)相比，OLED显示器具有低能耗、生产成本低、自发光、宽视角及响应速度快等优点。然而，现有的OLED显示面板中包括多个像素单元，每个像素单元包括多个子像素，每个子像素包括：一个OLED以及被配置为驱动OLED发光的像素电路。像素电路一般包括多个晶体管和电容。由于工艺制备精度的限制，导致像素电路会占用子像素中较大的面积，从而不利于实现高PPI的OLED显示面板。尤其是在OLED设置为Micro-OLED或Mini-OLED时，像素电路占用子像素中较大的面积对高PPI的OLED显示面板的影响尤为明显。
发明内容
本公开实施例提供一种阵列基板、驱动方法、有机发光显示面板及显示装置，用以降低像素电路占用面积，有利于实现高PPI显示面板。
本公开实施例提供了一种阵列基板，包括：
多个发光器件，所述多个发光器件位于显示区；
像素电路，所述像素电路位于所述显示区，且与各所述发光器件耦接，所述像素电路包括驱动晶体管；
多个电压控制电路，所述多个电压控制电路位于非显示区；至少两个所述像素电路共用一个电压控制电路，且所述像素电路中，各所述驱动晶体管的第一极与共用的所述电压控制电路耦接，各所述驱动晶体管的第二极与对应的所述发光器件耦接。
可选地，在本公开实施例中，所述阵列基板还包括：位于显示区中的多个像素单元，每个像素单元包括多个子像素；各所述子像素包括：一个所述发光器件与一个所述像素电路。
可选地，在本公开实施例中，像素电路成多行排列，同一行中相邻的至少两个子像素中的像素电路共用一个所述电压控制电路。
可选地，在本公开实施例中，同一行中的所有像素电路共用一个所述电压控制电路。
可选地，在本公开实施例中，所述电压控制电路包括：第一开关晶体管；
所述第一开关晶体管的栅极被配置为接收所述复位控制信号，所述第一开关晶体管的第一极被配置为接收所述初始化信号，所述第一开关晶体管的第二极与对应的驱动晶体管的第一极耦接。
所述电压控制电路还包括：第二开关晶体管；
所述第二开关晶体管的栅极被配置为接收发光控制信号，所述第二开关晶体管的第一极被配置为接收所述第一电源信号，所述第二开关晶体管的第二极与对应的驱动晶体管的第一极耦接。
可选地，在本公开实施例中，所述像素电路还包括：第三开关晶体管和存储电容；
所述第三开关晶体管的栅极被配置为接收第一栅极扫描信号，与第一栅极驱动电路耦接，所述第三开关晶体管的第一极被配置为接收数据信号，所述第三开关晶体管的第二极与所述驱动晶体管的栅极耦接；
所述存储电容的第一端与所述驱动晶体管的栅极耦接，所述存储电容的第二端与接地端耦接。
可选地，在本公开实施例中，所述像素电路还包括：第四开关晶体管；其中，所述第四开关晶体管与所述第三开关晶体管的类型不同；
所述第四开关晶体管的栅极被配置为接收第二栅极扫描信号，与第二栅极驱动电路耦接，所述第四开关晶体管的第一极被配置为接收所述数据信号，所述第四开关晶体管的第二极与所述驱动晶体管的栅极耦接。
可选地，在本公开实施例中，所述像素电路还包括：第五开关晶体管；其中，所述驱动晶体管的第二极通过所述第五开关晶体管与对应的发光器件耦接；
所述第五开关晶体管的栅极与参考信号端耦接，所述第五开关晶体管的第一极与所述驱动晶体管的第二极耦接，所述第五开关晶体管的第二极与对应的发光器件耦接。
可选地，在本公开实施例中，所述第五开关晶体管为P型晶体管，所述参考信号端为接地端。
可选地，在本公开实施例中，所述阵列基板还包括多条发光控制信号线，以及与各所述发光控制信号线电连接的发光控制电路；其中，一条所述发光控制信号线与一行所述像素电路电连接的所述电压控制电路电连接，被配置为向电连接的所述电压控制电路输入所述发光控制信号。
可选地，在本公开实施例中，所述发光控制电路包括多个级联的发光移位寄存器，每一所述发光移位寄存器与一条所述发光控制信号线对应电连接。
可选地，在本公开实施例中，所述阵列基板还包括：一条第一电源信号线；其中，所述第一电源信号线与所有所述电压控制电路电连接，被配置为向每一个所述电压控制电路输入所述第一电源信号；或者，
所述阵列基板还包括：多条第一电源信号线；其中，一条所述发光控制信号线与一行所述像素电路电连接的所述电压控制电路电连接，被配置为向电连接的所述电压控制电路输入所述第一电源信号。
相应地，本公开实施例还提供了一种有机发光显示面板，包括本公开实施例提供的阵列基板。
相应地，本公开实施例还提供了一种显示装置，包括本公开实施例提供的有机发光显示面板。
相应地，本公开实施例还提供了一种被配置为本公开实施例提供的阵列基板的驱动方法，包括：在一帧显示时间内，控制所述电压控制电路和所述像素电路，以驱动发光器件工作；其中，
驱动一行发光器件工作，包括：
重置阶段，所述电压控制电路响应于复位控制信号，将初始化信号输出至所述驱动晶体管的第一极，控制对应的发光器件复位；
数据写入阶段，将数据信号输出至所述驱动晶体管的栅极；
发光阶段，所述电压控制电路响应于发光控制信号，将第一电源信号输出至所述驱动晶体管的第一极，驱动发光器件发光。
可选地，在本公开实施例中，在所述发光阶段之后，所述驱动一行发光器件工作还包括：非发光阶段；
在所述非发光阶段，所述电压控制电路响应于发光控制信号，将第一电源信号与所述驱动晶体管的第一极断开，控制对应的像素电路驱动连接的发光器件停止发光。
可选地，在本公开实施例中，在所述一帧显示时间内，驱动每一行发光器件工作的非发光阶段在相同时间开启；或者，
在所述一帧显示时间内，驱动每一行发光器件工作的非发光阶段逐行依次开启。
可选地，在本公开实施例中，在所述发光阶段之后，所述驱动一行发光器件工作还包括：调光阶段；所述调光阶段包括：至少一个非发光阶段和至少一个发光阶段；其中，所述非发光阶段和所述发光阶段依次交替排列；
在所述非发光阶段，所述电压控制电路响应于发光控制信号，将第一电源信号与所述驱动晶体管的第一极断开，控制对应的像素电路驱动连接的发 光器件停止发光；
在所述发光阶段，所述电压控制电路响应于发光控制信号，将第一电源信号输出至所述驱动晶体管的第一极，控制对应的像素电路驱动连接的发光器件发光。
可选地，在本公开实施例中，在所述一帧显示时间内，驱动每一行发光器件工作的调光阶段在相同时间开启；或者，
在所述一帧显示时间内，驱动每一行发光器件工作的调光阶段逐行依次开启。
本公开有益效果如下：
本公开实施例提供的阵列基板、驱动方法、有机发光显示面板及显示装置，包括：位于显示区中的多个发光器件与各发光器件连接的像素电路，以及位于非显示区中的多个电压控制电路；其中，至少两个像素电路共用一个电压控制电路，从而可以简化显示区中各像素电路的结构，降低显示区中像素电路的占用面积，从而可以使显示区设置更多的像素电路和发光器件，实现高PPI的有机发光显示面板。并且，通过电压控制电路在复位控制信号的控制，将初始化信号输出至驱动晶体管的第一极，控制对应的发光器件复位，从而可以避免上一帧发光时加载于发光器件上电压对下一帧发光的影响，进而改善残影现象。
附图说明
图1为本公开实施例提供的一种阵列基板的结构示意图；
图2为本公开实施例提供的另一种阵列基板的结构示意图；
图3a为本公开实施例提供的另一种阵列基板的结构示意图；
图3b为本公开实施例提供的另一种阵列基板的结构示意图；
图4为本公开实施例提供的一种阵列基板的具体结构示意图；
图5为本公开实施例提供的另一种阵列基板的具体结构示意图；
图6为本公开实施例提供的驱动方法的流程图；
图7为本公开实施例提供的一种电路时序图；
图8为本公开实施例提供的另一种电路时序图；
图9为本公开实施例提供的另一种电路时序图；
图10为本公开实施例提供的另一种电路时序图；
图11为本公开实施例提供的另一种电路时序图；
图12为本公开实施例提供的另一种电路时序图；
图13为本公开实施例提供的另一种电路时序图。
具体实施方式
为了使本公开的目的，技术方案和优点更加清楚，下面结合附图，对本公开实施例提供的阵列基板、驱动方法、有机发光显示面板及显示装置的具体实施方式进行详细地说明。应当理解，下面所描述的优选实施例仅被配置为说明和解释本公开，并不被配置为限定本公开。并且在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互组合。需要注意的是，附图中各层薄膜厚度和形状不反映阵列基板的真实比例，目的只是示意说明本公开内容。并且自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。
本公开实施例提供了一种阵列基板，如图1所示，可以包括：
多个发光器件L，多个发光器件L位于显示区AA；
像素电路10，像素电路10位于显示区AA，且与各发光器件L耦接，具体的，可以是一个像素驱动电路10对应耦接一个发光器件L，像素驱动电路10与发光器件L一一对应，像素电路10包括驱动晶体管；
多个电压控制电路20，多个电压控制电路20位于非显示区(阵列基板中除显示区AA之外的区域)；至少两个像素电路10共用一个电压控制电路20，且像素电路10中驱动晶体管的第一极与共用的电压控制电路20耦接，各驱动晶体管的第二极与对应的发光器件L耦接。电压控制电路20被配置为响应于复位控制信号RE，将初始化信号Vinit输出至驱动晶体管的第一极，控制 对应的发光器件L复位；以及响应于发光控制信号EM，将第一电源信号VDD输出至驱动晶体管的第一极，以驱动发光器件L发光。
本公开实施例提供的上述阵列基板，包括：位于显示区中的多个发光器件与各发光器件连接的像素电路，以及位于非显示区中的多个电压控制电路；其中，至少两个像素电路共用一个电压控制电路，从而可以简化显示区中各像素电路的结构，降低显示区中像素电路的占用面积，从而可以使显示区设置更多的像素电路和发光器件，实现高PPI的有机发光显示面板。并且，通过电压控制电路在复位控制信号的控制，将初始化信号输出至驱动晶体管的第一极，控制对应的发光器件复位，从而可以避免上一帧发光时加载于发光器件上电压对下一帧发光的影响，进而改善残影现象。
在具体实施时，在本公开实施例中，如图1所示，阵列基板还可以包括：位于显示区AA中的多个像素单元PX，每个像素单元PX包括多个子像素40；各子像素40分别包括：一个发光器件L与一个像素电路10。进一步地，像素单元PX可以包括3个不同颜色的子像素40。这3个子像素40可以分别为红色子像素、绿色子像素以及蓝色子像素。当然，像素单元也可以包括4个、5个或更多的子像素，这需要根据实际应用环境来设计确定，在此不作限定。
在具体实施时，在本公开实施例中，像素电路成多行排列，可以使同一行中相邻的至少两个子像素中的像素电路共用一个电压控制电路。一行像素电路10中驱动晶体管的第一极与共用的电压控制电路20耦接。具体地，如图1所示，可以使同一行中的所有像素电路10共用一个电压控制电路20。或者，也可以使同一行中相邻的两个、三个子像素或更多中的像素电路共用一个电压控制电路，在此不作限定。这样通过共用电压控制电路可以降低显示区中像素电路的占用面积。
在具体实施时，在本公开实施例中，如图2所示，阵列基板还可以包括多条发光控制信号线SEM，以及与各发光控制信号线SEM电连接的发光控制电路30；其中，一条发光控制信号线SEM与一行像素电路电连接的电压控制电路电连接，被配置为向电连接的电压控制电路输入发光控制信号。具体地， 一条发光控制信号线SEM与显示区AA中的一行像素电路电连接的第二开关晶体管M2的栅极电连接。
在具体实施时，在本公开实施例中，如图3a与图3b所示，发光控制电路30可以包括多个级联的发光移位寄存器EOA，每一发光移位寄存器EOA与一条发光控制信号线SEM对应电连接。具体地，第一级发光移位寄存器EOA的发光输入信号端被配置为接收帧发光触发信号，其余各级发光移位寄存器EOA的发光输入信号端分别与其相邻的上一级发光移位寄存器EOA的发光输出信号端电连接，以实现对发光控制信号线SEM输入发光控制信号的功能。在实际应用中，发光移位寄存器的结构与现有的结构相同，在此不作赘述。
在具体实施时，在本公开实施例中，如图2与图3a所示，阵列基板还可以包括：一条第一电源信号线SVDD；其中，第一电源信号线SVDD与所有电压控制电路电连接，被配置为向每一个电压控制电路输入第一电源信号。具体地，该第一电源信号线SVDD与所有第二开关晶体管M2的第一极电连接。并且，第一电源信号线SVDD可以设置于非显示区中，进一步降低显示区AA中设置的走线数量，从而可以实现高PPI的有机发光显示面板。
在具体实施时，在本公开实施例中，如图3b所示，阵列基板还可以包括：多条第一电源信号线SVDD_m(1≤m≤M，m和M分别为整数，M代表第一电源信号线的总数，图3b以M＝4为例)；其中，一条发光控制信号线SVDD_m与一行像素电路电连接的电压控制电路电连接，被配置为向电连接的电压控制电路输入第一电源信号。具体地，一条发光控制信号线SVDD_m与一行中的所有第二开关晶体管M2的第一极电连接。并且，所有发光控制信号线SVDD_m可以设置于非显示区中，进一步降低显示区AA中设置的走线数量，从而可以实现高PPI的有机发光显示面板。
在具体实施时，在本公开实施例中，如图4与图5所示，驱动晶体管M0可以为N型晶体管，在电流由其第一端S流向第二端D时，可以将第一端S作为其源极，第二端D作为其漏极。在电流由其第二端D流向第一端S时， 可以将第二端D作为其源极，第一端S作为其漏极。并且，发光器件L可以包括OLED。这样OLED的正极与驱动晶体管M0的第二端D电连接，OLED的负极与第二电源端VSS电连接。第二电源端VSS的电压一般为负电压或接地电压V GND(一般为0V)，初始化信号的电压也可以设置为接地电压V GND，在此不作限定。其中，可以将OLED设置为Micro-OLED或Mini-OLED，这样进一步有利于实现高PPI的有机发光显示面板。
在具体实施时，电压控制电路可以包括：第一开关晶体管；第一开关晶体管的栅极被配置为接收复位控制信号，第一开关晶体管的第一极被配置为接收初始化信号，第一开关晶体管的第二极与对应的驱动晶体管的第一极耦接。具体的，电压控制电路还可以包括：第二开关晶体管；第二开关晶体管的栅极被配置为接收发光控制信号，第二开关晶体管的第一极被配置为接收第一电源信号，第二开关晶体管的第二极与对应的驱动晶体管的第一极耦接。以下以电压控制电路包括第一开关晶体管以及第二开关晶体管进行具体说明：如图4与图5(以一行中包括的两个像素电路为例)所示，电压控制电路20可以包括：第一开关晶体管M1和第二开关晶体管M2；其中，第一开关晶体管M1的栅极被配置为接收复位控制信号RE，第一开关晶体管M1的第一极被配置为接收初始化信号Vinit，第一开关晶体管M1的第二极与对应的驱动晶体管M0的第一极S耦接。第二开关晶体管M2的栅极被配置为接收发光控制信号EM，第二开关晶体管M2的第一极被配置为接收第一电源信号VDD，第二开关晶体管M2的第二极与对应的驱动晶体管M0的第一极S耦接。
在具体实施时，如图4与图5所示，可以使第一开关晶体管M1与第二开关晶体管M2的类型不同。例如，第一开关晶体管M1为N型晶体管，第二开关晶体管M2为P型晶体管。或者，第一开关晶体管为P型晶体管，第二开关晶体管为N型晶体管。当然，也可以使第一开关晶体管M1与第二开关晶体管M2的类型相同。在实际应用中，需要根据实际应用环境来设计第一开关晶体管与第二开关晶体管的类型，在此不作限定。
在具体实施时，在本公开实施例中，如图4与图5所示，像素电路10还 可以包括：第三开关晶体管M3和存储电容Cst；其中，第三开关晶体管M3的栅极被配置为接收第一栅极扫描信号S1，与第一栅极驱动电路耦接，第三开关晶体管M3的第一极被配置为接收数据信号DA，第三开关晶体管M3的第二极与驱动晶体管M0的栅极G耦接。存储电容Cst的第一端与驱动晶体管M0的栅极G耦接，存储电容Cst的第二端与接地端GND耦接。
进一步地，在具体实施时，在本公开实施例中，如图4与图5所示，像素电路10还可以包括：第四开关晶体管M4；其中，第四开关晶体管M4的栅极被配置为接收第二栅极扫描信号S2，与第二栅极驱动电路耦接，第四开关晶体管M4的第一极被配置为接收数据信号DA，第四开关晶体管M4的第二极与驱动晶体管M0的栅极G耦接。并且，第四开关晶体管M4与第三开关晶体管M3的类型不同。例如，第三开关晶体管M3为N型晶体管，第四开关晶体管M4为P型晶体管；或者，第三开关晶体管M3为P型晶体管，第四开关晶体管M4为N型晶体管。
在具体实施时，在本公开实施例中，如图5所示，像素电路10还可以包括：第五开关晶体管M5；其中，驱动晶体管M0的第二极D通过第五开关晶体管M5与对应的发光器件L耦接。并且，第五开关晶体管M5的栅极与参考信号端耦接，第五开关晶体管M5的第一极与驱动晶体管M0的第二极D耦接，第五开关晶体管M5的第二极与对应的发光器件L耦接。进一步地，可以将第五开关晶体管M5设置为P型晶体管，参考信号端设置为接地端GND。
进一步的，在具体实施时，P型晶体管在高电平的信号作用下截止，在低电平的信号作用下导通；N型晶体管在高电平的信号作用下导通，在低电平的信号作用下截止。
需要说明的是，上述开关晶体管可以是薄膜晶体管(TFT，Thin Film Transistor)，也可以是金属氧化物半导体场效应管(MOS，Metal Oxide Scmiconductor)，在此不作限定。在具体实施中，可以使上述开关晶体管的第一极作为其源极，第二极作为其漏极；或者，第二极作为其源极，第一极作为其漏极，在此不作限定。
基于同一发明构思，本公开实施例还提供了一种本公开实施例提供的阵列基板的驱动方法，可以包括：在一帧显示时间内，控制电压控制电路和像素电路，以驱动发光器件工作。
在具体实施时，如图6所示，驱动一行发光器件工作，可以包括如下步骤：
S601、重置阶段，电压控制电路响应于复位控制信号，将初始化信号输出至驱动晶体管的第一极，控制对应的发光器件复位；
S602、数据写入阶段，将数据信号输出至驱动晶体管的栅极；
S603、发光阶段，电压控制电路响应于发光控制信号，将第一电源信号输出至驱动晶体管的第一极，驱动发光器件发光。
下面以驱动一行发光器件工作，且分别以图4和图5所示的阵列基板的结构为例，结合电路时序图对本公开实施例提供的上述阵列基板的驱动方法作以说明。下述描述中以1表示高电平的信号，0表示低电平的信号，需要说明的是，1和0是逻辑电平，其仅是为了更好的解释本公开实施例的具体工作过程，而不是在具体实施时施加在各开关晶体管的栅极上的电平。
实施例一、
以图4所示的阵列基板，且M1为N型晶体管，M2为P型晶体管，M3为N型晶体管，M4为P型晶体管为例，对应的电路时序图如图7所示。驱动一行发光器件工作，可以包括：重置阶段T1、数据写入阶段T2、发光阶段T3。
在重置阶段T1，S1＝0，S2＝1，RE＝1，EM＝1。
由于EM＝1，因此第二开关晶体管M2截止。由于S1＝0，因此第三开关晶体管M3截止。由于S2＝1，因此第四开关晶体管M4截止。由于RE＝1，因此第一开关晶体管M1导通，以将初始化信号Vinit提供给驱动晶体管M0的第一极S。需要说明的是，若上一帧显示时，驱动晶体管M0的栅极G通过存储电容Cst存储的是高灰阶的数据信号(即显示高灰阶)，则驱动晶体管M0的第一极S、第二极D以及发光器件L的正极的电压可以均被重置到接地 电压V GND。若上一帧显示时，驱动晶体管M0的栅极G通过存储电容Cst存储的是低灰阶的数据信号(即显示低灰阶)，则驱动晶体管M0的第一极S的电压被重置到接地电压V GND，并且电流由驱动晶体管M0的第二极D流向其第一极S，使得第二极D和发光器件L的正极的电压可以重置为V GND-V th。其中，V th代表驱动晶体管M0的阈值电压。这样可以避免上一帧发光时加载于发光器件上电压对下一帧发光的影响，进而改善残影现象。
在数据写入阶段T1，S1＝1，S2＝0，RE＝0，EM＝1。
由于EM＝1，因此第二开关晶体管M2截止。由于RE＝0，因此第一开关晶体管M1截止。由于S1＝1，因此第三开关晶体管M3导通。由于S2＝0，因此第四开关晶体管M4导通。导通的第三开关晶体管M3和第四开关晶体管M4，可以将数据信号DA提供给驱动晶体管M0的栅极G，从而使驱动晶体管M0的栅极G为数据信号的电压V DA，并通过存储电容Cst进行存储。需要说明的是，在数据信号DA的电压为高灰阶对应的电压时，通过P型的第四开关晶体管M4导通以将数据信号DA传输给驱动晶体管M0的栅极G，可以避免数据信号DA的电压受N型的第三开关晶体管M3的阈值电压V th(M3)的影响。在数据信号DA的电压为低灰阶对应的电压时，通过N型的第三开关晶体管M3导通以将数据信号DA传输给驱动晶体管M0的栅极G，可以避免数据信号DA的电压受P型的第四开关晶体管M4的阈值电压V th(M4)的影响。这样可以提高输入到驱动晶体管M0的栅极G上的电压范围。
在发光阶段T3，S1＝0，S2＝1，RE＝0，EM＝0。
由于RE＝0，因此第一开关晶体管M1截止。由于S1＝0，因此第三开关晶体管M3截止。由于S2＝1，因此第四开关晶体管M4截止。由于EM＝1，因此第二开关晶体管M2导通，以将第一电源信号VDD提供给驱动晶体管M0的第一极S，使其第一极S的电压为第一电源信号VDD的电压V dd。根据电流特性可知，流过驱动晶体管M0且被配置为驱动发光器件L发光的工作电流I满足公式：I＝K(V GD-V th) 2＝K(V DA-V D-V th) 2，其中，V D代表驱动晶体管M0的第二极D的电压，K为结构参数，相同结构中此数值相对稳定，可以算 作常量。这样，工作电流I由第一电源信号VDD通过第二开关晶体管M2与驱动晶体管M0流向发光器件L，以驱动发光器件L发光。需要说明的是，驱动晶体管M0第二极D的电压V D可以近似为V DA-V th，但实际是V D<V DA-V th的。这样可以通过控制驱动晶体管M0的栅极G的电压，改变V D的电压，从而改变发光器件L两极之间的电压差，进而改变发光器件L的发光。
实施例二、
本实施例对应的阵列基板的结构示意图如图4所示，其针对实施例一中的实施方式进行了变形。下面仅说明本实施例与实施例一的区别之处，其相同之处在此不作赘述。在具体实施时，如图8所示，在发光阶段T3之后，驱动一行发光器件工作还可以包括：非发光阶段T4；其中，在非发光阶段T4，电压控制电路响应于发光控制信号EM，将第一电源信号与驱动晶体管的第一极断开，控制对应的像素电路驱动连接的发光器件停止发光。
具体地，对应的电路时序图如图8所示。驱动一行发光器件工作，可以包括：重置阶段T1、数据写入阶段T2、发光阶段T3以及非发光阶段T4。其中，重置阶段T1、数据写入阶段T2、发光阶段T3可以参见实施例一，在此不作赘述。
在非发光阶段T4，S1＝0，S2＝1，RE＝0，EM＝1。由于RE＝0，因此第一开关晶体管M1截止。由于S1＝0，因此第三开关晶体管M3截止。由于S2＝1，因此第四开关晶体管M4截止。由于EM＝0，因此第二开关晶体管M2截止。这样，第一电源信号VDD不再通过第二开关晶体管M2与驱动晶体管M0流向发光器件L，从而可以使驱动发光器件L停止发光。这样可以进一步避免上一帧发光时加载于发光器件L的正极上的电压对下一帧发光的影响，进而改善残影现象。
实施例三、
在具体实施时，如图9所示，可以在一帧显示时间F(即，Frame)内，使驱动每一行发光器件工作的非发光阶段T4在相同时间t0开启。
具体地，一般阵列基板可以包括K行像素单元，K为正整数。G_k(1≤ k≤K，且为整数)代表驱动第k行像素单元中像素电路工作的各信号。在一帧显示时间Frame内，可以通过逐行驱动方式，驱动像素电路工作，在驱动第一行像素单元至最后一行像素单元中的发光器件发光以后，再控制每一行像素单元中的发光器件同时停止发光。例如，在一帧显示时间Frame的时长为11.1ms时，可以使非发光阶段T4占用2ms，其余9.1ms为驱动第一行像素单元至最后一行像素单元中的像素电路发光的时长。
实施例四、
在具体实施时，如图10所示，在一帧显示时间Frame内，驱动每一行发光器件工作的非发光阶段T4逐行依次开启。在一帧显示时间Frame内，可以通过逐行驱动方式，在驱动第一行像素单元至最后一行像素单元中的像素电路依次工作。
具体地，在驱动第一行像素单元中的发光器件发光以后，在时间t_1时开启进入非发光阶段T4，控制第一行像素电路电连接的第二开关晶体管截止，以控制第一行像素单元中的发光器件停止发光。在驱动第二行像素单元中的发光器件发光以后，在时间t_2时开启进入非发光阶段T4，控制第二行像素电路电连接的第二开关晶体管截止，以控制第二行像素单元中的发光器件停止发光。在驱动第K行像素单元中的发光器件发光以后，在时间t_K时开启进入非发光阶段T4，控制第K行像素电路电连接的第二开关晶体管截止，以控制第K行像素单元中的发光器件停止发光。其余依次类推，在此不作赘述。
实施例五、
本实施例对应的阵列基板的结构示意图如图4所示，其针对实施例一中的实施方式进行了变形。下面仅说明本实施例与实施例一的区别之处，其相同之处在此不作赘述。
在具体实施时，如图11所示，在发光阶段T3之后，驱动一行发光器件工作还可以包括：调光阶段TS。调光阶段TS可以包括：至少一个非发光阶段TS1_x(1≤x≤X，x和X均为正数，X代表调光阶段具有的非发光阶段的总数，图11以X＝2为例)和至少一个发光阶段TS2_y(1≤y≤Y，y和Y均 为正数，Y代表调光阶段具有的发光阶段的总数，图11以Y＝2为例)；其中，非发光阶段TS1_x和发光阶段TS2_y依次交替排列。其中，X可以设置为1、2、3等，Y可以设置为1、2、3等，当然，在实际应用中，不同应用环境对发光器件的亮度的要求不同，因此调光阶段中非发光阶段和发光阶段的数量的具体实施可以根据实际应用环境来设计确定，在此不作限定。
具体地，在非发光阶段TS1_x，电压控制电路响应于发光控制信号，将第一电源信号与驱动晶体管的第一极断开，控制对应的像素电路驱动连接的发光器件停止发光；
在发光阶段TS2_y，电压控制电路响应于发光控制信号，将第一电源信号输出至驱动晶体管的第一极，控制对应的像素电路驱动连接的发光器件发光。这样可以通过设置调光阶段，从而可以有效控制发光器件的亮度。
具体地，如图11所示，调光阶段TS可以包括：依次设置的非发光阶段TS1_1、发光阶段TS2_1、非发光阶段TS1_2、发光阶段TS2_2。或者，调光阶段也可以包括依次设置的非发光阶段、发光阶段、非发光阶段。在此不作限定。
下面以图4为例，结合图11所示的电路时序图对调光阶段TS的工作过程进行说明。在非发光阶段TS1_1，S1＝0，S2＝1，RE＝0，EM＝1。由于RE＝0，因此第一开关晶体管M1截止。由于S1＝0，因此第三开关晶体管M3截止。由于S2＝1，因此第四开关晶体管M4截止。由于EM＝0，因此第二开关晶体管M2截止。这样，第一电源信号不再通过第二开关晶体管M2与驱动晶体管M0流向发光器件L，从而使驱动发光器件L停止发光。
在发光阶段TS2_1，S1＝0，S2＝1，RE＝0，EM＝0。由于RE＝0，因此第一开关晶体管M1截止。由于S1＝0，因此第三开关晶体管M3截止。由于S2＝1，因此第四开关晶体管M4截止。由于EM＝1，因此第二开关晶体管M2导通，以将第一电源信号VDD提供给驱动晶体管M0的第一极S。从而使工作电流I由第一电源信号VDD通过第二开关晶体管M2与驱动晶体管M0流向发光器件L，以驱动发光器件L发光。
在非发光阶段TS1_2，S1＝0，S2＝1，RE＝0，EM＝1。由于RE＝0，因此第一开关晶体管M1截止。由于S1＝0，因此第三开关晶体管M3截止。由于S2＝1，因此第四开关晶体管M4截止。由于EM＝0，因此第二开关晶体管M2截止。这样，第一电源信号不再通过第二开关晶体管M2与驱动晶体管M0流向发光器件L，从而使驱动发光器件L停止发光。
在发光阶段TS2_2，S1＝0，S2＝1，RE＝0，EM＝0。由于RE＝0，因此第一开关晶体管M1截止。由于S1＝0，因此第三开关晶体管M3截止。由于S2＝1，因此第四开关晶体管M4截止。由于EM＝1，因此第二开关晶体管M2导通，以将第一电源信号VDD提供给驱动晶体管M0的第一极S。从而使工作电流I由第一电源信号VDD通过第二开关晶体管M2与驱动晶体管M0流向发光器件L，以驱动发光器件L发光。
实施例六、
在具体实施时，如图12所示，在一帧显示时间Frame内，驱动每一行发光器件工作的调光阶段TS在相同时间ts0开启。
具体地，在一帧显示时间Frame内，可以通过逐行驱动方式，驱动像素电路工作，在驱动第一行像素单元至最后一行像素单元中的发光器件发光以后，再控制每一行像素单元中的发光器件在时间ts0同时进入调光阶段TS。
实施例七、
在具体实施时，如图13所示，在一帧显示时间Frame内，驱动每一行发光器件工作的调光阶段TS逐行依次开启。
具体地，在一帧显示时间Frame内，可以通过逐行驱动方式，在驱动第一行像素单元至最后一行像素单元中的像素电路依次工作。具体地，在驱动第一行像素单元中的发光器件发光以后，在时间ts_1时开启进入调光阶段TS。在驱动第二行像素单元中的发光器件发光以后，在时间ts_2时开启进入调光阶段TS。在驱动第K行像素单元中的发光器件发光以后，在时间t_K时开启进入调光阶段TS。其余依次类推，在此不作赘述。
实施例八、
进一步地，图5所示的阵列基板的结构相比图4，仅是在驱动晶体管M0的第二极D与发光器件L的正极之间设置有P型的第五开关晶体管M5。该第五开关晶体管M0可以起到对比度钳制器的作用。具体地，在数据信号DA的电压为高灰阶对应的电压(例如高电压)时，即在显示高灰阶画面时，由于第五开关晶体管M5的栅极连接接地端GND，使得第五开关晶体管M5可以在接地端GND的电压和驱动晶体管M0的第二极D的电压的控制下处于开启状态，从而使发光器件L的正极上施加有V DA-V th，这样使得发光器件L的最大亮度不会受到影响。在数据信号DA的电压为低灰阶(例如低电压)对应的电压时，即在显示低灰阶画面时，由于第五开关晶体管M5的栅极连接接地端GND，使得第五开关晶体管M5不足以在接地端GND的电压和驱动晶体管M0的第二极D的电压的控制下导通，从而可以使流经第五开关晶体管M5的电流非常小，可以相当于驱动晶体管M0的第二极D与发光器件L之间断路，这样使得发光器件L的亮度会达到超级低的水平。这样根据对比度公式可以得出，在这种模式下发光器件L的对比度是最低的。
并且，图5所示的阵列基板的结构在其他阶段的工作过程可以分别参见实施例一至实施例七，在此不作赘述。
基于同一公开构思，本公开实施例还提供了一种有机发光显示面板，包括本公开实施例提供的阵列基板。该有机发光显示面板解决问题的原理与前述阵列基板相似，因此该有机发光显示面板的实施可以参见前述阵列基板的实施，重复之处在此不再赘述。
基于同一公开构思，本公开实施例还提供了一种显示装置，包括本公开实施例提供的上述有机发光显示面板。该显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。该显示装置的实施可以参见上述有机发光显示面板的实施例，重复之处不再赘述。
本公开实施例提供的阵列基板、驱动方法、有机发光显示面板及显示装 置，包括：位于显示区中的多个发光器件与各发光器件连接的像素电路，以及位于非显示区中的多个电压控制电路；其中，一行中至少两个像素电路共用一个电压控制电路，从而可以简化显示区中各像素电路的结构，降低显示区中像素电路的占用面积，从而可以使显示区设置更多的像素电路和发光器件，实现高PPI的有机发光显示面板。并且，通过电压控制电路在复位控制信号的控制，将初始化信号输出至驱动晶体管的第一极，控制对应的发光器件复位，从而可以避免上一帧发光时加载于发光器件上电压对下一帧发光的影响，进而改善残影现象。
显然，本领域的技术人员可以对本公开进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (23)

  1. 一种阵列基板，包括：
    多个发光器件，所述多个发光器件位于显示区；
    像素电路，所述像素电路位于所述显示区，且与各所述发光器件耦接，所述像素电路包括驱动晶体管；
    多个电压控制电路，所述多个电压控制电路位于非显示区；至少两个所述像素电路共用一个电压控制电路，且所述像素电路中，各所述驱动晶体管的第一极与共用的所述电压控制电路耦接，各所述驱动晶体管的第二极与对应的所述发光器件耦接。
  2. 如权利要求1所述的阵列基板，其中，所述阵列基板还包括：位于所述显示区中的多个像素单元，每个所述像素单元包括多个子像素；各所述子像素包括：一个所述发光器件与一个所述像素电路。
  3. 如权利要求2所述的阵列基板，其中，像素电路成多行排列，同一行中相邻的至少两个所述子像素中的所述像素电路共用一个所述电压控制电路。
  4. 如权利要求3所述的阵列基板，其中，同一行中的所有所述像素电路共用一个所述电压控制电路。
  5. 如权利要求1-4任一项所述的阵列基板，其中，所述电压控制电路包括：第一开关晶体管；
    所述第一开关晶体管的栅极被配置为接收所述复位控制信号，所述第一开关晶体管的第一极被配置为接收所述初始化信号，所述第一开关晶体管的第二极与对应的所述驱动晶体管的第一极耦接。
  6. 如权利要求5所述的阵列基板，其中，所述电压控制电路还包括：第二开关晶体管；
    所述第二开关晶体管的栅极被配置为接收发光控制信号，所述第二开关晶体管的第一极被配置为接收所述第一电源信号，所述第二开关晶体管的第二极与对应的所述驱动晶体管的第一极耦接。
  7. 如权利要求1-4任一项所述的阵列基板，其中，所述像素电路还包括：第三开关晶体管和存储电容；
    所述第三开关晶体管的栅极被配置为接收第一栅极扫描信号，与第一栅极驱动电路耦接，所述第三开关晶体管的第一极被配置为接收数据信号，所述第三开关晶体管的第二极与所述驱动晶体管的栅极耦接；
    所述存储电容的第一端与所述驱动晶体管的栅极耦接，所述存储电容的第二端与接地端耦接。
  8. 如权利要求7所述的阵列基板，其中，所述像素电路还包括：第四开关晶体管；其中，所述第四开关晶体管与所述第三开关晶体管的类型不同；
    所述第四开关晶体管的栅极被配置为接收第二栅极扫描信号，与第二栅极驱动电路耦接，所述第四开关晶体管的第一极被配置为接收所述数据信号，所述第四开关晶体管的第二极与所述驱动晶体管的栅极耦接。
  9. 如权利要求1-4任一项所述的阵列基板，其中，所述像素电路还包括：第五开关晶体管；其中，所述驱动晶体管的第二极通过所述第五开关晶体管与对应的所述发光器件耦接；
    所述第五开关晶体管的栅极与参考信号端耦接，所述第五开关晶体管的第一极与所述驱动晶体管的第二极耦接，所述第五开关晶体管的第二极与对应的所述发光器件耦接。
  10. 如权利要求9所述的阵列基板，其中，所述第五开关晶体管为P型晶体管，所述参考信号端为接地端。
  11. 如权利要求1-4任一项所述的阵列基板，其中，所述阵列基板还包括多条发光控制信号线，以及与各所述发光控制信号线电连接的发光控制电路；其中，一条所述发光控制信号线与一行所述像素电路电连接的所述电压控制电路电连接，被配置为向电连接的所述电压控制电路输入所述发光控制信号。
  12. 如权利要求11所述的阵列基板，其中，所述发光控制电路包括多个级联的发光移位寄存器，每一所述发光移位寄存器与一条所述发光控制信号线对应电连接。
  13. 如权利要求11所述的阵列基板，其中，所述阵列基板还包括：一条第一电源信号线；其中，所述第一电源信号线与所有所述电压控制电路电连接，被配置为向每一个所述电压控制电路输入所述第一电源信号。
  14. 如权利要求11所述的阵列基板，其中，所述阵列基板还包括：多条第一电源信号线；其中，一条所述发光控制信号线与一行所述像素电路电连接的所述电压控制电路电连接，被配置为向电连接的所述电压控制电路输入所述第一电源信号。
  15. 一种有机发光显示面板，其中，包括如权利要求1-14任一项所述的阵列基板。
  16. 一种显示装置，其中，包括如权利要求15所述的有机发光显示面板。
  17. 一种用于如权利要求1-14任一项所述的阵列基板的驱动方法，其中，包括：在一帧显示时间内，控制所述电压控制电路和所述像素电路，以驱动发光器件工作；其中，
    驱动一行发光器件工作，包括：
    重置阶段，所述电压控制电路响应于复位控制信号，将初始化信号输出至所述驱动晶体管的第一极，控制对应的发光器件复位；
    数据写入阶段，将数据信号输出至所述驱动晶体管的栅极；
    发光阶段，所述电压控制电路响应于发光控制信号，将第一电源信号输出至所述驱动晶体管的第一极，驱动发光器件发光。
  18. 如权利要求17所述的驱动方法，其中，在所述发光阶段之后，所述驱动一行发光器件工作还包括：非发光阶段；
    在所述非发光阶段，所述电压控制电路响应于发光控制信号，将第一电源信号与所述驱动晶体管的第一极断开，控制对应的所述像素电路驱动连接的所述发光器件停止发光。
  19. 如权利要求18所述的驱动方法，其中，在所述一帧显示时间内，驱动每一行发光器件工作的非发光阶段在相同时间开启。
  20. 如权利要求18所述的驱动方法，其中，在所述一帧显示时间内，驱 动每一行发光器件工作的非发光阶段逐行依次开启。
  21. 如权利要求17所述的驱动方法，其中，在所述发光阶段之后，所述驱动一行发光器件工作还包括：调光阶段；所述调光阶段包括：至少一个非发光阶段和至少一个发光阶段；其中，所述非发光阶段和所述发光阶段依次交替排列；
    在所述非发光阶段，所述电压控制电路响应于发光控制信号，将第一电源信号与所述驱动晶体管的第一极断开，控制对应的像素电路驱动连接的发光器件停止发光；
    在所述发光阶段，所述电压控制电路响应于发光控制信号，将第一电源信号输出至所述驱动晶体管的第一极，控制对应的像素电路驱动连接的发光器件发光。
  22. 如权利要求19所述的驱动方法，其中，在所述一帧显示时间内，驱动每一行发光器件工作的调光阶段在相同时间开启。
  23. 如权利要求21所述的驱动方法，其中，在所述一帧显示时间内，驱动每一行发光器件工作的调光阶段逐行依次开启。
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