WO2020077922A1 - 阵列基板及其制造方法 - Google Patents

阵列基板及其制造方法 Download PDF

Info

Publication number
WO2020077922A1
WO2020077922A1 PCT/CN2019/075014 CN2019075014W WO2020077922A1 WO 2020077922 A1 WO2020077922 A1 WO 2020077922A1 CN 2019075014 W CN2019075014 W CN 2019075014W WO 2020077922 A1 WO2020077922 A1 WO 2020077922A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
groove
metal oxide
gate
oxide layer
Prior art date
Application number
PCT/CN2019/075014
Other languages
English (en)
French (fr)
Inventor
韦显旺
Original Assignee
深圳市华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Publication of WO2020077922A1 publication Critical patent/WO2020077922A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods

Definitions

  • the invention relates to the field of display technology, in particular to an array substrate for a display panel and a manufacturing method thereof.
  • LCD Liquid crystal display
  • OLED organic light emitting diode
  • Their production technology is very mature, the product yield is high, and the production cost is relatively low , High market acceptance.
  • Thin-film transistor thin film transistor
  • the display panel manufacturing industry has been developing for many years, and the production process for products has been very refined and mature.
  • parasitic capacitance that is: the ratio of Cgd and Cgs to the storage capacitance also increases. Therefore, when the above-mentioned thin film transistor is used as the transistor in the driving circuit, a considerable resistance and capacitive load (RC loading), causing the display quality of the monitor to deteriorate.
  • An object of the present invention is to provide an array substrate and a method of manufacturing the array substrate, which can reduce the overlapping area of the source electrode and the drain electrode and the gate electrode, effectively reduce the parasitic capacitance, and thereby improve the display quality.
  • the array substrate includes:
  • An organic photoresist layer is provided on the gate layer and the substrate, and the organic photoresist layer is provided with a groove corresponding to the gate line;
  • a gate insulating layer provided on the organic photoresist layer
  • a metal oxide layer provided on the gate insulating layer
  • a metal layer provided on the metal oxide layer, the metal layer and the metal oxide layer have source and drain region circuits, semiconductor regions and pixel regions, and the metal oxide layer and the The metal layer corresponding to the portion other than the groove and the pixel area are conductive;
  • the groove of the organic photoresist layer includes a bottom edge and a beveled edge located at opposite ends of the bottom edge, the two beveled edges are respectively inclined toward the outside of the groove in opposite directions, and the two beveled edges are respectively Extending beyond the radial width of the gate line;
  • the metal oxide layer includes a channel region corresponding to the bottom edge of the groove and above the gate line, and two corresponding to the groove The contact area on the hypotenuse, and the metal layer corresponding to the two hypotenuses on the groove is used as the source and drain, wherein the source and drain and the metal oxide layer The contact between them is in the vertical direction corresponding to the two hypotenuses of the groove.
  • the organic photoresist layer includes tetrafluoroethylene.
  • the present invention further provides an array substrate for a display panel.
  • the array substrate includes:
  • An organic photoresist layer is provided on the gate layer and the substrate, and the organic photoresist layer is provided with a groove corresponding to the gate line;
  • a gate insulating layer provided on the organic photoresist layer
  • a metal oxide layer provided on the gate insulating layer
  • a metal layer provided on the metal oxide layer, the metal layer and the metal oxide layer have source and drain area circuits, semiconductor areas, and pixel areas, and the metal oxide layer and the The metal layer corresponds to a portion other than the groove and the pixel area is conductive.
  • the groove of the organic photoresist layer includes a bottom edge and beveled edges at opposite ends of the bottom edge, and the two hypotenuse edges are respectively inclined toward the outside of the groove in opposite directions, and The two hypotenuses respectively extend beyond the radial width of the gate line.
  • the metal oxide layer includes a channel region corresponding to the bottom side of the groove, and a contact region corresponding to the two hypotenuse sides of the groove, and the metal layer corresponds to the The part of the two hypotenuses of the groove is used as a source and a drain, wherein the contact between the source and the drain and the metal oxide layer is on the two hypotenuses corresponding to the groove The vertical direction.
  • the organic photoresist layer includes tetrafluoroethylene.
  • the metal oxide layer includes indium gallium zinc oxide.
  • the present invention further provides a method of manufacturing an array substrate, which is used for a display panel, and the method includes:
  • the source and drain regions and the semiconductor region are formed by etching and ashing processes for the metal layer and the metal oxide layer , And pixel area;
  • the groove of the organic photoresist layer includes a bottom edge and beveled edges at opposite ends of the bottom edge, and the two hypotenuse edges are inclined outwards of the groove in opposite directions, The two hypotenuses respectively extend beyond the radial width of the gate line.
  • the metal oxide layer after passing through the etching process and the ashing process, forms a channel region corresponding to the bottom edge of the groove, and corresponding to the two oblique side surfaces of the groove.
  • the contact area, and the metal layer corresponding to the portion of the two oblique sides of the groove is used as the source and drain, wherein the contact between the source and drain and the metal oxide layer is It corresponds to the vertical direction of the two hypotenuses of the groove.
  • the organic photoresist layer includes tetrafluoroethylene.
  • the metal oxide layer includes indium gallium zinc oxide.
  • the metal oxide layer and the pixel region are conductorized by using the gate layer as a photomask, and the ultraviolet light from the substrate relative to the gate layer On one side, the substrate is irradiated to conduct the metal oxide layer and the pixel area.
  • the source and drain regions, the semiconductor region, and the pixel region are formed by wet etching the metal layer, wet etching the metal oxide layer, and Ashing, and then wet etching the metal layer.
  • the source and gate regions, the semiconductor region and the pixel region are formed by exposing and developing a half-tone mask on the metal layer and the metal oxide layer.
  • the invention uses an organic photoresist of tetrafluoroethylene to form a groove, so that each layer structure formed subsequently is self-aligned according to the configuration of the groove, which greatly reduces the overlapping area between the source electrode and the drain level between the gate electrode Furthermore, the parasitic capacitance and the resistance capacitance delay are reduced, and the display quality can be effectively improved.
  • FIG. 1 is a schematic diagram of a partial structure of an array substrate according to a preferred embodiment of the present invention.
  • FIG. 2 is a schematic diagram of another part of the array substrate according to the preferred embodiment of the present invention.
  • FIG. 3 is a schematic structural view of another part of an array substrate according to a preferred embodiment of the present invention.
  • FIG. 4 is a schematic diagram of another part of the structure of the array substrate according to the preferred embodiment of the present invention.
  • FIG. 5 is a schematic structural view of another part of the array substrate according to the preferred embodiment of the present invention.
  • FIG. 6 is a schematic diagram of another part of the structure of the array substrate according to the preferred embodiment of the present invention.
  • FIG. 7 is a schematic diagram of the array substrate of FIG. 6 being conductive by illumination.
  • FIG. 8 is a flowchart of a method of manufacturing an array substrate according to a preferred embodiment of the present invention.
  • the invention is an array substrate and a method for manufacturing the array substrate.
  • the array substrate is used for a display panel, and the display panel is a liquid crystal display panel (liquid crystal) display, LCD) or organic light emitting diode display (organic light emitting diode, OLED).
  • LCD liquid crystal display panel
  • OLED organic light emitting diode
  • FIG. 1 is a schematic diagram of a partial structure of an array substrate according to a preferred embodiment of the present invention.
  • the structural schematic diagram of the present invention can also be used as a description of the manufacturing process of the array substrate of the present invention.
  • the array substrate 1 of the present invention includes a substrate 11 on which a gate layer 12 is formed, and the gate layer 12 is made of a metal material.
  • a gate line 121 is formed on the gate layer 12 through a photolithography process of exposure and development and wet etching.
  • FIG. 2 is a schematic diagram of another part of the array substrate according to the preferred embodiment of the present invention.
  • An organic photoresist layer 13 is coated on the gate layer 12 and the substrate 11.
  • the organic photoresist layer 13 is made of polyfluoroalkoxy (PFA), which has Excellent chemical resistance and high temperature resistance.
  • PFA polyfluoroalkoxy
  • the organic photoresist layer 13 is provided with a groove 130 at a position corresponding to the gate line 121 through exposure and development.
  • the groove 130 includes a bottom edge 131 and beveled edges 132 at opposite ends of the bottom edge 131.
  • the two beveled edges 132 are respectively inclined toward the outside of the groove 130 in opposite directions, and the two beveled edges 132 They respectively extend beyond the radial width of the gate line 121.
  • the groove 130 has an approximately trapezoidal structure.
  • FIG. 3 is a schematic structural view of another part of an array substrate according to a preferred embodiment of the present invention.
  • a gate insulating layer 14 is provided on the organic photoresist layer 13 of the PFA, that is, the gate insulating layer 14 is deposited on the organic photoresist layer 13 including the groove 130.
  • FIGS. 4 and 5 are schematic diagrams of another part of an array substrate according to a preferred embodiment of the present invention.
  • a metal oxide layer 15 is provided on the gate insulating layer 14, and a metal layer 16 is provided on the metal oxide layer 15.
  • the metal oxide layer 15 is made of indium gallium zinc oxide (IGZO).
  • IGZO indium gallium zinc oxide
  • the metal layer 16 and the metal oxide layer 15 of the IGZO are exposed and developed using a half-tone mask 2 to complete patterning to define the source region 161 and the drain region 162, and the semiconductor ⁇ 3 ⁇ pixel ⁇ 4.
  • the use of the IGZO can greatly increase the rate of charge and discharge of the thin film transistor (TFT) to the pixel electrode, increase the response speed of the pixel and the line scanning rate of the pixel.
  • TFT thin film transistor
  • FIG. 6 is a schematic structural view of another part of the array substrate 1 according to the preferred embodiment of the present invention.
  • the metal layer 16 and the IGZO metal oxide layer 15 have different acid selection ratios, that is, different etching acid solution selection ratios, and the metal layer 16 and the metal oxide layer 15 are subjected to an etching process And the ashing process to form the source region and the drain region circuit, the semiconductor region 3 and the pixel region 4.
  • the etching process and the ashing process are performed by wet etching the metal layer 16, wet etching and ashing the metal oxide layer 15, and then wet etching the metal layer 16, That is, the circuit of the source and drain regions, the semiconductor region 3 and the pixel region 4 are formed through three wet etching and one ashing process.
  • the metal oxide layer 15 of the IGZO includes a channel region 151 corresponding to the bottom side 131 of the groove 130 and a surface corresponding to the second oblique side 132 of the groove 130
  • the contact region 152, the channel region 151 is located directly above the gate line 121.
  • the metal layer 16 retains the portion corresponding to the two hypotenuse sides 132 of the groove 130 as a source and a drain.
  • the contact between the source electrode and the drain electrode and the IGZO is in the vertical direction corresponding to the two hypotenuses 132 (ie, the side surfaces) of the groove 130, and does not contact in the horizontal direction, so The overlapping area of the source and drain and the gate of the gate line 121 can be greatly reduced, thereby effectively reducing the parasitic capacitance.
  • FIG. 7 is a schematic diagram of the array substrate of FIG. 6 being conductive by illumination.
  • the present invention uses the gate layer 12 as a photomask, and uses ultraviolet rays from the side of the substrate 11 opposite to the gate layer 12
  • the substrate 11 is irradiated to conduct the metal oxide layer 15 of the IGZO and the pixel region 4.
  • the metal oxide layer 15 of the IGZO, the portion below the source region 161 and the drain region 162, and the pixel region 4 are conductive due to the ultraviolet irradiation.
  • the structure corresponding to the groove 130 it is not conductive because it is shielded by the gate layer 12 (ie, the gate line 121).
  • the invention uses an organic photoresist of tetrafluoroethylene to form a groove, so that each layer structure formed subsequently is self-aligned according to the configuration of the groove, and the overlapping area between the source electrode and the drain stage and the gate electrode is greatly reduced. Furthermore, the parasitic capacitance and the resistance capacitance delay are reduced, and the display quality can be effectively improved.
  • the invention additionally provides a method of manufacturing an array substrate, which is used for a display panel.
  • 8 is a flowchart of a method of manufacturing an array substrate according to a preferred embodiment of the present invention.
  • the method for manufacturing an array substrate of the present invention includes:
  • Step S1 forming a gate layer on a substrate, and forming a gate line on the gate layer through a photolithography process and wet etching.
  • Step S2 coating an organic photoresist layer on the gate layer and the substrate, the organic photoresist layer including tetrafluoroethylene.
  • Step S3 At the position of the organic photoresist layer corresponding to the gate line, a groove corresponding to the gate line is formed by exposure and development.
  • Step S4 deposit a gate insulating layer on the organic photoresist layer and the groove.
  • Step S5 A metal oxide layer and a metal layer formed on the metal oxide layer are continuously deposited on the gate insulating layer.
  • the metal oxide layer includes indium gallium zinc oxide.
  • Step S6 The source and drain regions, the semiconductor region and the pixel region are defined in the metal layer and the metal oxide layer through exposure and development.
  • Step S7 Using the difference in acid selection ratio between the metal layer and the metal oxide layer, the source and drain regions are formed by etching and ashing processes , Semiconductor area and pixel area.
  • Step S8 Conducting the metal oxide layer and the pixel area with ultraviolet light.
  • the source and drain region lines, the semiconductor region, and the pixel region are formed by wet etching the metal layer, wet etching the metal oxide layer, and ashing And then wet etching the metal layer. That is, the circuit of the source and drain regions, the semiconductor region, and the pixel region are formed through three wet etching and one ashing process.
  • the metal oxide layer After passing through the etching process and the ashing process, the metal oxide layer forms a channel region corresponding to the bottom edge of the groove and a contact region corresponding to the two oblique side surfaces of the groove, and the metal The part of the layer corresponding to the two hypotenuses of the groove is used as the source and drain, wherein the contact between the source and drain and the metal oxide layer corresponds to the groove The vertical direction of the two hypotenuses.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)

Abstract

一种阵列基板，用于显示面板。所述阵列基板包含一基板;一栅极层，设于所述基板上，所述栅极层包括栅极线；一有机光阻层，涂布于所述栅极层及所述基板上，所述有机光阻层对应所述栅极线设有凹槽；一栅极绝缘层，设于所述有机光阻层上；一金属氧化物层，设于所述栅极绝缘层上；及一金属层，设于所述金属氧化物层上，所述金属层及所述金属氧化物层通过光刻及蚀刻工艺定义源极及漏极区线路、半导体区，及像素区。

Description

阵列基板及其制造方法 技术领域
本发明涉及显示技术领域，特别是涉及一种用于显示面板的阵列基板及其制造方法。
 背景技术
液晶显示器(liquid crystal display, LCD)及有机发光二极管显示器(organic light emitting diode, OLED)是目前市场上应用最为广泛的显示产品，其生产工艺技术十分成熟，产品良率高，生产成本相对较低，市场接受度高。而薄膜晶体管(thin film transistor)显示器面板制造行业已经发展多年，对于产品的生产流程已经十分精炼与成熟。
随着LCD与OLED的分辨率越来越高，单位面积下薄膜晶体管所占的比例也越来越多。也因为薄膜晶体管的栅极与源极以及栅极与漏极之间有部分区域重叠，导致薄膜晶体管的栅极-漏极与栅极-源极的寄生电容( parasiticcapacitance，亦即：Cgd与Cgs )相对于储存电容的比例也随之升高。因此，以上述的薄膜晶体管来作为驱动电路中的晶体管时，在信号的传输上往往会产生相当大的电阻电容负载(RC loading )，导致显示器的显示品质下降。
 技术问题
本发明的目的在于提供一种阵列基板及制造阵列基板的方法，其可减少源极和漏极与栅极的重叠区域，有效降低寄生电容，进而提高显示品质。
 技术解决方案
为实现上述目的，本发明提供一种阵列基板，用于显示面板，所述阵列基板包含：
一基板;
一栅极层，设于所述基板上，所述栅极层包括栅极线；
一有机光阻层，设于所述栅极层及所述基板上，所述有机光阻层对应所述栅极线设有凹槽；
一栅极绝缘层，设于所述有机光阻层上；
一金属氧化物层，设于所述栅极绝缘层上；及
一金属层，设于所述金属氧化物层上，所述金属层及所述金属氧化物层具有源极及漏极区线路、半导体区及像素区，且所述金属氧化物层及所述金属层对应所述凹槽以外的部分及所述像素区被导体化；
其中所述有机光阻层的凹槽包括一底边及位于所述底边相对二端的斜边，所述二斜边分别以相反方向朝所述凹槽外倾斜，且所述二斜边分别延伸超过所述栅极线的径向宽度外；所述金属氧化物层包括对应所述凹槽的底边，且位于所述栅极线上方的沟道区，以及对应所述凹槽的二斜边面上的接触区，而所述金属层对应所述凹槽的二斜边面上的部分作为源极及漏极使用，其中所述源极和漏极和所述金属氧化物层之间的接触是在对应于所述凹槽的二斜边的竖直方向。
在一优选实施例中，所述有机光阻层包括四氟乙烯。
本发明另外提供一种阵列基板，用于显示面板，所述阵列基板包含：
一基板;
一栅极层，设于所述基板上，所述栅极层包括栅极线；
一有机光阻层，设于所述栅极层及所述基板上，所述有机光阻层对应所述栅极线设有凹槽；
一栅极绝缘层，设于所述有机光阻层上；
一金属氧化物层，设于所述栅极绝缘层上；及
一金属层，设于所述金属氧化物层上，所述金属层及所述金属氧化物层具有源极及漏极区线路、半导体区，及像素区，且所述金属氧化物层及所述金属层对应所述凹槽以外的部分及所述像素区被导体化。
在一优选实施例中，所述有机光阻层的凹槽包括一底边及位于所述底边相对二端的斜边，所述二斜边分别以相反方向朝所述凹槽外倾斜，且所述二斜边分别延伸超过所述栅极线的径向宽度外。
在一优选实施例中，所述金属氧化物层包括对应所述凹槽的底边的沟道区，以及对应所述凹槽的二斜边面上的接触区，而所述金属层对应所述凹槽的二斜边面上的部分作为源极及漏极使用，其中所述源极和漏极和所述金属氧化物层之间的接触是在对应于所述凹槽的二斜边的竖直方向。
在一优选实施例中，所述有机光阻层包括四氟乙烯。
在一优选实施例中，所述金属氧化物层包括氧化铟镓锌。
本发明另外提供一种制造阵列基板的方法，所述阵列基板用于显示面板，所述方法包含：
在一基板上形成栅极层，并在所述栅极层通过光刻工艺及湿蚀形成栅极线；
在所述栅极层及所述基板上涂布一有机光阻层；
在所述有机光阻层对应所述栅极线的位置，通过曝光及显影以形成相应所述栅极线的凹槽；
在所述有机光阻层及所述凹槽上沉积一栅极绝缘层；
在所述栅极绝缘层上连续沉积一金属氧化物层及形成于所述金属氧化物层上的金属层；
在所述金属层及所述金属氧化物层通过曝光及显影定义源极区和漏极区、半导体区和像素区；
利用所述金属层和所述金属氧化物层酸选择比的不同，对所述金属层及所述金属氧化物层，通过蚀刻工艺及灰化工艺形成源极区和漏极区线路、半导体区，及像素区；及
利用紫外线光照将所述金属氧化物层及所述像素区进行导体化。
在一优选实施例中，所述有机光阻层的凹槽包括一底边及位于所述底边相对二端的斜边，所述二斜边分别以相反方向朝所述凹槽外倾斜，且所述二斜边分别延伸超过所述栅极线的径向宽度外。
在一优选实施例中，所述金属氧化物层在通过蚀刻工艺及灰化工艺之后，形成对应所述凹槽的底边的沟道区，以及对应所述凹槽的二斜边面上的接触区，而所述金属层对应所述凹槽的二斜边面上的部分作为源极及漏极使用，其中所述源极和漏极和所述金属氧化物层之间的接触是在对应于所述凹槽的二斜边的竖直方向。
在一优选实施例中，所述有机光阻层包括四氟乙烯。
在一优选实施例中，所述金属氧化物层包括氧化铟镓锌。
在一优选实施例中，所述金属氧化物层及所述像素区的导体化，是利用所述栅极层为光罩，藉由所述紫外线从所述基板相对于所述栅极层的一面，对所述基板进行照射而导体化所述金属氧化物层及所述像素区。
在一优选实施例中，所述源极区和漏极区线路、所述半导体区，及所述像素区的形成是通过对所述金属层湿刻、对所述金属氧化物层湿刻及灰化，并再对所述金属层湿刻。
在一优选实施例中，所述源极区和栅极区、半导体区和像素区，是在所述金属层及所述金属氧化物层通过半色调光罩曝光及显影形成。
 有益效果
本发明利用四氟乙烯的有机光阻形成凹槽，使后续形成于上的各层结构依据所述凹槽的构型自对准，大幅减少源极及漏级于栅极间的重叠区域，进而减小寄生电容及电阻电容延迟，而能有效提高显示品质。
 附图说明
图1为根据本发明的一较佳实施例的阵列基板的部分结构示意图。
图2为根据本发明较佳实施例的阵列基板的另一部分结构示意图。
图3为根据本发明较佳实施例的阵列基板的另一部分结构示意图。
图4为根据本发明较佳实施例的阵列基板的另一部分结构示意图。
图5为根据本发明较佳实施例的阵列基板的另一部分结构示意图。
图6为根据本发明较佳实施例的阵列基板的另一部分结构示意图。
图7为图6的阵列基板通过光照完成导体化的示意图。
图8为根据本发明的一较佳实施例的制造阵列基板的方法的流程图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
本发明为一种阵列基板及制造阵列基板的方法。所述阵列基板是用于显示面板，所述显示面板为液晶显示面板(liquid crystal display, LCD)或有机发光二极管显示显板(organic light emitting diode, OLED)。
图1为根据本发明的一较佳实施例的阵列基板的部分结构示意图。本发明的结构示意图亦可作为本发明阵列基板的制造流程的说明。本发明的阵列基板1包括基板11，在所述基板11上形成栅极层12，所述栅极层12为金属材料所制。在所述栅极层12通过曝光及显影的光刻工艺及湿式蚀刻形成栅极线121。
图2为根据本发明较佳实施例的阵列基板的另一部分结构示意图。一有机光阻层13涂布于所述栅极层12及所术基板11上，于此较佳实施中，所述有机光组层13为四氟乙烯(Polyfluoroalkoxy，PFA)所制，其具有卓越的耐化学腐蚀性及耐高温性。特别说明的是，所述有机光阻层13通过曝光及显影，在对应所述栅极线121处设有凹槽130。所述凹槽130包括一底边131及位于所述底边131相对二端的斜边132，所述二斜边132分别以相反方向朝所述凹槽130外倾斜，且所述二斜边132分别延伸超过所述栅极线121的径向宽度外。换言之，所述凹槽130具有一近似梯形的构造。
图3为根据本发明较佳实施例的阵列基板的另一部分结构示意图。所述PFA的有机光阻层13上设有一栅极绝缘层14，亦即所述栅极绝缘层14沉积于包括所述凹槽130的所述有机光阻层13上。
图4及图5分别为根据本发明较佳实施例的阵列基板的另一部分结构示意图。所述栅极绝缘层14上设有一金属氧化物层15，并于所述金属氧化物层15上设有一金属层16。于此较佳实施例中，所述金属氧化物层15为氧化铟镓锌(indium gallium zinc oxide，IGZO)所制。如图5所示，使用半色调光罩2对所述金属层16及所述IGZO的金属氧化物层15进行曝光及显影完成图形化，用以定义源极区161和漏极区162、半导体区3和像素区4。所述IGZO的使用可以大幅提高薄膜晶体膜管(thin film transistor，TFT)对像素电极的充放电速率，提高像素的响应速度及像素的行扫描速率。
图6为根据本发明较佳实施例的阵列基板1的另一部分结构示意图。利用所述金属层16和所述IGZO的金属氧化物层15酸选择比的不同，亦即对蚀刻酸液的选择比不同，对所述金属层16及所述金属氧化物层15通过蚀刻工艺及灰化工艺形成源极区和漏极区线路、所述半导体区3及像素区4。特别说明的是，所述蚀刻工艺及灰化工艺是通过对所述金属层16湿刻、对所述金属氧化物层15湿刻及灰化，并再对所述金属层16湿刻，亦即经过三次湿式蚀刻及一次灰化过程形成所述源极区和漏极区线路、所述半导体区3及所述像素区4。
如图6所示，藉由前述方法，所述IGZO的金属氧化物层15包括对应所述凹槽130的底边131的沟道区151，以及对应所述凹槽130二斜边132面上的接触区152，所述沟道区151位于所述栅极线121正上方。此外，所述金属层16则保留对应所述凹槽130的二斜边132面上的部分作为源极及漏极使用。因此，所述源极和漏极和所述IGZO之间的接触是在对应于所述凹槽130的二斜边132(亦即侧面)的竖直方向，而不会在水平方面接触，因此可大幅减少源极和漏极和所述栅极线121的栅极的重叠区域，从而有效降低了寄生电容。
图7为图6的阵列基板通过光照完成导体化的示意图。如图7所示，有别于传统导体化金属层的方式，本发明利用所述栅极层12为光罩，藉由紫外线从所述基板11相对于所述栅极层12的一面，对所述基板11进行照射而导体化所述IGZO的金属氧化物层15及所述像素区4。具体而言，所述IGZO的金属氧化物层15、所述源极区161和漏极区162下方的部分，及所述像素区4因所述紫外线照射而导体化。至于所述凹槽130对应的构造，由于受到所述栅极层12(即栅极线121)的遮挡而不会导体化。
本发明利用四氟乙烯的有机光阻形成凹槽，使后续形成于上的各层结构依据所述凹槽的构型自对准，大幅减少源极及漏级于栅极间的重叠区域，进而减小寄生电容及电阻电容延迟，而能有效提高显示品质。
本发明另外提供一种制造阵列基板的方法，所述阵列基板用于显示面板。图8为根据本发明的一较佳实施例的制造阵列基板的方法的流程图。本发明制造阵列基板的方法包含：
步骤S1：在一基板上形成栅极层，并在所述栅极层通过光刻工艺及湿蚀形成栅极线。
步骤S2：在所述栅极层及所述基板上涂布一有机光阻层，所述有机光阻层包括四氟乙烯。
步骤S3：在所述有机光阻层对应所述栅极线的位置，通过曝光及显影以形成相应所述栅极线的凹槽。
步骤S4：在所述有机光阻层及所述凹槽上沉积一栅极绝缘层。
步骤S5：在所述栅极绝缘层上连续沉积一金属氧化物层及形成于所述金属氧化物层上的金属层，所述金属氧化物层包括氧化铟镓锌。
步骤S6：在所述金属层及所述金属氧化物层通过曝光及显影定义源极区和漏极区、半导体区和像素区。
步骤S7：利用所述金属层和所述金属氧化物层酸选择比的不同，对所述金属层及所述金属氧化物层，通过蚀刻工艺及灰化工艺形成源极区和漏极区线路、半导体区及像素区。
步骤S8：利用紫外线光照将所述金属氧化物层及所述像素区进行导体化。
于一具体实施中，所述源极区和漏极区线路、所述半导体区，及所述像素区的形成是通过对所述金属层湿刻、对所述金属氧化物层湿刻及灰化，并再对所述金属层湿刻。亦即，经过三次湿式蚀刻及一次灰化过程形成所述源极区和漏极区线路、所述半导体区，及所述像素区。
根据本发明制造阵列基板的方法所形成所述有机光阻层的凹槽构造已详述于前述阵列基板的实施例中，于此不再复述。
所述金属氧化物层在通过蚀刻工艺及灰化工艺之后，形成对应所述凹槽的底边的沟道区，以及对应所述凹槽的二斜边面上的接触区，而所述金属层对应所述凹槽的二斜边面上的部分作为源极及漏极使用，其中所述源极和漏极和所述金属氧化物层之间的接触是在对应于所述凹槽的二斜边的竖直方向。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (14)

  1. 一种阵列基板，用于显示面板，所述阵列基板包含：
    一基板;
    一栅极层，设于所述基板上，所述栅极层包括栅极线；
    一有机光阻层，设于所述栅极层及所术基板上，所述有机光阻层对应所述栅极线设有凹槽；
    一栅极绝缘层，设于所述有机光阻层上；
    一金属氧化物层，设于所述栅极绝缘层上；及
    一金属层，设于所述金属氧化物层上，所述金属层及所述金属氧化物层具有源极及漏极区线路、半导体区及像素区，且所述金属氧化物层及所述金属层对应所述凹槽以外的部分及所述像素区被导体化；
    其中所述有机光阻层的凹槽包括一底边及位于所述底边相对二端的斜边，所述二斜边分别以相反方向朝所述凹槽外倾斜，且所述二斜边分别延伸超过所述栅极线的径向宽度外；所述金属氧化物层包括对应所述凹槽的底边，且位于所述栅极线上方的沟道区，以及对应所述凹槽的二斜边面上的接触区，而所述金属层对应所述凹槽的二斜边面上的部分作为源极及漏极使用，其中所述源极和漏极和所述金属氧化物层之间的接触是在对应于所述凹槽的二斜边的竖直方向。
  2. 如权利要求1的阵列基板，其中所述有机光阻层包括四氟乙烯。
  3. 一种阵列基板，用于显示面板，所述阵列基板包含：
    一基板;
    一栅极层，设于所述基板上，所述栅极层包括栅极线；
    一有机光阻层，设于所述栅极层及所述基板上，所述有机光阻层对应所述栅极线设有凹槽；
    一栅极绝缘层，设于所述有机光阻层上；
    一金属氧化物层，设于所述栅极绝缘层上；及
    一金属层，设于所述金属氧化物层上，所述金属层及所述金属氧化物层具有源极及漏极区线路、半导体区及像素区，且所述金属氧化物层及所述金属层对应所述凹槽以外的部分及所述像素区被导体化。
  4. 如权利要求3的阵列基板，其中所述有机光阻层的凹槽包括一底边及位于所述底边相对二端的斜边，所述二斜边分别以相反方向朝所述凹槽外倾斜，且所述二斜边分别延伸超过所述栅极线的径向宽度外。
  5. 如权利要求4的阵列基板，其中所述金属氧化物层包括对应所述凹槽的底边的沟道区，以及对应所述凹槽的二斜边面上的接触区，而所述金属层对应所述凹槽的二斜边面上的部分作为源极及漏极使用，其中所述源极和漏极和所述金属氧化物层之间的接触是在对应于所述凹槽的二斜边的竖直方向。
  6. 如权利要求3的阵列基板，其中所述有机光阻层包括四氟乙烯。
  7. 如权利要求3的阵列基板，其中所述金属氧化物层包括氧化铟镓锌。
  8. 一种制造阵列基板的方法，所述阵列基板用于显示面板，所述方法包含：
    在一基板上形成栅极层，并在所述栅极层通过光刻工艺及湿蚀形成栅极线；
    在所述栅极层及所述基板上涂布一有机光阻层；
    在所述有机光阻层对应所述栅极线的位置，通过曝光及显影以形成相应所述栅极线的凹槽；
    在所述有机光阻层及所述凹槽上沉积一栅极绝缘层；
    在所述栅极绝缘层上连续沉积一金属氧化物层及形成于所述金属氧化物层上的金属层；
    在所述金属层及所述金属氧化物层通过曝光及显影定义源极区和漏极区、半导体区和像素区；
    利用所述金属层和所述金属氧化物层酸选择比的不同，对所述金属层及所述金属氧化物层，通过蚀刻工艺及灰化工艺形成源极区和漏极区线路、半导体区，及像素区；及
    利用紫外线光照将所述金属氧化物层及所述像素区进行导体化。
  9. 如权利要求8的制造阵列基板的方法，其中所述有机光阻层的凹槽包括一底边及位于所述底边相对二端的斜边，所述二斜边分别以相反方向朝所述凹槽外倾斜，且所述二斜边分别延伸超过所述栅极线的径向宽度外。
  10. 如权利要求9的制造阵列基板的方法，其中所述金属氧化物层在通过蚀刻工艺及灰化工艺之后，形成对应所述凹槽的底边的沟道区，以及对应所述凹槽的二斜边面上的接触区，而所述金属层对应所述凹槽的二斜边面上的部分作为源极及漏极使用，其中所述源极和漏极和所述金属氧化物层之间的接触是在对应于所述凹槽的二斜边的竖直方向。
  11. 如权利要求8的制造阵列基板的方法，其中所述有机光阻层包括四氟乙烯。
  12. 如权利要求8的制造阵列基板的方法，其中所述金属氧化物层包括氧化铟镓锌。
  13. 如权利要求8的制造阵列基板的方法，其中所述金属氧化物层及所述像素区的导体化，是利用所述栅极层为光罩，藉由所述紫外线从所述基板相对于所述栅极层的一面，对所述基板进行照射而导体化所述金属氧化物层及所述像素区。
  14. 如权利要求8的制造阵列基板的方法，其中所述源极区和漏极区线路、所述半导体区，及所述像素区的形成是通过对所述金属层湿刻、对所述金属氧化物层湿刻及灰化，并再对所述金属层湿刻。
PCT/CN2019/075014 2018-10-15 2019-02-14 阵列基板及其制造方法 WO2020077922A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201811194330.3A CN109285844B (zh) 2018-10-15 2018-10-15 阵列基板及其制造方法
CN201811194330.3 2018-10-15

Publications (1)

Publication Number Publication Date
WO2020077922A1 true WO2020077922A1 (zh) 2020-04-23

Family

ID=65176374

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/075014 WO2020077922A1 (zh) 2018-10-15 2019-02-14 阵列基板及其制造方法

Country Status (2)

Country Link
CN (1) CN109285844B (zh)
WO (1) WO2020077922A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109285844B (zh) * 2018-10-15 2020-12-25 深圳市华星光电技术有限公司 阵列基板及其制造方法

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102655200A (zh) * 2011-03-02 2012-09-05 一品光学工业股份有限公司 发光二极管一次光学镜片封装方法及其发光二极管组件
CN102867778A (zh) * 2012-09-17 2013-01-09 上海华力微电子有限公司 一种对40/45纳米工艺金属硬光罩结构的缺陷解决方案
CN103489922A (zh) * 2013-09-30 2014-01-01 京东方科技集团股份有限公司 薄膜晶体管及制备方法、阵列基板及制备方法和显示装置
JP2014078618A (ja) * 2012-10-11 2014-05-01 Sharp Corp 光電変換素子および光電変換素子の製造方法
CN106449518A (zh) * 2016-10-14 2017-02-22 武汉华星光电技术有限公司 Ltps阵列基板的制造方法及阵列基板
CN107359258A (zh) * 2017-06-01 2017-11-17 深圳市华星光电技术有限公司 显示基板及其制造方法、显示装置
CN109285844A (zh) * 2018-10-15 2019-01-29 深圳市华星光电技术有限公司 阵列基板及其制造方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2953201B2 (ja) * 1992-07-02 1999-09-27 日本電気株式会社 薄膜トランジスタおよびその製造方法
JP2726786B2 (ja) * 1992-09-28 1998-03-11 株式会社フロンテック 薄膜トランジスタと液晶表示装置および薄膜トランジスタの製造方法
US9343579B2 (en) * 2013-05-20 2016-05-17 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
CN104022156B (zh) * 2014-05-20 2017-02-15 京东方科技集团股份有限公司 薄膜晶体管、阵列基板及相应的制作方法、显示装置
US9496415B1 (en) * 2015-12-02 2016-11-15 International Business Machines Corporation Structure and process for overturned thin film device with self-aligned gate and S/D contacts
TWI599023B (zh) * 2016-03-14 2017-09-11 友達光電股份有限公司 畫素結構與其製造方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102655200A (zh) * 2011-03-02 2012-09-05 一品光学工业股份有限公司 发光二极管一次光学镜片封装方法及其发光二极管组件
CN102867778A (zh) * 2012-09-17 2013-01-09 上海华力微电子有限公司 一种对40/45纳米工艺金属硬光罩结构的缺陷解决方案
JP2014078618A (ja) * 2012-10-11 2014-05-01 Sharp Corp 光電変換素子および光電変換素子の製造方法
CN103489922A (zh) * 2013-09-30 2014-01-01 京东方科技集团股份有限公司 薄膜晶体管及制备方法、阵列基板及制备方法和显示装置
CN106449518A (zh) * 2016-10-14 2017-02-22 武汉华星光电技术有限公司 Ltps阵列基板的制造方法及阵列基板
CN107359258A (zh) * 2017-06-01 2017-11-17 深圳市华星光电技术有限公司 显示基板及其制造方法、显示装置
CN109285844A (zh) * 2018-10-15 2019-01-29 深圳市华星光电技术有限公司 阵列基板及其制造方法

Also Published As

Publication number Publication date
CN109285844B (zh) 2020-12-25
CN109285844A (zh) 2019-01-29

Similar Documents

Publication Publication Date Title
US10115832B2 (en) Thin film transistor, method for manufacturing the same, array substrate and display device
US9515190B2 (en) Method for manufacturing polysilicon thin film transistor
WO2016176881A1 (zh) 双栅极tft基板的制作方法及其结构
WO2016173027A1 (zh) 薄膜晶体管阵列基板及其制作方法
US9865619B2 (en) Array substrate and manufacturing method thereof
TW201601292A (zh) 製作顯示面板之方法
WO2016090725A1 (zh) 一种ltps阵列基板
WO2019218566A1 (zh) Ltps tft基板的制作方法
US10153377B2 (en) Dual-gate thin film transistor and manufacturing method thereof and array substrate
WO2015161523A1 (zh) 薄膜晶体管及有机发光二极管显示器制备方法
WO2017024612A1 (zh) 氧化物半导体tft基板的制作方法及其结构
US20140206139A1 (en) Methods for fabricating a thin film transistor and an array substrate
US10205029B2 (en) Thin film transistor, manufacturing method thereof, and display device
US20210366942A1 (en) Array substrate and manufacturing method thereof
CN105720012A (zh) 双栅极tft阵列基板及制作方法
WO2016026177A1 (zh) Tft基板的制作方法及其结构
US20160284819A1 (en) Thin film transistor, its manufacturing method and display device
US10957713B2 (en) LTPS TFT substrate and manufacturing method thereof
JP2015515121A (ja) 薄膜トランジスタアレイ基板及びその製造方法
KR101908496B1 (ko) 박막 트랜지스터와 표시장치용 전극기판 및 이들의 제조방법
US11430819B2 (en) Array substrate and manufacturing method thereof
WO2016145726A1 (zh) 一种低温多晶硅薄膜晶体管阵列基板的制作方法
WO2019184026A1 (zh) Cmos晶体管的制备方法、阵列基板的制备方法
WO2016179882A1 (zh) Esl型tft基板结构及其制作方法
WO2020037723A1 (zh) 显示面板及显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19872422

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19872422

Country of ref document: EP

Kind code of ref document: A1