WO2020077848A1 - 一种高纯碳化硅单晶衬底及其制备方法 - Google Patents

一种高纯碳化硅单晶衬底及其制备方法 Download PDF

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WO2020077848A1
WO2020077848A1 PCT/CN2018/123710 CN2018123710W WO2020077848A1 WO 2020077848 A1 WO2020077848 A1 WO 2020077848A1 CN 2018123710 W CN2018123710 W CN 2018123710W WO 2020077848 A1 WO2020077848 A1 WO 2020077848A1
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silicon carbide
carbide single
single crystal
crystal substrate
purity silicon
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PCT/CN2018/123710
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English (en)
French (fr)
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高超
柏文文
张红岩
窦文涛
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山东天岳先进材料科技有限公司
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Priority claimed from CN201811204666.3A external-priority patent/CN109338463B/zh
Priority claimed from CN201811205277.2A external-priority patent/CN109234802B/zh
Application filed by 山东天岳先进材料科技有限公司 filed Critical 山东天岳先进材料科技有限公司
Priority to KR1020197037937A priority Critical patent/KR102345680B1/ko
Priority to JP2019571537A priority patent/JP7239182B2/ja
Priority to EP18922090.8A priority patent/EP3666935B1/en
Publication of WO2020077848A1 publication Critical patent/WO2020077848A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B23/00—Single-crystal growth by condensing evaporated or sublimed materials
    • C30B23/02—Epitaxial-layer growth
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/36—Carbides
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
    • C30B33/02—Heat treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers

Definitions

  • the application relates to a high-purity silicon carbide single crystal substrate and a preparation method thereof, which belong to the field of semiconductor materials.
  • Semi-insulating silicon carbide (silicon carbide) single crystal substrate is the preferred semiconductor base material for the preparation of GaN high-frequency microwave devices. This aspect depends on the excellent properties such as high resistivity of semi-insulating silicon carbide single crystal substrate, and can be prepared with excellent performance Electronic device; on the other hand, it depends on the higher matching degree of the lattice constant of silicon carbide and GaN, which can make the heteroepitaxial layer obtain good crystal quality.
  • the preparation of the semi-insulating silicon carbide single crystal substrate has two implementation methods of doping and high purity.
  • doping a high concentration of vanadium By doping a high concentration of vanadium, a large number of deep level centers are introduced, and the Fermi level is pinned to the center of the forbidden band to achieve semi-insulating characteristics.
  • high-concentration vanadium doping will trap electrons in the fabricated devices, causing back-gate effects, resulting in device performance degradation or even failure.
  • the effective carrier concentration in the crystal is reduced by reducing the concentration of shallow level impurities in the crystal, and a certain number of intrinsic point defects are introduced as compensation for the center of the deep level to achieve high purity of semi-insulating characteristics
  • Semi-insulating silicon carbide single crystal substrates have become mainstream.
  • GaN uses silicon carbide single crystal substrates for epitaxy
  • the introduction of point defects will lead to an increase in the lattice fit between GaN and silicon carbide. This further reduces the quality of the GaN epitaxial layer.
  • the present application provides a high-purity silicon carbide single crystal substrate.
  • the high-purity silicon carbide single crystal substrate of the present application balances the relationship between the crystal quality of the GaN epitaxial layer and the electrical characteristics of the high-purity silicon carbide crystal, and improves the quality of the high-purity silicon carbide single crystal substrate and its epitaxy with GaN
  • the lattice matching degree of the layer does not affect the physical performance of the high-purity semi-insulating silicon carbide single crystal substrate.
  • the high-purity silicon carbide single crystal substrate is characterized in that the high-purity silicon carbide single crystal substrate includes at least a surface layer of a silicon carbide single crystal substrate and a main layer of a silicon carbide single crystal substrate, and the silicon carbide single crystal
  • the intrinsic point defect concentration of the substrate surface layer is less than the intrinsic point defect concentration of the body layer of the silicon carbide single crystal substrate, and the silicon carbide single crystal substrate has a semi-insulating property.
  • the ratio of the thickness of the surface layer of the silicon carbide single crystal substrate to the thickness of the body layer of the silicon carbide single crystal substrate is 1: 4-25.
  • the high-purity silicon carbide single crystal substrate is composed of a silicon carbide single crystal substrate surface layer and a silicon carbide single crystal substrate body layer. Further, the high-purity silicon carbide single crystal substrate is composed of the surface of the silicon carbide single crystal substrate and the main layer of the silicon carbide single crystal substrate.
  • the ratio of the thickness of the surface layer of the silicon carbide single crystal substrate to the thickness of the silicon carbide single crystal substrate is not greater than 31%. Further, the ratio of the thickness of the surface layer of the silicon carbide single crystal substrate to the thickness of the silicon carbide single crystal substrate is 9% -31%. Furthermore, the lower limit of the ratio of the thickness of the surface layer of the silicon carbide single crystal substrate to the thickness of the silicon carbide single crystal substrate is selected from 10%, 15%, 20%, 25% or 30%, and the upper limit is selected from 10%, 15%, 20%, 25% or 30%.
  • the thickness of the semi-insulating silicon carbide single crystal substrate is 490-510 ⁇ m.
  • the intrinsic point defect concentration of the surface layer of the silicon carbide single crystal substrate at room temperature is not higher than 1 ⁇ 10 13 cm ⁇ 3 .
  • the concentration of the intrinsic point defects at the room temperature of the surface layer of the silicon carbide single crystal substrate is not higher than 1 ⁇ 10 12 cm ⁇ 3 .
  • the concentration of the intrinsic point defects of the main layer of the silicon carbide single crystal substrate is 1 ⁇ 10 14 ⁇ 1 ⁇ 10 16 cm ⁇ 3 .
  • the concentration of the intrinsic point defects of the main layer of the silicon carbide single crystal substrate is 1 ⁇ 10 14 to 1 ⁇ 10 15 cm ⁇ 3 .
  • the thickness of the surface layer of the semi-insulating silicon carbide single crystal substrate is not greater than 150 ⁇ m.
  • the thickness of the semi-insulating silicon carbide single crystal surface layer is 20-150 ⁇ m.
  • the surface layer of the high-purity silicon carbide single crystal substrate after annealing treatment has a thickness of 50-150 ⁇ m.
  • the lower limit of the surface layer thickness of the high-purity silicon carbide single crystal substrate subjected to the annealing treatment is selected from 55 ⁇ m, 70 ⁇ m, 90 ⁇ m, 110 ⁇ m, 130 ⁇ m or 140 ⁇ m
  • the upper limit is selected from 55 ⁇ m, 70 ⁇ m, 90 ⁇ m, 110 ⁇ m, 130 ⁇ m or 140 ⁇ m
  • the thickness of the surface layer of the high-purity silicon carbide single crystal substrate after annealing treatment is 80-120 ⁇ m.
  • the surface layer of the silicon carbide single crystal substrate does not substantially contain intrinsic point defects at room temperature, and the concentration of the intrinsic point defects of the main layer of the silicon carbide single crystal substrate makes the high purity silicon carbide single The crystal substrate has semi-insulating properties.
  • the surface layer of the silicon carbide single crystal substrate contains only the intrinsic point defects inherent at the temperature at room temperature, and the concentration of the intrinsic point defects of the main layer of the silicon carbide single crystal substrate makes the high
  • the pure silicon carbide single crystal substrate has semi-insulating properties.
  • the surface layer of the silicon carbide single crystal substrate does not substantially contain intrinsic point defects at room temperature, and the concentration of the intrinsic point defects of the main layer of the silicon carbide single crystal substrate is 1 ⁇ 10 14 ⁇ 1 ⁇ 10 16 cm -3 , the thickness ratio of the surface layer of the silicon carbide single crystal substrate and the main body layer of the silicon carbide single crystal substrate in the high-purity silicon carbide single crystal substrate is 1: 4-25.
  • the surface layer of the silicon carbide single crystal substrate basically does not contain intrinsic point defects at room temperature.
  • the concentration of intrinsic point defects is extremely low. Unless in absolute zero, the intrinsic point defects always exist in the crystal, and the defect concentration is the lowest within a certain thickness. .
  • the lattice of the silicon carbide single crystal on the surface layer of the silicon carbide single crystal substrate has complete integrity.
  • the concentration of the shallow-level impurities in the silicon carbide single crystal substrate is 1 ⁇ 10 14 to 1 ⁇ 10 16 cm ⁇ 3 .
  • the shallow-level impurities include at least one of N, B, and Al.
  • the high-purity silicon carbide single crystal substrate is prepared by a method including the following steps: subjecting the high-purity silicon carbide single wafer to high-temperature rapid heat treatment and surface annealing treatment, that is, to obtain the high-purity carbonization Silicon single crystal substrate.
  • the high-temperature rapid heat treatment includes a rapid temperature increase heating stage and a rapid temperature decrease stage.
  • the rapid temperature-rise heating stage includes the following processing conditions: the temperature is raised to 1800-2300 ° C at a rate of 30-100 ° C / s, and maintained for 60-600s; the rapid temperature-lowering stage includes the following treatment conditions: at 50-150 ° C / s rate cooling to room temperature quickly.
  • the heating rate of the rapid heating step is 50-80 ° C / s.
  • the holding temperature in the rapid heating-up heating stage is 2000-2200 ° C, and the holding time is 100s-500s. Furthermore, the holding temperature in the rapid heating-up heating stage is 2100-2000 ° C, and the holding time is 150s-200s.
  • the rapid cooling stage includes: rapid cooling at a rate of 100-150 ° C / s. Further, the rapid cooling stage includes: rapid cooling at a rate of 100-150 ° C / s.
  • the rapid cooling stage described above can freeze the intrinsic point defects injected in the rapid heating and heating stage in the crystal.
  • the high-temperature rapid heat treatment of the present application injects a certain number of intrinsic point defects into the silicon carbide single wafer to avoid excessive annihilation of intrinsic point defects in the subsequent surface annealing process, affecting the prepared silicon carbide single crystal substrate Semi-insulating characteristics.
  • the surface temperature of the silicon carbide single wafer controlled by the surface annealing treatment is 1200-1800 ° C, and the annealing treatment time is 30-90 min.
  • the lower limit of the surface temperature of the high-purity silicon carbide single wafer controlled by the surface annealing treatment is selected from 1250 ° C, 1300 ° C, 1400 ° C, 1500 ° C, 1600 ° C, 1700 ° C, or 1750 ° C
  • the upper limit is selected from 1250 ° C, 1300 °C, 1400 °C, 1500 °C, 1600 °C, 1700 °C or 1750 °C.
  • the lower limit of the time of the high-purity silicon carbide single wafer controlled by the surface annealing treatment is selected from 35 min, 45 min, 55 min, 65 min, 75 min or 85 min, and the upper limit is selected from 35 min, 45 min, 55 min, 65 min, 75 min or 85 min.
  • the surface temperature of the high-purity silicon carbide single wafer controlled by the surface annealing treatment is 1400-1600 ° C., and the annealing treatment time is 45-60 minutes. Furthermore, the surface temperature of the high-purity silicon carbide single wafer controlled by the surface annealing treatment is 1500-1600 ° C.
  • the surface annealing treatment is to use a surface laser to heat the surface of the silicon carbide single wafer after high temperature rapid heat treatment;
  • the step of laser heating includes: performing reciprocating surface scanning with a laser to scan the surface of the silicon carbide single wafer after high temperature rapid heat treatment Annealing treatment, the laser moving speed is 0.5-3000mm / s.
  • the lower limit of the moving speed of the laser is selected from 1 mm / s, 1000 mm / s, 1500 mm / s, 2000 mm / s or 2500 mm / s
  • the upper limit is selected from 5 mm / s, 1000 mm / s, 1500 mm / s, 2000 mm / s Or 2500mm / s.
  • the moving speed of the laser is 0.5-5 mm / s. The moving speed of the laser enables the laser to heat the substrate surface to a preset temperature but the temperature will not be quickly conducted to the inside of the silicon carbide single crystal substrate, thereby achieving the annealing effect on the surface of the silicon carbide single crystal substrate.
  • the surface annealing treatment includes annealing at least one surface of the silicon carbide single wafer. Further, the surface annealing treatment includes annealing the contact surface with the GaN crystal when growing the GaN crystal on the silicon carbide single crystal substrate.
  • the surface annealing treatment uses a laser to heat the surface of the silicon carbide single wafer after high temperature rapid heat treatment.
  • the wavelength of the laser is less than 352 nm, the pulse width is not greater than 60 ns, and the energy density is not greater than 150 mJ / cm 2 .
  • the wavelength of the laser is less than 352 nm, the pulse width is 20-60 ns, and the energy density is 70-110 mJ / cm 2 .
  • the parameters of the laser of the present application are used to process the surface of the high-purity silicon carbide single wafer with high uniformity.
  • a semiconductor device comprising the high-purity silicon carbide single crystal substrate according to any one of the above.
  • the semiconductor device is an epitaxial wafer or a transistor.
  • the semiconductor device is an epitaxial wafer or a transistor.
  • a method for preparing a high-quality semi-insulating silicon carbide single crystal substrate is provided.
  • the preparation method of the present application balances the relationship between the crystal quality of the GaN epitaxial layer and the electrical characteristics of the high-purity silicon carbide crystal.
  • the preparation method of the new high-purity semi-insulating silicon carbide substrate improves the quality of the semi-insulating silicon carbide single crystal substrate and its lattice matching degree with the GaN epitaxial layer, while not affecting the high-purity semi-insulating silicon carbide single crystal
  • the physical properties of the substrate are realized.
  • the high-purity silicon carbide single wafer is subjected to high-temperature rapid heat treatment and surface annealing treatment, that is, the high-quality semi-insulating silicon carbide single crystal substrate is prepared; the high-quality semi-insulating silicon carbide single crystal substrate It includes at least a surface layer of a silicon carbide single crystal substrate and a body layer of a silicon carbide single crystal substrate.
  • the ratio of the thickness of the surface layer of the silicon carbide single crystal substrate to the thickness of the silicon carbide single crystal substrate is not greater than 31%. Further, the ratio of the thickness of the surface layer of the silicon carbide single crystal substrate to the thickness of the silicon carbide single crystal substrate is 9% -31%. Furthermore, the lower limit of the ratio of the thickness of the surface layer of the silicon carbide single crystal substrate to the thickness of the silicon carbide single crystal substrate is selected from 10%, 15%, 20%, 25% or 30%, and the upper limit is selected from 10%, 15%, 20%, 25% or 30%.
  • the thickness of the semi-insulating silicon carbide single crystal substrate is 490-510 ⁇ m.
  • the thickness of the semi-insulating silicon carbide single crystal surface layer is not greater than 150 ⁇ m.
  • the thickness of the surface layer of the semi-insulating silicon carbide single crystal substrate after annealing treatment is 20-150 ⁇ m.
  • the thickness of the surface layer of the semi-insulating silicon carbide single crystal substrate after annealing treatment is 50-150 ⁇ m.
  • the lower limit of the thickness of the annealed surface layer of the semi-insulating silicon carbide single crystal substrate is selected from 55 ⁇ m, 70 ⁇ m, 90 ⁇ m, 110 ⁇ m, 130 ⁇ m or 140 ⁇ m
  • the upper limit is selected from 55 ⁇ m, 70 ⁇ m, 90 ⁇ m, 110 ⁇ m, 130 ⁇ m or 140 ⁇ m
  • the thickness of the surface layer of the semi-insulating silicon carbide single crystal substrate after annealing treatment is 80-120 ⁇ m.
  • the high-temperature rapid heat treatment includes a rapid heating-up heating stage, and the rapid heating-up heating stage includes: heating to 1800-2300 ° C at a rate of 30-100 ° C / s and maintaining it for 60-600s.
  • the heating rate of the rapid heating step is 50-80 ° C / s.
  • the holding temperature in the rapid heating-up heating stage is 2000-2200 ° C., and the holding time is 100-500 s. Furthermore, the holding temperature in the rapid heating-up heating stage is 2000-2100 ° C., and the holding time is 150-200 s.
  • the high-temperature rapid heat treatment further includes a rapid cooling stage, and the rapid cooling stage includes rapid cooling at a rate of 50-150 ° C / s. Further, the rapid cooling stage includes: rapid cooling at a rate of 100-150 ° C / s.
  • the rapid cooling stage described above can freeze the intrinsic point defects injected in the rapid heating and heating stage in the crystal.
  • the high-temperature rapid heat treatment of the present application injects a certain number of intrinsic point defects into a high-purity silicon carbide single wafer to avoid excessive annihilation of intrinsic point defects during subsequent surface annealing, which affects the preparation of semi-insulating silicon carbide single The semi-insulating properties of the crystal substrate.
  • the surface temperature of the high-purity silicon carbide single wafer controlled by the surface annealing treatment is 1200-1800 ° C, and the annealing treatment time is 30-90 min.
  • the lower limit of the surface temperature of the high-purity silicon carbide single wafer controlled by the surface annealing treatment is selected from 1250 ° C, 1300 ° C, 1400 ° C, 1500 ° C, 1600 ° C, 1700 ° C, or 1750 ° C
  • the upper limit is selected from 1250 ° C, 1300 °C, 1400 °C, 1500 °C, 1600 °C, 1700 °C or 1750 °C.
  • the lower limit of the time of the high-purity silicon carbide single wafer controlled by the surface annealing treatment is selected from 35 min, 45 min, 55 min, 65 min, 75 min or 85 min, and the upper limit is selected from 35 min, 45 min, 55 min, 65 min, 75 min or 85 min.
  • the surface temperature of the high-purity silicon carbide single wafer controlled by the surface annealing treatment is 1400-1600 ° C., and the annealing treatment time is 45-60 minutes. Furthermore, the surface temperature of the high-purity silicon carbide single wafer controlled by the surface annealing treatment is 1500-1600 ° C.
  • the surface annealing treatment includes annealing at least one surface of the high-purity silicon carbide single wafer. Further, the surface annealing treatment includes annealing the contact surface with the GaN crystal when the high purity silicon carbide single crystal substrate grows the GaN crystal.
  • the surface annealing treatment uses a laser to heat the surface of the high-purity silicon carbide single wafer after high-temperature rapid heat treatment.
  • the heating step of the laser includes: reciprocating surface scan of a high-purity silicon carbide single wafer subjected to high-temperature rapid heat treatment by a laser for surface annealing treatment, and the moving speed of the laser is 0.5-3000 mm / s.
  • the lower limit of the moving speed of the laser is selected from 1 mm / s, 1000 mm / s, 1500 mm / s, 2000 mm / s or 2500 mm / s
  • the upper limit is selected from 5 mm / s, 1000 mm / s, 1500 mm / s, 2000 mm / s Or 2500mm / s.
  • the moving speed of the laser is 0.5-5 mm / s.
  • the moving speed of the laser enables the laser to heat the surface of the substrate to a preset temperature but the temperature will not be quickly conducted to the inside of the semi-insulating silicon carbide single crystal substrate, thereby achieving the annealing effect on the surface of the semi-insulating silicon carbide single crystal substrate.
  • the wavelength of the laser is less than 352 nm, the pulse width is not greater than 60 ns, and the energy density is not greater than 150 mJ / cm 2 .
  • the wavelength of the laser is less than 352 nm, the pulse width is 20-60 ns, and the energy density is 70-110 mJ / cm 2 .
  • the parameters of the laser of the present application are used to process high-purity silicon carbide single wafers with high surface uniformity.
  • the step 1) a method for preparing a high-purity silicon carbide single wafer includes the following steps: after the high-purity silicon carbide single crystal is prepared through the impurity removal and growth phases of silicon carbide powder, cutting, grinding and polishing are performed To produce high-purity silicon carbide single wafers.
  • the low concentration of intrinsic point defects in the surface layer of the high-purity silicon carbide single crystal substrate of the present application makes the lattice matching degree of GaN and silicon carbide single crystal higher when the high-purity silicon carbide single crystal is used as the epitaxial substrate for GaN epitaxy , So that the quality of the prepared GaN epitaxial layer is higher; and the main layer of the high purity silicon carbide single crystal has a certain concentration of internal point defects, which can maintain the semi-insulating characteristics of the high purity silicon carbide single crystal substrate.
  • the preparation of the high-purity silicon carbide single crystal substrate of the present application uses high-temperature rapid heat treatment technology and surface laser annealing technology to remove the point defects introduced into a certain area on the surface of the high-purity semi-insulating silicon carbide substrate while keeping the distance from the substrate The internal point defects on the surface, so as to achieve a clean area on the surface of the substrate without defects and retain the semi-insulating characteristics of the high-purity silicon carbide single crystal substrate, so that the GaN epitaxial layer obtains the best quality.
  • the high-purity semi-insulating silicon carbide substrate of the present application balances the relationship between the crystal quality of the GaN epitaxial layer and the electrical properties of the high-purity silicon carbide crystal, and improves the quality of the high-purity silicon carbide single crystal substrate and its relationship with the GaN epitaxial layer
  • the lattice matching degree does not affect the physical properties of high-purity semi-insulating silicon carbide single crystal substrate.
  • FIG. 1 is a schematic diagram of high-temperature rapid heat treatment for preparing a high-purity silicon carbide single crystal substrate of the present application.
  • FIG. 2 is a schematic diagram of surface annealing treatment for preparing a high-purity silicon carbide single crystal substrate of the present application.
  • FIG. 3 is a schematic diagram showing the concentration of intrinsic point defects in a high-purity silicon carbide single wafer prepared by the present application, a high-purity silicon carbide single wafer subjected to high-temperature rapid heat treatment and a high-purity silicon carbide single crystal substrate.
  • the resistivity test uses Semimap's COREMA-WT non-contact semi-insulation resistivity tester.
  • the crystal type test adopts the HR800 type confocal Raman spectrometer of Horiba Company.
  • the surface test of silicon carbide single crystal substrate adopts MicroProf @ TTV200 type automatic surface tester of FRT company.
  • the element content test uses Cameca's IMS 7f-Auto secondary ion mass spectrometry instrument.
  • the preparation of the high-purity silicon carbide single wafer of the present application may be prepared by a method in the art, and the following preparation method of the high-purity silicon carbide single wafer may be used.
  • the method includes the following steps:
  • the purity of silicon carbide powder should be above 99.9999%, and the concentration of shallow-level donor impurities such as nitrogen contained in it should be below 1 ⁇ 10 16 cm -3 ,
  • the sum of the acceptor impurities such as boron and aluminum in the shallow energy level should be less than 1 ⁇ 10 16 cm -3 ;
  • the furnace pressure is increased to 10-100 mbar at a rate of 30-50 mbar / h, and the temperature in the furnace is increased to 2100-2200 °C at a rate of 10-20 °C / h, and maintained at this temperature for 50-100 h, Complete the growth process of silicon carbide single crystal;
  • a method for preparing a high-purity silicon carbide single wafer includes the following steps:
  • the purity of silicon carbide powder should be above 99.9999%, and the concentration of shallow-level donor impurities such as nitrogen contained in it should be below 1 ⁇ 10 16 cm -3 ,
  • the sum of the acceptor impurities such as boron and aluminum in the shallow energy level should be less than 1 ⁇ 10 16 cm -3 ;
  • the high-purity silicon carbide single wafer 1 # prepared by the above method is used to prepare a high-purity silicon carbide single crystal substrate.
  • the preparation method includes the following steps:
  • the obtained high-purity silicon carbide single wafer is subjected to high-temperature rapid heat treatment and a laser is used to perform reciprocating scanning annealing on the surface of the high-purity silicon carbide single wafer to obtain a high-purity silicon carbide single crystal substrate.
  • the temperature of the surface of the high-purity silicon carbide single wafer is controlled by controlling the power of the laser, the amount of defocus and the area of laser heat treatment.
  • FIG. 1 The schematic diagram of the high-temperature rapid heat treatment for preparing a high-purity silicon carbide single crystal substrate of this embodiment is shown in FIG. 1, where T is temperature and t is time.
  • FIG. 2 The schematic diagram of the surface annealing process for preparing a high-purity silicon carbide single crystal substrate of this embodiment is shown in FIG. 2, 1 is a laser, 2 is a high-purity silicon carbide single wafer, and the laser 1 is on the surface of the high-purity silicon carbide single wafer 2 The surface of the high-purity silicon carbide single wafer 2 is heated by reciprocating at a certain rate.
  • FIG. 3 The schematic diagram of the change in the concentration of intrinsic point defects from the semi-insulating silicon carbide single wafer to the high purity silicon carbide single crystal substrate product in this application is shown in FIG. 3, in which the high purity silicon carbide single wafer, high purity after high temperature rapid heat treatment
  • the concentration schematic diagrams of the intrinsic point defects in the silicon carbide single wafer and the high-purity silicon carbide single crystal substrate are shown in FIGS. 3a, 3b, and 3c, respectively.
  • 3 in FIG. 3 represents intrinsic point defects
  • 4 is the surface layer of the high-purity silicon carbide single crystal substrate
  • 5 is the main layer of the high-purity silicon carbide single crystal.
  • the high-temperature rapid heat treatment of the present application implants a certain number of intrinsic point defects 3 (as shown in FIG.
  • the high-purity silicon carbide single crystal substrate is annealed using KrF pulse laser irradiation to control the energy density of the high-purity silicon carbide single crystal substrate to be no more than 150 mJ / cm 2 .
  • High purity silicon carbide single crystal substrate 1 #, high purity silicon carbide single crystal substrate 1 #, high purity silicon carbide single crystal substrate 2 #, high purity silicon carbide were prepared according to the above method and the specific parameters shown in Table 1 Single crystal substrate 3 #, high purity silicon carbide single crystal substrate 4 # and high purity silicon carbide single crystal substrate 5 #.
  • the specific preparation parameters and substrate properties of high-purity silicon carbide single crystal substrate 1 # -5 # are shown in Table 1.
  • the intrinsic point defect concentration of the surface layer of the silicon carbide single crystal substrate of the high purity silicon carbide single crystal substrate 1 # -5 # is smaller than the intrinsic point defect concentration of the body layer of the silicon carbide single crystal substrate, and the prepared silicon carbide The single crystal substrate 1 # -5 # is semi-insulating.
  • the high-purity silicon carbide single crystal substrate 1 # surface layer has a very low concentration of spot defect defects, and has good lattice integrity.
  • the high-purity silicon carbide single crystal substrate 1 # main layer has an intrinsic point defect concentration that makes the The high-purity silicon carbide single crystal substrate has semi-insulating properties.
  • the concentration of intrinsic point defects in the surface layer of silicon carbide single crystal substrate is extremely low at room temperature. Unless in absolute zero, intrinsic point defects always exist in the crystal, and the concentration of intrinsic point defects is the lowest within a certain thickness.
  • the resistivity of the 4-12 inch semi-insulating silicon carbide single crystal substrate prepared in this application can reach more than 2 ⁇ 10 11 ⁇ ⁇ cm, and the radial distribution of resistivity is controlled within 2 orders of magnitude, so as to realize the semi-insulating silicon carbide single
  • the resistivity of the crystal substrate is evenly distributed.
  • the curvature and warpage are tested, and the curvature and warpage can be controlled within 45 ⁇ m.
  • the same size of high-purity silicon carbide single crystal substrate 1 # -5 # and high-purity silicon carbide single wafer 1 # prepared in Example 1 were used as the substrates for preparing GaN single crystal epitaxial wafers respectively. method.
  • the crystal quality of the GaN single crystal made from the high purity silicon carbide single crystal substrate 1 # -5 # is higher than that of the GaN single crystal epitaxial wafer made with the high purity silicon carbide single wafer 1 # as the base, specific data As shown in table 2.

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Abstract

本申请公开了一种高纯碳化硅单晶衬底及其制备方法，属于半导体材料领域。该高纯碳化硅单晶衬底至少包括碳化硅单晶衬底表层和碳化硅单晶衬底主体层，该碳化硅单晶衬底表层的本征点缺陷浓度小于该碳化硅单晶衬底本体层的本征点缺陷浓度，所述碳化硅单晶衬底具有半绝缘性。该制备方法通过对高纯碳化硅单晶晶片进行高温快速热处理技术和表面激光退火技术，将引入到高纯半绝缘碳化硅衬底表面一定区域内的点缺陷进行清除，同时保留距离衬底表面的内部点缺陷，从而实现在无缺陷的碳化硅单晶衬底表层洁净区并保留碳化硅单晶衬底的半绝缘特性，且制备的GaN外延层的获得最佳的质量。

Description

一种高纯碳化硅单晶衬底及其制备方法 技术领域
本申请涉及一种高纯碳化硅单晶衬底及其制备方法，属于半导体材料领域。
背景技术
半绝缘碳化硅(碳化硅)单晶衬底是制备GaN高频微波器件的优选半导体基底材料，这一方面取决于半绝缘碳化硅单晶衬底的高电阻率等优异性能，能够制备性能优异的电子器件；另一方面取决于碳化硅和GaN晶格常数的较高的匹配度，能够使异质外延层获得良好的结晶质量。
从实现方法上来讲，半绝缘碳化硅单晶衬底的制备有掺杂和高纯两种实现方式。通过掺杂高浓度的钒元素引入大量深能级中心，将费米能级钉扎在禁带中心从而实现半绝缘特性。目前已有研究表明，高浓度的钒掺杂会在制备的器件中俘获电子从而引起背栅效应，造成器件性能降低甚至失效。随着技术的发展，通过降低晶体中的浅能级杂质浓度减少晶体中的有效载流子浓度，同时引入一定数量的本征点缺陷作为深能级中心进行补偿从而实现半绝缘特性的高纯半绝缘碳化硅单晶衬底成为主流。
高纯半绝缘碳化硅单晶衬底的高阻特性的实现建立在晶体内部低浓度的电活性杂质和一定浓度的本征点缺陷如碳空位及其复合体的基础上。本征点缺陷是实现高纯半绝缘晶体的电学特性的不可或缺的特征，然而，这些点缺陷本身会引入较大的晶格应力，造成晶格畸变，从而破坏了碳化硅单晶晶格的完整性，在一定程度上影响碳化硅单晶的晶格参数。考虑到GaN采用碳化硅单晶衬底作为外延的主要原因之一即是两者晶格参 数较小的失配度，点缺陷的引入将会导致GaN和碳化硅的晶格适配度增加，进而降低GaN外延层的质量。
发明内容
为了解决上述问题，本申请提供了一种高纯碳化硅单晶衬底。本申请的高纯碳化硅单晶衬底平衡了GaN外延层的晶体质量与高纯碳化硅晶体的电学特性之间的关系，提高了高纯碳化硅单晶衬底的质量及其与GaN外延层的晶格匹配度，同时不影响高纯半绝缘碳化硅单晶衬底的物理性能实现。
该高纯碳化硅单晶衬底，其特征在于，所述的高纯碳化硅单晶衬底至少包括碳化硅单晶衬底表层和碳化硅单晶衬底主体层，所述碳化硅单晶衬底表层的本征点缺陷浓度小于所述碳化硅单晶衬底本体层的本征点缺陷浓度，所述碳化硅单晶衬底具有半绝缘性。
可选地，所述碳化硅单晶衬底表层厚度和碳化硅单晶衬底主体层的厚度比例为1：4‐25。
可选地，所述的高纯碳化硅单晶衬底由碳化硅单晶衬底表层和碳化硅单晶衬底主体层构成。进一步地，所述的高纯碳化硅单晶衬底由碳化硅单晶衬底表面和碳化硅单晶衬底主体层构成。
可选地，所述碳化硅单晶衬底表层厚度与所述碳化硅单晶衬底厚度的比值不大于31％。进一步地，所述碳化硅单晶衬底表层厚度与所述碳化硅单晶衬底厚度的比值为9％‐31％。更进一步地，所述碳化硅单晶衬底表层厚度与所述碳化硅单晶衬底厚度的比值下限选自10％、15％、20％、25％或30％，上限选自10％、15％、20％、25％或30％。
可选地，所述半绝缘碳化硅单晶衬底的厚度为490‐510μm。
可选地，所述碳化硅单晶衬底表层室温下的本征点缺陷浓度不高于1×10 13cm ‐3。优选地，所述碳化硅单晶衬底表层室温下的本征点缺陷的浓 度不高于1×10 12cm ‐3。
可选地，所述碳化硅单晶衬底主体层的本征点缺陷的浓度为1×10 14～1×10 16cm ‐3。优选地，所述碳化硅单晶衬底主体层的本征点缺陷的浓度为1×10 14～1×10 15cm ‐3。
可选地，所述半绝缘碳化硅单晶衬底表层的厚度不大于150μm。可选地，所述半绝缘碳化硅单晶表层的厚度为20‐150μm。优选地，所述高纯碳化硅单晶衬底经退火处理的表层厚度为50‐150μm。进一步地，该高纯碳化硅单晶衬底经退火处理的表层厚度的下限选自55μm、70μm、90μm、110μm、130μm或140μm，上限选自55μm、70μm、90μm、110μm、130μm或140μm。更进一步地，所述高纯碳化硅单晶衬底经退火处理的表层厚度为80‐120μm。
可选地，所述碳化硅单晶衬底表层室温下基本不含有本征点缺陷，所述的碳化硅单晶衬底主体层的本征点缺陷的浓度使得所述的高纯碳化硅单晶衬底具有半绝缘性。
可选地，所述碳化硅单晶衬底表层室温下仅含有该温度下固有的本征点缺陷，所述的碳化硅单晶衬底主体层的本征点缺陷的浓度使得所述的高纯碳化硅单晶衬底具有半绝缘性。
作为一种实施方式，所述碳化硅单晶衬底表层室温下基本不含有本征点缺陷，所述碳化硅单晶衬底主体层的本征点缺陷的浓度为1×10 14～1×10 16cm ‐3，所述的高纯碳化硅单晶衬底中的碳化硅单晶衬底表层和碳化硅单晶衬底主体层的厚度比为1：4‐25。所述碳化硅单晶衬底表层室温下基本不含有本征点缺陷是本征点缺陷浓度极低，本征点缺陷除非在绝对零度下，否则始终存在于晶体中，一定厚度内缺陷浓度最低。
优选地，所述碳化硅单晶衬底表层的碳化硅单晶的晶格具有完全的完整性。
可选地，所述碳化硅单晶衬底中的浅能级杂质的浓度为1×10 14～1×10 16cm ‐3。进一步地，所述浅能级杂质包括N、B、Al中的至少一种。
可选地，所述的高纯碳化硅单晶衬底由包括下述步骤的方法制备得到：将高纯碳化硅单晶片进行高温快速热处理和表面退火处理，即制得所述的高纯碳化硅单晶衬底。
可选地，所述高温快速热处理包括快速升温加热阶段和快速降温阶段。
优选地，所述快速升温加热阶段包括以下处理条件：以30‐100℃/s的速率升温至1800‐2300℃，保持60‐600s；所述快速降温阶段包括以下处理条件：以50‐150℃/s速率快速冷却至室温。
进一步地，所述快速升温加热阶段的升温速率为50‐80℃/s。
进一步地，所述快速升温加热阶段的保持温度为2000‐2200℃，保持时间为100s‐500s。更进一步地，所述快速升温加热阶段的保持温度为2100‐2000℃，保持时间为150s‐200s。
进一步地，所述快速降温阶段包括：以100‐150℃/s速率快速冷却。进一步地，所述快速降温阶段包括：以100‐150℃/s速率快速冷却。所述的快速降温阶段可以将快速升温加热阶段注入的本征点点缺陷冻结在晶体中。
本申请的高温快速热处理在碳化硅单晶片中注入一定数量的本征点缺陷，以避免在后续的表面退火的过程中造成过量的本征点缺陷湮灭，影响制备的碳化硅单晶衬底的半绝缘特性。
优选地，所述表面退火处理控制的碳化硅单晶片的表面温度为1200‐1800℃，退火处理的时间为30‐90min。
进一步地，该表面退火处理控制的高纯碳化硅单晶片的表面温度的下限选自1250℃、1300℃、1400℃、1500℃、1600℃、1700℃或1750℃， 上限选自1250℃、1300℃、1400℃、1500℃、1600℃、1700℃或1750℃。
进一步地，该表面退火处理控制的高纯碳化硅单晶片的时间的下限选自35min、45min、55min、65min、75min或85min，上限选自35min、45min、55min、65min、75min或85min。
优选地，所述表面退火处理控制的高纯碳化硅单晶片的表面温度为1400‐1600℃，退火处理的时间为45‐60min。更进一步地，所述表面退火处理控制的高纯碳化硅单晶片的表面温度为1500‐1600℃。
优选地，所述表面退火处理为使用表面激光加热经高温快速热处理后的碳化硅单晶片表面；所述激光加热的步骤包括：通过激光进行往复面扫描经过高温快速热处理的碳化硅单晶片进行表面退火处理，所述激光移动速率为0.5‐3000mm/s。
进一步地，所述激光器移动速率的下限选自1mm/s、1000mm/s、1500mm/s、2000mm/s或2500mm/s，上限选自5mm/s、1000mm/s、1500mm/s、2000mm/s或2500mm/s。更进一步地，所述激光器移动速率为0.5‐5mm/s。该激光器移动速率使得激光能够加热衬底表面至预设温度但温度不会快速传导至碳化硅单晶衬底内部，从而实现对碳化硅单晶衬底表面的退火效果。
可选地，所述表面退火处理包括至少退火处理碳化硅单晶片的一个表面。进一步地，所述表面退火处理包括退火处理碳化硅单晶衬底生长GaN晶体时与GaN晶体的接触面。
可选地，所述表面退火处理为使用激光器加热经高温快速热处理后的碳化硅单晶片表面。
可选地，所述激光器的波长小于352nm，脉冲宽度不大于60ns，能量密度不大于150mJ/cm 2。优选地，所述激光器的波长小于352nm，脉冲宽度20‐60ns，能量密度70‐110mJ/cm 2。使用本申请的激光器的参数处 理高纯碳化硅单晶片的表面的均匀度高。
根据本申请的另一方面，提供了一种半导体器件，其包含上述任一项所述的高纯碳化硅单晶衬底。
优选地，所述半导体器件为外延晶片或晶体管。
根据本申请的又一方面，提供了由上述任一种所述的高纯碳化硅单晶衬底在制备半导体器件中的应用。
优选地，所述半导体器件为外延晶片或晶体管。
根据本申请的又一方面，提供了一种制备高质量的半绝缘碳化硅单晶衬底的方法。本申请的制备方法平衡了GaN外延层的晶体质量与高纯碳化硅晶体的电学特性之间的关系。该新的高纯半绝缘碳化硅衬底的制备方法，提高了半绝缘碳化硅单晶衬底的质量及其与GaN外延层的晶格匹配度，同时不影响高纯半绝缘碳化硅单晶衬底的物理性能实现。
该制备高质量的半绝缘碳化硅单晶衬底的方法，其特征在于，所述方法包括下述步骤：
1)选择高纯碳化硅单晶片；
2)将高纯碳化硅单晶片进行高温快速热处理和表面退火处理，即制得所述的高质量的半绝缘碳化硅单晶衬底；所述的高质量的半绝缘碳化硅单晶衬底至少包括碳化硅单晶衬底表层和碳化硅单晶衬底主体层。
可选地，所述碳化硅单晶衬底表层厚度与所述碳化硅单晶衬底厚度的比值不大于31％。进一步地，所述碳化硅单晶衬底表层厚度与所述碳化硅单晶衬底厚度的比值为9％‐31％。更进一步地，所述碳化硅单晶衬底表层厚度与所述碳化硅单晶衬底厚度的比值下限选自10％、15％、20％、25％或30％，上限选自10％、15％、20％、25％或30％。
可选地，所述半绝缘碳化硅单晶衬底的厚度为490‐510μm。
可选地，所述半绝缘碳化硅单晶表层的厚度不大于150μm。优选地， 所述半绝缘碳化硅单晶衬底经退火处理的表层厚度为20‐150μm。优选地，所述半绝缘碳化硅单晶衬底经退火处理的表层厚度为50‐150μm。进一步地，该半绝缘碳化硅单晶衬底经退火处理的表层厚度的下限选自55μm、70μm、90μm、110μm、130μm或140μm，上限选自55μm、70μm、90μm、110μm、130μm或140μm。更进一步地，所述半绝缘碳化硅单晶衬底经退火处理的表层厚度为80‐120μm。
可选地，所述高温快速热处理包括快速升温加热阶段，所述快速升温加热阶段包括：以30‐100℃/s的速率升温至1800‐2300℃，保持60‐600s。
进一步地，所述快速升温加热阶段的升温速率为50‐80℃/s。
进一步地，所述快速升温加热阶段的保持温度为2000‐2200℃，保持时间为100‐500s。更进一步地，所述快速升温加热阶段的保持温度为2000‐2100℃，保持时间为150‐200s。
可选地，所述高温快速热处理还包括快速降温阶段，所述快速降温阶段包括以50‐150℃/s速率快速冷却。进一步地，所述快速降温阶段包括：以100‐150℃/s速率快速冷却。所述的快速降温阶段可以将快速升温加热阶段注入的本征点点缺陷冻结在晶体中。
本申请的高温快速热处理在高纯碳化硅单晶片中注入一定数量的本征点缺陷，以避免在后续的表面退火的过程中造成过量的本征点缺陷湮灭，影响制备的半绝缘碳化硅单晶衬底的半绝缘特性。
可选地，所述表面退火处理控制的高纯碳化硅单晶片的表面温度为1200‐1800℃，退火处理的时间为30‐90min。
进一步地，该表面退火处理控制的高纯碳化硅单晶片的表面温度的下限选自1250℃、1300℃、1400℃、1500℃、1600℃、1700℃或1750℃，上限选自1250℃、1300℃、1400℃、1500℃、1600℃、1700℃或1750℃。
进一步地，该表面退火处理控制的高纯碳化硅单晶片的时间的下限 选自35min、45min、55min、65min、75min或85min，上限选自35min、45min、55min、65min、75min或85min。
优选地，所述表面退火处理控制的高纯碳化硅单晶片的表面温度为1400‐1600℃，退火处理的时间为45‐60min。更进一步地，所述表面退火处理控制的高纯碳化硅单晶片的表面温度为1500‐1600℃。
可选地，所述表面退火处理包括至少退火处理高纯碳化硅单晶片的一个表面。进一步地，所述表面退火处理包括退火处理高纯碳化硅单晶衬底生长GaN晶体时与GaN晶体的接触面。
可选地，所述表面退火处理为使用激光器加热经高温快速热处理后的高纯碳化硅单晶片表面。
可选地，所述激光器加热的步骤包括：通过激光器进行往复面扫描经过高温快速热处理的高纯碳化硅单晶片进行表面退火处理，所述激光器移动速率为0.5‐3000mm/s。进一步地，所述激光器移动速率的下限选自1mm/s、1000mm/s、1500mm/s、2000mm/s或2500mm/s，上限选自5mm/s、1000mm/s、1500mm/s、2000mm/s或2500mm/s。更进一步地，所述激光器移动速率为0.5‐5mm/s。该激光器移动速率使得激光能够加热衬底表面至预设温度但温度不会快速传导至半绝缘碳化硅单晶衬底内部，从而实现对半绝缘碳化硅单晶衬底表面的退火效果。
可选地，所述激光器的波长小于352nm，脉冲宽度不大于60ns，能量密度不大于150mJ/cm 2。优选地，所述激光器的波长小于352nm，脉冲宽度20‐60ns，能量密度70‐110mJ/cm 2。使用本申请的激光器的参数处理高纯碳化硅单晶片的表面均匀度高。
可选地，所述步骤1)高纯碳化硅单晶片的制备方法包括如下步骤：将碳化硅粉料经除杂、长晶阶段制得高纯碳化硅单晶后，进行切割、研磨和抛光，制得高纯碳化硅单晶片。
本申请的有益效果包括但不限于：
本申请的高纯碳化硅单晶衬底表层的本征点缺陷的低浓度，使得高纯碳化硅单晶作为GaN外延的外延基底时，GaN和碳化硅单晶的晶格适配度更高，使得制备的GaN外延的层的质量更高；且高纯碳化硅单晶的主体层具有一定浓度的内部点缺陷，可以保持高纯碳化硅单晶衬底的半绝缘特性。
本申请的高纯碳化硅单晶衬底的制备通过高温快速热处理技术和表面激光退火技术，将引入到高纯半绝缘碳化硅衬底表面一定区域内的点缺陷进行清除，同时保留距离衬底表面的内部点缺陷，从而实现在无缺陷的衬底表层洁净区并保留高纯碳化硅单晶衬底的半绝缘特性，从而使GaN外延层获得最佳的质量。
本申请的高纯半绝缘碳化硅衬底平衡了GaN外延层的晶体质量与高纯碳化硅晶体的电学之间的关系，提高了高纯碳化硅单晶衬底的质量及其与GaN外延层的晶格匹配度，同时不影响高纯半绝缘碳化硅单晶衬底的物理性能实现。
附图说明
图1为本申请制备高纯碳化硅单晶衬底的高温快速热处理的示意图。
图2为本申请制备高纯碳化硅单晶衬底的表面退火处理示意图。
图3为本申请制备的高纯碳化硅单晶片、经高温快速热处理的高纯碳化硅单晶片和高纯碳化硅单晶衬底中含本征点缺陷的浓度示意图。
具体实施方式
下面结合实施例详述本申请，但本申请并不局限于这些实施例。
如无特别说明，本申请的实施例中涉及的原料等均通过商业途径购买。
本申请的实施例中分析方法如下：
电阻率测试采用Semimap公司的COREMA‐WT型非接触式半绝缘电阻率测试仪。
晶型测试采用Horiba公司的HR800型共聚焦拉曼光谱仪。
碳化硅单晶衬底的面型测试采用FRT公司的MicroProf@TTV200型全自动面型测试仪。
元素含量测试采用Cameca公司的IMS 7f‐Auto型二次离子质谱仪器。
本申请的高纯碳化硅单晶片的制备利用本领域内的方法制备即可，可使用下述高纯碳化硅单晶片的制备方法，该方法包括下述步骤：
①、将一定数量的碳化硅粉料置于石墨坩埚内，碳化硅粉料纯度应在99.9999％以上，其中所含的浅能级施主杂质如氮的浓度在1×10 16cm ‐3以下，浅能级受主杂质如硼、铝等浓度之和应在1×10 16cm ‐3以下；
②、将用于生长碳化硅单晶的籽晶置于石墨坩埚内部的碳化硅粉料上部后，将石墨坩埚密封；密封后的石墨坩埚放置于石墨保温毡内部后，整体移至单晶生长设备内后密封炉膛；
③、将炉膛内的压力抽真空至10 ‐5Pa并保持5‐10h，以去除炉腔内的残余杂质后，逐步向炉腔内通入保护气氛，例如氩气或氦气；
④、以30‐50mbar/h的速率将炉膛压力提升至10‐100mbar，同时以10‐20℃/h的速率将炉膛内的温度提升至2100‐2200℃，在此温度下保持50‐100h，完成碳化硅单晶的生长过程；
⑤、单晶生长过程结束后，停止加热炉膛，使炉膛温度自然降低至室温后，打开炉膛取出石墨坩埚，即可得所述的高纯碳化硅单晶，继续进行切割和抛光过程即制得高纯碳化硅单晶片。
实施例1 高纯碳化硅单晶衬底的制备
作为一种实施方式，高纯碳化硅单晶片的制备方法，该方法包括下 述步骤：
①、将一定数量的碳化硅粉料置于石墨坩埚内，碳化硅粉料纯度应在99.9999％以上，其中所含的浅能级施主杂质如氮的浓度在1×10 16cm ‐3以下，浅能级受主杂质如硼、铝等浓度之和应在1×10 16cm ‐3以下；
②、将用于生长碳化硅单晶的籽晶置于石墨坩埚内部的碳化硅粉料上部后，将石墨坩埚密封；密封后的石墨坩埚放置于石墨保温毡内部后，整体移至单晶生长设备内后密封炉膛；
③、将炉膛内的压力抽真空至10 ‐5Pa并保持8h，以去除炉腔内的残余杂质后，逐步向炉腔内通入氩气；
④、以40mbar/h的速率将炉膛压力提升至50mbar，同时以15℃/h的速率将炉膛内的温度提升至2100‐2200℃，在此温度下保持80h，完成碳化硅单晶的生长过程；
⑤、单晶生长过程结束后，停止加热炉膛，使炉膛温度自然降低至室温后，打开炉膛取出石墨坩埚，即可得所述的高纯碳化硅单晶，继续进行切割和抛光过程即制得高纯碳化硅单晶片1#。
使用上述方法制备的高纯碳化硅单晶片1#制备高纯碳化硅单晶衬底，该制备方法包括下述步骤：
1)将制得的高纯碳化硅单晶片进行高温快速热处理和使用激光器对高纯碳化硅单晶片的表面进行往复扫描退火，即制得高纯碳化硅单晶衬底。
通过控制激光器的功率、离焦量和激光热处理面积等的值控制高纯碳化硅单晶片表面的温度。
本实施方式的制备高纯碳化硅单晶衬底的高温快速热处理的示意图如图1所示，T为温度，t为时间。
本实施方式的制备高纯碳化硅单晶衬底的表面退火处理示意图如图 2所示，1为激光器，2为高纯碳化硅单晶片，激光器1在高纯碳化硅单晶片2的表面以一定速率往复移动加热高纯碳化硅单晶片2的表面。
本申请由半绝缘碳化硅单晶片到高纯碳化硅单晶衬底产品的本征点缺陷的浓度变化示意图如图3所示，其中，高纯碳化硅单晶片、经高温快速热处理的高纯碳化硅单晶片和高纯碳化硅单晶衬底中本征点缺陷的浓度示意图分别如图3a、图3b和图3c所示。图3中的3代表本征点缺陷，4为高纯碳化硅单晶衬底表层，5为高纯碳化硅单晶主体层。本申请的高温快速热处理在高纯碳化硅单晶片(如图3a)中注入一定数量的本征点缺陷3(如图3b)，以避免在后续的表面退火的过程中造成过量的本征点缺陷3湮灭，影响制备的高纯碳化硅单晶衬底(如图3c)的半绝缘特性。本申请的高纯碳化硅单晶衬底(如图3c)的制备通过高温快速热处理技术和表面激光退火技术，将引入到高纯半绝缘碳化硅衬底表面4一定区域内的点缺陷进行清除，同时保留距离衬底表面的内部点缺陷即纯碳化硅单晶主体层5，从而实现在无缺陷的衬底表层4洁净区并保留半绝缘碳化硅衬底的半绝缘特性，从而使GaN外延层获得最佳的质量。
使用KrF脉冲激光照射对高纯碳化硅单晶衬底进行退火处理，控制高纯碳化硅单晶衬底能量密度不大于150mJ/cm 2。
按照上述的方法和表1所示的具体参数将高纯碳化硅单晶片1#分别制得高纯碳化硅单晶衬底1#、高纯碳化硅单晶衬底2#、高纯碳化硅单晶衬底3#、高纯碳化硅单晶衬底4#和高纯碳化硅单晶衬底5#。高纯碳化硅单晶衬底1#‐5#的具体制备参数和衬底性质如表1所示。
表1
Figure PCTCN2018123710-appb-000001
Figure PCTCN2018123710-appb-000002
分别测试制得的高纯碳化硅单晶衬底1#、高纯碳化硅单晶衬底2#、 高纯碳化硅单晶衬底3#、高纯碳化硅单晶衬底4#和高纯碳化硅单晶衬底5#的电阻率、浅能级杂质含量、碳化硅衬底表层本征点浓度、碳化硅衬底主体层本征点浓度等，测试结果如表1所示。由表1数据可知高纯碳化硅单晶衬底1#‐5#的电阻率高，具有半绝缘性质。高纯碳化硅单晶衬底1#‐5#的碳化硅单晶衬底表层的本征点缺陷浓度小于所述碳化硅单晶衬底本体层的本征点缺陷浓度，且制备的碳化硅单晶衬底1#‐5#具有半绝缘性。其中，高纯碳化硅单晶衬底1#表层征点缺陷浓度极低，具有良好的晶格完整性，高纯碳化硅单晶衬底1#主体层的本征点缺陷的浓度使得所述的高纯碳化硅单晶衬底具有半绝缘性。碳化硅单晶衬底表层室温下本征点缺陷浓度极低，本征点缺陷除非在绝对零度下，否则始终存在于晶体中，一定厚度内本征点缺陷浓度最低。
本申请制得的4‐12英寸半绝缘碳化硅单晶衬底电阻率可以达到2×10 11Ω·cm绝以上，且电阻率径向分布控制在2数量级以内，从而实现半绝缘碳化硅单晶衬底的电阻率均匀分布。对于4‐12英寸半绝缘碳化硅单晶衬底测试其弯曲度和翘曲度，其弯曲度和翘曲度可以控制在45μm以内。
实施例2 制备GaN单晶及性能测试
分别利用实施例1中制备的同尺寸的高纯碳化硅单晶衬底1#‐5#和高纯碳化硅单晶片1#作为制备GaN单晶外延片的基底，制备方法根据本领域的常规方法。由高纯碳化硅单晶衬底1#‐5#制得的GaN单晶的晶型质量高于以高纯碳化硅单晶片1#作为基底制得的GaN单晶外延片的质量，具体数据如表2所示。
表2
Figure PCTCN2018123710-appb-000003
Figure PCTCN2018123710-appb-000004
以上所述，仅为本申请的实施例而已，本申请的保护范围并不受这些具体实施例的限制，而是由本申请的权利要求书来确定。对于本领域技术人员来说，本申请可以有各种更改和变化。凡在本申请的技术思想和原理之内所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (20)

  1. 一种高纯碳化硅单晶衬底，其特征在于，所述的高纯碳化硅单晶衬底至少包括碳化硅单晶衬底表层和碳化硅单晶衬底主体层，所述碳化硅单晶衬底表层的本征点缺陷浓度小于所述碳化硅单晶衬底本体层的本征点缺陷浓度，所述碳化硅单晶衬底具有半绝缘性。
  2. 根据权利要求1所述的高纯碳化硅单晶衬底，其特征在于，所述碳化硅单晶衬底表层厚度和碳化硅单晶衬底主体层的厚度比例为1：4‐25。
  3. 根据权利要求1所述的高纯碳化硅单晶衬底，其特征在于，所述碳化硅单晶衬底表层的本征点缺陷的室温浓度不高于1×10 13cm ‐3，所述碳化硅单晶衬底主体层的本征点缺陷的浓度为1×10 14～1×10 16cm ‐3；
    优选地，所述碳化硅单晶衬底表层室温下的本征点缺陷的室温浓度不高于1×10 12cm ‐3，所述碳化硅单晶衬底主体层的本征点缺陷的浓度为1×10 14～1×10 15cm ‐3。
  4. 根据权利要求1所述的高纯碳化硅单晶衬底，其特征在于，所述碳化硅单晶衬底表层的厚度不大于150μm；
    优选地，所述碳化硅单晶衬底表层的厚度为20‐150μm。
  5. 根据权利要求2所述的高纯碳化硅单晶衬底，其特征在于，所述碳化硅单晶衬底表层室温下基本不含有本征点缺陷，所述的碳化硅单晶衬底主体层的本征点缺陷的浓度使得所述的高纯碳化硅单晶衬底具有半绝缘性。
  6. 根据权利要求1‐5中任一项所述的高纯碳化硅单晶衬底，其特征在于，所述衬底由以下制备方法制备得到：
    将高纯碳化硅单晶片进行高温快速热处理和表面退火处理，即制得所述的高纯碳化硅单晶衬底。
  7. 根据权利要求6所述的高纯碳化硅单晶衬底，所述高温快速热处理包括快速升温加热阶段和快速降温阶段；
    优选地，所述快速升温加热阶段包括下述步骤：以30‐100℃/s的速率升温至1800‐2200℃，保持60‐600s；所述快速降温阶段包括下述步骤：以50‐150℃/s速率快速冷却至室温。
  8. 根据权利要求6所述的高纯碳化硅单晶衬底，其特征在于，所述表面退火处理控制的碳化硅单晶片的表面温度为1200‐1800℃，退火处理的时间为30‐90min；
    优选地，所述表面退火处理为使用表面激光加热经高温快速热处理后的碳化硅单晶片表面；
    所述激光加热的步骤包括：通过激光进行往复面扫描经过高温快速热处理的碳化硅单晶片进行表面退火处理，所述激光移动速率为0.5‐3000mm/s。
  9. 一种半导体器件，其包含权利要求1‐8任一项所述的高纯碳化硅单晶衬底；
    优选地，所述半导体器件为外延晶片或晶体管。
  10. 权利要求1‐8中任一项所述的高纯碳化硅单晶衬底在制备半导体器件中的应用；
    优选地，所述半导体器件为外延晶片或晶体管。
  11. 一种制备高质量的半绝缘碳化硅单晶衬底的方法，其特征在于，所述方法包括下述步骤：
    1)选择高纯碳化硅单晶片；
    2)将高纯碳化硅单晶片进行高温快速热处理和表面退火处理，即制得所述的高质量的半绝缘碳化硅单晶衬底；
    所述的高质量的半绝缘碳化硅单晶衬底至少包括碳化硅单晶衬底表 层和碳化硅单晶衬底主体层。
  12. 根据权利要求11所述的制备方法，其特征在于，所述碳化硅单晶衬底表层厚度与所述碳化硅单晶衬底厚度的比值不大于31％；
    进一步地，所述碳化硅单晶衬底表层厚度与所述碳化硅单晶衬底厚度的比值为9％‐31％。
  13. 根据权利要求11所述的制备方法，其特征在于，所述高温快速热处理包括快速升温加热阶段，所述快速升温加热阶段包括：以30‐100℃/s的速率从室温升温至1800‐2300℃，保持60‐600s。
  14. 根据权利要求13所述的制备方法，其特征在于，所述高温快速热处理还包括快速降温阶段，所述快速降温阶段包括以50‐150℃/s速率快速冷却。
  15. 根据权利要求13所述的制备方法，其特征在于，所述快速降温阶段包括：以100‐150℃/s速率快速冷却至室温。
  16. 根据权利要求11所述的制备方法，其特征在于，所述表面退火处理控制的高纯碳化硅单晶片的表面温度为1200‐1800℃，退火处理的时间为30‐90min；
    优选地，所述表面退火处理控制的高纯碳化硅单晶片的表面温度为1400‐1600℃，退火处理的时间为45‐60min。
  17. 根据权利要求11所述的制备方法，其特征在于，所述表面退火处理为使用激光器加热经高温快速热处理后的高纯碳化硅单晶片表面。
  18. 根据权利要求17所述的制备方法，其特征在于，所述激光器加热的步骤包括：通过激光器进行往复面扫描经过高温快速热处理的高纯碳化硅单晶片进行表面退火处理，所述激光器移动速率为0.5‐3000mm/s；
    优选地，所述激光器移动速率为0.5‐5mm/s。
  19. 根据权利要求18所述的制备方法，其特征在于，所述激光器的 波长小于352nm，脉冲宽度不大于60ns，能量密度不大于150mJ/cm 2；
    优选地，所述激光器的波长小于352nm，脉冲宽度20‐60ns，能量密度70‐110mJ/cm 2。
  20. 根据权利要求11所述的制备方法，其特征在于，步骤1)高纯碳化硅单晶片的制备方法包括如下步骤：将碳化硅粉料经除杂、长晶阶段制得高纯碳化硅单晶后，进行切割、研磨和抛光，制得高纯碳化硅单晶片。
PCT/CN2018/123710 2018-10-16 2018-12-26 一种高纯碳化硅单晶衬底及其制备方法 WO2020077848A1 (zh)

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