WO2020062230A1 - 阵列基板栅极驱动电路、薄膜晶体管及显示装置 - Google Patents

阵列基板栅极驱动电路、薄膜晶体管及显示装置 Download PDF

Info

Publication number
WO2020062230A1
WO2020062230A1 PCT/CN2018/109069 CN2018109069W WO2020062230A1 WO 2020062230 A1 WO2020062230 A1 WO 2020062230A1 CN 2018109069 W CN2018109069 W CN 2018109069W WO 2020062230 A1 WO2020062230 A1 WO 2020062230A1
Authority
WO
WIPO (PCT)
Prior art keywords
film transistor
thin film
gate
circuit
back gate
Prior art date
Application number
PCT/CN2018/109069
Other languages
English (en)
French (fr)
Inventor
袁泽
管曦萌
余晓军
Original Assignee
深圳市柔宇科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市柔宇科技有限公司 filed Critical 深圳市柔宇科技有限公司
Priority to PCT/CN2018/109069 priority Critical patent/WO2020062230A1/zh
Priority to CN201880094120.9A priority patent/CN112639940A/zh
Priority to TW108100612A priority patent/TW202015028A/zh
Publication of WO2020062230A1 publication Critical patent/WO2020062230A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays

Definitions

  • the present invention relates to a display technology and structure, and in particular, to a thin film transistor for display driving, a gate driving circuit having a thin film transistor, and a display device.
  • the GOA Gate Driver On Array
  • LCD and AMOLED display devices It is a key part of the display device and is used to provide scanning pulse signals to the pixel matrix.
  • the thin film transistor (TFT) constituting the GOA needs to have a sufficiently large on-current and a sufficiently small leakage current.
  • the threshold voltage of the thin film transistor is too small, the increase in leakage current will cause the nodes inside the GOA circuit to discharge incorrectly, causing the GOA circuit to malfunction, and eventually causing the screen to fail.
  • the threshold voltage of the thin film transistor is too large, the transistor cannot be turned on normally, which will also cause the GOA circuit to malfunction and eventually cause the screen to fail.
  • the threshold voltages of thin film transistors on different batches or on different substrates in the same batch often have a systematic overall drift.
  • the threshold voltage of the thin film transistor will also drift.
  • the overall threshold voltage is biased to a negative value, an increase in leakage current may cause the GOA to malfunction, and if the overall threshold voltage is biased to a positive value, the failure of the transistor to turn on may also cause the GOA to malfunction. Therefore, compensating the threshold voltage drift of the thin film transistor after reducing it, and reducing the effect of the threshold voltage drift on the GOA circuit are of great significance for improving the display effect of the display screen and extending the life of the display screen.
  • the embodiment of the invention discloses an array substrate gate driving circuit, a thin film transistor and a display device, which are used for correcting the threshold voltage drift generated by the thin film transistor.
  • An embodiment of the present invention discloses an array substrate gate driving circuit.
  • the array substrate gate driving circuit includes a plurality of thin film transistors. At least one thin film transistor has a gate at the position of a back gate, and each back gate is added to the thin film transistor.
  • the back gate is used for accessing a compensation voltage to compensate a threshold voltage drift of the thin film transistor.
  • An embodiment of the present invention also discloses a thin film transistor, a gate of the thin film transistor is added with a back gate, and the back gate is used for accessing a compensation voltage to compensate a threshold voltage drift of the thin film transistor.
  • An embodiment of the present invention also discloses a display device including a voltage output circuit and a gate driving circuit of an array substrate.
  • the array substrate gate driving circuit includes a plurality of thin film transistors, and a position of a gate of at least one thin film transistor is increased.
  • Back gate The back gate of each thin film transistor to which the back gate is added is used as a compensation voltage access terminal to access a compensation voltage to compensate a threshold voltage drift of the thin film transistor.
  • the voltage output circuit includes at least one DC voltage terminal, and each DC voltage terminal is used to be electrically connected to a back gate of a corresponding thin-film transistor with a back gate, so as to provide a corresponding compensation voltage for the back gate of the thin-film transistor. .
  • the thin film transistor, the array substrate gate driving circuit, and the display device of the present application have a structure in which a back gate is added to a gate position of at least one thin film transistor in the array substrate gate driving circuit, and a compensation voltage is obtained through the back gate. It can effectively eliminate the voltage drift phenomenon of the thin film transistor from the source and ensure the normal operation of the gate driving circuit of the array substrate.
  • FIG. 1 is a structural block diagram of an array substrate gate driving circuit according to an embodiment of the present application.
  • FIG. 2 is a schematic circuit structure diagram of an array substrate gate driving circuit according to an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of a thin film transistor with a back gate added in another embodiment of the present application.
  • FIG. 4 is a structural block diagram of a display device according to an embodiment of the present application.
  • FIG. 5 is a schematic plan view of a display device according to an embodiment of the present application.
  • FIG. 1 is a structural block diagram of a GOA (Gate Driver On Array) circuit 1 in an embodiment of the present invention.
  • the GOA circuit 1 includes a plurality of thin film transistors T1, wherein a gate of at least one thin film transistor T1 is added with a back gate 10.
  • the back gate 10 of each thin film transistor T1 to which the back gate 10 is added is used as a compensation voltage access terminal for accessing a compensation voltage to compensate the threshold voltage drift of the thin film transistor T1. That is, the threshold voltage of the thin film transistor T1 is compensated and corrected to eliminate the threshold voltage drift.
  • the GOA circuit 1 includes an output thin film transistor 12 for determining a driving capability, that is, the thin film transistors T1 included in the GOA circuit 1 include an output thin film transistor 12.
  • the thin film transistor T1 to which the back gate 10 is added may include all or part of the thin film transistor T1 in the GOA circuit 1 except for the output thin film transistor 12 for determining the driving capability.
  • the thin film transistor T1 with the added back gate 10 may be a thin film transistor selected from the thin film transistors T1 other than the output thin film transistor 12 for determining the driving capability in the GOA circuit 1 according to a preset standard.
  • T1 that is, in this application, a back gate 10 is added to the thin film transistor T1 selected from the thin film transistors T1 other than the output thin film transistor 12 for determining the driving capability in the GOA circuit 1 according to a preset standard. structure.
  • the preset standard may include at least one of the GOA circuit that is prone to cause malfunctions, has only a control function, and has a small size.
  • the thin-film transistor T1 with the back gate 10 added is a thin-film transistor T1 that meets at least one of the criteria such as the control function and the small size that easily cause malfunction.
  • the thin film transistor T1 with the added back gate 10 is a thin film transistor T1 that simultaneously meets standards that are liable to cause malfunctions and only have a control function and have a small size.
  • the back gate 10 since the introduction of the back gate 10 is selective, the back gate 10 is added only to the thin film transistor T1 that is liable to cause malfunction and has only a small control function, and the output film with the largest size that determines the driving capability
  • the transistor does not introduce a back gate, so the increase in overall power consumption is very limited, which does not cause a significant increase in power consumption. In actual use, it can be gradually adjusted according to the actual voltage drift of the thin film transistor T1 as the thin film transistor T1 ages.
  • the compensation voltage connected to the back gate 10 can simultaneously achieve the purpose of optimizing the driving effect and extending the service life.
  • the back gate 10 of each thin film transistor T1 with the back gate 10 is connected to a corresponding DC voltage terminal 2, and the compensation voltage is obtained from the DC voltage terminal 2.
  • the compensation voltage output from the DC voltage terminal 2 can be determined according to the threshold voltage drift value of the corresponding thin film transistor T1. For example, if the threshold voltage drift value is negative, a negative compensation voltage with the same absolute value is output. If the threshold voltage drifts, If the value is positive, a positive compensation voltage with the same absolute value is output.
  • the specific introduction of the DC voltage terminal 2 will be described later with reference to the display device 100 shown in FIGS. 4 and 5.
  • the GOA circuit 1 specifically includes a front-stage input circuit 11, an output thin film transistor 12, a first pull-down circuit 13, a second pull-down circuit 14, and a pull-down suppression circuit 15.
  • the front-stage input circuit 11, the first pull-down circuit 13, the second pull-down circuit 14, and the pull-down suppression circuit 15 each include at least one thin film transistor T1.
  • the thin film transistor T1 with the back gate 10 added may include a front stage Some or all of the input circuit 11, the first pull-down circuit 13, the second pull-down circuit 14, and the pull-down suppression circuit 15 are part or all of the thin film transistor T1.
  • the thin film transistor T1 with the back gate 10 added includes a part or all of the thin film transistor T1 in at least one of the front-stage input circuit 11, the first pull-down circuit 13, the second pull-down circuit 14, and the pull-down suppression circuit 15.
  • the reason is that at least one of the front-stage input circuit 11, the first pull-down circuit 13, the second pull-down circuit 14, and the pull-down suppression circuit 15 has a thin-film transistor T1 and a back gate 10 structure. Since each circuit May include one or more thin film transistors T1, then, for a circuit having a thin film transistor T1 with an added back gate 10, all of the thin film transistors T1 included in the circuit are added with the back gate 10, or Part of the thin film transistor T1 included in the circuit is added with a back gate 10.
  • a structure in which the back gate 10 is added to only some or all of the thin-film transistors T1 in each of the front-stage input circuit 11, the first pull-down circuit 13, and the second pull-down circuit 14 may be input only in the front stage.
  • the circuit 11 and the pull-down suppression circuit 15 each have a structure in which a part or all of the thin film transistors T1 are added with a back gate 10.
  • the front-stage input circuit 11, the first pull-down circuit 13, and the second pull-down circuit 14 may also be used.
  • a structure in which a back gate 10 is added to some or all of the thin film transistors T1 in each of the pull-down suppression circuits 15.
  • the front-stage input circuit 11 may include thin film transistors T11 and T12
  • the first pull-down circuit 13 includes thin-film transistors T13 and T14
  • the second pull-down circuit 14 includes thin-film transistors T15
  • the pull-down suppression circuit 15 includes thin-film transistors. T16.
  • the back gate 10 is added to one of the thin film transistors T11 and T12 in the front-stage input circuit 11, and the back gate 10 is added to one of the thin film transistors T13 and T14 in the first pull-down circuit 13.
  • the thin-film transistor T15 in the second pull-down circuit 14 and the thin-film transistor T16 in the pull-down suppression circuit 15 also increase the back gate 10.
  • the thin-film transistors T1 in the front-stage input circuit 11, the first pull-down circuit 13, the second pull-down circuit 14, and the pull-down suppression circuit 15 are satisfied, they only have control functions and are relatively small in size.
  • the thin-film transistor T1 of the small standard is added with a back gate 10 to some or all of the thin-film transistors T1 in at least one of the front-stage input circuit 11, the first pull-down circuit 13, the second pull-down circuit 14, and the pull-down suppression circuit 15. , Can effectively compensate the voltage drift of the corresponding thin film transistor T1 without causing a significant increase in power consumption.
  • FIG. 2 Please refer to FIG. 2 together for a circuit structure diagram of the GOA circuit 1.
  • the GOA circuit 1 further includes a pull-up control node PU, a bootstrap capacitor C1, a holding capacitor C2, and a pull-down control node PD.
  • the thin-film transistor T11 of the front-stage input circuit 11 is electrically connected to an enable.
  • the thin film transistor T13 of the first pull-down circuit 13 is electrically connected between the pull-up control node PU and the low-potential terminal Vgl.
  • the gates of the thin-film transistor T13 of the first pull-down circuit 13 and the thin-film transistor T15 of the second pull-down circuit 14 are connected to each other, and the connection node of the thin-film transistor T13 and the thin-film transistor T15 constitutes a pull-down control node PD.
  • the thin film transistor T16 of the pull-down suppression circuit 15 is electrically connected between the pull-down control node PD and the low potential terminal Vgl.
  • the thin film transistor T12 of the front-stage input circuit 11 and the thin film transistor T14 of the first pull-down circuit 13 are connected in series between the high potential terminal Vgh and the low potential terminal Vgl, and the connection node of the thin film transistor T12 and the thin film transistor T14 It is also electrically connected to the pull-down control node PD.
  • the gate of the thin film transistor T12 of the front-stage input circuit 11 is electrically connected to the clock reset terminal Clkrst
  • the gate of the thin film transistor T14 of the first pull-down circuit 13 is electrically connected to the pull-down reset terminal PDrst.
  • the output thin film transistor 12 is electrically connected between a clock signal terminal Clkb and the output terminal O1 of the GOA circuit 1, and the gate of the output thin film transistor 12 is electrically connected to the pull-up control node PU.
  • the gate and source of the thin film transistor T11 of the front-stage input circuit 11 are electrically connected to the enable terminal EN, and the gate of the thin film transistor T16 of the pull-down suppression circuit 15 is also electrically connected to the enable terminal. EN.
  • the bootstrap capacitor C1 is electrically connected between the pull-up control node PU and the output terminal O1.
  • the holding capacitor C2 and the thin film transistor T16 are connected in parallel between the pull-down control node PD and the ground point Vgl.
  • the thin film transistor T1 is described by taking an N-channel thin film transistor as an example.
  • the normal action is to enable the terminal EN to output a high-level enable signal, and turn on the thin film transistor T11 of the previous-stage input circuit 11, so that the high-level enable signal passes through the conductive thin film.
  • the transistor T11 charges the pull-up control node PU and charges the voltage of the pull-up control node PU.
  • the high-level enable signal output from the enable terminal EN also turns on the thin film transistor T16 of the pull-down suppression circuit 15.
  • the turned-on thin film transistor T16 discharges the pull-down control node PD.
  • the output thin film transistor 12 will be turned on. At this time, the turned on output thin film transistor 12 is at a scanning signal that allows the clock signal terminal Clkb to output. Ready state of the output.
  • the threshold voltage will be too low, which will cause a false turn-on, and a discharge path to the pull-up control node PU will be formed, which will lead to the pull-up control node.
  • the pre-charging of the PU fails and the output thin film transistor 12 cannot be turned on, so the GOA circuit 1 cannot normally output a scan pulse in the next cycle, resulting in abnormal operation.
  • the normal action is that the clock reset terminal Clkrst outputs a clock reset signal to control the thin film transistor T12 to turn on.
  • the voltage provided by the high potential terminal Vgh passes the turned on thin film transistor T12
  • the pull-down control node PD is charged, and the voltage of the pull-down control node PD is gradually increased.
  • the thin film transistors T13 and T15 are turned on.
  • the shutdown mechanism is activated, the pull-up control node PU will discharge through the turned-on thin-film transistor T13 and reset to a low level. At this time, the output thin-film transistor 12 cannot be turned on, and the output thin-film transistor 12 is turned off and turned on at the same time.
  • the thin film transistor T15 keeps the output terminal O1 at a low level.
  • the thin-film transistor T16 of the pull-down suppression circuit 15 may be turned on to a certain extent, resulting in leakage of the pull-down control node PD. If the voltage of the thin film transistors T13 and T15 cannot be raised, and the thin film transistors T13 and T15 cannot be turned on, the pull-up control node PU fails to discharge, and the GOA circuit 1 is triggered by mistake in the next clock cycle.
  • the normal operation is to keep the pull-down control node PD high by the holding capacitor C2, and at the same time, the turned-on thin-film transistor T15 connects the output terminal O1 to the low potential terminal Vgl to electrically connect the voltage of the output terminal O1. It is kept at a low level.
  • the turned-on thin film transistor T13 keeps the voltage of the pull-up control node PU at a low level by electrically connecting the pull-up control node PU to the low potential terminal Vgl.
  • the thin-film transistor T16 of the pull-down suppression circuit 15 may be turned on to a certain extent, resulting in leakage of the pull-down control node PD. If the voltage of the thin film transistors T13 and T15 cannot be raised, and the thin film transistors T13 and T15 cannot be turned on, the above-mentioned holding operation cannot be achieved.
  • the thin-film transistor T11 of the front-stage input circuit 11 has a low threshold voltage due to a negative drift, the thin-film transistor T11 may be turned on to a certain extent, which causes the pull-up control node PU to obtain an additional voltage increase, which will cause GOA The circuit falsely triggers on the next clock cycle.
  • the thin film transistor T1 to which the back gate 10 is added includes the thin film transistor T11, the thin film transistor T12, the thin film transistor T13 of the first pull-down circuit 13, and the pull-down suppression circuit 15 of the front-stage input circuit 11.
  • Thin film transistor T16 Thin film transistor T16.
  • the thin film transistor T15 of the second pull-down circuit 14 has a threshold voltage drift, for example, the threshold voltage is too low, which may also cause a false discharge to the output terminal OUT.
  • the thin film transistor T1 to which the back gate 10 is added includes the thin film transistor T11, the thin film transistor T12, the thin film transistor T13 of the first pull-down circuit 13, and the second pull-down circuit 14 of the front-stage input circuit 11. And a thin film transistor T16 of the pull-down suppression circuit 15.
  • the thin-film transistor T14 in the first pull-down circuit 14 has a threshold voltage drift.
  • the threshold voltage is too low, which may also cause a false discharge to the pull-down control node PD. Therefore, in some embodiments, the thin film transistor T1 to which the back gate 10 is added includes a thin film transistor T11, a thin film transistor T12, a thin film transistor T13, a thin film transistor T14, The thin film transistor T15 of the two pull-down circuits 14 and the thin film transistor T16 of the pull-down suppression circuit 15.
  • the threshold voltage offset of these thin film transistors T1 can be effectively avoided, thereby Can effectively avoid abnormal working of GOA circuit 1.
  • the high-potential terminal Vgh can provide a high-level voltage such as + 5V
  • the low-potential terminal Vgl can provide a low-level voltage such as 0V.
  • FIG. 3 is a schematic structural diagram of a thin film transistor T1 with a back gate 10 added thereto.
  • the thin film transistor T1 includes a top gate 21, a channel layer 22, a source electrode 23, and a drain electrode 24.
  • the top gate electrode 21 is stacked with the channel layer 22, and the source electrode 23 and the drain electrode 24 are provided.
  • the two sides of the channel layer 22 are electrically connected through the channel layer 22.
  • the resistance of the channel layer 22 is controlled by the top gate 21.
  • the back gate 10 is disposed on the channel layer 22 away from the top gate 21. the other side.
  • the back gate 10 and the top gate 21 together form a gate of the thin film transistor T1. Therefore, by applying a compensation voltage to the back gate 10, the threshold voltage drift generated by the thin film transistor T1 can be compensated.
  • the threshold voltage of a certain thin film transistor T1 drifts by + 2V
  • the threshold voltage can be adjusted back by applying a certain compensation voltage to the back gate 10.
  • the threshold voltage is shifted in the forward direction, that is, larger than the normal value
  • a positive voltage can be applied to the back gate 10
  • the required voltage for turning on the thin film transistor T1 is reduced.
  • a threshold voltage to offset the forward drift If the threshold voltage is a negative drift, that is, smaller than a normal value, a negative voltage may be applied to the back gate 10 and the threshold voltage required to turn on the thin film transistor T1 may be increased to offset the negative drift. Therefore, the threshold voltage can be compensated and corrected by applying a compensation voltage to the back gate 10.
  • the thin film transistor T1 further includes a top gate oxide layer 25 between the channel layer 22 and the top gate 21, a dielectric isolation layer 26 covering the top gate 21, the source 23 and the drain 24, and A metal wire 27 electrically connected to the source electrode 23 and the drain electrode 24, a back gate oxide layer 28 located between the channel layer 22 and the back gate 10, and the like.
  • the top gate 21 and the back gate 10 are metal electrode sheets.
  • the thin film transistor T1 is formed by a patterning molding process including a top gate 21, a back gate 10, a channel layer 22, a source electrode 23, and a drain electrode 24.
  • the back gate 10 may also be a conductive metal layer formed by coating.
  • FIG. 4 is a structural block diagram of the display device 100.
  • the display device 100 includes the aforementioned GOA circuit 1, a voltage output circuit 3, and a drift detection circuit 4.
  • the voltage output circuit 3 includes at least one DC voltage terminal 2.
  • the number of the at least one DC voltage terminal 2 is the same as the number of the thin film transistors T1 with the back gate 10 added in the GOA circuit 1, and each DC voltage terminal 2 is electrically connected to the back gate 10 of a corresponding thin film transistor T1.
  • the drift detection circuit 4 is configured to detect a threshold voltage drift value of the thin film transistor T1 with the back gate 10 added in the GOA circuit 1, and the voltage output circuit 3 is configured to detect each voltage detected by the drift detection circuit 4.
  • the threshold voltage drift value of the thin film transistor T1 of the back gate 10 is increased, and the corresponding DC voltage terminal 2 is controlled to output the corresponding compensation voltage, so as to compensate and calibrate the threshold voltage drift of the corresponding thin film transistor T1.
  • the drift detection circuit 4 may include a plurality of detection units capable of detecting the thin film transistor T1.
  • the threshold voltage drift value of the thin film transistor T1 and certain parameters of the thin film transistor T1, such as temperature have Certain relationship.
  • a temperature sensor that can detect corresponding parameters, such as a temperature sensor, at each thin film transistor T1 to which the back gate 10 is added, the temperature and other parameters of the thin film transistor T1 can be detected.
  • the parameter gives the threshold voltage drift value of the corresponding thin film transistor T1.
  • the threshold voltage drift value of each thin film transistor T1 with the back gate 10 added thereto may also be obtained by simulation software simulation, for example, the corresponding relationship between the use time and the threshold voltage drift value may be obtained according to the simulation software. Therefore, the voltage output circuit 3 can obtain a corresponding threshold voltage drift value corresponding to the increase in the use time, and control and output the corresponding compensation voltage.
  • the drift detection circuit 4 can also be any other circuit that can detect the threshold voltage drift value of the thin film transistor T1.
  • the voltage output circuit 3 may be a power management chip, and may control different DC voltage terminals 2 to output different voltages according to needs, thereby providing a suitable compensation voltage for each thin film transistor T1 with a back gate 10 added, and Perform targeted compensation for the threshold voltage drift value of each thin film transistor T1.
  • FIG. 5 is a schematic plan view of the display device 100.
  • the display device 100 further includes a plurality of pixel units 5 distributed in an array, for example, including N rows * M columns of pixel units 5, where N and M are natural numbers greater than 1.
  • the number of GOA circuits 1 included in the display device 100 is multiple, and the number of GOA circuits 1 is the same as the number of rows of pixel units 5, for example, N.
  • Each GOA circuit 1 is corresponding to one row of pixel units 5. Connection for supplying scanning signals to the pixel units 5 in the same row.
  • the back gate 10 is added to the thin film transistor T1 at the same position in each GOA circuit 1, that is, the position of the thin film transistor T1 with the back gate 10 added to each GOA circuit 1 is the same in the GOA circuit 1.
  • a back gate 10 is added to the thin film transistor T16 of the pull-down suppression circuit 15.
  • the back gates 10 of the thin film transistors T1 at the same position in all GOA circuits 1 are connected to the same DC voltage terminal 2, and the same compensation voltage is received from the same DC voltage terminal 2 to perform threshold voltage drift compensation .
  • the function of each GOA circuit is the same (both generate a scanning signal), the circuit structure is the same, and the frequency of use is the same, so the aging rates of these GOA circuits are the same: the compensation that needs to be obtained is also the same. Therefore, their back gates 10 can be connected to the same DC voltage terminal 2 for unified compensation.
  • the back gate 10 of the thin film transistor T1 in the GOA circuit 1 may be connected to a corresponding DC voltage terminal by a wire, a FPC (flexible circuit board), or the like.
  • the plurality of GOA circuits 1 may be arranged in a non-display area of the display device 100, or may be arranged under a plurality of pixel units 5 of the display device 100, that is, in a display area.
  • the display device 100 is a display screen or display panel including AMOLED (Active Matrix Organic Light Emitting Diode; Active Matrix Organic Light Emitting Diode), LCD (liquid crystal display, liquid crystal display), or the like. It is an electronic device including a mobile phone, a tablet computer, a camera, etc. having a corresponding display screen, a display panel, and the like.
  • AMOLED Active Matrix Organic Light Emitting Diode
  • LCD liquid crystal display, liquid crystal display
  • It is an electronic device including a mobile phone, a tablet computer, a camera, etc. having a corresponding display screen, a display panel, and the like.

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种薄膜晶体管（T1）、阵列基板栅极驱动电路（1）及具有阵列基板栅极驱动电路（1）的显示装置（100）。阵列基板栅极驱动电路（1）包括若干薄膜晶体管（T1），至少一个薄膜晶体管（T1）的栅极的位置增加了背栅（10），每一增加了背栅（10）的薄膜晶体管（T1）的背栅（10）用于接入补偿电压，以补偿薄膜晶体管（T1）的阈值电压漂移。通过在阵列基板栅极驱动电路（1）中的至少一个薄膜晶体管（T1）的栅极的位置增加背栅（10）这一结构，并通过背栅（10）获得补偿电压，可有效的从源头上消除薄膜晶体管（T1）的电压漂移现象，保证了阵列基板栅极驱动电路（1）的正常工作。

Description

阵列基板栅极驱动电路、薄膜晶体管及显示装置 技术领域
本发明涉及一种显示技术及结构，尤其涉及一种用于显示驱动的薄膜晶体管、具有薄膜晶体管的栅极驱动电路及显示装置。
背景技术
GOA(Gate driveron array，阵列基板栅极驱动电路)电路广泛应用于LCD和AMOLED等类型的显示装置中，它是显示装置的关键部分，用于向像素矩阵提供扫描脉冲信号。通常，为了保证GOA电路正常工作，组成GOA的薄膜晶体管(TFT)需要具有足够大的导通电流和足够小的漏电流。当薄膜晶体管阈值电压过小时，漏电流增加会导致GOA电路内部的节点误放电，造成GOA电路误动作，最终引起屏幕失效。当薄膜晶体管阈值电压过大时，晶体管无法正常开启，也会造成GOA电路误动作，最终引起屏幕失效。由于制造薄膜晶体管的材料和工艺限制，不同批次或是同一批次不同基板上的薄膜晶体管的阈值电压往往出现系统性的整体漂移，另外，随着使用时间和次数的增加，当显示装置的屏幕老化时，薄膜晶体管的阈值电压也会发生漂移。通常，如果阈值电压整体偏向负值，漏电流的增加会引起GOA误动作，如果阈值电压整体偏向正值，晶体管无法开启也会引起GOA误动作。因此，当薄膜晶体管的阈值电压漂移后对其进行补偿，减少阈值电压漂移对GOA电路的影响，对于改进显示屏的显示效果、延长显示屏的寿命具有重要意义。
发明内容
本发明实施例公开一种阵列基板栅极驱动电路、薄膜晶体管及显示装置，用于对薄膜晶体管产生的阈值电压漂移进行校正。
本发明实施例公开一种阵列基板栅极驱动电路，所述阵列基板栅极驱动电路包括若干薄膜晶体管，至少一个薄膜晶体管的栅极的位置增加了背栅，每一增加了背栅的薄膜晶体管的背栅用于接入补偿电压，以补偿所述薄膜晶体管的 阈值电压漂移。
本发明实施例还公开一种薄膜晶体管，所述薄膜晶体管的栅极的位置增加了背栅，所述背栅用于接入补偿电压，以补偿所述薄膜晶体管的阈值电压漂移。
本发明实施例还公开一种显示装置，所述显示装置包括电压输出电路阵列基板栅极驱动电路，所述阵列基板栅极驱动电路包括若干薄膜晶体管，至少一个薄膜晶体管的栅极的位置增加了背栅，每一增加了背栅的薄膜晶体管的背栅用于作为补偿电压接入端而接入补偿电压，以补偿所述薄膜晶体管的阈值电压漂移。其中，所述电压输出电路包括至少一个直流电压端，每一直流电压端用于与相应的增加了背栅的薄膜晶体管的背栅电连接，以为所述薄膜晶体管的背栅提供相应的补偿电压。
本申请的薄膜晶体管、阵列基板栅极驱动电路及显示装置，通过在阵列基板栅极驱动电路中的至少一个薄膜晶体管的栅极的位置增加背栅这一结构，并通过背栅去获得补偿电压，可有效从源头上消除薄膜晶体管的电压漂移现象，保证了阵列基板栅极驱动电路的正常工作。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请一实施例中的阵列基板栅极驱动电路的结构框图。
图2为本申请一实施例中的阵列基板栅极驱动电路的电路结构示意图。
图3为本申请另一实施例中的增加了背栅的薄膜晶体管的结构示意图。
图4为本申请一实施例中的显示装置的结构框图。
图5为本申请一实施例中的显示装置的平面示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请一并参阅图1，为本发明一实施例中的GOA(Gate driver on array，阵列基板栅极驱动电路)电路1的结构框图。如图1所示，所述GOA电路1包括若干薄膜晶体管T1，其中，至少一个薄膜晶体管T1的栅极的位置增加了背栅10。每一增加了背栅10的薄膜晶体管T1的背栅10用于作为补偿电压接入端而用于接入补偿电压，以对所述薄膜晶体管T1的阈值电压漂移进行补偿。即，对薄膜晶体管T1的阈值电压进行补偿校正，而消除阈值电压漂移。
本申请中，通过在GOA电路中的至少一个薄膜晶体管T1的栅极的位置增加背栅10这一结构，并通过背栅10去获得补偿电压，可有效从源头上消除薄膜晶体管T1的电压漂移现象，保证了GOA电路的正常工作。
如图1所示，所述GOA电路1包括用于决定驱动能力的输出薄膜晶体管12，即，所述GOA电路1包括的若干薄膜晶体管T1中包括输出薄膜晶体管12。在一些实施例中，增加了背栅10的薄膜晶体管T1可包括GOA电路1中用于决定驱动能力的输出薄膜晶体管12之外的所有或部分的薄膜晶体管T1。
在一些实施例中，增加了背栅10的薄膜晶体管T1可为从GOA电路1中的用于决定驱动能力的输出薄膜晶体管12之外的薄膜晶体管T1中根据预设标准而选择出来的薄膜晶体管T1，即，本申请中，为在从GOA电路1中的用于决定驱动能力的输出薄膜晶体管12之外的薄膜晶体管T1中根据预设标准选择出来的薄膜晶体管T1中增加背栅10这一结构。
在一些实施例中，所述预设标准可包括GOA电路中容易引起误动作的、仅起控制作用的、尺寸较小等标准中的至少一个。所述增加了背栅10的薄膜晶体管T1为满足容易引起误动作的、仅起控制作用的、尺寸较小等标准中的至少一个的薄膜晶体管T1。较佳的，所述增加了背栅10的薄膜晶体管T1为同时满足容易引起误动作的、仅起控制作用的、尺寸较小等标准的薄膜晶体管T1。
从而，由于背栅10的引入具有选择性，仅在容易引起误动作的、仅起控制作用的、尺寸较小的薄膜晶体管T1中增加背栅10，而尺寸最大的、决定驱动能力的输出薄膜晶体管并不引入背栅，因此整体功耗的增加十分有限，不会导致功耗的明显增加，且实际使用中，可以随着薄膜晶体管T1的老化，根据薄膜晶体管T1的实际电压漂移而逐渐调整背栅10所接入的补偿电压，以同时达到优化驱动效果、延长使用寿命的目的。
在一些实施例中，如图1所示，每一增加了背栅10的薄膜晶体管T1的背栅10分别连接至一相应的直流电压端2，从直流电压端2获得所述补偿电压。其中，直流电压端2输出的补偿电压可根据对应的薄膜晶体管T1的阈值电压漂移值来确定，例如，阈值电压漂移值为负值，则输出绝对值相同的负值补偿电压，如果阈值电压漂移值为正值，则输出绝对值相同的正值补偿电压。其中，直流电压端2的具体介绍将在后面结合图4和图5所示的显示装置100进行说明。
进一步的，如图1所示，所述GOA电路1具体包括前级输入电路11、输出薄膜晶体管12、第一下拉电路13、第二下拉电路14以及下拉抑制电路15。
其中，前级输入电路11、第一下拉电路13、第二下拉电路14以及下拉抑制电路15中均包括有至少一个薄膜晶体管T1，所述增加了背栅10的薄膜晶体管T1可包括前级输入电路11、第一下拉电路13、第二下拉电路14以及下拉抑制电路15中至少一个电路中的部分或全部薄膜晶体管T1。
其中，所述增加了背栅10的薄膜晶体管T1包括前级输入电路11、第一下拉电路13、第二下拉电路14以及下拉抑制电路15中至少一个电路中的部分或全部薄膜晶体管T1指的是：前级输入电路11、第一下拉电路13、第二下拉电路14以及下拉抑制电路15中的至少一个电路中有薄膜晶体管T1增加了背栅10这一结构，由于，每一个电路可能包括一个或多个薄膜晶体管T1，则，对于具有增加了背栅10的薄膜晶体管T1的电路而言，可以是所述电路包括的所有薄膜晶体管T1均增加了背栅10，也可以是所述电路包括的部分薄膜晶体管T1增加了背栅10。
例如，仅在前级输入电路11、第一下拉电路13、第二下拉电路14中的每一个电路中的部分或全部薄膜晶体管T1增加背栅10这一结构，也可仅在前级 输入电路11、下拉抑制电路15中的每一个电路中的部分或全部薄膜晶体管T1中增加背栅10这一结构，也可在前级输入电路11、第一下拉电路13、第二下拉电路14以及下拉抑制电路15中的每一个电路中的部分或全部薄膜晶体管T1中增加背栅10这一结构。
如图1示，所述前级输入电路11可包括薄膜晶体管T11和T12，第一下拉电路13包括薄膜晶体管T13、T14、第二下拉电路14包括薄膜晶体管T15，下拉抑制电路15包括薄膜晶体管T16。
在一些实施例中，所述前级输入电路11中的薄膜晶体管T11和T12中的一个增加了背栅10，第一下拉电路13中的薄膜晶体管T13、T14中的一个增加了背栅10，第二下拉电路14中的薄膜晶体管T15以及下拉抑制电路15中的薄膜晶体管T16也增加了背栅10。
从而，由于前级输入电路11、第一下拉电路13、第二下拉电路14以及下拉抑制电路15中的部分或全部薄膜晶体管T1为满足容易引起误动作的、仅起控制作用的、尺寸较小等标准的薄膜晶体管T1，通过在前级输入电路11、第一下拉电路13、第二下拉电路14以及下拉抑制电路15中至少一个电路中的部分或全部薄膜晶体管T1中增加背栅10，可有效对相应的薄膜晶体管T1的电压漂移进行补偿，且不会导致功耗的明显增加。
请一并参阅图2，为GOA电路1的电路结构图。为了更好地说明如何选择哪些薄膜晶体管T1进行背栅10的增加，以下将结合图2进行说明，其中，图2更具体的为薄膜晶体管T1未增加背栅10时的GOA电路1的电路结构图。如图2所示，所述GOA电路1还包括上拉控制节点PU、自举电容C1、保持电容C2以及下拉控制节点PD，所述前级输入电路11的薄膜晶体管T11电连接于一使能端EN与上拉控制节点PU之间，所述第一下拉电路13的薄膜晶体管T13电连接于上拉控制节点PU和低电势端Vgl之间。所述第一下拉电路13的薄膜晶体管T13和第二下拉电路14的薄膜晶体管T15的栅极相互连接，且薄膜晶体管T13和薄膜晶体管T15的连接节点构成下拉控制节点PD。所述下拉抑制电路15的薄膜晶体管T16电连接于所述下拉控制节点PD和低电势端Vgl之间。
所述前级输入电路11的薄膜晶体管T12和第一下拉电路13的薄膜晶体管 T14串联于高电势端Vgh和所述低电势端Vgl之间，所述薄膜晶体管T12和薄膜晶体管T14的连接节点还与所述下拉控制节点PD电连接。所述前级输入电路11的薄膜晶体管T12的栅极与时钟重置端Clkrst电连接，第一下拉电路13的薄膜晶体管T14的栅极与下拉重置端PDrst电连接。
所述输出薄膜晶体管12电连接于一时钟信号端Clkb与GOA电路1的输出端O1之间，所述输出薄膜晶体管12的栅极与所述上拉控制节点PU电连接。其中，前级输入电路11的薄膜晶体管T11的栅极和源极均电连接于所述使能端EN，所述下拉抑制电路15的薄膜晶体管T16的栅极也电连接于所述使能端EN。所述自举电容C1电连接于上拉控制节点PU与输出端O1之间。所述保持电容C2与薄膜晶体管T16并联于下拉控制节点PD和地势点Vgl之间。
其中，本申请中，上述薄膜晶体管T1以N沟道型薄膜晶体管为例进行说明。在GOA电路1的预充电阶段，正常动作为使能端EN输出高电平使能信号，而导通前级输入电路11的薄膜晶体管T11，从而，高电平使能信号通过导通的薄膜晶体管T11对上拉控制节点PU充电，而将上拉控制节点PU的电压充高，同时使能端EN输出的高电平使能信号还导通下拉抑制电路15的薄膜晶体管T16，此时，导通的薄膜晶体管T16对下拉控制节点PD进行放电。随着上拉控制节点PU的电压充高达到输出薄膜晶体管12的阈值电压，则会使得输出薄膜晶体管12导通，此时，导通的输出薄膜晶体管12处于允许时钟信号端Clkb输出的扫描信号输出的准备状态。
此时，如果薄膜晶体管T12和T13由于阈值电压发生负向漂移，则会导致阈值电压过低，而导致误开启，则会形成对上拉控制节点PU的放电通路，而导致对上拉控制节点PU的预充电失败，而无法导通所述输出薄膜晶体管12，则GOA电路1在下一个周期就不能正常输出扫描脉冲，而导致工作异常。
而在上拉控制节点PU重置的阶段，正常动作为时钟重置端Clkrst输出时钟重置信号而控制薄膜晶体管T12导通，此时，高电势端Vgh提供的电压通过导通的薄膜晶体管T12对下拉控制节点PD充电，而逐渐抬高下拉控制节点PD的电压，当下拉控制节点PD的电压升高到大于或等于薄膜晶体管T1的阈值电压时，则会导通薄膜晶体管T13和T15，此时激活关闭机制，上拉控制节点PU将通过导通的薄膜晶体管T13放电，而重置为低电平，此时将无法导通 输出薄膜晶体管12，而使得输出薄膜晶体管12关闭，同时导通的薄膜晶体管T15则将输出端O1保持为低电平。
在这个阶段，如果下拉抑制电路15的薄膜晶体管T16由于发生负向漂移而导致阈值电压过低，则会导致下拉抑制电路15的薄膜晶体管T16可能会一定程度导通，造成下拉控制节点PD漏电，而无法升高到能够导通薄膜晶体管T13和T15的电压，而无法导通薄膜晶体管T13和T15，则会导致上拉控制节点PU放电失败，而造成GOA电路1在下一个时钟周期被误触发。
而在保持阶段，正常动作为通过保持电容C2保持下拉控制节点PD为高电平，同时，导通的薄膜晶体管T15通过将输出端O1与低电势端Vgl电连接，而将输出端O1的电压保持在低电平，同样的，导通的薄膜晶体管T13通过将上拉控制节点PU与低电势端Vgl电连接，而将上拉控制节点PU的电压保持在低电平。
在此阶段，如果下拉抑制电路15的薄膜晶体管T16由于发生负向漂移而导致阈值电压过低，则会导致下拉抑制电路15的薄膜晶体管T16可能会一定程度导通，造成下拉控制节点PD漏电，而无法升高到能够导通薄膜晶体管T13和T15的电压，而无法导通薄膜晶体管T13和T15，则同样无法实现上述的保持动作。同时，如果前级输入电路11的薄膜晶体管T11由于发生负向漂移而导致阈值电压过低，则薄膜晶体管T11可能会一定程度导通，而使得上拉控制节点PU获得额外电压提升，会造成GOA电路在下一个时钟周期误触发。
因此，由上可见，前级输入电路11的薄膜晶体管T11、薄膜晶体管T12、第一下拉电路13的薄膜晶体管T13、下拉抑制电路15的薄膜晶体管T16发生阈值电压漂移时，则会导致GOA电路1无法正常工作。
因此，在一些实施例中，所述加入了背栅10的薄膜晶体管T1包括前级输入电路11的薄膜晶体管T11、薄膜晶体管T12、第一下拉电路13的薄膜晶体管T13以及下拉抑制电路15的薄膜晶体管T16。
在一些情况中，第二下拉电路14的薄膜晶体管T15发生阈值电压漂移，例如阈值电压过低，同样会导致对输出端OUT的误放电。
因此，在一些实施例中，所述加入了背栅10的薄膜晶体管T1包括前级输入电路11的薄膜晶体管T11、薄膜晶体管T12、第一下拉电路13的薄膜晶体 管T13、第二下拉电路14的薄膜晶体管T15以及下拉抑制电路15的薄膜晶体管T16。
显然，在一些实施例中，第一下拉电路14中的薄膜晶体管T14发生阈值电压漂移，例如阈值电压过低，同样会导致对下拉控制节点PD的误放电。因此，在一些实施例中，所述加入了背栅10的薄膜晶体管T1包括前级输入电路11的薄膜晶体管T11、薄膜晶体管T12、第一下拉电路13的薄膜晶体管T13、薄膜晶体管T14、第二下拉电路14的薄膜晶体管T15以及下拉抑制电路15的薄膜晶体管T16。
因此，本申请中，通过选择性地在输出薄膜晶体管12之外的薄膜晶体管T1中增加背栅10这一结构去接入补偿电压，可有效避免该些薄膜晶体管T1发生阈值电压偏移，从而能够有效避免GOA电路1工作异常。
其中，所述高电势端Vgh提供的可为+5V等高电平电压，所述低电势端Vgl提供的可为0V等低电平电压。
请参阅图3，为增加了背栅10的薄膜晶体管T1的结构示意图。如图3所示，所述薄膜晶体管T1包括顶栅21、沟道层22、源极23以及漏极24，所述顶栅21与沟道层22层叠设置，源极23以及漏极24设置于沟道层22的两侧，通过沟道层22电连接，所述沟道层22的电阻受所述顶栅21控制，所述背栅10设置于沟道层22的远离顶栅21的另一面。
所述背栅10与顶栅21共同构成了薄膜晶体管T1的栅极。从而，通过背栅10接入补偿电压，可以将薄膜晶体管T1产生的阈值电压漂移补偿回来。
例如，如果某一个薄膜晶体管T1的阈值电压漂移了+2V，那么可以通过对背栅10施加一定的补偿电压，将阈值电压调回来。以薄膜晶体管T1为N沟道型晶体管为例，如果阈值电压向正向漂移，即比正常值增大，则可对背栅10施加正电压，而降低导通所述薄膜晶体管T1所需的阈值电压，抵消所述正向漂移。如果阈值电压为负向漂移，即，比正常值要小，则可对背栅10施加负电压，而增大导通所述薄膜晶体管T1所需的阈值电压，抵消所述负向漂移。从而，可通过对背栅10施加补偿电压而实现阈值电压的补偿和校正。
如图3所示，所述薄膜晶体管T1还包括位于沟道层22和顶栅21之间的顶栅氧化层25、覆盖顶栅21、源极23以及漏极24的介质隔离层26、与源极 23、漏极24电连接的金属导线27、位于沟道层22和背栅10之间的背栅氧化层28等。
在一些实施例中，所述顶栅21和背栅10等均为金属电极片。
在一些实施例中，所述薄膜晶体管T1通过图案化成型工艺而形成所包括顶栅21、背栅10、沟道层22、源极23以及漏极24等部分。
所述背栅10也可为通过涂布形成的导电金属层。
请参阅图4，为显示装置100的结构框图。如图4所示，显示装置100包括前述的GOA电路1、电压输出电路3以及漂移侦测电路4。其中，所述电压输出电路3包括至少一个直流电压端2。所述至少一个直流电压端2的数量与GOA电路1中增加了背栅10的薄膜晶体管T1的数量相同，每一直流电压端2与一相应的薄膜晶体管T1的背栅10电连接。
所述漂移侦测电路4用于侦测GOA电路1中的增加了背栅10的薄膜晶体管T1的阈值电压漂移值，所述电压输出电路3用于根据漂移侦测电路4侦测的每个增加了背栅10的薄膜晶体管T1的阈值电压漂移值，控制相应的直流电压端2输出相应的补偿电压，从而对相应的薄膜晶体管T1的阈值电压漂移进行补偿和校准。
其中，所述漂移侦测电路4可包括若干可侦测薄膜晶体管T1的侦测单元，例如，在一些情况下，薄膜晶体管T1的阈值电压漂移值与薄膜晶体管T1的某些参数，例如温度具有一定关系，通过在每个增加了背栅10的薄膜晶体管T1处设置一个可侦测相应参数，例如可侦测温度的温度传感器，来侦测薄膜晶体管T1的温度等参数，而可根据温度等参数得出相应的薄膜晶体管T1的阈值电压漂移值。
在一些实施例中，本申请中，各个增加了背栅10的薄膜晶体管T1的阈值电压漂移值也可通过仿真软件仿真得出，例如根据仿真软件得出使用时长与阈值电压漂移值的对应关系，从而，电压输出电路3可随着使用时长的增加，而相应得出对应的阈值电压漂移值，并控制输出相应的补偿电压即可。
显然，所述漂移侦测电路4还可为其他任意的可以侦测薄膜晶体管T1的阈值电压漂移值的电路。
其中，所述电压输出电路3可为电源管理芯片，可控制不同的直流电压端 2根据需要输出不同的电压，从而为各个增加了背栅10的薄膜晶体管T1提供相适配的补偿电压，而对每个薄膜晶体管T1的阈值电压漂移值进行针对性的补偿。
请参阅图5，为显示装置100的平面示意图。如图5所示，显示装置100还包括若干呈阵列分布的像素单元5，例如包括N行*M列个像素单元5，其中，N和M为大于1的自然数。其中，所述显示装置100包括的GOA电路1的数量为多个，且GOA电路1的数量与像素单元5的行数相同，例如为N个，每个GOA电路1与对应的一行像素单元5连接，用于对同一行像素单元5提供扫描信号。
其中，每个GOA电路1中相同位置处的薄膜晶体管T1中增加了背栅10，即，每个GOA电路1中增加了背栅10的薄膜晶体管T1在GOA电路1中的位置相同。例如，如前所述的，每个GOA电路1中的前级输入电路11的薄膜晶体管T11、薄膜晶体管T12、第一下拉电路13的薄膜晶体管T13、第二下拉电路14的薄膜晶体管T15以及下拉抑制电路15的薄膜晶体管T16中增加背栅10。
在一些实施例中，所有GOA电路1中相同位置处的薄膜晶体管T1的背栅10连接至同一个直流电压端2，而从同一个直流电压端2接收相同的补偿电压进行阈值电压漂移的补偿。这是由于，每个GOA电路的功能相同(都是产生一个扫描信号)、电路结构相同、使用频率相同，因此这些GOA电路的老化速率一致：需要得到的补偿也一致。因此可以把它们的背栅10连接到同一个直流电压端2上，统一补偿。
其中，本申请中，所述GOA电路1中的薄膜晶体管T1的背栅10可通过导线、FPC(柔性电路板)等方式连接至对应的直流电压端。
其中，所述若干GOA电路1可布设于显示装置100的非显示区，也可布设于显示装置100的若干像素单元5的下方，即布设于显示区域。
其中，所述显示装置100为包括AMOLED(Active Matrix Organic Light Emitting Diode；主动矩阵式有机发光二极管)、LCD(liquid crystal display，液晶显示屏)等类型在内的显示屏、显示面板，或者，可为包括具有相应显示屏、显示面板的手机、平板电脑、照相机等在内的电子装置。
以上所述是本发明的优选实施例，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也视为本发明的保护范围。

Claims (20)

  1. 一种阵列基板栅极驱动电路，其特征在于，所述阵列基板栅极驱动电路包括若干薄膜晶体管，至少一个薄膜晶体管的栅极的位置增加了背栅，每一增加了背栅的薄膜晶体管的背栅用于接入补偿电压，以补偿所述薄膜晶体管的阈值电压漂移。
  2. 如权利要求1所述的阵列基板栅极驱动电路，其特征在于，所述若干薄膜晶体管包括输出薄膜晶体管，所述增加了背栅的薄膜晶体管包括阵列基板栅极驱动电路中的输出薄膜晶体管之外的所有或部分的薄膜晶体管。
  3. 如权利要求2所述的阵列基板栅极驱动电路，其特征在于，所述增加了背栅的薄膜晶体管为从阵列基板栅极驱动电路中的输出薄膜晶体管之外的薄膜晶体管中根据预设标准而选择出来的薄膜晶体管。
  4. 如权利要求2所述的阵列基板栅极驱动电路，其特征在于，所述阵列基板栅极驱动电路包括前级输入电路、第一下拉电路、第二下拉电路以及下拉抑制电路，所述增加了背栅的薄膜晶体管包括前级输入电路、第一下拉电路、第二下拉电路以及下拉抑制电路中至少一个电路中的部分或全部薄膜晶体管。
  5. 如权利要求1所述的阵列基板栅极驱动电路，其特征在于，所述背栅为金属电极片。
  6. 如权利要求1-5任一项所述的阵列基板栅极驱动电路，其特征在于，所述薄膜晶体管包括顶栅、沟道层、源极以及漏极，所述顶栅与沟道层层叠设置，源极以及漏极设置于沟道层的两侧并通过沟道层电连接，所述沟道层的电阻受所述顶栅控制，所述背栅设置于沟道层的远离顶栅的另一面。
  7. 如权利要求6所述的阵列基板栅极驱动电路，其特征在于，所述背栅与顶栅共同构成了薄膜晶体管的栅极。
  8. 如权利要求6所述的阵列基板栅极驱动电路，其特征在于，所述薄膜晶体管还包括位于沟道层和顶栅之间的顶栅氧化层、覆盖顶栅、源极以及漏极的介质隔离层、与源极、漏极电连接的金属导线、位于沟道层和背栅之间的背栅氧化层。
  9. 一种薄膜晶体管，其特征在于，所述薄膜晶体管的栅极的位置增加了 背栅，所述背栅用于接入补偿电压，以补偿所述薄膜晶体管的阈值电压漂移。
  10. 如权利要求9所述的薄膜晶体管，其特征在于，所述背栅为金属电极片。
  11. 如权利要求9-10任一项所述的薄膜晶体管，其特征在于，所述薄膜晶体管包括顶栅、沟道层、源极以及漏极，所述顶栅与沟道层层叠设置，源极以及漏极设置于沟道层的两侧并通过沟道层电连接，所述沟道层的电阻受所述顶栅控制，所述背栅设置于沟道层的远离顶栅的另一面。
  12. 如权利要求11所述的薄膜晶体管，其特征在于，所述背栅与顶栅共同构成了薄膜晶体管的栅极。
  13. 如权利要求11所述的薄膜晶体管，其特征在于，所述薄膜晶体管还包括位于沟道层和顶栅之间的顶栅氧化层、覆盖顶栅、源极以及漏极的介质隔离层、与源极、漏极电连接的金属导线、位于沟道层和背栅之间的背栅氧化层。
  14. 一种显示装置，其特征在于，所述显示装置包括电压输出电路以及如权利要求1-8任一项所述的阵列基板栅极驱动电路，所述电压输出电路包括至少一个直流电压端，每一直流电压端用于与相应的增加了背栅的薄膜晶体管的背栅电连接，以为所述薄膜晶体管的背栅提供相应的补偿电压。
  15. 如权利要求14所述的显示装置，其特征在于，所述显示装置还包括漂移侦测电路，用于侦测阵列基板栅极驱动电路中的增加了背栅的薄膜晶体管的阈值电压漂移值，所述电压输出电路用于根据漂移侦测电路侦测的每个增加了背栅的薄膜晶体管的阈值电压漂移值控制相应的直流电压端输出相应的补偿电压，从而对相应的薄膜晶体管的阈值电压漂移进行补偿和校准。
  16. 如权利要求15所述的显示装置，其特征在于，所述电压输出电路为电源管理芯片，用于控制不同的直流电压端根据需要输出不同的电压，以为各个增加了背栅的薄膜晶体管提供相适配的补偿电压，而对每个薄膜晶体管的阈值电压漂移值进行针对性的补偿。
  17. 如权利要求14所述的显示装置，其特征在于，所述显示装置还包括若干呈阵列分布的像素单元，所述显示装置包括的阵列基板栅极驱动电路的数量为多个，且阵列基板栅极驱动电路的数量与像素单元的行数相同，每个阵列基板栅极驱动电路与对应的一行像素单元接，用于对同一行像素单元提供扫描 信号，其中，每个阵列基板栅极驱动电路中增加了背栅的薄膜晶体管在阵列基板栅极驱动电路中的位置相同。
  18. 如权利要求17所述的显示装置，其特征在于，所有阵列基板栅极驱动电路中相同位置处的薄膜晶体管的背栅连接至同一个直流电压端，而从同一个直流电压端接收相同的补偿电压进行阈值电压漂移的补偿。
  19. 如权利要求17所述的显示装置，其特征在于，所述阵列基板栅极驱动电路中的薄膜晶体管的背栅通过导线或FPC连接至对应的直流电压端。
  20. 如权利要求14所述的显示装置，其特征在于，所述显示装置为包括AMOLED和LCD类型在内的显示屏、显示面板，或者，为具有相应显示屏、显示面板的包括手机、平板电脑、照相机在内的电子装置。
PCT/CN2018/109069 2018-09-30 2018-09-30 阵列基板栅极驱动电路、薄膜晶体管及显示装置 WO2020062230A1 (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
PCT/CN2018/109069 WO2020062230A1 (zh) 2018-09-30 2018-09-30 阵列基板栅极驱动电路、薄膜晶体管及显示装置
CN201880094120.9A CN112639940A (zh) 2018-09-30 2018-09-30 阵列基板栅极驱动电路、薄膜晶体管及显示装置
TW108100612A TW202015028A (zh) 2018-09-30 2019-01-08 陣列基板柵極驅動電路、薄膜電晶體及顯示裝置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2018/109069 WO2020062230A1 (zh) 2018-09-30 2018-09-30 阵列基板栅极驱动电路、薄膜晶体管及显示装置

Publications (1)

Publication Number Publication Date
WO2020062230A1 true WO2020062230A1 (zh) 2020-04-02

Family

ID=69950207

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2018/109069 WO2020062230A1 (zh) 2018-09-30 2018-09-30 阵列基板栅极驱动电路、薄膜晶体管及显示装置

Country Status (3)

Country Link
CN (1) CN112639940A (zh)
TW (1) TW202015028A (zh)
WO (1) WO2020062230A1 (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112382619A (zh) * 2020-11-13 2021-02-19 京东方科技集团股份有限公司 一种显示背板及其控制方法
CN113823236A (zh) * 2020-06-19 2021-12-21 凸版印刷株式会社 移位寄存器及显示装置
CN115909938A (zh) * 2022-11-24 2023-04-04 惠科股份有限公司 Goa驱动电路、装置以及显示装置

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114170967A (zh) * 2021-12-22 2022-03-11 云谷（固安）科技有限公司 阵列基板、阵列基板的制作方法和显示面板

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030001832A1 (en) * 1998-06-12 2003-01-02 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
CN101556833A (zh) * 2008-04-11 2009-10-14 北京京东方光电科技有限公司 移位寄存器及液晶显示器栅极驱动装置
CN102163400A (zh) * 2010-02-19 2011-08-24 瑞萨电子株式会社 解码器及使用该解码器的显示装置的数据驱动器
CN102484471A (zh) * 2009-10-30 2012-05-30 株式会社半导体能源研究所 驱动器电路、包括该驱动器电路的显示设备和包括该显示设备的电子设备
CN108257549A (zh) * 2016-12-29 2018-07-06 乐金显示有限公司 电致发光显示器
CN108269760A (zh) * 2016-12-30 2018-07-10 乐金显示有限公司 薄膜晶体管及其制造方法以及包括其的有机发光显示装置

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105741781B (zh) * 2016-04-12 2018-10-26 深圳市华星光电技术有限公司 Amoled像素驱动电路及像素驱动方法
CN106356015B (zh) * 2016-10-31 2020-05-12 合肥鑫晟光电科技有限公司 移位寄存器及驱动方法、显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030001832A1 (en) * 1998-06-12 2003-01-02 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
CN101556833A (zh) * 2008-04-11 2009-10-14 北京京东方光电科技有限公司 移位寄存器及液晶显示器栅极驱动装置
CN102484471A (zh) * 2009-10-30 2012-05-30 株式会社半导体能源研究所 驱动器电路、包括该驱动器电路的显示设备和包括该显示设备的电子设备
CN102163400A (zh) * 2010-02-19 2011-08-24 瑞萨电子株式会社 解码器及使用该解码器的显示装置的数据驱动器
CN108257549A (zh) * 2016-12-29 2018-07-06 乐金显示有限公司 电致发光显示器
CN108269760A (zh) * 2016-12-30 2018-07-10 乐金显示有限公司 薄膜晶体管及其制造方法以及包括其的有机发光显示装置

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113823236A (zh) * 2020-06-19 2021-12-21 凸版印刷株式会社 移位寄存器及显示装置
CN112382619A (zh) * 2020-11-13 2021-02-19 京东方科技集团股份有限公司 一种显示背板及其控制方法
CN115909938A (zh) * 2022-11-24 2023-04-04 惠科股份有限公司 Goa驱动电路、装置以及显示装置

Also Published As

Publication number Publication date
CN112639940A (zh) 2021-04-09
TW202015028A (zh) 2020-04-16

Similar Documents

Publication Publication Date Title
WO2020062230A1 (zh) 阵列基板栅极驱动电路、薄膜晶体管及显示装置
US10109251B2 (en) Gate driver on array (GOA) circuit of IGZO thin film transistor and display device thereof
US10453389B2 (en) Pixel circuit, organic electroluminescent display panel and display apparatus
US9396813B2 (en) Shift register cell, shift register, gate driver and display panel
US9887013B2 (en) Shift register unit, shift register, and display apparatus
EP3163562B1 (en) Pixel circuit, display panel and display device
US20190066597A1 (en) Goa unit and driving method thereof, goa circuit, display device
US20140064439A1 (en) Shift Register Unit, Shift Register And Display Apparatus
EP3444802A1 (en) Drive method for preventing afterimage on display panel during power-off, and display device
US10559258B2 (en) Pixel circuit and driving method, array substrate, and display apparatus
US20170193879A1 (en) Pixel compensation circuit and method for driving the same, display panel and display device
US20170092375A1 (en) Shift register and driving method thereof, and gate driving circuit
US10777118B2 (en) Shift register and method for driving the same, gate driving circuit and display device
US11217175B2 (en) Pixel-driving circuit and method, and a display utilizing the same
US11594182B2 (en) Gate driver on array (GOA) circuit, display panel and threshold voltage compensating method for a thin film transistor
US11328675B2 (en) Shift register unit, driving method, gate driving circuit, and display device
US10658352B2 (en) Protective circuit, array substrate and display panel
JP2018180414A (ja) 液晶表示装置
KR20150069787A (ko) 더블 게이트 트랜지스터를 갖는 시프트 레지스터
US9240155B2 (en) Driving circuit and driving method thereof and liquid crystal display
US10902813B2 (en) Shift register and display device provided with same
KR20150086771A (ko) 게이트 드라이버 및 그것을 포함하는 표시 장치
WO2020199553A1 (zh) 电平转换控制电路与电平转换电路
JP2011048225A (ja) 液晶表示装置
US10832605B2 (en) Inverter circuit and driving method thereof, array substrate and detection method thereof, and display apparatus including the same

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18935155

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 18935155

Country of ref document: EP

Kind code of ref document: A1