WO2020051832A1 - 静电泄放保护电路及集成电路芯片 - Google Patents

静电泄放保护电路及集成电路芯片 Download PDF

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WO2020051832A1
WO2020051832A1 PCT/CN2018/105486 CN2018105486W WO2020051832A1 WO 2020051832 A1 WO2020051832 A1 WO 2020051832A1 CN 2018105486 W CN2018105486 W CN 2018105486W WO 2020051832 A1 WO2020051832 A1 WO 2020051832A1
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Prior art keywords
field effect
voltage
module
effect transistor
unit
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French (fr)
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张�浩
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Shenzhen Goodix Technology Co Ltd
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Shenzhen Goodix Technology Co Ltd
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Priority to PCT/CN2018/105486 priority Critical patent/WO2020051832A1/zh
Priority to CN201880001540.8A priority patent/CN109314388B/zh
Publication of WO2020051832A1 publication Critical patent/WO2020051832A1/zh
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
    • H02H9/045—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere
    • H02H9/047—Free-wheeling circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/811—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using FETs as protective elements

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  • the present application relates to the field of electronic technology, and in particular, to an electrostatic discharge protection circuit and an integrated circuit chip.
  • Electrostatic discharge is a transient process in which a large amount of electric charge is poured into an integrated circuit from the outside to the inside of the integrated circuit when it is floating. In this process, it is easy to cause the failure of the integrated circuit chip.
  • FIG. 1 a typical electrostatic discharge protection circuit in the prior art is shown in FIG. 1 and includes a capacitor C1, a capacitor C3, a resistor R1, and field effect transistors M1, M2, M3, M4, M5, M6, and M7. , M8, and M9.
  • VDDH at the power supply pins is slowly powered on, GND is at 0 potential, M5, M6, M7, M8, and M9 provide the VDDH to GND voltage division, and VM is the intermediate potential obtained after VDDH voltage division (VM equals 0.5VDDH) ), VG_ND is low, M2 is on, M1 is off, there is no leakage from VDDH to GND, and the potential between VM and VDDH is not too high to break through M2.
  • VDDH During the VDDH electrostatic attack at the power pin, VDDH increases sharply, the power pin is at a high potential, the VM potential is pulled up under the coupling of C3, and the capacitor C1 is slowly charged through the resistor R1, and VG_ND is pulled to VM , M1 and M2 are turned on at the same time to achieve electrostatic discharge at VDDH.
  • VG_ND before the upper plate of C1 is charged to a high potential, VG_ND is always at the same high potential as VM, and static electricity is discharged from VDDH to GND through M1 and M2.
  • M1 is turned off, and the static discharge path is disconnected.
  • VM in the above circuit is coupled by C3 to a high level as close to VDDH as possible.
  • M1 and M2 it is necessary to make VM equal to VDDH, but under this condition, the size of M2 is larger, the required capacitance of capacitor C3 is larger, and the size of C3 is larger, so that the layout area of the entire circuit It is very large, and it is easy to cause waste of chip area.
  • the purpose of some embodiments of the present application is to provide an electrostatic discharge protection circuit and an integrated circuit chip, which aim to reduce the layout area of the electrostatic discharge circuit and obtain a stronger electrostatic discharge capability.
  • An embodiment of the present application provides an electrostatic discharge protection circuit, including a field effect tube triggering module, a voltage dividing module, and a bleeding module connected in parallel between a power pin and a ground pin; wherein the voltage dividing module includes a first A voltage dividing unit and a second voltage dividing unit, the first voltage dividing unit and the second voltage dividing unit are connected in series, and the connection point of the first voltage dividing unit and the second voltage dividing unit is used as an output terminal of the voltage dividing module;
  • the output of the FET trigger module is connected to the output of the voltage divider module
  • the output of the voltage divider module is connected to the input of the bleeder module
  • the FET trigger module is turned on when the power pin is subjected to electrostatic attack, the first voltage dividing unit is shorted, the voltage of the output terminal of the voltage dividing module is pulled up to a high level, the bleeder module is turned on and the power pin is discharged. Of static electricity.
  • An embodiment of the present application further provides an integrated circuit chip including the above-mentioned electrostatic discharge protection circuit.
  • the embodiment of the present application provides a field effect tube triggering module in the electrostatic discharge protection circuit to replace the capacitor C3 in the prior art.
  • the field effect tube triggering module is directly guided when the power pin is subjected to electrostatic attack.
  • the output terminal voltage of the voltage-dividing module is pulled up to a high level.
  • the bleeder module is turned on, and a point of static electricity at the power pin is discharged to the ground through the bleeder module.
  • the field-effect transistor trigger module is directly turned on, the voltage at the output end of the voltage-dividing module can be pulled up to be equal to the voltage at the power supply pin, without the need for coupling through capacitors. Capacity, and reduce the overall layout area of the electrostatic discharge circuit.
  • the FET trigger module specifically includes: a detection unit and a FET; the detection unit is connected between the power pin and the ground pin, and the output end of the detection unit is connected to the gate of the FET; The source is connected to the power pin, and the drain is used as the output terminal of the FET trigger module. Among them, when the power pin is electrostatically attacked, the output of the detection unit is low.
  • This embodiment provides a specific implementation form of the FET trigger module, which increases the flexibility of the embodiments of the present application.
  • the detection unit is used to ensure that the FET has no risk of overvoltage during static operation, and the FET trigger module is more reliable.
  • the detection unit specifically includes: a resistor and a capacitor; the resistor and the capacitor are connected in series between the power pin and the ground pin in sequence; wherein the connection end of the resistor and the capacitor serves as the output end of the detection unit.
  • the structure of the detection unit provided in this embodiment is relatively simple.
  • the field-effect tube triggering module specifically includes a third voltage-dividing unit, a fourth voltage-dividing unit, a detection unit, a driving unit, and a field-effect tube; a first end of the third voltage-dividing unit is connected to a power pin, and a second end Connected to the first end of the fourth voltage division unit; the second end of the fourth voltage division unit is connected to the ground pin; the detection unit and the drive unit are connected in parallel between the power pin and the ground pin; the third voltage division unit The second end of the MOSFET is connected to the first input of the drive unit; the output of the detection unit is connected to the second input of the drive unit; the gate of the FET is connected to the output of the drive unit, and the source is connected to the power pin The drain is used as the output terminal of the FET trigger module.
  • the second terminal of the third voltage dividing unit When the power pin is subjected to electrostatic attack, the second terminal of the third voltage dividing unit is low, and the output of the detection unit is high. The output is low.
  • This embodiment provides a specific implementation form of the FET trigger module, which increases the flexibility of the embodiments of the present application.
  • the detection unit and the driving unit are used to ensure that the FET has no risk of overvoltage during static operation, and the FET trigger module is more reliable.
  • the detection unit specifically includes: a capacitor and a resistor; the capacitor and the resistor are connected in series between the power pin and the ground pin in sequence; wherein the connection end of the capacitor and the resistance is used as the output terminal of the detection unit.
  • the structure of the detection unit provided in this embodiment is relatively simple.
  • the driving unit specifically includes: a first field-effect transistor, a second field-effect transistor, a third field-effect transistor, and a fourth field-effect transistor; the gate of the first field-effect transistor is connected to the output terminal of the detection unit, and the source and The ground pin is connected, the drain is connected to the source of the second FET; the gate of the second FET is connected to the second end of the third voltage division unit, and the drain is connected to the drain of the third FET ; The source of the third FET is connected to the power pin, the gate is connected to the source of the fourth FET; the gate of the fourth FET is connected to the second end of the third voltage-dividing unit, and the drain Connected to the output of the detection unit.
  • This embodiment provides a specific implementation form of the driving unit, which increases the flexibility of the embodiments of the present application.
  • the driving unit is composed of a plurality of field effect transistors, and the layout area of the driving unit is small.
  • FIG. 1 is a circuit diagram of an electrostatic discharge protection circuit in the prior art
  • FIG. 2 is a schematic diagram of an electrostatic discharge protection circuit in the first embodiment of the present application.
  • FIG. 3 is a schematic diagram of an electrostatic discharge protection circuit in a second embodiment of the present application.
  • the first embodiment of the present application relates to an electrostatic discharge protection circuit, as shown in FIG. 2, including a field effect tube trigger module, a voltage division module, and a bleeder module connected in parallel between a power pin VDDH and a ground pin GND. 103.
  • the voltage dividing module includes a first voltage dividing unit 1021 and a second voltage dividing unit 1022.
  • the first voltage dividing unit 1021 and the second voltage dividing unit 1022 are connected in series, and the first voltage dividing unit 1021 and the second voltage dividing unit 1022.
  • the connection point is used as the output of the voltage divider module.
  • the output terminal of the field effect tube triggering module is connected to the output terminal of the voltage dividing module, and the output terminal of the voltage dividing module is connected to the input terminal of the bleeder module 103.
  • the FET trigger module is turned on when the power pin VDDH is subjected to an electrostatic attack, the first voltage dividing unit 1021 is shorted, the output terminal voltage of the voltage dividing module is pulled up to a high level, and the bleeder module 103 is turned on and discharged. Discharge the static electricity at the pin VDDH.
  • the field-effect transistor triggering module includes a detection unit 1011 and a field-effect transistor M10.
  • the detection unit 1011 is connected between the power pin VDDH and the ground pin GND, and the output terminal of the detection unit 1011 is connected to the gate of the field effect transistor M10.
  • the source of the MOSFET M10 is connected to the power pin VDDH, and the drain is used as the output terminal of the MOSFET trigger module.
  • the detection unit 1011 includes a resistor R2 and a capacitor C2.
  • the resistor R2 and the capacitor C2 are connected in series between the power pin VDDH and the ground pin GND in order.
  • the connection terminal of the resistor R2 and the capacitor C2 is used as the output terminal of the detection unit, that is, RC2_OUT is used as the output terminal.
  • the first voltage dividing unit 1021 may include field effect transistors M7, M8, and M9.
  • the specific connection relationship may be as shown in FIG. 2:
  • the source of M9 is connected to VDDH.
  • the gate of M9 is connected to the drain and connected to the source of M8.
  • the gate of M8 is connected to the drain and connected to the source of M7.
  • the gate of M7 is connected to the drain, and is connected to the second voltage dividing unit 1022.
  • the second voltage dividing unit 1022 may include field effect transistors M5 and M6.
  • the specific connection relationship may be as shown in FIG. 2, that is, the gate of M7 is connected to the drain, and the gate and drain of M6 are connected, and the source of M6
  • the electrode is connected to the gate and drain of M5, and the source of M5 is connected to the ground pin GND.
  • the bleed module 103 includes a buffer unit, an inverter, a fifth field-effect transistor M1 and a sixth field-effect transistor M2.
  • the buffer unit and the inverter are connected in parallel between the output terminal of the voltage dividing module and the ground pin GND.
  • the output of the buffer unit is connected to the input of the inverter, the output of the inverter is connected to the gate of M1, the source of M1 is connected to the ground pin GND, and the drain is connected to the source of M2.
  • the drain of M2 is connected to the power pin VDDH, and the gate is used as the input terminal of the bleeder module 103.
  • the buffer unit is an RC oscillation circuit, which is composed of a resistor R1 and a capacitor C1.
  • One end of the resistor R1 is connected to the output end of the voltage dividing module, and the other end is connected to C1, and C1 is also connected to the ground pin GND.
  • the inverter consists of field-effect transistors M3 and M4. The specific connection is shown in Figure 2.
  • VDDH has not been attacked by static electricity
  • VDDH is slowly powered on.
  • M5, M6, M7, M8, and M9 provide the voltage division from VDDH to GND.
  • VM is the intermediate potential obtained after VDDH division. VM is equal to 0.5VDDH, and M2 is turned on.
  • RC1_OUT is high, RC1_OUT is VG_ND via the inverter, VG_ND is low, M1 is off, there is no static current, and the bleeder module 103 is not turned on.
  • RC2_OUT is high-level VDDH, M10 is in the off state, there is no quiescent current, and because the drain voltage of M10 is VM, there is no risk of overvoltage in M10.
  • VDDH is subject to electrostatic attack
  • VDDH voltage increases sharply, and R2 and C2 in the detection unit 1011 are too late to respond, so RC2_OUT is low relative to VDDH, M10 is turned on, the first voltage dividing unit 1021 is shorted, and VM is pulled up to VDDH, M2 Continuity.
  • R1 and C1 in the buffer unit are too late to respond, so RC1_OUT is low level relative to VM, RC1_OUT gets VG_ND through the inverter, VG_ND is high level, and M1 is turned on. Since M1 and M2 are both on, that is, the bleeder module 103 is on, the static electricity at VDDH is discharged to GND through M1 and M2.
  • a field-effect transistor triggering module is provided in the electrostatic discharge protection circuit to replace the capacitor C3 in the prior art.
  • the field-effect transistor triggering module directly conducts electricity when the power pin VDDH is subjected to an electrostatic attack.
  • the output terminal voltage of the voltage dividing module is pulled up to a high level.
  • the bleeder module 103 is turned on, and a point of static electricity at the power pin VDDH is discharged to the ground through the bleeder module 103.
  • the field-effect transistor trigger module is directly turned on, the voltage of the output terminal of the voltage-dividing module can be pulled up to be equal to the voltage at the power pin VDDH, and no coupling is required through the capacitor. Discharge capacity, and reduce the overall layout area of the electrostatic discharge circuit.
  • the second embodiment of the present application relates to an electrostatic discharge protection circuit, as shown in FIG. 3.
  • the second embodiment is substantially the same as the first embodiment, and the main difference is that the implementation form of the field effect tube trigger module is different, which will be described in detail below:
  • the field-effect transistor triggering module specifically includes a third voltage-dividing unit 1012, a fourth voltage-dividing unit 1013, a detection unit 1011, a driving unit 1014, and a field-effect tube M10.
  • the first terminal of the third voltage dividing unit 1012 is connected to the power pin VDDH
  • the second terminal is connected to the first terminal of the fourth voltage dividing unit 1013
  • the second terminal of the fourth voltage dividing unit 1013 is connected to the ground pin GND.
  • the detection unit 1011 and the driving unit 1014 are both connected in parallel between the power pin VDDH and the ground pin GND.
  • the second terminal of the third voltage dividing unit 1012 is connected to the first input terminal of the driving unit 1014, the output terminal of the detecting unit 1011 is connected to the second input terminal of the driving unit 1014, and the gate of the field effect tube M10 is connected to the driving unit 1014.
  • the output terminal is connected, the source is connected to the power pin VDDH, and the drain is used as the output terminal of the FET trigger module.
  • the second terminal of the third voltage dividing unit 1012 is at a low level
  • the output terminal of the detection unit 1011 is at a high level
  • the output terminal of the driving unit 1013 is at a low level.
  • the detection unit 1011 includes a capacitor C3 and a resistor R3.
  • the capacitor C3 and the resistor R3 are connected in series between the power pin VDDH and the ground pin GND.
  • the connection terminal of the capacitor C3 and the resistor R3 serves as an output terminal of the detection unit 1011.
  • the third voltage-dividing unit 1012 includes field-effect transistors M17, M18, and M19.
  • the specific connection is shown in FIG. That is, the source of M19 is connected to VDDH.
  • the gate of M19 is connected to the drain and is connected to the source of M18.
  • the gate of M18 is connected to the drain and is connected to the source of M17.
  • the gate of M17 is connected to the drain, and is connected to the second voltage dividing unit 1013.
  • the second voltage dividing unit 1013 includes field effect tubes M15 and M16, and the specific connection is shown in FIG. 3. That is, the gate of M17 is connected to the gate and drain of M6, the source of M16 is connected to the gate and drain of M15, and the source of M15 is connected to the ground pin GND.
  • the driving unit 1014 includes a first field effect tube M11, a second field effect tube M12, a third field effect tube M13, and a fourth field effect tube M14.
  • the gate of M11 is connected to the output terminal of detection unit 1011, the source is connected to the ground pin, and the drain is connected to the source of M12.
  • the gate of M12 is connected to the second end of the third voltage dividing unit 1012, and the drain is connected to the drain of M13.
  • the source of M13 is connected to the power pin VDDH, and the gate is connected to the source of M14.
  • the gate of M14 is connected to the second terminal of the third voltage division unit 1012, and the drain is connected to the output terminal of the detection unit 1011.
  • VDDH has not been attacked by static electricity.
  • VDDH powers up slowly.
  • M5, M6, M7, M8, and M9 provide the voltage division from VDDH to GND.
  • VM is the intermediate potential obtained after VDDH division.
  • VM is equal to 0.5VDDH, VM is high, M2 is on, and RC2_OUT is low Level, M11 is off.
  • M15, M16, M17, M18, and M19 provide the voltage division from VDDH to GND
  • VX is the intermediate potential obtained after VDDH division.
  • VX is equal to 0.5VDDH, VX is high, and M14 and M12 are turned off.
  • the gate of M13 is low level, M13 is turned on, the gate voltage of M10 is pulled to a high potential VDDH by M13, M10 is in the off state, and no leakage will occur in M10 and M11. Since VM is equal to 0.5VDDH and VM is high level, RC1_OUT is high level, RC1_OUT is VG_ND via the inverter, VG_ND is low level, M1 is turned off, there is no static current, and the bleeder module 103 is not turned on.
  • VDDH is attacked by static electricity.
  • VDDH voltage increases sharply, RC2_OUT is high level, VX is equal to 0.5VDDH, VX is high level, M11, M12, M14 are turned on at the same time, so that the gate voltage of M10 is pulled to low level GND, and M10 is turned on, so that VM is pulled to VDDH and M2 is turned on.
  • R1 and C1 in the buffer unit are too late to respond, so RC1_OUT is low level relative to VM, RC1_OUT gets VG_ND through the inverter, VG_ND is high level, and M1 is turned on.
  • a field-effect transistor triggering module is provided in the electrostatic discharge protection circuit to replace the capacitor C3 in the prior art.
  • the field-effect transistor triggering module directly conducts electricity when the power pin VDDH is subjected to an electrostatic attack.
  • the output terminal voltage of the voltage dividing module is pulled up to a high level.
  • the bleeder module 103 is turned on, and a point of static electricity at the power pin VDDH is discharged to the ground through the bleeder module 103.
  • the field-effect transistor trigger module is directly turned on, the voltage of the output terminal of the voltage-dividing module can be pulled up to be equal to the voltage at the power pin VDDH, without the need for coupling through the capacitor, so that the strong discharge of the electrostatic discharge circuit can be achieved. Discharge capacity, and reduce the overall layout area of the electrostatic discharge circuit.
  • the third embodiment of the present application relates to an integrated circuit chip, and the integrated circuit chip is provided with the electrostatic discharge protection circuit mentioned in the above embodiment.

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Abstract

本申请涉及电子技术领域，提供了一种静电泄放保护电路及集成电路芯片。静电泄放保护电路包括：并联在电源接脚与接地接脚之间的场效应管触发模块、分压模块与泄放模块(103)；分压模块包括第一分压单元(1021)与第二分压单元(1022)；第一分压单元与第二分压单元串联连接，连接点作为分压模块的输出端；场效应管触发模块的输出端与分压模块的输出端连接；分压模块的输出端与泄放模块的输入端连接；场效应管触发模块在电源接脚受到静电攻击时导通，第一分压单元被短路，分压模块的输出端电压被上拉至高电平，泄放模块导通并泄放电源接脚处的静电。本申请能够缩小静电泄放电路的版图面积，并获取更强的静电泄放能力。

Description

静电泄放保护电路及集成电路芯片 技术领域
本申请涉及电子技术领域，特别涉及一种静电泄放保护电路及集成电路芯片。
背景技术
在集成电路芯片的生产、封装、测试、运输等过程中，都会出现不同程度的静电泄放事件。静电泄放是集成电路浮接的情况下，大量的电荷从外向内灌入集成电路的瞬间过程，在此过程中很容易造成集成电路芯片的失效。
本专利申请的发明人发现：现有技术典型的静电泄放保护电路如图1所示，包括电容C1、电容C3、电阻R1以及场效应晶体管M1、M2、M3、M4、M5、M6、M7、M8以及M9。在正常工作时，电源接脚处VDDH缓慢上电，GND为0电位，M5、M6、M7、M8以及M9提供VDDH到GND的分压，VM为VDDH分压后所得中间电位(VM等于0.5VDDH)，VG_ND为低电平，M2导通，M1截止，没有从VDDH至GND的漏电，并且实现VM和VDDH之间的电位不会太高而击穿M2。在电源接脚处VDDH静电攻击时，VDDH猛增，电源接脚处为高电位，在C3的耦合作用下VM电位被拉高，同时通过电阻R1为电容C1缓慢充电，VG_ND被拉高至VM，M1和M2同时导通实现VDDH处的静电泄放。其中，C1上极板充至高电位前，VG_ND一直处于与 VM相同的高电位，静电由VDDH经M1和M2泄放至GND。C1上极板充至高电位时，VG_ND被拉至GND，此时M1截止，静电泄放通路断开。
不难看出，上述电路中的VM是靠C3耦合至尽可能接近VDDH的高电平。为实现M1和M2最高的放电能力，需使得VM等于VDDH，但在此条件下，M2尺寸较大，所需要的电容C3容值较大，C3尺寸也较大，从而使得整个电路的版图面积很大，容易造成芯片面积的浪费。
发明内容
本申请部分实施例的目的在于提供一种静电泄放保护电路及集成电路芯片，旨在缩小静电泄放电路的版图面积，并获取更强的静电泄放能力。
本申请实施例提供了一种静电泄放保护电路，包括：并联在电源接脚与接地接脚之间的场效应管触发模块、分压模块以及泄放模块；其中，分压模块包括第一分压单元以及第二分压单元，第一分压单元与第二分压单元串联连接，且第一分压单元与第二分压单元的连接点作为分压模块的输出端；
场效应管触发模块的输出端与分压模块的输出端连接；
分压模块的输出端与泄放模块的输入端连接；
场效应管触发模块在电源接脚受到静电攻击时导通，第一分压单元被短路，分压模块的输出端电压被上拉至高电平，泄放模块导通并泄放电源接脚处的静电。
本申请实施例还提供了一种集成电路芯片，包括上述的静电泄放保护电路。
本申请实施例相对于现有技术而言，在静电泄放保护电路中设置场效应 管触发模块来替代现有技术中的电容C3，场效应管触发模块在电源接脚受到静电攻击时直接导通，实现分压模块的输出端电压被上拉至高电平，此时泄放模块导通，电源接脚处点静电经泄放模块泄放至地。其中，由于场效应管触发模块直接导通便可以实现分压模块的输出端电压上拉至与电源接脚处电压相等，无需借助电容进行耦合，因而能够实现静电泄放电路的较强泄放能力，并缩小静电泄放电路的整体版图面积。
另外，场效应管触发模块具体包括：检测单元以及场效应管；检测单元连接在电源接脚以及接地接脚之间，且检测单元的输出端与场效应管的栅极连接；场效应管的源极与电源接脚连接，漏极作为场效应管触发模块的输出端；其中，电源接脚静电攻击时，检测单元的输出端为低电平。本实施例提供了场效应管触发模块的一种具体实现形式，增加了本申请实施例的灵活性。并且，利用检测单元来保证场效应管在静态工作时没有过压风险，场效应管触发模块更可靠。
另外，检测单元具体包括：电阻以及电容；电阻以及电容依次串联在电源接脚以及接地接脚之间；其中，电阻与电容的连接端作为检测单元的输出端。本实施例提供的检测单元结构较为简单。
另外，场效应管触发模块具体包括：第三分压单元、第四分压单元、检测单元、驱动单元以及场效应管；第三分压单元的第一端与电源接脚连接，第二端与第四分压单元的第一端连接；第四分压单元的第二端与接地接脚连接；检测单元以及驱动单元均并联在电源接脚以及接地接脚之间；第三分压单元的第二端与驱动单元的第一输入端连接；检测单元的输出端与驱动单元的第二输入端连接；场效应管的栅极与驱动单元的输出端连接，源极与电源接脚连接， 漏极作为场效应管触发模块的输出端；其中，电源接脚受到静电攻击时，第三分压单元的第二端为低电平，检测单元的输出端为高电平，驱动单元的输出端为低电平。本实施例提供了场效应管触发模块的一种具体实现形式，增加了本申请实施例的灵活性。并且，利用检测单元以及驱动单元来保证场效应管在静态工作时没有过压风险，场效应管触发模块更可靠。
另外，检测单元具体包括：电容以及电阻；电容以及电阻依次串联在电源接脚以及接地接脚之间；其中，电容与电阻的连接端作为检测单元的输出端。本实施例提供的检测单元结构较为简单。
另外，驱动单元具体包括：第一场效应管、第二场效应管、第三场效应管以及第四场效应管；第一场效应管的栅极与检测单元的输出端连接，源极与接地接脚连接，漏极与第二场效应管的源极连接；第二场效应管的栅极与第三分压单元的第二端连接，漏极与第三场效应管的漏极连接；第三场效应管的源极与电源接脚连接，栅极与第四场效应管的源极连接；第四场效应管的栅极与第三分压单元的第二端连接，漏极与检测单元的输出端连接。本实施例提供了驱动单元的一种具体实现形式，增加了本申请实施例的灵活性。并且，驱动单元是由多个场效应管构成的，驱动单元的版图面积较小。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，附图中具有相同参考数字标号的元件表示为类似的元件，除非有特别申明，附图中的图不构成比例限制。
图1是现有技术中静电泄放保护电路的电路图；
图2是本申请第一实施例中的静电泄放保护电路的示意图；
图3是本申请第二实施例中的静电泄放保护电路的示意图。
具体实施方式
为了使本申请的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本申请部分实施例进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本申请，并不用于限定本申请。
本申请第一实施例涉及一种静电泄放保护电路，如图2所示，包括：并联在电源接脚VDDH与接地接脚GND之间的场效应管触发模块、分压模块以及泄放模块103。其中，分压模块包括第一分压单元1021以及第二分压单元1022，第一分压单元1021与第二分压单元1022串联连接，且第一分压单元1021与第二分压单元1022的连接点作为分压模块的输出端。
具体地说，场效应管触发模块的输出端与分压模块的输出端连接，分压模块的输出端与泄放模块103的输入端连接。其中，场效应管触发模块在电源接脚VDDH受到静电攻击时导通，第一分压单元1021被短路，分压模块的输出端电压被上拉至高电平，泄放模块103导通并泄放电源接脚VDDH处的静电。以下对本实施例中静电泄放保护电路各功能模块的具体结构进行说明：
场效应管触发模块，包括：检测单元1011以及场效应管M10。检测单元1011连接在电源接脚VDDH以及接地接脚GND之间，且检测单元1011的输出端与场效应管M10的栅极连接。场效应管M10的源极与电源接脚VDDH连接，漏极作为场效应管触发模块的输出端。
其中，检测单元1011包括电阻R2以及电容C2。电阻R2以及电容C2 依次串联在电源接脚VDDH以及接地接脚GND之间。电阻R2与电容C2的连接端作为检测单元的输出端，即RC2_OUT作为输出端。
第一分压单元1021可以包括场效应管M7、M8以及M9，具体连接关系可以如图2所示：M9的源极连接至VDDH。M9的栅极与漏极连接，并连接至M8的源极。M8的栅极与漏极连接，并连接至M7的源极。M7的栅极与漏极连接，并连接至第二分压单元1022。第二分压单元1022可以包括场效应管M5、M6，具体连接关系可以如图2所示，即，M7的栅极与漏极连接，并与M6的栅极以及漏极连接，M6的源极与M5的栅极以及漏极连接，M5的源极连接至接地接脚GND。
泄放模块103包括缓冲单元、反相器、第五场效应管M1以及第六场效应管M2。缓冲单元以及反相器并联在分压模块的输出端以及接地接脚GND之间。缓冲单元的输出端与反相器的输入端连接，反相器的输出端与M1的栅极连接，M1的源极与接地引脚GND连接，漏极与M2的源极连接。M2的漏极与电源引脚VDDH连接，栅极作为泄放模块103的输入端。
其中，缓冲单元为RC振荡电路，由电阻R1以及电容C1构成。电阻R1一端与分压模块的输出端连接，另一端与C1连接，C1还与接地引脚GND连接。反相器由场效应管M3、M4构成，具体连接如图2所示。
以下对本实施例中静电泄放电路的工作原理进行解释说明：
(1)VDDH未受到静电攻击：
VDDH缓慢上电，M5、M6、M7、M8以及M9提供VDDH到GND的分压，VM为VDDH分压后所得中间电位，VM等于0.5VDDH，M2导通。RC1_OUT为高电平，RC1_OUT经反相器得到VG_ND，VG_ND为低电平， M1截止，没有静态电流，泄放模块103不导通。此时，RC2_OUT为高电平VDDH，M10处于截止状态，无静态电流，且由于M10的漏极电压为VM，因此M10没有过压风险。
(2)VDDH受到静电攻击：
VDDH电压猛增，而检测单元1011中的R2、C2来不及响应，因此RC2_OUT相对于VDDH而言为低电平，M10导通，第一分压单元1021被短路，VM被上拉至VDDH，M2导通。同时，缓冲单元中的R1、C1来不及响应，因此RC1_OUT相对于VM而言为低电平，RC1_OUT经反相器得到VG_ND，VG_ND为高电平，M1导通。由于M1，M2均导通，即泄放模块103导通，因此VDDH处的静电经M1和M2泄放至GND。在缓冲单元中的电容C1上极板被充至高电平时，M1截止，泄放模块103再次不导通。
本实施例相对于现有技术而言，在静电泄放保护电路中设置场效应管触发模块来替代现有技术中的电容C3，场效应管触发模块在电源接脚VDDH受到静电攻击时直接导通，实现分压模块的输出端电压被上拉至高电平，此时泄放模块103导通，电源接脚VDDH处点静电经泄放模块103泄放至地。其中，由于场效应管触发模块直接导通便可以实现分压模块的输出端电压上拉至与电源接脚VDDH处电压相等，无需借助电容进行耦合，因而能够实现静电泄放电路的较强泄放能力，并缩小静电泄放电路的整体版图面积。
本申请第二实施例涉及一种静电泄放保护电路，如图3所示。第二实施例与第一实施例大致相同，主要区别之处在于：场效应管触发模块的实现形式不同，以下进行具体说明：
本实施例中，场效应管触发模块具体包括：第三分压单元1012、第四分 压单元1013、检测单元1011、驱动单元1014以及场效应管M10。第三分压单元1012的第一端与电源接脚VDDH连接，第二端与第四分压单元1013的第一端连接，第四分压单元1013的第二端与接地接脚GND连接。检测单元1011以及驱动单元1014均并联在电源接脚VDDH以及接地接脚GND之间。第三分压单元1012的第二端与驱动单元1014的第一输入端连接，检测单元1011的输出端与驱动单元1014的第二输入端连接，场效应管M10的栅极与驱动单元1014的输出端连接，源极与电源接脚VDDH连接，漏极作为场效应管触发模块的输出端。其中，电源接脚VDDH受到静电攻击时，第三分压单元1012的第二端为低电平，检测单元1011的输出端为高电平，驱动单元1013的输出端为低电平。以下对本实施例中场效应管触发模块各功能模块的具体结构进行说明：
检测单元1011包括：电容C3以及电阻R3。电容C3以及电阻R3依次串联在电源接脚VDDH以及接地接脚GND之间。其中，电容C3与电阻R3的连接端作为检测单元1011的输出端。
第三分压单元1012，包括场效应管M17、M18以及M19，具体连接如图3所示。即，M19的源极连接至VDDH。M19的栅极与漏极连接，并连接至M18的源极。M18的栅极与漏极连接，并连接至M17的源极。M17的栅极与漏极连接，并连接至第二分压单元1013。第二分压单元1013，包括场效应管M15、M16，具体连接如图3所示。即，M17的栅极与漏极连接，并与M6的栅极以及漏极连接，M16的源极与M15的栅极以及漏极连接，M15的源极连接至接地接脚GND。
驱动单元1014包括：第一场效应管M11、第二场效应管M12、第三场效应管M13以及第四场效应管M14。M11的栅极与检测单元1011的输出端连 接，源极与接地接脚连接，漏极与M12的源极连接。M12的栅极与第三分压单元1012的第二端连接，漏极与M13的漏极连接。M13的源极与电源接脚VDDH连接，栅极与M14的源极连接。M14的栅极与第三分压单元1012的第二端连接，漏极与检测单元1011的输出端连接。
以下对本实施例中静电泄放电路的工作原理进行解释说明：
(1)VDDH未受到静电攻击。
VDDH缓慢上电，M5、M6、M7、M8以及M9提供VDDH到GND的分压，VM为VDDH分压后所得中间电位，VM等于0.5VDDH，VM为高电平，M2导通，RC2_OUT为低电平，M11截止。同理，M15、M16、M17、M18、M19提供VDDH到GND的分压，VX为VDDH分压后所得中间电位，VX等于0.5VDDH，VX为高电平，M14、M12截止。M13的栅极为低电平，M13导通，M10的栅极电压被M13拉至高电位VDDH，M10处于截止状态，且M10、M11均不会产生漏电。由于VM等于0.5VDDH，VM为高电平，因此RC1_OUT为高电平，RC1_OUT经反相器得到VG_ND，VG_ND为低电平，M1截止，没有静态电流，泄放模块103不导通。
(2)VDDH受到静电攻击。
VDDH电压猛增，RC2_OUT为高电平，VX等于0.5VDDH，VX为高电平，M11、M12、M14同时导通，使得M10栅极电压被拉至低电平GND，M10导通，从而使得VM被拉至VDDH，M2导通。同时，缓冲单元中的R1、C1来不及响应，因此RC1_OUT相对于VM而言为低电平，RC1_OUT经反相器得到VG_ND，VG_ND为高电平，M1导通。由于M1，M2均导通，即泄放模块103导通，因此VDDH处的静电经M1和M2泄放至GND。在缓冲单元中 的电容C1上极板被充至高电平时，M1截止，泄放模块103再次不导通。
本实施例相对于现有技术而言，在静电泄放保护电路中设置场效应管触发模块来替代现有技术中的电容C3，场效应管触发模块在电源接脚VDDH受到静电攻击时直接导通，实现分压模块的输出端电压被上拉至高电平，此时泄放模块103导通，电源接脚VDDH处点静电经泄放模块103泄放至地。其中，由于场效应管触发模块直接导通便可以实现分压模块的输出端电压上拉至与电源接脚VDDH处电压相等，无需借助电容进行耦合，因而能够实现静电泄放电路的较强泄放能力，并缩小静电泄放电路的整体版图面积。
本申请第三实施例涉及一种集成电路芯片，该集成电路芯片中设有上述实施例中所提及到的静电泄放保护电路。
本领域的普通技术人员可以理解，上述各实施例是实现本申请的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本申请的精神和范围。

Claims (12)

  1. 一种静电泄放保护电路，其特征在于，包括：并联在电源接脚与接地接脚之间的场效应管触发模块、分压模块以及泄放模块；其中，所述分压模块包括第一分压单元以及第二分压单元，所述第一分压单元与所述第二分压单元串联连接，且所述第一分压单元与所述第二分压单元的连接点作为所述分压模块的输出端；
    所述场效应管触发模块的输出端与所述分压模块的输出端连接；
    所述分压模块的输出端与所述泄放模块的输入端连接；
    所述场效应管触发模块在所述电源接脚受到静电攻击时导通，所述第一分压单元被短路，所述分压模块的输出端电压被上拉至高电平，所述泄放模块导通并泄放所述电源接脚处的静电。
  2. 如权利要求1所述的静电泄放保护电路，其中，所述场效应管触发模块包括：检测单元以及场效应管；
    所述检测单元连接在所述电源接脚以及所述接地接脚之间，且所述检测单元的输出端与所述场效应管的栅极连接；
    所述场效应管的源极与所述电源接脚连接，漏极作为所述场效应管触发模块的输出端；
    其中，所述电源接脚静电攻击时，所述检测单元的输出端为低电平。
  3. 如权利要求2所述的静电泄放保护电路，其中，所述检测单元具体包括：电阻以及电容；
    所述电阻以及所述电容依次串联在所述电源接脚以及所述接地接脚之间；
    其中，所述电阻与所述电容的连接端作为所述检测单元的输出端。
  4. 如权利要求1所述的静电泄放保护电路，其中，所述场效应管触发模块包括：第三分压单元、第四分压单元、检测单元、驱动单元以及场效应管；
    所述第三分压单元的第一端与所述电源接脚连接，第二端与所述第四分压单元的第一端连接；
    所述第四分压单元的第二端与所述接地接脚连接；
    所述检测单元以及所述驱动单元均并联在所述电源接脚以及所述接地接脚之间；
    所述第三分压单元的第二端与所述驱动单元的第一输入端连接；
    所述检测单元的输出端与所述驱动单元的第二输入端连接；
    所述场效应管的栅极与所述驱动单元的输出端连接，源极与所述电源接脚连接，漏极作为所述场效应管触发模块的输出端；
    其中，所述电源接脚受到静电攻击时，所述第三分压单元的第二端为低电平，所述检测单元的输出端为高电平，所述驱动单元的输出端为低电平。
  5. 如权利要求4所述的静电泄放保护电路，其中，所述检测单元包括：电容以及电阻；
    所述电容以及电阻依次串联在所述电源接脚以及所述接地接脚之间；
    其中，所述电容与所述电阻的连接端作为所述检测单元的输出端。
  6. 如权利要求4所述的静电泄放保护电路，其中，所述驱动单元包括：第一场效应管、第二场效应管、第三场效应管以及第四场效应管；
    所述第一场效应管的栅极与所述检测单元的输出端连接，源极与所述接地接脚连接，漏极与所述第二场效应管的源极连接；
    所述第二场效应管的栅极与所述第三分压单元的第二端连接，漏极与所述第三场效应管的漏极连接；
    所述第三场效应管的源极与所述电源接脚连接，栅极与所述第四场效应管的源极连接；
    所述第四场效应管的栅极与所述第三分压单元的第二端连接，漏极与所述检测单元的输出端连接。
  7. 如权利要求1所述的静电泄放保护电路，其中，所述泄放模块包括：缓冲单元、反相器、第五场效应管以及第六场效应管；
    所述缓冲单元以及所述反相器并联在所述分压模块的输出端以及所述接地接脚之间；
    所述缓冲单元的输出端与所述反相器的输入端连接，所述反相器的输出端与所述第五场效应管的栅极连接；
    所述第五场效应管的源极与所述接地引脚连接，漏极与所述第六场效应管的源极连接；
    所述第六场效应管的漏极与所述电源引脚连接，栅极作为所述泄放模块的输入端。
  8. 如权利要求4所述的静电泄放保护电路，其中，所述第三分压单元包括：第七场效应管、第八场效应管以及第九场效应管；
    所述第七场效应管的源极作为所述第三分压单元的第一端，连接至所述电源接脚；
    所述第七场效应管的栅极与漏极连接，并连接至所述第八场效应管的源极；
    所述第八场效应管的栅极与漏极连接，并连接至所述第九场效应管的源极；
    所述第九场效应管的栅极与漏极连接，并作为所述第三分压单元的第二端连接至所述第四分压单元的第一端。
  9. 如权利要求4所述的静电泄放保护电路，其中，所述第四分压单元包括：第十场效应管以及第十一场效应管；
    所述第十场效应管的栅极与漏极连接，并作为所述第四分压单元的第一端；
    所述第十场效应管的源极与所述第十一场效应管的的栅极与漏极连接；
    所述第十一场效应管的源极作为所述第四分压单元的第二端与所述接地接脚连接。
  10. 如权利要求1至9任意一项所述的静电泄放保护电路，其中，所述第一分压单元包括：第十二场效应管、第十三场效应管以及第十四场效应管；
    所述第十二场效应管的源极连接至所述电源接脚；
    所述第十二场效应管的栅极与漏极连接，并连接至所述第十三场效应管的源极；
    所述第十三场效应管的栅极与漏极连接，并连接至所述第十四场效应管的源极；
    所述第十四场效应管的栅极与漏极连接，并连接至所述第二分压单元。
  11. 如权利要求1至10任意一项所述的静电泄放保护电路，其中，所述第二分压单元包括：第十五场效应管以及第十六场效应管；
    所述第十五场效应管的栅极与漏极连接，源极与所述第十六场效应管的栅极与漏极连接；
    所述第十六场效应管的源极与所述接地接脚连接。
  12. 一种集成电路芯片，其特征在于，包括如权利要求1至7中任意一项所述的静电泄放保护电路。
PCT/CN2018/105486 2018-09-13 2018-09-13 静电泄放保护电路及集成电路芯片 Ceased WO2020051832A1 (zh)

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