WO2020044625A1 - ゲート駆動回路および電圧駆動型ワイドギャップ半導体の駆動方法 - Google Patents

ゲート駆動回路および電圧駆動型ワイドギャップ半導体の駆動方法 Download PDF

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Publication number
WO2020044625A1
WO2020044625A1 PCT/JP2019/009656 JP2019009656W WO2020044625A1 WO 2020044625 A1 WO2020044625 A1 WO 2020044625A1 JP 2019009656 W JP2019009656 W JP 2019009656W WO 2020044625 A1 WO2020044625 A1 WO 2020044625A1
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Prior art keywords
gate
voltage
drive circuit
driving
gate drive
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PCT/JP2019/009656
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English (en)
French (fr)
Japanese (ja)
Inventor
鈴木　弘
石川　勝美
栗原　直樹
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株式会社日立製作所
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of AC power input into DC power output; Conversion of DC power input into AC power output
    • H02M7/42—Conversion of DC power input into AC power output without possibility of reversal
    • H02M7/44—Conversion of DC power input into AC power output without possibility of reversal by static converters
    • H02M7/48—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/04—Modifications for accelerating switching
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/16—Modifications for eliminating interference voltages or currents
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors

Definitions

  • the present invention relates to a gate drive circuit of a voltage drive type wide gap semiconductor device.
  • IGBTs Insulated Gate Bipolar Transistors
  • a gate driver which is a gate drive circuit that controls on / off of the semiconductor element by controlling a voltage applied to a gate is used.
  • Si silicon
  • MOSFETs Metal-Oxide-Semiconductor Field Effect Transistors
  • Patent Document 1 discloses a configuration of a gate drive circuit of an inverter to which a SiC-SBD (Schottky barrier diode; Shottky Barrier Diode) and a Si-IGBT are applied.
  • SiC-SBD Schottky barrier diode
  • Si-IGBT Si-IGBT
  • SiC-MOSFET has lower turn-off loss than Si-IGBT. Since the Si-IGBT is a bipolar element, a tail current accompanying the recombination of carriers is generated at the time of turn-off, so that the turn-off loss increases. On the other hand, since the SiC-MOSFET is a unipolar element, no tail current is generated in principle, and the turn-off loss is small. For this reason, the SiC element having a small switching loss is more advantageous for increasing the frequency, and the SiC element is required to further reduce the switching loss for high frequency driving.
  • the gate resistance for adjusting the charging and discharging speed is reduced, thereby increasing the switching speed to reduce the switching loss. Reducing is commonly practiced.
  • the switching loss can be reduced by reducing the gate resistance, the rate of time change (dv / dt or di / dt) of the voltage or current at the time of switching increases, and noise generally emitted from the semiconductor element increases.
  • the driving method described in Patent Document 1 uses a SiC-SBD as a freewheeling diode to suppress intense voltage and current oscillations (ringing) that occur when the IGBT of the opposite arm is turned on.
  • the gate-emitter capacitance (Cge) of the IGBT is discharged for a certain time.
  • the collector-emitter voltage (Vce) of the IGBT changes from a decrease to an increase during the discharge period, and the turn-on loss increases.
  • Patent Document 1 when an SiC-SBD is applied as a freewheeling diode to drive a pair of Si-IGBTs, a means of allowing a certain amount of increase in turn-on loss with priority given to suppression of ringing is effective. .
  • driving a SiC-MOSFET as a semiconductor element applying the driving method of Patent Document 1 reduces the switching speed during a mirror period during which a turn-on loss occurs, which significantly increases the turn-on loss. I do.
  • the object of the present invention relates to achieving both noise and switching loss reduction at the time of switching of a voltage-driven wide gap semiconductor device.
  • the present invention relates to driving a voltage-driven wide-gap semiconductor device such that a gate current increases during a mirror period.
  • the turn-on loss can be reduced without increasing the current change rate (di / dt) when turning on the voltage-driven wide gap semiconductor device. Therefore, highly reliable and low-loss driving with improved trade-off between noise and switching loss can be realized.
  • FIG. 4 is a schematic diagram of a turn-on waveform of a semiconductor device, showing the effect of the first embodiment.
  • Explanatory drawing of the range of timing to start increasing the gate current for achieving the effect of the first embodiment Configuration diagram of a gate driver according to a second embodiment
  • Configuration diagram of a gate driver according to a third embodiment Explanatory drawing of the turn-on operation according to the third embodiment.
  • a gate drive circuit for driving a voltage-driven wide gap semiconductor device having a means for increasing a gate current during a mirror period is disclosed.
  • the embodiment discloses a method of driving a voltage-driven wide-gap semiconductor device that increases a gate current during a mirror period.
  • the embodiment discloses that the gate current is increased during the mirror period.
  • the embodiment discloses that the increase in the gate current is started during the turn-on period and after the drain current reaches the on-current.
  • the embodiment discloses that the increase of the gate current is started during the turn-on period and before the drain-source voltage reaches the on-state voltage.
  • the embodiment discloses that the gate voltage of the semiconductor element is controlled using a voltage driving circuit connected to a constant voltage source.
  • the embodiment discloses that the increase of the gate current is started after a predetermined time has elapsed from the input time of the drive command of the semiconductor element.
  • the embodiment discloses that the increase in the gate current is started after the voltage between the gate and the source of the voltage-driven wide gap semiconductor device reaches a predetermined value.
  • the embodiment discloses that the gate resistance is reduced and the gate current is increased.
  • the embodiment discloses that the gate drive voltage is increased to increase the gate current.
  • the embodiments disclose that the voltage-driven wide gap semiconductor device is a SiC-MOSFET.
  • the embodiments disclose a power converter equipped with a gate drive circuit and an electric vehicle equipped with the power converter.
  • FIG. 1 is a configuration diagram of a railway inverter system according to the present embodiment.
  • the power unit 100 is configured by the MOSFET 101, which is a voltage-driven wide gap semiconductor element, and the filter capacitor 103.
  • MOSFET 101 is connected in series, and a reflux diode 102 is connected to each MOSFET 101 in parallel so that the flow direction is reversed.
  • a diode built in the MOSFET 101 may be used as the free wheel diode 102, and in such a case, the free wheel diode 102 is not necessarily required.
  • a gate driver 104 for driving the MOSFET in accordance with a command from the command logic unit 105 is arranged.
  • the connection point between the upper MOSFET (upper arm) and the lower MOSFET (lower arm) of each UVW phase is connected to the motor 106 as the output of the power unit 100.
  • the power from the overhead wire 107 is input to the high voltage side of the filter capacitor 103 for smoothing the DC power and removing noise via the current collector 108, the plurality of circuit breakers 109, and the filter reactor 110.
  • the low-voltage side of the filter capacitor 103 is connected to a rail 112 serving as an electrical ground via wheels 111.
  • the railway inverter system generates a three-phase alternating current by alternately switching the UVW-phase MOSFETs in the power unit and sends it to the motor 106.
  • a gate driver 104 disposed in the power unit 100 together with the MOSFET 101 and the filter capacitor 103 drives the MOSFET 101 according to a command from the command logic unit 105.
  • the command logic unit 105 includes an arithmetic unit, a memory, and input / output means, and outputs a command for driving the MOSFET according to a predetermined program.
  • a MOSFET is driven as a semiconductor element
  • the semiconductor element is not limited to the MOSFET but may be a voltage-driven element, such as an IGBT.
  • FIG. 2 is a configuration diagram of the gate driver according to the present embodiment.
  • the source of the P-type MOSFET 3 a is connected to the positive power supply 1, and the drain is connected to the on-side gate resistor 5.
  • the source of the N-type MOSFET 4 is connected to the negative power supply 2, and the drain is connected to the off-side gate resistor 6.
  • a connection point between the on-side gate resistance 5 and the off-side gate resistance 6 becomes an output section of the gate driver 104 and is connected to the gate of the semiconductor element 101.
  • the gates of the P-type MOSFET 3a and the N-type MOSFET 4 are both connected to the output of the drive control device 7.
  • the command logic unit 105 is connected to an input of the drive control device 7 and an input of the timer circuit 8.
  • the gate resistance reducing circuit 9 includes a P-type MOSFET 3b, a driving device 10, and a gate current increasing resistor 11 (Ron2).
  • the output of the timer circuit 8 is connected to the input of the driving device 10, and the output of the driving device 10 is connected to the gate of the P-type MOSFET 3b.
  • the source of the P-type MOSFET 3b is connected to the positive power supply 1, and the drain of the P-type MOSFET 3b is connected to the output of the gate driver 104, that is, the gate of the semiconductor element 101, via the gate current increasing resistor 11.
  • the drive control device 7 controls the P-type MOSFET 3a and the N-type MOSFET 4 at the output stage of the gate driver so as to complementarily turn on and off the semiconductor.
  • the gate of the element 101 is charged and discharged.
  • the charging and discharging speeds can be controlled by the resistance values of the on-side gate resistance 5 and the off-side gate resistance 6, respectively.
  • the gate resistance reduction circuit 9 is operated to increase the charge speed of the gate charge at the time of turn-on, and the turn-on operation is quickly completed, thereby turning on the semiconductor device 101. Loss can be reduced.
  • the timer circuit 8 operates starting from the point in time when a gate drive command (ON command) is input from the command logic unit 105 to the drive control device 7, and the gate resistance reduction circuit 9 operates after a certain delay time determined by the timer circuit 8 has elapsed. I do.
  • the drive circuit 10 turns on the P-type MOSFET 3b
  • the gate of the MOSFET 101 is supplied with electric charge from the positive power supply 1 via the P-type MOSFET 3b. Since the charging speed of the transistor 101 increases (the gate current increases) and the turn-on operation ends quickly, the turn-on loss generated in the MOSFET 101 can be reduced.
  • the gate after the gate resistance reducing circuit 9 is activated.
  • the current can be increased.
  • FIG. 3 is a schematic diagram of a turn-on waveform of a semiconductor device, showing the effect of the present embodiment.
  • the dashed waveform shows the case where the gate resistance at the time of turn-on is fixed to a constant value Rg1.
  • the solid line waveform shows a case where the gate resistance at the time of turn-on is Rg1 before the mirror period, and is reduced to Rg2 ( ⁇ Rg1) during the mirror period.
  • the waveform of the drain current (Id) overlaps the solid line and the broken line.
  • the drain-source voltage (Vds) is substantially equal to the power supply voltage Vcc, and the drain current (Id) is zero.
  • Vds drops to the ON voltage (Von), and the turn-on operation is completed.
  • the drain current (Id) reaches the on-current (Ion) by adjusting the delay time determined by the timer circuit 8 so that the gate resistance reduction circuit 9 starts operating during the mirror period. After that, the gate current can be increased. For this reason, only the time change rate (dv / dt) of Vds at the time of turn-on is increased without increasing the time change rate (di / dt) of the current at the time of turn-on. Therefore, the turn-on loss determined by the time integration of the product of Vds and Id can be reduced.
  • the gate resistance reducing circuit 9 is a voltage driving circuit connected to the positive power supply 1 of the gate driver, which is a constant voltage source, the voltage of the positive power supply 1 of the gate driver becomes the absolute maximum of the gate voltage of the MOSFET 101. As long as the voltage is less than the rating, the gate voltage of the MOSFET 101 can be controlled to be less than the absolute maximum rating even after the operation of the gate resistance reduction circuit 9, and the reliability of the element is secured.
  • FIG. 4 is an explanatory diagram showing the trade-off relationship between di / dt and turn-on loss, showing the effect of the present embodiment.
  • the driving is performed with the gate resistance fixed at a constant value (Ron1)
  • Ron1 ⁇ Ron2 when the driving is performed with the gate resistance reduced (Ron1 ⁇ Ron2) during the mirror period as in the present embodiment, the same noise level (di / It can be seen that at dt), the turn-on loss can be reduced and the trade-off between noise and loss can be improved.
  • FIG. 5 is an explanatory diagram of the range of the timing at which the increase of the gate current for starting the effect of the present embodiment starts.
  • FIG. 5 is a schematic diagram of a locus (trajectory) of the turn-on waveform shown in FIG. 3, in which the vertical axis represents the drain current (Id) and the horizontal axis represents the drain-source voltage (Vds).
  • Point (A) indicates the start point of turn-on (the point at which Id starts to flow)
  • point (B) indicates the point in time when the mirror period is entered
  • point (C) indicates the end point of the turn-on (point at which Vds reaches the on-voltage Von).
  • the timing to start increasing the gate current may be between the points (B) and (C).
  • This embodiment monitors the gate-source voltage (Vgs) of the semiconductor element as a means for determining the timing of starting the increase of the gate current in the configuration of the gate driver of the first embodiment, and the Vgs is a constant value. The difference is that the time point when the above occurs is detected.
  • Vgs gate-source voltage
  • FIG. 6 is a configuration diagram of the gate driver according to the present embodiment.
  • the timer circuit 8 of the first embodiment is not required because it becomes unnecessary.
  • a gate voltage detection circuit 12 is connected between the output of the gate driver 104 and the gate resistance reduction circuit 9.
  • Other connection modes are the same as in the first embodiment.
  • a comparator 13 As an embodiment of the gate voltage detection circuit 12, an example configured by a comparator 13 as shown in FIG.
  • the negative input terminal of the comparator 13 is connected to the output of the gate driver 104, and the positive input terminal is connected to the negative power supply 2 of the gate driver via a reference voltage source (Vref).
  • the output terminal of the comparator 13 is connected to the gate resistance reduction circuit 9.
  • the voltage at the negative input terminal of the comparator 13 is equal to the gate-source voltage (Vgs) of the MOSFET 101.
  • Vgs gate-source voltage
  • the delay time from the input of the gate drive command (ON command) from the command logic unit 105 until the MOSFET 101 enters the mirror period may also change.
  • the gate-source voltage (Vgs) during the actual driving at the temperature is monitored, the timing at which the increase in the gate current starts even when the temperature changes does not easily change from the mirror period. There is.
  • the present embodiment is different from the gate driver of the second embodiment in that a means for increasing the gate current uses a method for increasing the gate drive voltage instead of a method for reducing the gate resistance.
  • a means for increasing the gate current uses a method for increasing the gate drive voltage instead of a method for reducing the gate resistance.
  • FIG. 7 is a configuration diagram of the gate driver according to the present embodiment.
  • the gate resistance reducing circuit 9 shown in the first and second embodiments is unnecessary and has been removed.
  • a gate voltage increasing circuit 14 is connected between the output of the gate voltage detecting circuit 12 and the drain of the P-type MOSFET 3a.
  • Other connection modes are the same as in the second embodiment.
  • the gate voltage increasing circuit 14 includes a first positive power supply 1, a second positive power supply 15, a one-shot IC 16, a P-type MOSFET 17, and an N-type MOSFET 18 of a gate driver.
  • the input of the one-shot IC 16 is connected to the output of the gate voltage detection circuit 12.
  • the drain of the P-type MOSFET 17 and the drain of the N-type MOSFET 18 are both connected to the drain of the P-type MOSFET 3a.
  • the gate of the P-type MOSFET 17 and the gate of the N-type MOSFET 18 are both connected to the output of the one-shot IC 16.
  • the source of the P-type MOSFET 17 is connected to the second positive power supply 15 of the gate driver, and the source of the N-type MOSFET 18 is connected to the first positive power supply 1 of the gate driver.
  • the voltage (+ Vp2) of the second positive power supply 15 is set higher than the voltage (+ Vp1) of the first positive power supply 1 and lower than the absolute maximum rating (+ Vgs_abs) of the gate voltage of the semiconductor element 101. (+ Vp1 ⁇ + Vp2 ⁇ + Vgs_abs).
  • the output of the comparator 13 becomes high due to the relationship between the input voltages of the comparator 13 (Vgs ⁇ Vref).
  • the output of the one-shot IC 16 in the gate voltage increasing circuit 14 remains high, the P-type MOSFET 17 is turned off, and the N-type MOSFET 18 is turned on. Therefore, the potential of the drain of the P-type MOSFET 3a becomes equal to the voltage (+ Vp1) of the first positive power supply 1.
  • the output of the comparator 13 becomes low due to the relationship between the input voltages of the comparator 13 (Vgs> Vref).
  • the output of the one-shot IC 16 in the gate voltage increasing circuit 14 outputs high to low for a certain period ( ⁇ T) determined by the internal circuit of the one-shot IC 16, and only during this period ⁇ T,
  • the P-type MOSFET 17 is turned on, and the N-type MOSFET 18 is turned off. Therefore, the potential of the drain of the P-type MOSFET 3a becomes equal to the voltage (+ Vp2) of the second positive power supply 15 only during the period ⁇ T.
  • the potential of the drain of the P-type MOSFET 3a can be set to + Vp1 in the first half section (Vgs ⁇ Vref), and the potential of the drain of the P-type MOSFET 3a can be set in the second half section (Vgs> Vref). + Vp2 (> + Vp1).
  • the one-shot IC 16 has a role of outputting a low output for a certain period ( ⁇ T) triggered by the low output of the comparator 13, and need not be a one-shot IC as long as the element has a similar function.
  • FIG. 8 is an explanatory diagram of the turn-on operation according to the present embodiment.
  • the broken line waveform shows the case where the gate drive voltage at the time of turn-on is fixed to a fixed value + Vp1.
  • the solid line waveform shows a case where the gate drive voltage at the time of turn-on is set to + Vp1 before the mirror period, and is boosted to + Vp2 (> + Vp1) during the mirror period.
  • the waveform of the drain current (Id) overlaps the solid line and the broken line.
  • Vref the reference voltage
  • Id drain current
  • Ion on-current
  • T1 is a condition for continuously increasing the gate current during the mirror period of the MOSFET 101
  • ⁇ T ⁇ T2 is a condition in which the potential of the drain of the P-type MOSFET 3a is changed by the gate driver until the next turn-on operation starts. This is a condition necessary to return the voltage (+ Vp2) of the second positive power supply 15 to the voltage (+ Vp1) of the first positive power supply 1.
  • the power supply voltage of the second positive power supply 15 of the gate driver is set to be higher than the power supply voltage of the first positive power supply 1 within a range of less than the absolute maximum rating of the gate voltage of the semiconductor element 101 + Vgs_abs.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Power Conversion In General (AREA)
  • Inverter Devices (AREA)
  • Electronic Switches (AREA)
PCT/JP2019/009656 2018-08-29 2019-03-11 ゲート駆動回路および電圧駆動型ワイドギャップ半導体の駆動方法 WO2020044625A1 (ja)

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JP2018159894A JP7262945B2 (ja) 2018-08-29 2018-08-29 ゲート駆動回路および電圧駆動型ワイドギャップ半導体の駆動方法

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JP7695964B2 (ja) * 2021-01-22 2025-06-19 ナブテスコ株式会社 インバータ、インバータの制御方法、インバータの制御プログラム、コンバータ、駆動装置
JP7470084B2 (ja) * 2021-09-10 2024-04-17 株式会社東芝 電子回路、電子システム及び駆動方法
DE112022007737T5 (de) * 2022-09-02 2025-07-03 Mitsubishi Electric Corporation Gate-Treibereinrichtung
JP2024178755A (ja) * 2023-06-13 2024-12-25 日立Astemo株式会社 スイッチング駆動装置

Citations (5)

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Publication number Priority date Publication date Assignee Title
JP2004266368A (ja) * 2003-02-20 2004-09-24 Hitachi Ltd 半導体装置の駆動方法および装置
JP2012147492A (ja) * 2007-06-19 2012-08-02 Panasonic Corp スイッチング素子駆動回路
JP2013168905A (ja) * 2012-02-17 2013-08-29 Mitsubishi Electric Corp パワーデバイス制御回路およびパワーデバイス回路
WO2014155541A1 (ja) * 2013-03-26 2014-10-02 三菱電機株式会社 電力変換装置および冷却装置
JP2018038174A (ja) * 2016-08-31 2018-03-08 富士電機株式会社 ゲート駆動装置

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Publication number Priority date Publication date Assignee Title
JP5993749B2 (ja) 2013-01-30 2016-09-14 株式会社 日立パワーデバイス 半導体装置のゲート駆動回路およびそれを用いた電力変換装置
JP6451429B2 (ja) 2015-03-16 2019-01-16 株式会社デンソー スイッチング素子の駆動装置

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Publication number Priority date Publication date Assignee Title
JP2004266368A (ja) * 2003-02-20 2004-09-24 Hitachi Ltd 半導体装置の駆動方法および装置
JP2012147492A (ja) * 2007-06-19 2012-08-02 Panasonic Corp スイッチング素子駆動回路
JP2013168905A (ja) * 2012-02-17 2013-08-29 Mitsubishi Electric Corp パワーデバイス制御回路およびパワーデバイス回路
WO2014155541A1 (ja) * 2013-03-26 2014-10-02 三菱電機株式会社 電力変換装置および冷却装置
JP2018038174A (ja) * 2016-08-31 2018-03-08 富士電機株式会社 ゲート駆動装置

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