WO2020039531A1 - 光センサ及びその信号読み出し方法並びに光エリアセンサ及びその信号読み出し方法 - Google Patents
光センサ及びその信号読み出し方法並びに光エリアセンサ及びその信号読み出し方法 Download PDFInfo
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- 230000003287 optical effect Effects 0.000 title claims abstract description 54
- 238000000034 method Methods 0.000 title claims description 17
- 238000009792 diffusion process Methods 0.000 claims abstract description 86
- 238000007667 floating Methods 0.000 claims abstract description 86
- 239000004065 semiconductor Substances 0.000 claims abstract description 14
- 230000015654 memory Effects 0.000 claims description 205
- 238000005070 sampling Methods 0.000 claims description 62
- 238000009825 accumulation Methods 0.000 claims description 30
- 230000002596 correlated effect Effects 0.000 claims description 4
- 239000011159 matrix material Substances 0.000 claims description 3
- 238000012546 transfer Methods 0.000 abstract description 18
- 230000008901 benefit Effects 0.000 abstract description 13
- 230000016507 interphase Effects 0.000 description 46
- 230000000875 corresponding effect Effects 0.000 description 36
- 239000003990 capacitor Substances 0.000 description 31
- 238000003384 imaging method Methods 0.000 description 25
- 238000010586 diagram Methods 0.000 description 15
- 238000006073 displacement reaction Methods 0.000 description 13
- 238000006243 chemical reaction Methods 0.000 description 10
- 230000008878 coupling Effects 0.000 description 8
- 238000010168 coupling process Methods 0.000 description 8
- 238000005859 coupling reaction Methods 0.000 description 8
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 7
- 230000035945 sensitivity Effects 0.000 description 7
- 238000003491 array Methods 0.000 description 6
- 229920006395 saturated elastomer Polymers 0.000 description 5
- 230000006378 damage Effects 0.000 description 4
- 238000013461 design Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 230000007704 transition Effects 0.000 description 4
- 238000004458 analytical method Methods 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 230000003247 decreasing effect Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- ORQBXQOJMQIAOY-UHFFFAOYSA-N nobelium Chemical compound [No] ORQBXQOJMQIAOY-UHFFFAOYSA-N 0.000 description 2
- 230000002265 prevention Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 206010028980 Neoplasm Diseases 0.000 description 1
- 206010034960 Photophobia Diseases 0.000 description 1
- 206010034972 Photosensitivity reaction Diseases 0.000 description 1
- 101150082606 VSIG1 gene Proteins 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 201000011510 cancer Diseases 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000002485 combustion reaction Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000446 fuel Substances 0.000 description 1
- 230000036541 health Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000000608 laser ablation Methods 0.000 description 1
- 208000013469 light sensitivity Diseases 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000474 nursing effect Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000036211 photosensitivity Effects 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 239000007921 spray Substances 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 230000002123 temporal effect Effects 0.000 description 1
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-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/50—Control of the SSIS exposure
- H04N25/57—Control of the dynamic range
- H04N25/59—Control of the dynamic range by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14643—Photodiode arrays; MOS imagers
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
- H04N25/616—Noise processing, e.g. detecting, correcting, reducing or removing noise involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/50—Control of the SSIS exposure
- H04N25/53—Control of the integration time
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
- H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
- H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
Definitions
- the present invention relates to an optical sensor capable of reading a clear image applied to an apparatus such as an optical measurement / analysis apparatus at a high speed of 1,000,000 frames or more per second, a signal reading method thereof, an optical area sensor and a signal thereof. This is related to reading.
- optical sensors line-shaped or area-shaped optical sensors, solid-state imaging devices, etc.
- any of these or collectively referred to as "optical sensors” has jumped.
- high-sensitivity, high-speed, wide dynamic range, wide optical wavelength band compatible optical sensors and solid-state imaging devices for still images and moving images that are applied to devices such as optical measurement and analysis are indispensable for new market development. Items are strongly demanded by the market.
- optical sensors and solid-state imaging devices with a wider dynamic range are used in the medical, pharmaceutical, health, and nursing care markets, the life sciences market, and the disaster prevention and crime prevention markets essential for the formation of a safe and secure society. Coveted by such.
- An example of a high-sensitivity, high-speed, wide dynamic range, wide light wavelength band compatible optical sensor and solid-state imaging device is described in, for example, Japanese Patent Application Laid-Open No. H11-157,036.
- optical sensor in either or both senses
- optical sensor is certainly compared to the conventional one. It is excellent in terms of high sensitivity, high speed, wide dynamic range, and wide optical wavelength band, but in order to cope with the above-mentioned markets and eras, it is required to cope with higher speeds while taking advantage of the advantages.
- the above-mentioned optical sensor has a transfer switch between a photodiode (hereinafter sometimes abbreviated as “PD”), which is one of the light receiving elements, and a floating diffusion (hereinafter sometimes abbreviated as “CFD”).
- PD photodiode
- CCD floating diffusion
- the pixel means a pixel configured by a light receiving element (PD) and a floating diffusion (CFD).
- the present invention has been made in view of the above points, and a main object of the present invention is to provide a conventional optical sensor in which a transfer switch is provided between a light receiving element (PD) such as a photodiode and a floating diffusion (CFD).
- PD light receiving element
- CFD floating diffusion
- An object of the present invention is to provide an optical sensor that can read data at a higher speed than before and maintain power and power consumption while maintaining advantages and advantages.
- the present invention has been made as a result of intensive research and development in view of the above points, and one of its features is that the semiconductor junction is completely depleted and the potential curve of the electrons is shifted toward the floating diffusion direction.
- the light receiving element connected to the top of the electron potential well of the floating diffusion receives light in the negative inclination state, and electrons generated inside the light receiving element in response to the light reception. Transferring the signal according to the potential curve and accumulating the potential in the potential well at least twice during the same frame period provided in the light receiving period, at least twice.
- An optical sensor used in the signal reading method is used in the signal reading method.
- the capacitance (C PD ) of the light receiving element and the capacitance (C FD ) of the floating diffusion are: 0.0008 ⁇ (C PD ) / (C FD ) ⁇ 0.8 (1) 4.0 ⁇ 10 ⁇ 18 F ⁇ (C PD ) ⁇ 4.0 ⁇ 10 ⁇ 16 F (2) 5.0 ⁇ 10 ⁇ 16 F ⁇ (C FD ) ⁇ 5.0 ⁇ 10 ⁇ 15 F (3)
- the semiconductor junction of the light receiving element is fully depleted and the electron potential curve has a negative slope toward the floating diffusion direction, and the electron potential well of the floating diffusion remains in the negative slope state.
- the optical sensor and its signal reading method is used to read the floating diffusion.
- Still another feature of the present invention includes a light receiving element and a floating diffusion electrically connected to the light receiving element and storing a charge generated by light input to the light receiving element,
- the semiconductor junction In the light-receiving element, the semiconductor junction is completely depleted and has a negative slope toward the floating diffusion direction, and at the top of the electron potential well of the floating diffusion in the negative tilt state.
- a photosensor pixel circuit having two output systems used alternatively on a time axis; Noise cancellation based on a first output (a1) and a second output (b1) based on the amount of photocharge generated in the light receiving element by light irradiation, output from one output system, and a signal An intra-pixel correlated double sampling circuit that outputs (ab1); And a photosensor pixel circuit portion comprising: The signal (ab1), and the first output (a2) and the second output (b2) output from the other output system An analog memory array in which a plurality of memory cells holding any of the signals described above are arranged in a matrix; A memory cell row selection switch array for selecting any one of the memory cell arrangement rows; A memory read circuit for reading a signal held in any of the memory cells; And an analog memory circuit section comprising: And a signal readout method therefor.
- an optical sensor capable of reading data at a higher speed than the conventional one while maintaining the advantages and advantages of the conventional optical sensor and reducing power consumption, and a signal reading method using the optical sensor. it can.
- FIG. 1 is a circuit diagram of a pixel circuit section for explaining one of typical examples of a preferred embodiment of the optical sensor of the present invention.
- FIG. 2A is a potential explanatory diagram for explaining the principle of driving a pixel of a photo sensor according to a preferred embodiment of the present invention, which is at the time of completion of reset (t1).
- FIG. 2B is a potential explanatory diagram for explaining the principle of driving the pixel of the photo sensor according to the preferred embodiment of the present invention, and is at the time of reading the first voltage signal (t2).
- FIG. 2C is a potential explanatory diagram for explaining the principle of driving a pixel of a photosensor according to a preferred embodiment of the present invention, and is at the time of reading out the second voltage signal (t3).
- FIG. 3 is a circuit diagram of an analog memory circuit unit of the optical sensor according to the present invention.
- FIG. 4 is a timing chart showing an example of a pixel drive timing and a time transition of a floating diffusion voltage (VFD) of the optical sensor according to the present invention.
- FIG. 5 is a timing chart showing another example of the pixel drive timing of the optical sensor of the present invention and the time transition of the floating diffusion voltage (VFD).
- FIG. 6 is a block diagram for explaining the configuration of the image sensor of the present invention.
- FIG. 7 is a layout diagram showing an example of the arrangement of the photosensor pixel circuit unit 100, the analog memory circuit unit 300, and the pixel output signal line (PIXEL_OUT) 117 that constitute the light receiving signal generation / holding element according to the present invention.
- FIG. 8 is a layout diagram showing another example of the arrangement of the photosensor pixel circuit unit 100, the analog memory circuit unit 300, and the pixel output signal line (PIXEL_OUT) 117 that constitute the light receiving signal generation / holding element according to the present invention.
- FIG. 1 is a circuit diagram of a pixel circuit section for explaining one of typical examples of a preferred embodiment of the optical sensor of the present invention.
- the optical sensor pixel circuit section 100 shown in FIG. 1 includes an optical sensor pixel circuit 101a and an intra-pixel inter-phase double sampling circuit (In-pixel CDS) 101b.
- In-pixel CDS intra-pixel inter-phase double sampling circuit
- the light sensor pixel circuit 101a includes a light receiving element (PD) 102, a floating diffusion (CFD) 103, a reset transistor (R) 104, a first source follower transistor (SF1) 105, a first selection transistor (X1) 106, a first current A source transistor (CS1) 107; an intra-pixel inter-phase double sampling selection switch (CDS) 108; and an intra-pixel inter-phase double sampling bypass switch (CDSb) 109.
- PD light receiving element
- CCD floating diffusion
- R reset transistor
- SF1 first source follower transistor
- X1 first selection transistor
- CS1 first current A source transistor
- CDS intra-pixel inter-phase double sampling selection switch
- CDSb intra-pixel inter-phase double sampling bypass switch
- a photodiode is shown as a preferred example of the light receiving element (PD) 102, but a phototransistor may be used in addition to the photodiode.
- the intra-pixel inter-phase double sampling circuit 101b includes an intra-pixel correlated double sampling coupling capacitance (C C ) 110, an intra-pixel correlated double sampling sample-hold capacitance (C SH ) 111, and an intra-pixel inter-phase double sampling reset transistor (C SH ).
- NS intra-pixel correlated double sampling coupling capacitance
- C SH intra-pixel correlated double sampling sample-hold capacitance
- C SH intra-pixel inter-phase double sampling reset transistor
- NS a second source follower transistor
- X2 second selection transistor
- X2 ' second selection transistor
- CS2 second current source transistor
- a pixel output signal line (PIXEL_OUT) 117 for transferring a signal to the next electric circuit is wired from the intra-pixel inter-phase double sampling circuit 101b.
- the features of the optical sensor of the present invention that are advanced and useful and large compared to the preceding example are the physical structure of the light receiving element (PD) 102 and the energy potential related to its photocharge (electrons).
- the internal structure of the light receiving element (PD) 102 two different types of semiconductor layer regions (P + type, P type, P ⁇ type, I type, N + type, N type, N ⁇ type) are joined. At least one semiconductor junction is formed.
- the energy of the semiconductor junction of the light receiving element (PD) 102 is completely or substantially completely depleted (hereinafter sometimes referred to as “fully depleted” in any meaning).
- a potential (related to photocharge) is formed.
- “completely depleted” means that the potential displacement (or slope or gradient) in the potential section 201 changes from the left terminal to the right terminal in FIG. 2 as shown in FIGS. 2A to 2C. It means that it gradually decreases until it reaches.
- substantially completely depleted means that a photocharge generated in a semiconductor junction region of a light receiving element (PD) 102 by receiving light smoothly flows into an adjacent floating diffusion (CFD) 103. This means that a potential displacement having a shape that can be transferred is formed. Details of these will be described later.
- the capacitance (C PD ) of the light receiving element (PD) 102 and the capacitance (C FD ) of the floating diffusion (CFD) 103 satisfy the following equation so that the capacitance (C FD ) satisfies the following expression.
- C PD ) and the capacity (C FD ) are preferably set. 0.0008 ⁇ (C PD ) / (C FD ) ⁇ 0.8 (1) 4.0 ⁇ 10 ⁇ 18 F ⁇ (C PD ) ⁇ 4.0 ⁇ 10 ⁇ 16 F (2) 5.0 ⁇ 10 ⁇ 16 F ⁇ (C FD ) ⁇ 5.0 ⁇ 10 ⁇ 15 F (3)
- the semiconductor junction region in the internal structure of the light receiving element (PD) 102 may be either a lateral type or a vertical type, but the vertical type is more preferably employed. .
- the capacitance “C PD ” is proportional to the junction area of the semiconductor junction of the light receiving element (PD) 102.
- the “junction area” is not always the same as the area of the light receiving element (PD) 102 on the light incident side (the area where light actually hits: the light receiving area), and may be larger than the light receiving area.
- the “area on the light incident side” may be simply written as “area”.
- the “maximum moving distance of the photocharge” means that the photocharge generated at the semiconductor junction of the light receiving element (PD) 102 when the light receiving element (PD) 102 receives light from the outside is a floating diffusion (CFD). It refers to the maximum moving distance in the distance (moving distance) to move to 103.
- the time required to reach the floating diffusion (CFD) 103 differs between the photocharge generated near the floating diffusion (CFD) 103 and the photocharge generated far from the floating diffusion (CFD) 103.
- Photocharges generated farther from the floating diffusion (CFD) 103 need more time to reach the floating diffusion (CFD) 103 (arrival time).
- arrival time When the difference in the arrival time is large, for example, when the frame rate is increased for high-speed imaging, the photocharges having the arrival time slower than the frame rate are generated in the subsequent frame even though the photocharges are generated at the same time. It will be detected as an optical signal, and the effective time resolution will be inferior to the frame rate.
- the present invention it is premised that high time sensitivity is ensured so as to minimize the difference in the movement time of the photocharge generated in the light receiving element (PD) 102 so as to increase the time resolution and support high-speed reading.
- the physical structure of the light receiving element (PD) 102 is designed.
- the light receiving area of the fully depleted light receiving element (PD) 102 in the present invention is an area that can secure a sufficient amount of received light and can collect generated photocharge within 10 nsec.
- such an area is in the range of 5 m to 50 m square. Therefore, the capacitance (C PD ) of the light receiving element (PD) 102 has a light receiving area of 4.0 ⁇ 10 ⁇ 18 F or more corresponding to 5 ⁇ m square and 4.0 ⁇ 10 ⁇ 16 F corresponding to 50 ⁇ m square. It is desirable to be in the following range.
- the floating diffusion (CFD) 103 is directly connected to the fully depleted light receiving element (PD) 102 which forms an electric field for drift transporting the photocharge in the direction of the floating diffusion (CFD) 103. It is preferable to set the capacitance (C FD ) and the capacitance (C PD ) so that the charge-voltage conversion gain and the number of saturated charges are hardly influenced by the light receiving area and the layout of the light receiving element (PD) 102.
- the capacitance (C FD) capacity is desirably greater than (C PD), more preferably the capacity (C PD) is higher capacitance (C FD) is greater than the capacity (C PD) negligible, (C FD + C PD) capacitance (C FD) match or substantially is desirable to match.
- FD is preferably 5.0 ⁇ 10 ⁇ 16 F to 5.0 ⁇ 10 ⁇ 15 F It is desirable to be within the range.
- the gain is 320 µ V / e- or less.
- the capacity (C FD ) of the floating diffusion (CFD) 103 is equal to or less than 80 µ Vrms, the accuracy of counting the number of photocharges is obtained even when the number of collected photocharges is small.
- the capacitance (C FD ) is larger than the capacitance (C PD ), the charge-voltage conversion gain and the number of saturated charges should be designed in consideration of only the capacitance (C FD ) without being affected by the area or shape of the photodiode. Therefore, it is desirable that (C PD / C FD ) is smaller than 1. However, in the present invention, the value of (C PD / C FD ) is preferably in the range of 0.0008 to 0.8. It is desirable to be within.
- Terminal 118 is for pixel reset voltage (VR_FD)
- Terminals 119a and 119b are for power supply voltage (AVDD)
- the terminal 120 is used for a reset voltage (VR_CDS) of a double sampling circuit between phases in a pixel.
- Terminal 121 is for the first current source bias voltage (VB1)
- Terminal 122 is for a second current source bias voltage (VB2)
- Terminal 123 is for pixel reset pulse ( ⁇ R)
- Terminal 124 is for pixel selection first pulse ( ⁇ X1)
- a terminal 125 is for an intra-pixel inter-phase double sampling circuit selection pulse ( ⁇ CDS)
- the terminal 126 is for an intra-pixel inter-phase double sampling circuit bypass pulse ( ⁇ CDSb)
- the terminal 127 is for a pixel selection second pulse ( ⁇ X2)
- the terminal 127a is for the pixel selection second A pulse ( ⁇ X2 ⁇ )
- Terminal 128 is for a double sampling reset pulse ( ⁇ NS) between phases in a pixel, It is.
- FIGS. 2A to 2C are potential explanatory diagrams for explaining the principle of driving a pixel of the optical sensor according to the present invention.
- FIG. 2A is a potential diagram at the time of reset completion (t1)
- FIG. 2B is a potential diagram at the time of reading the first voltage signal (t2)
- FIG. 2C is a potential diagram at the time of reading the second voltage signal (t3).
- the vertical axis represents the potential for electrons (e ⁇ ), and the horizontal axis is an arbitrary spatial axis.
- a potential section (PD) 201 of a fully depleted photodiode which is one of the light receiving elements (PD) 102 and a potential diffusion (CFD) section 202 of a floating diffusion (CFD) 103 adjacent to the section 201 are used.
- the potential for the electron (e-) is shown.
- the “fully depleted type” means that the potential displacement (or slope or gradient) in the potential section 201 gradually decreases from the left terminal to the right terminal in FIG. 2 as shown in FIGS. 2A to 2C. Means you are.
- the potential displacement is not limited to the “fully depleted type”, but may be a “substantially fully depleted type” potential displacement.
- substantially fully depleted means a potential displacement within a range that does not lose the essence of the present invention.
- the potential displacement in the portion near the left terminal and / or the right terminal may be flat or the rate of decrease may be more gradual than the center of the potential displacement, or may be gradually reduced and decreased stepwise. .
- any of the generated photocharges can drift or be transported by drift to the end point of the potential displacement within the reading time (floating diffusion (CFD) 103
- the potential displacement or potential gradient, electric field gradient
- the displacement shape from the left terminal to the right terminal of the potential displacement is one. Either a gradual reduction, a stepwise reduction, or a wavy reduction can be employed in the present invention.
- FIG. 3 is a circuit diagram of the analog memory circuit section of the optical sensor according to the present invention.
- the analog memory circuit unit 300 is one of the typical examples of the preferred embodiment.
- FIG. 3 shows the photosensor pixel circuit unit 100 and the analog memory circuit unit 300.
- the analog memory circuit unit 300 includes an analog memory array (Analog Memories) 301, a memory cell row selection switch array 301a, and a memory readout circuit (Memory Readout) 302.
- Analog Memories Analog Memories
- Memory Readout Memory Readout
- the analog memory array 301 includes memory cells each including one memory selection switch (SW) and one memory capacitor (CAM ) arranged in a 4 H ⁇ 20 V array. I have. A total of 20 memory cells in each row share one signal wiring, and the signal wiring is selected by row selection switches (WS1 to WS4).
- the analog memory array 301 is described as (4 H ⁇ 20 V ) memory arrays. However, in actuality, only (4 H ⁇ 2 V ) memory cells are shown, and other The memory cells are not shown.
- the memory cell column selection switch array 301a includes memory column selection switches (WS1 to WS4) 305 (1 to 4). In FIG. 3, four switches are shown as the memory column selection switches (WS1 to WS4) 305 (1 to 4). However, the present invention is not limited to this. May be increased or decreased according to a predetermined design.
- the pixel signal holding memory array 303 in FIG. 3 is shown a set of memory cells 307a is four sets composed of the pixel signal holding memory selection switch (SW) 306 and the pixel signal holding capacitor (C AM) 307 .
- SW pixel signal holding memory selection switch
- C AM pixel signal holding capacitor
- the pixel signal holding memory array 304 in FIG. 3 has the same memory configuration as the pixel signal holding memory array 303.
- analog memory arrays (Analog Memories)
- Reference numeral 301 denotes an array of (4 H ⁇ 20 V ) memory cells 307a.
- the display of “4 H ⁇ 20 V ” means that four memory cells are arranged in the horizontal direction (each row) and 20 memory cells are vertically arranged (in each column).
- the two-dimensional matrix analog memory array 301 originally has 20 rows of pixel signal holding memory arrays, but FIG. 3 shows two pixel signal holding memory arrays (303, 304). However, the other pixel signal holding memory arrays are not shown.
- a total of 20 memory cells in each column share one signal line among the four pixel signal transfer signal lines 313 (1 to 4), and each signal line of “1 to 4”
- the selection is made by turning on the corresponding memory column selection switch (any of WS1 to WS4) among the four memory cell column selection switches 305 (WS1 to WS4).
- the analog memory circuit unit 300 is desirably arranged adjacent to the photosensor pixel circuit unit 100 in order to shorten the distance of the pixel output signal line (PIXEL_OUT) 117 and shorten the time required for signal reading. As shown in FIG. 7, they are arranged on the same plane adjacent to the photosensor pixel circuit unit 100.
- the photosensor pixel circuit section 100 may be stacked and disposed. In the case of the stacked arrangement shown in FIG. 8, the area of the photodiode (PD) 102 can be relatively increased, which is suitable for increasing the light receiving area and obtaining higher sensitivity.
- a row selection pulse is applied to the row selection switch 305 in order to select a row in which a memory cell in which a signal is to be written is present.
- a memory selection pulse is applied to a memory selection switch (SW) to select a memory cell to which a signal is to be written, and the pixel output is electrically connected to one memory capacitor (CAM ) .
- the pixel output signal voltage is written to the memory capacitor (CAM ) .
- the memory selection switch (SW) is turned off to hold the signal voltage written in the memory capacitor (CAM ) .
- the intra-pixel inter-phase double sampling selection switch (CDS) 108 When the intra-pixel inter-phase double sampling selection switch (CDS) 108 is ON, one signal is output from one pixel in one frame, and the intra-pixel inter-phase double sampling selection switch (CDS) 108 is OFF. In this case, since two or more signals are output from one pixel in one frame, the memory selection switch (SW) 306 and the row selection switch (WS) 305 are switched in one frame period to electrically connect with the pixel output. It performs an operation of writing and holding the memory capacitor (C AM) to be connected by switching each pixel output signal. By the above read operation, the pixel output signal is written and held in the memory cell of the analog memory array 301.
- the memory reading circuit 302 is driven to sequentially scan the memory cells to read a voltage signal held in each memory cell. Specifically, first, a row selection pulse is applied to a corresponding row selection switch in order to select a row having memory cells to be read. Next, the signal wiring is reset to a specified voltage, and then the signal wiring is floated. Next, the memory selection pulse, a capacitor (C AM) 309 for the corresponding pixel signals held in applied to the memory selection switch 108 in question is electrically connected to the corresponding signal line.
- C AM capacitor
- the capacity and corresponding capacitance (C AM) 309 and stored have capacity division of the charge to the corresponding signal line, the signal voltage corresponding to the voltage held in the memory capacitor CAM is generated in the signal line I do.
- the memory read circuit 302 amplifies the signal voltage and reads a signal outside the analog memory array 301.
- FIG. 4 is a timing chart showing one example of the pixel driving timing of the photosensor of the present invention and the time transition of the floating diffusion voltage (VFD).
- the pulse waveform indicated by the frame period ( ⁇ Frame) is a pulse indicating the frame period, and the number corresponds to the frame number.
- the pulse waveform represented by the reset pulse ( ⁇ R) indicates ON / OFF of the reset pulse ( ⁇ R) transmitted to the reset transistor (R) 104.
- the pulse waveforms indicated by the first voltage signal readout pulse ( ⁇ Sig1) and the second voltage signal readout pulse ( ⁇ Sig2) are timings related to the signal readout of the first voltage signal (1) and the second voltage signal (2), respectively. Is shown.
- VFD floating diffusion voltage
- the falling times (t2, t3) of the first voltage signal readout pulse ( ⁇ Sig1) and the second voltage signal readout pulse ( ⁇ Sig2) are the first voltage, respectively.
- the timing at which the signal (A1) and the second voltage signal (A2) are started to be held by different pixel signal holding capacitors ( CAM ) is shown.
- the falling time (t2) of the first voltage signal readout pulse ( ⁇ Sig1) is set to the intra-pixel inter-phase double sampling sample-and-hold capacity (C SH ) 111.
- C SH intra-pixel inter-phase double sampling sample-and-hold capacity
- the first noise signal (1) is subtracted from the second voltage signal (2) to cancel the reset noise voltage signal (VN).
- the reset pulse ( ⁇ R) first rises with the start of the frame period ( ⁇ Frame) in any case of using the photodiode (
- the capacitance (C FD ) of the PD 102 and the floating diffusion (CFD) 103 is reset to a predetermined reset voltage (VR_FD).
- VR_FD a predetermined reset voltage
- the reset pulse ( ⁇ R) falls and the reset operation is completed, and the floating diffusion voltage (VFD) takes in the reset noise voltage (VN).
- VN reset noise voltage
- photocharges corresponding to the amount of irradiated light are accumulated in the floating diffusion capacitance (C FD ), and the floating diffusion voltage (VFD) changes over time.
- the first voltage signal readout pulse ( ⁇ Sig1) falls, and a floating period occurs between the reset noise voltage (VN) and the predetermined period (t2-t1).
- VN reset noise voltage
- t2-t1 The time when the first voltage signal (A1) based on the voltage signal (Vsig1) generated by the photocharge accumulated in the diffusion capacitance (C FD ) is read is shown.
- the accumulation time (t3 ⁇ t2) is desirably set to 1 ⁇ sec or less.
- the intra-pixel inter-phase double sampling bypass switch (CDSb) 109 is turned on when a signal ( ⁇ CDSb) is applied to the terminal 126, and The case where the double sampling selection switch (CDS) 108 is in the OFF state will be described. Note that light is irradiated during the frame period.
- a reset pulse ( ⁇ R) for pixel reset is applied to the terminal 123 of the reset transistor (R) 104, and the light receiving element (PD) 102 and the floating diffusion (CFD) 103 constituting the pixel in the photosensor pixel circuit 101a are reset. Is done.
- a reset noise voltage signal (VN) is induced in the floating diffusion (CFD) 103 when the reset is completed (t1) when the reset transistor (R) 104 is turned off.
- the first voltage signal (A1) is read from the photosensor pixel circuit 101a as follows.
- the first voltage signal (A1) read out on the pixel reading signal line (PIXEL_OUT) 117 after the reset is completed includes the reset noise voltage signal (VN) and the time from the completion of the reset to the reading of the first voltage signal (A1).
- a first photocharge voltage signal (VsigA1) based on photocharges collected by the light receiving element (PD) 102 and transported to the floating diffusion (CFD) 103 during a predetermined period (t2-t1). A).
- the first source follower transistor (SF1) 105 becomes active and the voltage signal (A1-A) The corresponding first voltage signal (A1) is output to the pixel output signal line (PIXEL_OUT) 117.
- one of the four memory column selection switches 305 (WS1 to WS4) is turned ON to select a corresponding memory column, and a predetermined signal is supplied to a pulse signal line (311 to 320) for selecting a signal holding memory cell. the combination of the pulse signal is applied, to electrically couple the pixel signal holding capacitor (C AM) 307 in the pixel output signal line (PIXEL_OUT) 117 and one memory cell 307a.
- a combination of pulses is transmitted to the pulse signal lines (311 to 320) for selecting a signal holding memory, and only the pulse signal line 310-1 and the pulse signal line 311-1 are set to the High level, and the other signals are set.
- the pulse signal line is set to Low level.
- the corresponding one of the four memory column selection switches 305 (WS1 to WS4) (WS1) and the corresponding one of the four pixel signal holding memory selection switches 306 (SW1 to SW4) ( SW1) is turned on to select the memory cell 307a in the pixel signal holding memory array 303 via the pixel signal transfer signal line 313-1.
- the first voltage signal (A1) corresponding to the voltage signal (A1-A) is supplied to the pixel signal of one memory cell 307a via the pixel output signal line 117 and the pixel signal transfer signal line 313-1.
- the data is transferred to the storage capacity ( CAM ) 307.
- the pulse state transmitted to the signal holding memory selection pulse signal line 311-1 is changed to set the signal holding memory selection pulse signal line 311-1 to the low level, and the corresponding pixel signal holding memory selection switch is selected.
- SW1 306 and by causing turned OFF, a first voltage signal (A1) is, time to be read by the drive of the memory read circuit 302, and is held in the pixel signal holding capacitor (C AM) 307.
- an accumulation period (t3-t2) is provided.
- the photocharge generated during the accumulation period (t3 ⁇ t2) is drift-transported to the floating diffusion (CFD) 103 by the potential gradient of the light receiving element (PD) 102 shown in the potential section 201 shown in FIG. CFD) 103 is stored in the capacity (C FD ).
- the first selection transistor (X1) 106 By turning off the first selection transistor (X1) 106 during the accumulation period (t3-t2), power consumed by the first source follower transistor (SF1) 105 can be suppressed. However, if the accumulation period (t3 ⁇ t2) is as short as several nsec or less, the ratio of the time during which the first source follower (SF1) 105 is driven during the accumulation period (t3 ⁇ t2) increases. The effect of reducing power consumption obtained by turning off the one-selection transistor (X1) 106 becomes relatively small. Therefore, in the above case, it is rather advantageous to omit the time required to switch the state of the first selection transistor (X1) 106 between ON and OFF, which has the effect of obtaining a higher imaging speed. During t3-t2), the first selection transistor (X1) 106 may be left in the ON state.
- the second voltage signal (A2) includes a reset noise voltage signal (VN) and a floating diffusion (CFD) 103 collected by the light receiving element (PD) 102 after the completion of reset and before the reading of the second voltage signal (A2). And a second photocharge voltage signal (VsigA2) based on the photocharges transported to the photovoltaic device.
- VN reset noise voltage signal
- CCD floating diffusion
- the pixel selection first pulse ( ⁇ X1) is applied to the terminal 124, the first source follower transistor (SF1) 105 becomes active, and the voltage signal ( A second voltage signal (A2) corresponding to A2-A) is output to the pixel output signal line (PIXEL_OUT) 117.
- one of the four memory column selection switches 305 (WS1 to WS4) is turned ON to select the corresponding memory column, and a predetermined signal signal is supplied to the pulse signal line (311 to 320) for signal holding memory selection.
- the combination of the pulse signal is applied, the pixel output signal line (PIXEL_OUT) 117 and one memory cell, for example, electrically coupling the pixel signal holding capacitor of the memory cell 309a (C AM) 309.
- a combination of pulses is transmitted to the pulse signal lines 310 to 320 for selecting a signal holding memory, only the pulse signal line 310-1 and the pulse signal line 312-1 are set to the high level, and the others are set to the low level.
- one of the memory column selection switch (WS1) 305 and one of the selection switches 306 (SW1 to SW4) for selecting the pixel signal holding memory for example, the selection switch 306 (SW1) is turned on, and the pixel signal The memory cell 309a is selected via the transfer signal line 313-1.
- the second voltage signal (A2) corresponding to the voltage signal (A2-A) is supplied to the pixel signal of one memory cell 309a via the pixel output signal line 117 and the pixel signal transfer signal line 313-1.
- the data is stored in a storage capacitor ( CAM ) 309.
- the pulse state transmitted to the signal holding memory selection pulse signal line 312-1 is changed to set the signal holding memory selection pulse signal line 312-1 to the low level, and the pixel signal holding memory selection selection switch 308 is turned on. was turned OFF, the write signals to the pixel signal holding capacitor (C AM) 309, a second voltage signal (A2) is held time to be read by the drive of the memory read circuit 302.
- a voltage signal (VN) in which the reset noise voltage signal (VN) is canceled is obtained.
- VsigA2-VsigA1 can be obtained.
- the voltage signal (VsigA2-VsigA1) which is the difference between the signals is obtained by reading the first voltage signal (A1) and the second voltage signal (A2) out of the chip by a method described later, It is obtained by performing subtraction in.
- the above is the same as the first voltage signal (A1) (pixel signal) corresponding to the voltage signal (A1-A) formed in the capacitance (C FD ) of the floating diffusion (CFD) 103 within one frame period.
- a second voltage signal (A2) (pixel signal) corresponding to the voltage signal (A2-A) formed in the capacitor (C FD ) is read twice, and the intra-pixel interphase double sampling circuit 101b is used.
- pixel signals can be read three or more times in the same frame period ( ⁇ Frame) as described later.
- a predetermined combination of pulse signals is applied to the signal holding memory selection pulse signal line 310 in the same manner as described above, and the corresponding memory cell is selected at the time of reading each signal, and the signal output is written and held. I do.
- a reset pulse ( ⁇ R) for pixel reset is input to the terminal 123 of the reset transistor (R) 104, and the next frame period starts.
- the above series of operations is repeated, imaging is performed for a plurality of frame periods, and signal writing is performed to all memory cells of the analog memory array 301.
- the memory cell to be selected may be returned to the initial address, and the overwriting operation may be repeated until an imaging stop trigger signal is input from the camera.
- the signal written in the memory cell is read out by a method described later.
- the intra-pixel inter-phase double sampling selection switch (CDS) 108 is ON, and the intra-pixel inter-phase double sampling bypass switch (CDSb) 109 is OFF. The case where is described.
- a reset pulse ( ⁇ R) for resetting a pixel is applied to a terminal 123 of a reset transistor (R) 104, and a light receiving element (PD) 102 and a floating diffusion (CFD) 103 constituting a pixel in the photosensor pixel circuit 101a. And are reset.
- a reset noise voltage signal (VN) is generated in the floating diffusion (CFD) 103 when the reset is completed (t1) when the reset transistor (R) 104 is turned off.
- the first voltage signal (B1) is read from the photosensor pixel circuit 101a to the intra-pixel inter-phase double sampling circuit 101b as follows.
- the first voltage signal (B1) read from the photosensor pixel circuit 101a to the intra-pixel inter-phase double sampling circuit 101b after the completion of the reset is the same as the reset noise voltage signal (VN) taken into the floating diffusion (CFD) 103 after the completion of the reset.
- the first source follower transistor (SF1) 105 becomes active and is based on the voltage signal (B1-A).
- the first voltage signal (B1) is generated at an electrode of the intra-pixel inter-phase double sampling bypass switch (CDS) 108 of the intra-pixel inter-phase double sampling coupling capacitance (C C ) 110.
- an intra-pixel inter-phase double sampling reset pulse ( ⁇ NS) is applied to the terminal 128 to turn on / off the intra-pixel inter-phase double sampling reset switch (NS) 112, and the intra-pixel inter-phase double sampling coupling capacitance (C C).
- ⁇ NS intra-pixel inter-phase double sampling reset pulse
- the intra-pixel inter-phase double sampling sample hold capacitor (C SH ) 111 is reset to the inter-pixel inter-phase double sampling circuit reset voltage (VR_CDS).
- an accumulation period (t3-t2) is provided.
- Accumulation period (t3-t2) photocharge generated during is drift transported to the floating diffusion (CFD) 103 by the potential gradient 201 of the light receiving element (PD) 102, a floating diffusion (CFD) 103 of the capacitor (C FD) Stored.
- a floating diffusion (CFD) 103 of the capacitor (C FD) Stored.
- the first selection transistor (X1) 106 may be in the ON state during the accumulation period (t3 ⁇ t2) for the reason described above. .
- the second voltage signal (B2) is read from the photosensor pixel circuit 101a to the intra-pixel inter-phase double sampling circuit 101b as follows.
- the second voltage signal (B2) is collected by the light receiving element (PD) 102 after the reset noise voltage signal (VN) and the completion of the reset and until the second voltage signal (B2) is read out, and the floating diffusion (CFD) 103 And a second photocharge voltage signal (VsigB2) based on the photocharges transported to the photovoltaic device, and a voltage signal (B2-A).
- a second voltage signal (B2) is a pixel internal phase between double sampling coupling capacitance (C C) double sampling bypass switches between 110 pixels internal phase (CDS) 108 side electrodes corresponding to the photoelectric charge voltage signal (VsigB2) Occurs.
- the voltage of the inter-pixel double-sampling sample-and-hold capacitor (C SH ) 111 that is capacitively coupled to the intra-pixel inter-phase double sampling coupling capacitance (C C ) 110 becomes the reset voltage of the intra-pixel inter-phase double sampling circuit.
- the voltage signal (BA) in which the reset noise voltage signal (VN) is canceled is obtained by subtracting the first voltage signal (B1) from the second voltage signal (B2).
- the pixel selection second pulse ( ⁇ X2) is applied to the terminal 127 to apply the second selection transistor (X2) 114 to the pixel selection second A pulse ( ⁇ X2 ⁇ ) to the terminal 127a to apply the second selection transistor (X2 ⁇ ) to the terminal 127a.
- ) 115 are turned ON to output a voltage signal (BB) corresponding to the voltage signal (BA) to the pixel output signal line 117.
- one of the four memory column selection switches (WS1 to WS4) in the memory column selection switch array 301a is turned on to select the corresponding memory column, and a pulse signal line (311) for selecting a signal holding memory.
- ⁇ 320) to apply a pulse signal of a predetermined combination, one memory cell and the pixel output signal line 117, for example, electrically coupling the pixel signal holding capacitor of the memory cell 307a (C AM) 307.
- a pulse signal of a combination of pulses is applied to the pulse signal lines 310 to 320 for selecting a signal holding memory, only the pulse signal line 310-1 and the pulse signal line 311-1 are set to the High level, and the others are set.
- the memory column / row selection switch (WS1) 305 and the selection switch (SW1) 306 for selecting a pixel signal holding memory are turned on, and the pixel signal is transferred via the pixel signal transfer signal line 313-1. is selected memory cell 307a in the holding memory array 303, the voltage signal (BB) is induced in the pixel signal holding capacitor (C AM) 307.
- the pulse state transmitted to the signal holding memory selection pulse signal line 311-1 is changed to set the signal holding memory selection pulse signal line 311-1 to the low level, and the pixel signal holding memory selection switch (SW1) is selected.
- ) 306 is turned off, the voltage signal (BB) is held in the pixel signal holding capacitor ( CAM ) 307. It said voltage signal (BB) a period from the read by the drive of the memory read circuit 302, and is held in the pixel signal holding capacitor (C AM) 307.
- the corresponding frame period is completed as described above.
- the reset pulse ( ⁇ R) for pixel reset is input to the terminal 123 of the reset transistor (R) 104, and the next frame period starts.
- the series of operations described above are repeated, and imaging is performed for a plurality of frame periods ( ⁇ Frame).
- a signal is written to all the memory cells in the analog memory array 301.
- the selected memory cell may be returned to the initial address, and the overwriting operation may be repeated until a trigger signal for stopping imaging is input from the camera.
- the signal written in each memory cell is read out by a method described later.
- FIG. 5 shows a timing chart when the pixel signal is read four times in the same frame period ( ⁇ Frame).
- t1 indicates the time when the reset is completed
- t2 indicates the time at which the first voltage signal is read out from the photosensor pixel circuit 101a after a lapse of a predetermined period (t2 ⁇ t1) from t1, and t3.
- T4, and t5 indicate the times at which the second voltage signal, the third voltage signal, and the fourth voltage signal are read from the photosensor pixel circuit 101a, respectively
- the accumulation periods T1, T2, and T3 are respectively the accumulation periods (t3 ⁇ t2), (t4 ⁇ t3), and (t5 ⁇ t4).
- Light is irradiated during the frame period.
- a reset pulse ( ⁇ R) for pixel reset is applied to the terminal 123 of the reset transistor (R) 104, and the light receiving element (PD) 102 and the floating diffusion (CFD) 103 constituting the pixel in the photosensor pixel circuit 101a are reset. Is done.
- a reset noise voltage signal (VN) is induced in the floating diffusion (CFD) 103 when the reset is completed (t1) when the reset transistor (R) 104 is turned off.
- the first voltage signal (C1) is read from the photosensor pixel circuit 101a as follows.
- the first voltage signal (C1) read out on the pixel reading signal line (PIXEL_OUT) 117 after the completion of the reset is the reset noise voltage signal (VN) and from the completion of the reset to the reading of the first voltage signal (C1).
- VN reset noise voltage signal
- VsigC1 a first photocharge voltage signal based on photocharges collected by the light receiving element (PD) 102 and transported to the floating diffusion (CFD) 103 during a predetermined period (t2-t1).
- the pixel selection first pulse ( ⁇ X1) is applied to the terminal 124 of the first selection transistor (X1) 106
- the first source follower transistor (SF1) 105 becomes active, and the voltage signal (C1-A) is applied.
- the corresponding first voltage signal (C1) is output to the pixel output signal line (PIXEL_OUT) 117.
- one of the four memory column selection switches 305 (WS1 to WS4) is turned ON to select a corresponding memory column, and a predetermined signal is supplied to a pulse signal line (311 to 320) for selecting a signal holding memory cell.
- a pulse signal of a combination is applied, and the pixel output signal line (PIXEL_OUT) 117 and the pixel signal holding capacitor (C AM ) 307 in one memory cell 307a are electrically coupled to each other according to the voltage signal (C1-A).
- the first voltage signal (C 1) is transferred to the pixel signal holding capacitor (C AM ) 307 and is held until it is read out by driving the memory reading circuit 302.
- an accumulation period 1 (t3-t2) is provided.
- the photocharge generated during the accumulation period 1 (t3-t2) is drift-transported to the floating diffusion (CFD) 103 by the potential gradient of the light receiving element (PD) 102 shown in the potential section 201 shown in FIG. It is stored in the capacity (C FD ) of the (CFD) 103.
- the second voltage signal (C2) is read.
- the second voltage signal (C2) is a reset noise voltage signal (VN) and a floating diffusion (CFD) 103 collected by the light receiving element (PD) 102 after the completion of reset and before the reading of the second voltage signal (C2).
- VsigC2 a second photocharge voltage signal based on the photocharges transported to the photovoltaic device.
- the pixel selection first pulse ( ⁇ X1) is applied to the terminal 124, the first source follower transistor (SF1) 105 becomes active, and the voltage signal ( A second voltage signal (C2) corresponding to C2-A) is output to the pixel output signal line (PIXEL_OUT) 117.
- one of the four memory column selection switches 305 (WS1 to WS4) is turned ON to select the corresponding memory column, and a predetermined signal signal is supplied to the pulse signal line (311 to 320) for signal holding memory selection.
- the combination of the pulse signal is applied, the pixel output signal line (PIXEL_OUT) 117 and one memory cell, for example, the pixel signal holding capacity of the memory cell 309a (C AM) 309 electrically coupled to the voltage signal (C2-a) Is transferred to the pixel signal holding capacitor (C AM ) 307 and held for a period until the memory reading circuit 302 reads out the first voltage signal (C 2).
- the pixel output signal line (PIXEL_OUT) 117 and one memory cell for example, the pixel signal holding capacity of the memory cell 309a (C AM) 309 electrically coupled to the voltage signal (C2-a) Is transferred to the pixel signal holding capacitor (C AM ) 307 and held for a period until the memory reading circuit 302 reads out the first voltage signal (C 2).
- the third voltage signal (C3) is output after the end of the accumulation period 2 (t4-t3), and the third voltage signal is output after the end of the accumulation period 3 (t5-t4). 4 is read out.
- a reset noise voltage signal (VN) is obtained.
- a signal based on the photocharge accumulated in the capacitance (C FD ) of the floating diffusion (CFD) 103 during the canceled accumulation period 1 is obtained.
- the method of processing the second to fourth voltage signals is not limited to the above, and the third voltage signal (C3) is obtained by subtracting the second voltage signal (C2) from the fourth voltage signal (C4). ) Is subtracted from the first voltage signal (C1), and during the accumulation period 2-1 (t5-t3) and the accumulation period 2-2 (t4-t2), the capacitance of the floating diffusion (CFD) 103 is substantially reduced. A signal based on the photocharge accumulated in C FD may be obtained.
- the second to fourth voltage signals may be added and averaged, and then the first voltage signal (C1) may be subtracted, so that the signal can be used for reading in which random noise superimposed during signal reading is reduced. Further, the timings of t1 to t5 may be synchronized with the modulated light irradiation, and applied to a time-of-flight type distance imaging or fluorescence lifetime imaging.
- the pulse operation during the frame period ( ⁇ Frame) is minimized, which is suitable for high-speed operation.
- the frame period can be divided into shorter periods, which is suitable for obtaining a higher time resolution.
- the present invention has an advantage that the operation mode can be switched according to the priority of the frame rate and the number of recording frames.
- the choice between using and not using the intra-pixel inter-phase double sampling circuit 101b is optional. However, in order to maximize the advantages of the present invention, the circuit is based on the following criteria. It is preferable to selectively use or not use 101b.
- the intra-pixel inter-phase double sampling circuit 101b is preferably used when priority is given to the number of continuous recording frames because the effect can be maximized. Specific examples of the case where the number of continuous recording frames is to be prioritized include shooting such as combustion injection and spark discharge of an automobile engine, ink discharge of an ink jet printer, etc., which are phenomena that occur relatively continuously.
- the mode (B) in which the circuit 101b is bypassed is preferably used when priority is given to the shooting speed because the effect can be maximized.
- the use of this mode (B) is suitable for imaging of high-speed phenomena such as imaging of material destruction phenomena, laser ablation and discharge phenomena.
- mode (A) it is possible to switch from using the circuit 101b for each frame (“mode (A)”) to bypassing (“mode (B)”).
- mode (B) the number of recording frames can be increased. Therefore, the operation is performed in the mode (A), and the image is captured at a higher speed in the mode (B) from the time when the high-speed phenomenon of the shooting target occurs. You can do it.
- the frame number immediately before the mode switching is recorded, all the signals held in the analog memory array 301 are read out, and the signal before the mode switching is visualized as a noise-cancelled signal.
- the signal after the mode switching is subtracted from the first voltage signal (A1) and the second voltage signal (A2) for noise cancellation recorded for each frame, and then imaged after noise cancellation.
- the number of memory cells included in the analog memory array 301 is 80, but the number of memory cells is not limited to this, and the number is determined according to the design. Since the number of memory cells is limited by the area of the analog memory array 301, it becomes a design factor that determines the aperture ratio and the pixel size. Is determined.
- the number of memory cells is preferably 10 or more, but is preferably 40 or more, and more preferably 128 or more, in order to increase the number of recording frames. In order to further increase the number of recording frames, it is desirable that the number be 256 or more.
- the analog memory circuit section 300 is provided below the optical sensor pixel circuit section 100.
- FIG. 6 is a block diagram of the image sensor according to the present invention.
- the image sensor 600 of the example shown in FIG. 6 includes a light receiving signal generation / holding element array 602 in which a plurality of light receiving signal generation / holding elements 601 are two-dimensionally arranged, a memory selection circuit 603, and a pixel driving pulse buffer column circuit 604. , A column selection circuit 605.
- the pixel drive pulse buffer array circuit 604 is provided with an output buffer 606 and a signal output terminal 607 on the downstream side of the signal transmission path.
- the light receiving signal generation / holding element 601 includes the photosensor pixel circuit unit 100 and the analog memory circuit unit 300.
- the imaging period of the image sensor 600 ends, and then the process proceeds to the signal output period of the image sensor 600.
- signal reading is performed for each analog memory array 301 corresponding to pixels in each row. That is, the memory selection circuit 603 is driven to select the memory read circuit 302 for one pixel row, and the output signal line 302a of the memory read circuit 302 and the vertical signal line 608 are connected.
- a row in the analog memory 301 in which a memory cell to be read is located is selected.
- the memory row selection switch WS1 is selectively turned on by setting only 310-1 out of 310-1 to 310-1 to High level, and the signal line 313-1 for transferring pixel signals and the memory readout circuit 302 are coupled.
- the pixel signal transfer signal line 313-1 is brought into a floating state. Then, combining the selected one of the memory cells corresponding pixel signal storage capacitor (C AM) and the corresponding pixel signal transfer signal line for 313-1. At this time, the corresponding pixel signal holding capacitor (C AM) written have voltage signal (5S-1), the corresponding pixel signal holding capacitor (C AM) and the corresponding pixel signal the signal lines for the transfer 313-1 And is input to the memory read circuit 302 after being divided by the parasitic capacitance.
- the memory read circuit 302 outputs a voltage signal (5S-2) based on the voltage signal (5S-1) to the vertical signal line 608.
- the voltage signal (5S-2) of the vertical signal line 608 is temporarily held in the column circuit 604.
- the column selection circuit 605 is sequentially driven, and the voltage signal (5S-1) held in the column circuit 604 is sequentially output to the signal output terminal 607 via the output buffer 606.
- the memory read circuit 302 by resetting the signal line 313-1 for transferring the pixel signal and selecting the memory cell to be read next to divide the capacity of the voltage signal, drive the memory read circuit 302, drive the column circuit 504, and output the chip, the memory is repeated.
- the signals of all the memory cells selected by the column selection switch (WS1) 305 are read.
- other columns in the analog memory 301 are sequentially selected, signals of all memory cells in each column are read, and signals of all memory cells in the selected analog memory 301 are read out of the chip.
- the memory selection circuit 603 is driven to select a memory cell of a pixel column to be read next, and the same operation is repeated. This signal read operation is performed for the memory cells of all the pixel columns. With the above operation, the signals of the memory cells for all the pixels are read.
- the only factor governing the frame rate is the charge collection / transport time in the light receiving element, and the frame rate can be increased to 125 Mbps.
- a pixel drive pulse circuit can be arranged in a pixel or a pixel block without sacrificing area.
- the fully-depleted light-receiving element having a small capacitance density is coupled to the floating diffusion, an increase in the floating diffusion capacitance, which is inversely proportional to the charge-voltage conversion gain, can be minimized, and a high charge-voltage conversion gain can be obtained. Since the reset noise of the floating diffusion can be canceled, the signal can be read with high sensitivity and low signal read noise.
- a higher frame rate can be obtained although the floating diffusion is saturated.
- (6) By performing signal readout in synchronization with modulated light irradiation, it can be applied to optical time-of-flight distance imaging and fluorescence lifetime imaging.
Abstract
Description
高感度・高速・広ダイナミックレンジ・広光波長帯域対応の光センサ・固体撮像装置の例としては、例えば、特許文献1に記載されている。
しかしながら上記の光センサは、受光素子の一つであるフォトダイオード(以後、「PD」と略記することもある)とフローティングディフュージョン(以後、「CFD」と略記することもある)の間に転送スイッチが設けてあり、この転送スイッチをON-OFFすることで前記フォトダイオード(PD)にある電荷を前記フローティングディフュージョン(CFD)に転送している。そのために、転送スイッチをONーOFFするのに必要な画素駆動パルスのセトリング期間が必要であり、そのための時間がかかることで、フレームレートの高速化に限界があった。また、複数の画素駆動パルスを高速に画素領域全体に伝搬させる必要があり、消費電力を押し上げていた。
尚、特に断りなく本件で「画素」と記す場合のその画素は、受光素子(PD)とフローティングディフュージョン(CFD)で構成されたものを意味する。
受光素子と該受光素子に電気的に直結され、該受光素子に入力する光によって発生する電荷を蓄積するフローティングディフュージョンと画素信号出力線、を有し、前記画素信号出力線に信号読出し経路が接続されており、
前記受光素子の容量(CPD)と前記フローティングディフュージョンの容量(CFD)とが、
0.0008 ≦(CPD)/(CFD)≦ 0.8・・・・・・・・・・・(1)
4.0×10-18 F ≦(CPD)≦ 4.0×10-16 F・・・・・(2)
5.0×10-16 F≦(CFD)≦ 5.0×10-15 F・・・・・・(3)
の関係にあり、
前記受光素子の半導体接合部は完全空乏化されかつ電子のポテンシャルカーブが前記フローティングディフュージョン方向に向かって負の傾斜をしており、その負の傾斜状態のままで、前記フローティングディフュージョンの電子ポテンシャル・ウェルの最上位に繋がっている、光センサ及びその信号読出し方法にある。
前記受光素子は、半導体接合部が完全に空乏化されかつ前記フローティングディフュージョン方向に向かって負の傾斜をしており、その負の傾斜状態のままで前記フローティングディフュージョンの電子ポテンシャル・ウェルの最上位に繋がっている電子のポテンシャルカーブを有し、
時間軸上で択一的に使用される二つの出力系統を有している光センサ画素回路;
一方の出力系統から出力される、光照射により前記受光素子内に生じた光電荷量に基づいた第一の出力(a1)と第二の出力(b1)とに基づいてノイズキャンセレーションして信号(ab1)を出力する画素内相関二重サンプリング回路;
と、を備えた光センサ画素回路部:
前記信号(ab1)、及び他方の出力系統から出力される第一の出力(a2)と第二の出力(b2)
との何れかの信号を保持するメモリセルの複数を行列配置したアナログメモリアレイ;
何れかのメモリセル配設行を選択するためのメモリセル行選択スイッチアレイ;
何れかのメモリセルに保持されている信号を読出すためのメモリ読出し回路;
と、を備えたアナログメモリ回路部:
を具備する光エリアセンサ及びその信号読出し方法にある。
図1に示される光センサ画素回路部100は、光センサ画素回路101aと画素内相間二重サンプリング回路(In-pixel CDS)101bとを備えている。
画素内相間二重サンプリング回路101bからは、次の電気的回路に信号を転送するための画素出力信号線(PIXEL_OUT)117が配線されている。
受光素子(PD)102の内部構造には、2つの異種の半導体型(P+型、P型、P―型、I型、N+型、N型、N―型)の半導体層領域が接合されて形成された半導体接合少なくとも一つ設けてある。
本発明において、「完全に空乏化されている」とは、図2A~2Cに示されるように、ポテンシャル区分201において、ポテンシャル変位(若しくは、傾斜或いは勾配)が図2の左端末から右端末に至るまで漸次減少していることを意味する。
本発明において、「実質完全に空乏化されている」とは、受光することによって受光素子(PD)102の半導体接合の領域に発生した光電荷が、隣接するフローティングディフュージョン(CFD)103にスムーズに移送され得る形状のポテンシャル変位が形成されていることを意味する。
これらの詳細については、後述する。
0.0008 ≦(CPD)/(CFD)≦ 0.8・・・・・・・・・・・・・(1)
4.0×10-18 F ≦(CPD)≦ 4.0×10-16 F・・・・(2)
5.0×10-16 F≦(CFD)≦ 5.0×10-15 F・・・・・(3)
本発明の光センサの画素において、
飽和電荷量は、
「Vsat×(CFD+CPD)/q」・・・・・・(a)
であるから、
電荷電圧変換ゲインは、
「q/ (CFD+CPD)」・・・・・・・・・・・・(b)
で与えられる。
ここで、
「CPD」:完全空乏型受光素子(PD)102の容量
「CFD」:フローティングディフュージョン(CFD)103の容量
「Vsat」:フローティングディフュージョンン(CFD)103における飽和信号電圧
「q」:素電荷量
とする。
「接合面積」は、受光素子(PD)102の光入射側の面積(実際に光が当たる面積:受光面積)とは必ずしも同一ではなく、受光面積より大きい場合もある。
以後、「光入射側の面積」を単に「面積」と書く場合もある。
ここでいう「光電荷の最大移動距離」とは、受光素子(PD)102が外部からの光を受光することで受光素子(PD)102の半導体接合で発生した光電荷がフローティングディフュージョン(CFD)103に移動する距離(移動距離)の中の最大の移動距離のことをいう。
従って、受光素子(PD)102の容量(CPD)は、受光面積が5µm角に相当する4.0×10-18F以上から50µm角に相当する4.0×10-16 F以下の範囲にあるのが望ましい。
好ましくは、容量(CFD)は容量(CPD)より大きくすることが望ましく、より好適には容量(CPD)が無視できるほど容量(CFD)が容量(CPD)より大きく、(CFD+CPD)が容量(CFD)と一致若しくはほぼ一致するのが望ましい。
5.0×10-16 Fから 5.0×10-15 F
の範囲にあるのが望ましい。
一方、容量(CFD)が5.0×10-15 F以下で、「Vsat」が1V以上の場合には、飽和電荷数は3万個以上となり、局所的に強い光量が画素に照射された場合にも白飛びを抑制することが出来る。
(CPD/CFD)の値が、0.0008未満では、受光素子(PD)102の受光面積が実質的に小さくなり、本発明の目的を達成するには光感度が低く過ぎて高速読み取りセンサとして適正でなくなる場合がある。
(CPD/CFD)の値が、0.8を超えると、電荷電圧変換ゲインが小さくなり光感度が小さくなって本発明の目的を達成することが出来なくなる場合が生じる。
端子118は、画素リセット電圧(VR_FD)用、
端子119a及び端子119bは、電源電圧(AVDD)用、
端子120は、画素内相間二重サンプリング回路リセット電圧(VR_CDS)用、
端子121は、第1電流源バイアス電圧(VB1)用、
端子122は、第2電流源バイアス電圧(VB2)用、
端子123は、画素リセットパルス(ΦR)用、
端子124は、画素選択第1パルス(ΦX1)用、
端子125は、画素内相間二重サンプリング回路選択パルス(ΦCDS)用、
端子126は、画素内相間二重サンプリング回路バイパスパルス(ΦCDSb)用、
端子127は、画素選択第2パルス(ΦX2)用、
端子127aは、画素選択第2Aパルス(ΦX2`)用、
端子128は、画素内相間二重サンプリングリセットパルス(ΦNS)用、
である。
アナログメモリ回路部300は、アナログメモリアレイ(Analog Memories)301、メモリセル行選択スイッチアレイ301a、メモリ読出し回路(Memory Readout)302、を備えている。
尚、図3においては、アナログメモリアレイ301は、(4Hx20V)個のメモリアレイとして説明されるが、実際は(4Hx2V)個のメモリセルが図示されているだけで、他のメモリセルは図示が省略されている。
301は、メモリセル307aが(4H×20V)個、アレイ状に配置されている。
ここで、「4H×20V」の表示は、メモリセルが、水平方向に(各行に)4個、垂直方向に(各列に)20個、配列されていることを意味する。
アナログメモリ回路部300は画素出力信号線(PIXEL_OUT)117の距離を短くして信号読出しに要する時間を短縮化するために光センサ画素回路部100に隣接して配置されることが望ましく、例えば、図7に示されるように光センサ画素回路部100に隣接して同一プレナー上に配置される。もしくは、図8に示されるように光センサ画素回路部100に積層して配置しても良い。図8に示される積層配置の場合には、フォトダイオード(PD)102の面積を相対的に大きくすることが出来るため、受光面積を広げてより高い感度を得るために好適である。
まず信号書き込みを行うメモリセルがある行を選択するために、行選択スイッチ305に行選択パルスを印加する。
以上の読出動作によって画素出力信号がアナログメモリアレイ301のメモリセルに書き込まれ保持される。
尚、フレーム期間(ΦFrame)中は光が照射されている。
(1) 画素内相間二重サンプリング回路101bを迂回する場合
先ず、画素内相間二重サンプリング迂回スイッチ(CDSb)109が端子126に信号(фCDSb)が印加されてON状態にあり、画素内相間二重サンプリング選択スイッチ(CDS)108がOFF状態となっている場合について説明する。尚、フレーム期間中は光が照射されている。
リセットトランジスタ(R)104の端子123に画素リセット用のリセットパルス(ΦR)が印加され、光センサ画素回路101a中の画素を構成する受光素子(PD)102とフローティングディフュージョン(CFD)103とがリセットされる。
リセットトランジスタ(R)104がOFF状態となるリセット完了時(t1)にリセットノイズ電圧信号(VN)がフローティンディフュージョン(CFD)103に誘起される。
リセット完了後に読画素出力信号線(PIXEL_OUT)117上に読み出す第1の電圧信号(A1)は、前記リセットノイズ電圧信号(VN)と、リセット完了後から第1の電圧信号(A1)の読出しまでの所定の期間(t2-t1)に受光素子(PD)102で収集されフローティングディフュージョン(CFD)103に輸送された光電荷による第一光電荷電圧信号(VsigA1)と、からなる電圧信号(A1-A)に基づくものである。
この状況下で、4つのメモリ列選択スイッチ305(WS1~WS4)の該当する一つ(WS1)と、4つの画素信号保持メモリ選択用の選択スイッチ306(SW1~SW4)の該当する一つ(SW1)をONさせ、画素信号転送用の信号線313-1を介して画素信号保持メモリアレイ303中のメモリセル307aを選択する。
その結果、電圧信号(A1-A)に応じた第1の電圧信号(A1)が、画素出力信号線117、画素信号転送用の信号線313-1を介して一つのメモリセル307aの画素信号保持容量(CAM)307に転送される。
蓄積期間(t3-t2)中に発生した光電荷は、図2に示されるポテンシャル区間201に示される受光素子(PD)102のポテンシャル勾配によりフローティングディフュージョン(CFD)103へドリフト輸送され、フローティングディフュージョン(CFD)103の容量(CFD)に蓄積される。
第2の電圧信号(A2)は、リセットノイズ電圧信号(VN)と、リセット完了後から第2の電圧信号(A2)の読出しまでに受光素子(PD)102で収集されフローティングディフュージョン(CFD)103に輸送された光電荷による第2の光電荷電圧信号(VsigA2)、とからなる電圧信号(A2-A)に基づくものである。
そうすることで、メモリ列選択スイッチ(WS1)305と、画素信号保持メモリ選択用の選択スイッチ306(SW1~SW4)の一つ、例えば、選択スイッチ306(SW1)をONさせ、画素信号転送用の信号線313ー1を介してメモリセル309aを選択する。
その結果、電圧信号(A2-A)に応じた第2の電圧信号(A2)が、画素出力信号線117、画素信号転送用の信号線313-1を介して一つのメモリセル309aの画素信号保持容量(CAM)309に保持される。
メモリセル307aに書き込まれた第1の電圧信号(A1)をメモリセル309aに書き込まれた第2の電圧信号(A2)から引き算する事でリセットノイズ電圧信号(VN)がキャンセルされた電圧信号(VsigA2―VsigA1)を得ることが出来る。
本実施態様では、この信号の差分である電圧信号(VsigA2―VsigA1)は後述する方法で第1の電圧信号(A1)と第2の電圧信号(A2)をチップ外部に読み出した後に、チップ外部にて引き算を行って得る。
上記の一連の動作を繰り返し、複数のフレーム期間分、撮像を行い、アナログメモリアレイ301の全てのメモリセルに信号書込みを行う。
全てのメモリセルに信号書込みを行った後は、選択するメモリセルを冒頭のアドレスに戻してカメラから撮像停止のトリガ信号が入力されるまで上書き動作を繰り返しても良い。
撮像動作終了後、メモリセルに書き込まれた信号を後述する方法で読み出す。
次に、画素内相間二重サンプリング選択スイッチ(CDS)108がON状態で、画素内相間二重サンプリング迂回スイッチ(CDSb)109がOFF状態となっている場合について説明する。
リセット完了後に光センサ画素回路101aから画素内相間二重サンプリング回路101bに読み出す第1の電圧信号(B1)は、リセット完了後にフローティングディフュージョン(CFD)103に取り込まれたリセットノイズ電圧信号(VN)とリセット完了後から第1の電圧信号(B1)の読出しまでの所定の期間(t2-t1)に受光素子(PD)102で収集されフローティングディフュージョン(CFD)103に輸送された光電荷による第1の光電荷電圧信号(VsigB1)と、からなる電圧信号(B1-A)に基づくものである。
同時に、画素内相間二重サンプリングリセットパルス(ΦNS)を端子128に印加して画素内相間二重サンプリングリセットスイッチ(NS)112をON・OFFさせ、画素内相間二重サンプリングカップリング容量(CC)110の対向電極側、即ち、画素内相間二重サンプリングサンプルホールド用容量(CSH)111を画素内相間二重サンプリング回路リセット電圧(VR_CDS)にリセットする。
蓄積期間(t3―t2)中に発生した光電荷は、受光素子(PD)102のポテンシャル勾配201によってフローティングディフュージョン(CFD)103へドリフト輸送され、フローティングディフュージョン(CFD)103の容量(CFD)に蓄積される。
蓄積期間(t3―t2)中、第1選択トランジスタ(X1)106はOFF状態とすることで、第1ソースフォロワトランジスタ(SF1)105で消費される電力を抑制することが出来る。
蓄積期間(t3―t2)終了後、第2の電圧信号(B2)を光センサ画素回路101aから画素内相間二重サンプリング回路101bに、次のようにして読み出す。
この時、画素内相間二重サンプリングカップリング容量(CC)110と容量結合されている画素内相間二重サンプリングサンプルホールド容量(CSH)111の電圧は、画素内相間二重サンプリング回路リセット電圧(VR_CDS)を基準として、第1の電圧信号(B1)から第2の電圧信号(B2)の電圧変化分(VsigB2-VsigB1)とCC/(CC+CSH)の積だけ変動する。
同時に、メモリ列選択スイッチアレイ301a中にある4つのメモリ列選択スイッチ(WS1~WS4)うちの1つをON状態として該当のメモリ列を選択すると共に、信号保持メモリ選択用のパルス信号線(311~320)に所定の組み合わせのパルス信号を印加し、画素出力信号線117と1つのメモリセル、例えばメモリセル307aの画素信号保持容量(CAM)307を電気的に結合させる。
以上の一連の動作を繰り返し、複数のフレーム期間(ΦFrame)、撮像を行う。アナログメモリアレイ301内の全てのメモリセルに信号書込みを行う。
又、全てのメモリセルに信号書込み後に、選択するメモリセルを冒頭のアドレスに戻してカメラから撮像停止のトリガ信号が入力されるまで上書き動作を繰り返しても良い。
撮像動作終了後、各メモリセルに書き込まれた信号は後述する方法で読み出す。
リセットトランジスタ(R)104の端子123に画素リセット用のリセットパルス(ΦR)が印加され、光センサ画素回路101a中の画素を構成する受光素子(PD)102とフローティングディフュージョン(CFD)103とがリセットされる。
リセットトランジスタ(R)104がOFF状態となるリセット完了時(t1)にリセットノイズ電圧信号(VN)がフローティンディフュージョン(CFD)103に誘起される。
リセット完了後に読画素出力信号線(PIXEL_OUT)117上に読み出す第1の電圧信号(C1)は、前記リセットノイズ電圧信号(VN)と、リセット完了後から第1の電圧信号(C1)の読出しまでの所定の期間(t2-t1)に受光素子(PD)102で収集されフローティングディフュージョン(CFD)103に輸送された光電荷による第一光電荷電圧信号(VsigC1)と、からなる電圧信号(C1-A)に基づくものである。
同時に、4つのメモリ列選択スイッチ305(WS1~WS4)のうちの1つをON状態として該当のメモリ列を選択すると共に、信号保持メモリセル選択用のパルス信号線(311~320)に所定の組み合わせのパルス信号を印加し、画素出力信号線(PIXEL_OUT)117と1つのメモリセル307aの中の画素信号保持容量(CAM)307を電気的に結合させ、電圧信号(C1-A)に応じた第1の電圧信号(C1)を画素信号保持容量(CAM)307に転送させ、メモリ読出し回路302の駆動によって読み出されるまでの期間、保持する。
蓄積期間1(t3-t2)中に発生した光電荷は、図2に示されるポテンシャル区間201に示される受光素子(PD)102のポテンシャル勾配によりフローティングディフュージョン(CFD)103へドリフト輸送され、フローティングディフュージョン(CFD)103の容量(CFD)に蓄積される。
第2の電圧信号(C2)は、リセットノイズ電圧信号(VN)と、リセット完了後から第2の電圧信号(C2)の読出しまでに受光素子(PD)102で収集されフローティングディフュージョン(CFD)103に輸送された光電荷による第2の光電荷電圧信号(VsigC2)、とからなる電圧信号(C2-A)に基づくものである。
まず、第1選択トランジスタ(X1)106がOFF状態の場合には、画素選択第1パルス(ΦX1)が端子124に印加されて第1ソースフォロワトランジスタ(SF1)105がアクティブ状態となり、電圧信号(C2-A)に応じた第2の電圧信号(C2)が画素出力信号線(PIXEL_OUT)117に出力される。
同時に4つのメモリ列選択スイッチ305(WS1~WS4)の中の1つをON状態とさせて該当のメモリ列を選択すると共に、信号保持メモリ選択用のパルス信号線(311~320)に所定の組み合わせのパルス信号を印加し、画素出力信号線(PIXEL_OUT)117と1つのメモリセル、例えばメモリセル309aの画素信号保持容量(CAM)309を電気的に結合させ、電圧信号(C2-A)に応じた第1の電圧信号(C2)を画素信号保持容量(CAM)307に転送させ、メモリ読出し回路302の駆動によって読み出されるまでの期間、保持する。
以上の動作の説明からも明らかな通り、画素内相間二重サンプリング回路101bを迂回した場合には、フレーム期間(ΦFrame)中のパルス動作が最小に抑えられ、高速動作には好適である。さらに、1フレーム期間に3回以上画素信号を読みだす場合には、フレーム期間内をさらに短く分割することが出来、さらに高い時間分解能を得るのには好適である。
このように、従来例と比べて、本発明ではフレームレートと記録コマ数の優先度に応じて動作モードを切り替えることが出来る優勢がある。
画素内相間二重サンプリング 回路101bは、連続記録コマ数を優先したい場合に使用するとその効果を最大限に発揮できるので好ましい。
連続記録コマ数を優先したい場合として、具体的には、比較的長く継続して生じる現象である自動車エンジンの燃焼噴射や火花放電、インクジェットプリンタのインク吐出等の撮影等が挙げられる。
一方、回路101bを迂回するモード(B)は、撮影速度を優先したい場合に使用するとその効果を最大限に発揮できるので好ましい。
このモード(B)の使用は、具体的には、材料の破壊現象や、レーザーアブレーション、放電現象の撮影等の高速現象の撮影に適している。
例えば、回路101bを使用すると記録コマ数をより多くすることが出来るので、モード(A)で動作をさせておき、撮影対象の高速現象が起こるきっかけの時点からモード(B)でより高速に撮像するといったことができる。
この場合、アナログメモリアレイ301においては、回路101bを迂回してノイズがキャンセルされていない信号が保持される容量(CAM)Aと。回路101bを使用してノイズがキャンセルされた信号が保持される容量(CAM)Bと、が混在するので、保持されている信号を映像化する際には、以下の技術的手当てをする必要がある。
即ち、モードの切り替えを行う直前のフレーム番号を記録しておき、アナログメモリアレイ301に保持されている全ての信号を読み出してから、モード切替え前の信号はノイズがキャンセルされた信号として映像化し、モード切替え後の信号はフレーム毎に記録されていたノイズキャンセル用の第1の電圧信号(A1)と第2の電圧信号(A2)から引き算することでノイズキャンセルを行った後に映像化する。
本発明においては、メモリセル数としては10個以上とするのが好適であるが、記録コマ数を増やすためには40個以上が望ましく、より好適には128個以上が望ましい。さらに記録コマ数を増やすためには256個以上とするのが望ましい。
図6に示す例のイメージセンサ600は、複数の受光信号生成・保持要素601が二次元的に配列されている受光信号生成・保持要素アレイ602、メモリ選択回路603、画素駆動パルスバッファ列回路604、列選択回路605を備えている。
画素駆動パルスバッファ列回路604は、その信号伝達経路の下流側には出力バッファ606、信号出力端子607が設けられている。
受光信号生成・保持要素601は、光センサ画素回路部100とアナログメモリ回路部300で構成されている。
イメージセンサ600における信号出力期間では、各行の画素に対応するアナログメモリアレイ301毎に信号読出しを行う。すなわち、メモリ選択回路603を駆動させて、1画素行分のメモリ読出し回路302を選択し、メモリ読出し回路302の出力信号線302aと垂直信号線608とを結合する。
同様に、アナログメモリ301内の他の列を順次選択し、各列内のメモリセル全ての信号の読出しを行い、選択しているアナログメモリ301内の全てのメモリセルの信号をチップ外へ読み出す。
次いで、メモリ選択回路603を駆動させて次に読み出す画素列分のメモリセルを選択し、同様の動作を繰り返す。この信号読出し動作を全画素列分のメモリセルについて行う。
以上の動作によって全画素分のメモリセルの信号の読出しを行う。
(1)従来技術で必要であった、転送期間と転送ゲートをON・OFFするのに必要な画素駆動パルスのセトリング時間が不要となる。
(2)フレームレートの律則要因は受光素子における電荷収集・輸送時間のみとなり、125Mfpsとフレームレートを高速化することが出来る。
(3)画素内に最短距離で接続されたメモリに信号を読み出す構成であるため画素読出しに必要な回路駆動電流を低減することが出来る。また、画素駆動パルスが少ないことから画素駆動パルスに係る消費電力を低減することができる。そのため、低消費電力化された光センサの商品を市場に提供できる。
(4)画素駆動パルス種類が少ないことで、面積を犠牲にせずに画素駆動パルス回路を画素内乃至は画素ブロック内に配置することが出来る。
(5)容量密度の小さい完全空乏型受光素子とフローティングディフュージョンが結合されているため、電荷電圧変換ゲインに反比例するフローティングディフュージョン容量の増加を最小限に抑えられ、高い電荷電圧変換ゲインが得られると共に、フローティングディフュージョンのリセットノイズはキャンセルすることできるため、信号読出しノイズが小さい高感度な信号読出しを行える。
(5)受光素子とフローティングディフュージョンをリセット後にN回の信号を読出すことで、フローティングディフュージョンが飽和するまでの間ではあるが、さらに高速なフレームレートが得られる。
(6)変調された光照射と同期した信号読出しを行うことで、光飛行時間型の距離イメージングや蛍光寿命イメージングに適用することが出来る。
高速現象の可視化が可能なので、
・材料破壊現象の観察:破壊過程の解析と、材料の改良
・マイクロバブルの観察
・放電現象の観察
・がん細胞治療の観察
・インクジェットの観察
・MEMS駆動の観察
・衝撃波の観察
・エンジンルームへの燃料噴霧の観察
・レーザービーム加工
など、
いずれも2次元画像で連続したフレームの映像情報が必要であり、この要求に適した本発明に係わる高速カメラが有用である。
この他、本発明は、2次元画像で距離や生体反応のイメージングが必要な距離イメージングやバイオイメージングの分野で使用される高時間分解能なカメラにも有用である。
101a 光センサ画素回路
101b 画素内相間二重サンプリング回路 (In-pixel CDS)
102 フォトダイオード(PD)
103 フローティングディフュージョン(CFD)
104 リセットトランジスタ(R)
105 第1ソースフォロワトランジスタ(SF1)
106 第1選択トランジスタ(X1)
107 第1電流源トランジスタ(CS1)
108 画素内相間二重サンプリング選択スイッチ(CDS)
109 画素内相間二重サンプリング迂回スイッチ(CDSb)
110 画素内相関二重サンプリングカップリング容量(CC)
111 画素内相関二重サンプリングサンプルホールド容量(CSH)
112 画素内相間二重サンプリングリセットトランジスタ(NS)
113 第2ソースフォロワトランジスタ(SF2)
114 第2選択トランジスタ(X2)
115 第2選択トランジスタ(X2’)
116 第2電流源トランジスタCS2
117 画素出力信号線(PIXEL_OUT)
118 画素リセット電圧(VR_FD)印加用の電気的端子
119a,119b 電源電圧(AVDD)印加用の電気的端子
120 画素内相間二重サンプリング回路リセット電圧(VR_CDS)用の電気的端子
121 第1電流源バイアス電圧(VB1)印加用の電気的端子
122 第2電流源バイアス電圧(VB2)印加用の電気的端子
123 画素リセットパルス(ΦR)印加用の電気的端子
124 画素選択第1パルス(ΦX1)印加用の電気的端子
125 画素内相間二重サンプリング回路選択パルス(ΦCDS)入力用の電気的端子
126 画素内相間二重サンプリング回路バイパスパルス(ΦCDSb)入力用の電気的端子
127 画素選択第2パルス(ΦX2)入力用の電気的端子
128 画素内相間二重サンプリングリセットパルス(ΦNS)
201 完全空乏型受光素子(PD)102のポテンシャル区分
202 フローティングディフュージョン(CFD)103の容量(CFD)のポテンシャル区分
300 アナログメモリ回路部
301 アナログメモリアレイ(Analog Memories:4H x20V)
301a メモリセル行選択スイッチアレイ
302 メモリ読出し回路(Memory Readout Circuit)
302a 出力信号線
303,304 画素信号保持メモリアレイ
305 メモリセル行選択スイッチ(WS1~WS4)(1~4)
306 画素信号保持メモリ選択用スイッチ(SW1~SW4)
307 画素信号保持用容量(CAM)
307a メモリセル
308 画素信号保持メモリ選択用スイッチ
309 画素信号保持用容量
310 信号保持用メモリセル行選択用パルス信号線(1~4)
311,312~320 信号保持用メモリセル選択用パルス信号線(1~4)
313 画素信号転送用の信号線(1~4)
600 イメージセンサ
601 受光信号生成・保持要素
602 受光信号生成・保持要素アレイ
603 メモリ選択回路
604 画素駆動パルスバッファ列回路
605 列選択回路
606 出力バッファ
607 信号出力端子
608 垂直信号線
Claims (7)
- 半導体接合部が完全に空乏化されかつ電子のポテンシャルカーブが前記フローティングディフュージョン方向に向かって負の傾斜をしており、その負の傾斜状態のままで前記フローティングディフュージョンの電子ポテンシャル・ウェルの最上位に繋がっている受光素子で受光し、該受光に応じて前記受光素子内部に発生する電子を前記ポテンシャルカーブに従って移送して前記ポテンシャル・ウェルに蓄積する工程を、前記受光の期間内に設けた同一フレーム期間中に、順次、少なくとも2回行う、ことを特徴とする光センサの信号読出方法。
- 前記蓄積する工程における蓄積期間が、1μs以下である請求項1に記載の光センサの信号読出方法。
- 受光素子と該受光素子に電気的に直結され、該受光素子に入力する光によって発生する電荷を蓄積するフローティングディフュージョンと画素信号出力線、を有し、前記画素信号出力線に信号読出し経路が接続されており、
前記受光素子の容量(CPD)と前記フローティングディフュージョンの容量(CFD)とが、
0.0008 ≦(CPD)/(CFD)≦ 0.8・・・・・・・・・・・・(1)
4.0×10-18 F ≦(CPD)≦ 4.0×10-16 F・・・・・(2)
5.0×10-16 F≦(CFD)≦ 5.0×10-15 F・・・・・・(3)
の関係にあり、
前記受光素子の半導体接合部は完全空乏化されかつ電子のポテンシャルカーブが前記フローティングディフュージョン方向に向かって負の傾斜をしており、その負の傾斜状態のままで前記フローティングディフュージョンの電子ポテンシャル・ウェルの最上位に繋がっている、
ことを特徴とする光センサ。 - (1)受光素子と該受光素子に電気的に直結され、該受光素子に入力する光によって発生する電荷を蓄積するフローティングディフュージョンとを備え、
前記受光素子は、半導体接合部が完全に空乏化されかつ前記フローティングディフュージョン方向に向かって負の傾斜をしており、その負の傾斜状態のままで前記フローティングディフュージョンの電子ポテンシャル・ウェルの最上位に繋がっている電子のポテンシャルカーブを有し、
時間軸上で択一的に使用される二つの出力系統を有している光センサ画素回路;
一方の出力系統から出力される、光照射により前記受光素子内に生じた光電荷量に基づいた第一の出力(a1)と第二の出力(b1)とに基づいてノイズキャンセレーションして信号(ab1)を出力する画素内相関二重サンプリング回路;
と、を備えた光センサ画素回路部:
(2)前記信号(ab1)、及び他方の出力系統から出力される第一の出力(a2)と第二の出力(b2)
との何れかの信号を保持するメモリセルの複数を行列配置したアナログメモリアレイ;
何れかのメモリセル配設行を選択するためのメモリセル行選択スイッチアレイ;
何れかのメモリセルに保持されている信号を読出すためのメモリ読出し回路;
と、を備えたアナログメモリ回路部:
を具備することを特徴とする光エリアセンサ。 - 前記受光素子の容量(CPD)と前記フローティングディフュージョンの容量(CFD)とが、
0.0008 ≦(CPD)/(CFD)≦ 0.8・・・・・・・・・・・・・(1)
4.0×10-18 F ≦(CPD)≦ 4.0×10-16 F・・・・・(2)
5.0×10-16 F≦(CFD)≦ 5.0×10-15 F・・・・・・(3)
の関係にある請求項4に記載の光エリアセンサ。 - 前記光センサ画素回路部と前記アナログメモリ回路部とは隣接して同一プレナー上に配置されている請求項4に記載の光エリアセンサ。
- 前記光センサ画素回路部と前記アナログメモリ回路部とは隣接して積層配置されている請求項4に記載の光エリアセンサ。
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WO2022118538A1 (ja) * | 2020-12-01 | 2022-06-09 | ソニーセミコンダクタソリューションズ株式会社 | 受光素子及び電子機器 |
WO2023062947A1 (ja) * | 2021-10-15 | 2023-04-20 | ソニーセミコンダクタソリューションズ株式会社 | 固体撮像素子、撮像装置、および、固体撮像素子の制御方法 |
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KR20210039468A (ko) | 2021-04-09 |
US20210217801A1 (en) | 2021-07-15 |
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JPWO2020039531A1 (ja) | 2021-08-26 |
TW202010145A (zh) | 2020-03-01 |
JP7333562B2 (ja) | 2023-08-25 |
KR102482883B1 (ko) | 2022-12-29 |
TWI822697B (zh) | 2023-11-21 |
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