WO2020037733A1 - 一种阵列基板及其制造方法 - Google Patents

一种阵列基板及其制造方法 Download PDF

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Publication number
WO2020037733A1
WO2020037733A1 PCT/CN2018/105244 CN2018105244W WO2020037733A1 WO 2020037733 A1 WO2020037733 A1 WO 2020037733A1 CN 2018105244 W CN2018105244 W CN 2018105244W WO 2020037733 A1 WO2020037733 A1 WO 2020037733A1
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Prior art keywords
film layer
scattering film
array substrate
layer
scattering
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PCT/CN2018/105244
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English (en)
French (fr)
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吴豪旭
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深圳市华星光电技术有限公司
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Publication of WO2020037733A1 publication Critical patent/WO2020037733A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods

Definitions

  • the present application relates to the field of display technology, and in particular, to an array substrate and a manufacturing method thereof.
  • the display panel along with the high-generation thin film transistor liquid crystal display TFT-LCD (thin With the development of film transistor-liquid crystal display, the display panel has evolved toward large size, high picture quality and high resolution. With the increasing size, the number and length of metal wirings have increased significantly. In order to increase the visual and appearance effects of the display panel, narrow borders and even four-sided borderless technologies are currently being developed. However, this method, like the array substrate side facing outward, may have defects such as light leakage at the edges and reduced contrast.
  • a liquid crystal display product is designed and actually produced with an array substrate side facing outward, but when the array substrate side is facing outward, the metal gate (Gate) wiring is mainly made of Cu / Mo, Mo / Al, Cu / MoTi Highly reflective metals such as, Cu / Ti, the reflectivity of their metal parts are very high.
  • the reflectivity of general metal electrodes for visible light with a wavelength of 400-700nm has an average reflectance of greater than 40%, and strong reflections seriously affect the viewing effect of the human eye.
  • the present application provides an array substrate and a manufacturing method thereof, which can reduce the reflectivity of a metal electrode on the array substrate, and can solve the technical problem that the reflectivity of the metal electrode of the array substrate is too high.
  • an array substrate including:
  • a transparent substrate which is a glass substrate
  • a scattering film layer is disposed on the transparent substrate, the scattering film layer includes a first scattering film layer and a second scattering film layer, and the first scattering film layer is disposed between the transparent substrate and the gate
  • the second scattering film layer is disposed between the source electrode, the drain electrode, and the active layer, and a surface of the scattering film layer has a specific irregularly shaped surface morphology.
  • the material of the scattering film layer is molybdenum oxide or its doped metal oxide material.
  • the thickness of the scattering film layer is 35 nm to 75 nm.
  • an array substrate including:
  • a scattering film layer is disposed on the transparent substrate, the scattering film layer includes a first scattering film layer and a second scattering film layer, and the first scattering film layer is disposed between the transparent substrate and the gate
  • the second scattering film layer is disposed between the source electrode, the drain electrode, and the active layer, and a surface of the scattering film layer has a specific irregularly shaped surface morphology.
  • the material of the scattering film layer is molybdenum oxide or its doped metal oxide material.
  • the thickness of the scattering film layer is 35 nm to 75 nm.
  • the present application provides a method for manufacturing an array substrate, including the following steps:
  • the first scattering film layer is disposed between the transparent substrate and the gate, and the second scattering film layer is disposed between the source electrode, the drain electrode, and the active layer.
  • the first scattering film layer and the second scattering film layer constitute a scattering film layer, and the surface of the scattering film layer has a specific irregularly shaped surface morphology.
  • a thickness of the scattering film layer is 35 nm to 75 nm.
  • the steps of preparing the first scattering film layer and preparing the second scattering film layer specifically include:
  • the thickness of the thin film is 35 nm to 75 nm.
  • a material of the thin film is molybdenum oxide or a doped metal oxide material thereof.
  • the thin film is directly formed into a film by a physical vapor deposition method.
  • a dry etching method is used to form a specific irregular morphology interface on the surface of the film.
  • the polystyrene ball film layer remaining on the surface of the film is removed by a wet chemical cleaning method.
  • a scattering film layer composed of molybdenum oxide or its doped metal oxide material is provided on an array substrate, and it is prepared as a specific irregular metal by a dry etching method.
  • the oxide morphology structure can enhance the scattering and absorption of visible light sources, thereby reducing the reflectivity of the metal electrodes on the array substrate, providing contrast and viewing visual effects, saving costs and improving product competitiveness.
  • FIG. 1 is a schematic cross-sectional structure diagram of an array substrate according to an embodiment of the present application.
  • FIG. 2 is a flowchart of a method for manufacturing an array substrate according to an embodiment of the present application
  • FIG. 3 is a flowchart of a method for manufacturing a first scattering film layer according to an embodiment of the present application.
  • FIG. 4 is a schematic diagram of a method for manufacturing a first scattering film layer according to an embodiment of the present application
  • FIG. 5 is a schematic diagram of another method for manufacturing a first scattering film layer according to an embodiment of the present application.
  • FIG. 1 is a schematic cross-sectional view of an array substrate 100 according to an embodiment of the present application.
  • the array substrate 100 includes a transparent substrate 101, a scattering film layer 10, and a gate 103, a gate insulating layer 104, an active layer 106, a source 107, and a drain 108 on a side of the transparent substrate 101.
  • the transparent substrate 101 may be a glass substrate, and has characteristics of high insulation and light transmission.
  • the scattering film layer 10 includes a first scattering film layer 102 and a second scattering film layer 105.
  • the first scattering film layer 102 is disposed on a surface of the transparent substrate 101, and the gate electrode 103 is located on the first scattering film.
  • the gate insulating layer 104 is located on the first scattering film layer 101 and covers the gate 103, and the active layer 106 is located on the gate insulating layer 104 and is located on the gate Above 103, the second scattering film layer 105 is disposed on the gate insulating layer 104, and the source electrode 107 and the drain electrode 108 are respectively located on the second scattering film layer 105 and cover a part of the active layer 106.
  • the gate 103 and the gate insulating layer 104 are not directly in contact with the transparent substrate 101, so that the adhesion between the gate 103, the gate insulating layer 104, and the transparent substrate 101 is enhanced on the one hand Adhesion, on the other hand, reduces the reflectivity of the gate 103, prevents the metal elements in the gate 103 from diffusing into the transparent substrate, and further improves the performance of the array substrate.
  • a plurality of gate scanning lines (not shown in the figure) and a plurality of source data lines (not shown in the figure) crossing each other are formed on the transparent substrate 101, and a thin film is provided at the intersection position of the two.
  • Transistor Thin Film Transistor, TFT.
  • the gate 103 is connected to the gate scan line (not shown)
  • the source 107 is connected to the source data line (not shown)
  • the drain 108 is connected to Pixel electrodes (not shown) are connected to control the opening and closing of the pixels.
  • the gate insulating layer 104 is located between the gate 103 and the active layer 106. Its function is to prevent the conduction of the gate 103 and the active layer 106, and to play an insulating role. The effect of static electricity is very important.
  • the main materials of the gate 103, the source 107, and the drain 108 are metals such as Cu / Mo, Mo / Al, Cu / MoTi, and Cu / Ti.
  • the scattering film layer 10 is disposed on the transparent substrate 101.
  • the scattering film layer 10 includes a first scattering film 102 and a second scattering film layer 105.
  • the first scattering film layer 102 and the second scattering film The surface of the film layer 105 has an irregularly shaped surface morphology and has a certain roughness.
  • the first scattering film layer 102 is disposed between the transparent substrate 101 and the grid electrode 103.
  • the first scattering film layer 102 completely covers the grid electrode 103. Therefore, when light from a visible light source passes through the grid electrode, When the metal part of the electrode 103 generates reflection, it can enter the first scattering film layer 102, and the first scattering film layer 102 plays a role of scattering and absorbing light entering the inside thereof.
  • the second scattering film layer 105 is disposed between the source electrode 107, the drain electrode 108, and the gate insulating layer 104. Similarly, when the light of a visible light source is between the metal portion of the source electrode 107 and the drain electrode When the metal part of 108 is reflected, it can enter the second scattering film layer 105, and the second scattering film layer 105 scatters and absorbs the light entering the inside.
  • the material of the scattering film layer 10 is molybdenum oxide or its doped metal oxide material or an intermetallic compound composed of molybdenum and other metals.
  • the material has low reflectivity and the material is environmentally friendly.
  • the substrate 100 performs the deposition process of the scattering film layer 10, it can reduce the pollution to the equipment, thereby improving the overall performance of the product.
  • the thickness of the scattering film layer 10 is 35 nm to 75 nm.
  • the reflectivity of the single scattering film layer is about 4.2%, and the scattering film layer 10 The highest scattering and absorption of light, the reflectivity of the metal electrode portions of the gate 103, source 107, and drain 108 can be minimized, and the effect is the best.
  • FIG. 2 is a flowchart of a method for manufacturing an array substrate according to an embodiment of the present application, which is specifically:
  • a gate 103, a gate insulating layer 104, and an active layer 106 are sequentially formed on the first scattering film layer 102 through a patterning process, and the first scattering film layer 102 is formed to include the A pattern of the gate electrode 103, a gate insulating layer 104 is formed on the gate electrode 103 through a patterning process, and the active layer 106 is formed on the gate insulating layer 104;
  • a source electrode 107 and a drain electrode 108 are prepared on the second scattering film layer 105, and a pattern including the source electrode 107 and the drain electrode 108 is formed on the second scattering film layer 105 by a patterning process.
  • FIG. 3 is a flowchart of a method for manufacturing the first scattering film layer 102 according to an embodiment of the present application.
  • 4 is a schematic diagram of a manufacturing method of a first scattering film layer 102 provided in an embodiment of the present application. The steps of the manufacturing method are:
  • a transparent substrate 101 is provided, and a thin film 102 'is formed on the surface of the transparent substrate 101.
  • the material of the transparent substrate 101 may be glass, and the material of the thin film 102' is molybdenum oxide or its doped metal oxide. Material or molybdenum and other metals constitute an intermetallic compound, and the thin film 102 'is directly formed into a film by a physical vapor deposition method, such as vacuum evaporation, sputtering, and the like.
  • the thin film 102 'is formed by physical vapor deposition (Physical A Vapor Deposition (PVD) device is directly deposited on the transparent substrate 101.
  • PVD Physical A Vapor Deposition
  • the thickness of the formed thin film 102 ′ is set to 35 nm to 75 nm.
  • the prepared first scattering film layer 102 has the highest projection and absorption of light, and the reflectance of the scattering film layer is about 4.2%.
  • the reflectivity of the metal electrode portions of the gate electrode 103, the source electrode 107, and the drain electrode 108 is reduced to a minimum, and a good effect can be achieved.
  • S202 uniformly forming a polystyrene ball film layer (PS) on the film 102 ' Sphere Film) 1021, the particle size of the polystyrene balls in the polystyrene ball film layer 1021 is controllable, so the particle diameters dispersed on the film 102 'are different, and the thickness of the contact surface of different spheres is also different.
  • a dry etching technique is used to prepare a surface with different irregular shapes on the surface of the film 102 '.
  • a specific irregularly shaped surface morphology is formed on the surface of the thin film 102 '.
  • a dry etching technique is used to place a specific gas, such as oxygen, helium, etc.
  • a specific gas such as oxygen, helium, etc.
  • oxygen can be used as the dry etching gas, which has lower cost and high economy.
  • FIG. 5 is a schematic diagram of a method for manufacturing a first scattering film layer provided in an embodiment of the present application.
  • the sphere diameter of the polystyrene sphere layer 1021 is large, the irregularly-shaped surface morphology is formed. smooth.
  • FIG. 5 is a schematic diagram of forming a first scattering film layer provided by an embodiment of the present application.
  • the particle size of the sphere of the polystyrene sphere layer 1021 is small, for example, 1 ⁇ m, the formed The surface shape of the regular shape is rough.
  • S205 Apply a graphene solution on the surface of the final irregularly formed surface to form a graphene film layer 1022.
  • the irregularly shaped surface is uniform.
  • the strong light absorption of graphene can be used to increase the anti-reflection effect of the special structure of the oxide material; on the other hand, the electric field effect between graphene and Cu surface can enhance graphene in the visible light band Light absorption effect.
  • the first scattering film layer 102 is finally prepared.
  • step S40 For a specific method for preparing the second scattering film layer 105 on the gate insulating layer 104 in step S40, refer to the method for preparing the first scattering film layer 102 on the transparent substrate as described in step S20 in the above embodiment. Repeat them one by one.
  • a scattering film layer composed of molybdenum oxide or its doped metal oxide material is provided on the array substrate, and it is prepared into a specific irregular metal oxide morphology structure by a dry etching method. It can strengthen the scattering and absorption of visible light sources, thereby reducing the reflectivity of metal electrodes on the array substrate, providing contrast and viewing visual effects, saving costs and improving product competitiveness.

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Abstract

本申请提供一种阵列基板及其制造方法，阵列基板包括：透明基板、栅极、栅极绝缘层、有源层、源极及漏极；散射膜层，包括设置于透明基板与栅极之间的第一散射膜层及设置于源极、漏极与有源层之间的第二散射膜层，通过干法刻蚀将其制备为不规则金属氧化物形貌结构，加强对光源的散射和吸收，降低阵列基板金属电极的反射。

Description

一种阵列基板及其制造方法 技术领域
本申请涉及显示技术领域，尤其是涉及一种阵列基板及其制造方法。
 背景技术
在液晶显示面板中，随着高世代薄膜晶体管液晶显示器TFT-LCD（thin film transistor-liquid crystal display）的发展，显示面板向大型化、高画质、高分辨率演变。而随着尺寸越来越大，金属布线数量及长度均有大幅度增多。为了增加显示面板的视觉和外观效果，目前开发窄边框、甚至四边无边框技术，但此种方法与阵列基板侧朝外一样，可能存在边缘漏光、对比度降低的缺陷。现有技术以阵列基板侧朝外的方案设计并实际产出液晶显示产品，但阵列基板侧朝外时，其金属栅极（Gate）布线主要材质为Cu/Mo、Mo/Al、Cu/MoTi、Cu/Ti等强反射的金属，其金属部分的反射率都很高。一般金属电极的反射率对于波长为400-700nm的可见光，其平均反射率大于40%，强烈的反光严重影响人眼观赏的效果。
而以低反射金属膜层作为阻挡层降低反射率或通过贴附低反射膜偏光片来减少金属反光等方案，会相对增加生产工艺成本。
因此，需要提供一种新的可降低阵列基板上金属电极的反射率的阵列基板及其制造方法，来解决上述问题。
 技术问题
本申请提供一种阵列基板及其制造方法，可降低阵列基板上金属电极的反射率，能够解决阵列基板金属电极的反射率过高的技术问题。
 技术解决方案
为解决上述问题，本申请提供的技术方案如下：
本申请提供一种阵列基板，包括：
透明基板，所述透明基板为玻璃基板；
位于所述透明基板一侧的栅极、栅极绝缘层、有源层、源极及漏极；
散射膜层，设置于所述透明基板上，所述散射膜层包括第一散射膜层及第二散射膜层，所述第一散射膜层设置于所述透明基板与所述栅极之间，所述第二散射膜层设置于所述源极、漏极与所述有源层之间，所述散射膜层表面为特定的不规则形状的表面形态。
在本申请所述的阵列基板中，所述散射膜层的材料为氧化钼或其掺杂类金属氧化物材料。
在本申请所述的阵列基板中，所述散射膜层的厚度为35nm~75nm。
本申请提供一种阵列基板，包括：
透明基板；
位于所述透明基板一侧的栅极、栅极绝缘层、有源层、源极及漏极；
散射膜层，设置于所述透明基板上，所述散射膜层包括第一散射膜层及第二散射膜层，所述第一散射膜层设置于所述透明基板与所述栅极之间，所述第二散射膜层设置于所述源极、漏极与所述有源层之间，所述散射膜层表面为特定的不规则形状的表面形态。
在本申请所述的阵列基板中，所述散射膜层的材料为氧化钼或其掺杂类金属氧化物材料。
在本申请所述的阵列基板中，所述散射膜层的厚度为35nm~75nm。
本申请提供一种阵列基板的制造方法，包括以下步骤：
S10：提供一透明基板；
S20：在所述透明基板上制备第一散射膜层；
S30：在所述第一散射膜层上依次形成栅极、栅极绝缘层、有源层；
S40：在所述栅极绝缘层上制备第二散射膜层；
S50：在所述第二散射膜层上形成源极及漏极。
其中，所述第一散射膜层设置于所述透明基板与所述栅极之间，所述第二散射膜层设置于所述源极、漏极与所述有源层之间，所述第一散射膜层与所述第二散射膜层构成散射膜层，所述散射膜层表面为特定的不规则形状的表面形态。
在本申请所述的阵列基板的制造方法中，所述散射膜层的厚度为35nm~75nm。
在本申请所述的阵列基板的制造方法中，所述制备第一散射膜层及制备第二散射膜层的步骤，具体包括：
S201：在所述透明基板及所述栅极绝缘层表面形成一层薄膜；
S202：在所述薄膜上均匀涂覆形成一层聚苯乙烯球膜层；
S203：在所述薄膜表面形成特定的不规则形状的表面形态；
S204：清除残余在所述薄膜表面的所述聚苯乙烯球膜层；
S205:在所述形成的不规则形状表面涂覆石墨烯溶液，形成石墨烯膜层。
在本申请所述的阵列基板的制造方法中，所述薄膜的厚度为35nm~75nm。
在本申请所述的阵列基板的制造方法中，所述薄膜的材料为氧化钼或其掺杂类金属氧化物材料。
在本申请所述的阵列基板的制造方法中，所述薄膜采用物理气相沉积法直接成膜。
在本申请所述的阵列基板的制造方法中，利用干法刻蚀方法在所述薄膜表面形成特定的不规则形貌界面。
在本申请所述的阵列基板的制造方法中，采用湿式化学清洗法清除残余在所述薄膜表面的所述聚苯乙烯球膜层。
 有益效果
本申请的有益效果：本申请通过在阵列基板上设置一层由氧化钼或其掺杂类金属氧化物材料组成的散射膜层，并通过干法刻蚀方法将其制备为特定的不规则金属氧化物形貌结构，能够加强对可见光源的散射和吸收，从而降低阵列基板上金属电极的反射率，提供对比度和观赏视觉效果，节省成本，提升了产品竞争力。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的一种阵列基板的剖面结构示意图。
图2为本申请实施例提供的一种阵列基板的制造方法流程图；
图3为本申请实施例提供的一种第一散射膜层的制造方法流程图。
图4为本申请实施例提供的一种第一散射膜层的制造方法示意图；
图5为本申请实施例提供的另一种第一散射膜层的制造方法示意图。
本申请的实施方式
以下各实施例的说明是参考附加的图示，用以实例本申请可用以实施的特定实施例。本申请所提到的方向用语，例如[上]、[下 ]、[前]、 [后]、 [左]、 [右]、 [内]、 [外]、 [侧面 ]、[竖直]、[水平]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。在图中，结构相似的单元是用以相同标号表示。
如图1所示为本申请实施例提供的一种阵列基板100的剖面示意图。参考图1，阵列基板100包括透明基板101、散射膜层10以及位于所述透明基板101一侧的栅极103、栅极绝缘层104、有源层106、源极107、漏极108。其中，所述透明基板101可以为玻璃基板，具有绝缘性和透光性高的特性。所述散射膜层10包括第一散射膜层102、第二散射膜层105，所述第一散射膜层102设置于所述透明基板101表面，所述栅极103位于所述第一散射膜层102上，所述栅极绝缘层104位于所述第一散射膜层101上并覆盖所述栅极103，所述有源层106位于所述栅极绝缘层104上并位于所述栅极103上方，所述第二散射膜层105设置于所述栅极绝缘层104上，所述源极107、漏极108分别位于所述第二散射膜层105上并覆盖部分有源层106。因此，所述栅极103与所述栅极绝缘层104并未直接与所述透明基板101接触，这样一方面增强了所述栅极103、栅极绝缘层104与透明基板101之间的粘附力，另一方面，降低了所述栅极103的反射率、避免了所述栅极103中金属元素扩散到所述透明基板中，进一步提高了阵列基板的性能。
同时，在该透明基板101上形成设置彼此交叉的多条栅极扫描线(图中未示出)和多条源极数据线(图中未示出)，在二者的交叉位置设置有薄膜晶体管 (Thin Film Transistor，TFT)。所述栅极103与所述栅极扫描线(图中未示出)相连接，所述源极107与所述源极数据线(图中未示出)相连接，所述漏极108与像素电极(图中未示出)相连接，用于控制像素的打开和闭合。所述栅极绝缘层104位于所述栅极103与有源层106中间，其作用为防止栅极103和有源层106的导通，起到绝缘的作用，对于薄膜晶体管的稳定性及防静电效果非常重要。所述栅极103、源极107、漏极108的主要材质为Cu/Mo、Mo/Al、Cu/MoTi、Cu/Ti等金属。
所述散射膜层10，设置于所述透明基板101上，所述散射膜层10包括第一散射膜102及第二散射膜层105，所述第一散射膜层102与所述第二散射膜层105的表面均为不规则形状的表面形态，具有一定的粗糙度。所述第一散射膜层102设置于所述透明基板101与所述栅极103之间，所述第一散射膜层102完全遮盖所述栅极103，因此当可见光源的光线在所述栅极103金属部分产生反射时，其能够进入到所述第一散射膜层102，所述第一散射膜层102对进入到其内部的光线起到散射和吸收的作用。所述第二散射膜层105设置于所述源极107、漏极108与所述栅极绝缘层104之间，同理，当可见光源的光线在所述源极107的金属部分与漏极108的金属部分发生反射时，其能够进入到所述第二散射膜层105，所述第二散射膜层105对进入到其内部的光线发生散射和吸收。
所述散射膜层10的材料为氧化钼或其掺杂类金属氧化物材料或钼与其他金属组成的金属间化合物等，其材质反射率较低，同时该材质为环保材料，当所述阵列基板100在进行所述散射膜层10的沉积工序时，可以减少对设备的污染，进而提高产品的整体性能。
所述散射膜层10的厚度为35nm~75nm，优选的，当所述散射膜层10的厚度为55nm时，单层所述散射膜层的反射率约为4.2%，所述散射膜层10对光线的散射和吸收达到最高，所述栅极103、源极107、漏极108的金属电极部分的反射率可降到最低，效果最好。
如图2所示为本申请实施例提供的一种阵列基板的制造方法流程图，具体为：
S10：提供一透明基板101；
S20：在所述透明基板101上制备第一散射膜层102，所述第一散射膜层102表面为不规则形状的表面形态；
S30：在所述第一散射膜层102上依次通过构图工艺形成栅极103、栅极绝缘层104、有源层106，通过构图工艺在所述第一散射膜层102上形成包含有所述栅极103的图案，在所述栅极103上通过构图工艺形成栅极绝缘层104，在所述栅极绝缘层104上形成所述有源层106；
S40：在所述栅极绝缘层104上制备第二散射膜层105，所述第二散射膜层105表面为不规则形状的表面形态；
S50：在所述第二散射膜层105上制备源极107、漏极108，通过构图工艺在所述第二散射膜层105上形成包含有所述源极107、漏极108的图案。
步骤S20中在透明基板上制备第一散射膜层的具体方法如下，请见图3与图4，图3为本申请实施例提供的一种第一散射膜层102的制造方法流程图，图4为本申请实施例提供的一种第一散射膜层102的制造方法示意图，制造方法的步骤为：
S201：提供一透明基板101，在所述透明基板101表面形成一层薄膜102＇，所述透明基板101的材料可为玻璃，所述薄膜102＇的材料为氧化钼或其掺杂类金属氧化物材料或钼与其他金属组成金属间化合物，所述薄膜102＇采用物理气相沉积法直接成膜，如真空蒸镀、溅镀等。优选的，所述薄膜102＇通过物理气相沉积(Physical Vapor Deposition，PVD)设备直接在所述透明基板101上沉积形成。优选的，将形成的所述薄膜102＇的厚度设置为35nm~75nm。优选的，当制备的所述薄膜102＇的厚度为55nm时，制备成的所述第一散射膜层102对光线的投射和吸收达到最高，所述散射膜层的反射率约为4.2%，所述栅极103、源极107、漏极108的金属电极部分的反射率降到最低，可达到良好的效果。
S202：在所述薄膜102＇上均匀涂覆形成一层聚苯乙烯球膜层（PS Sphere Film）1021，所述聚苯乙烯球膜层1021中的聚苯乙烯球粒径可控，因此分散在所述薄膜102＇上的粒径不同，不同球体接触界面厚度也随之不同，为后续步骤S203利用干法刻蚀技术在所述薄膜102＇表面形成不同的不规则形状的表面形态做准备。
S203：在所述薄膜102＇表面形成特定的不规则形状的表面形态，根据所述薄膜102＇的不均匀特性，采用干法刻蚀技术，将特定气体，例如氧气、氦气等，置于低压状态下，利用所述薄膜102＇表面的所述聚苯乙烯球膜层1021间的接触界面及球体的本身厚度的区别，以去除部分所述薄膜102＇，在其表面形成特定的不规则形状的表面形态。优选的，可选用氧气作为干法刻蚀气体，成本较低，经济性高。
所述聚苯乙烯球膜层1021的球径的大小影响制备的所述第一散射膜层102表面不规则形状的表面形态的粗糙度。如图5所示为本申请实施例提供的一种第一散射膜层的制造方法示意图，当所述聚苯乙烯球层1021的球体粒径较大时，形成的不规则形状的表面形态较光滑。如图5所示为本申请实施例提供的一种形成第一散射膜层的示意图，当所述聚苯乙烯球层1021的球体粒径较小时,例如为1微米时，形成的所述不规则形状的表面形态较粗糙。
S204：清除残余在所述薄膜102＇表面的所述聚苯乙烯球膜层1021，通过湿式化学清洗法（RCA cleaning）将残余在所述薄膜102＇表面的聚苯乙烯球膜层1021清除，利用液状酸碱溶剂与去离子水之混合液之后清洗所述薄膜102＇表面，之后对所述薄膜102＇表面加以干燥，得到最终具有不规则形状的表面形态。
S205：在所述形成的最终不规则形状的表面形态表面涂覆石墨烯溶液，形成石墨烯膜层1022，为方便后续制程的制备及反射率的进一步降低，在该不规则形状的表面上均匀涂覆一层石墨烯溶液，一方面可利用石墨烯的强吸光性，增加氧化物材料特殊结构的减反效果；另一方面，石墨烯与Cu表面的电场作用，可增强石墨烯在可见光波段的吸光作用。
经过以上步骤，最终制备得到所述第一散射膜层102。
步骤S40在所述栅极绝缘层104上制备第二散射膜层105的具体方法参照上述实施例中步骤S20所描述的在所述透明基板上制备第一散射膜层102的方法，在此不再一一赘述。
本申请通过在阵列基板上设置一层由氧化钼或其掺杂类金属氧化物材料组成的散射膜层，并通过干法刻蚀方法将其制备为特定的不规则金属氧化物形貌结构，能够加强对可见光源的散射和吸收，从而降低阵列基板上金属电极的反射率，提供对比度和观赏视觉效果，节省成本，提升了产品竞争力。
综上所述，虽然本申请已以优选实施例揭露如上，但上述优选实施例并非用以限制本申请，本领域的普通技术人员，在不脱离本申请的精神和范围内，均可作各种更动与润饰，因此本申请的保护范围以权利要求界定的范围为准。

Claims (14)

  1. 一种阵列基板，包括：
    透明基板，所述透明基板为玻璃基板；
    位于所述透明基板一侧的栅极、栅极绝缘层、有源层、源极及漏极；
    散射膜层，设置于所述透明基板上，所述散射膜层包括第一散射膜层及第二散射膜层，所述第一散射膜层设置于所述透明基板与所述栅极之间，所述第二散射膜层设置于所述源极、漏极与所述有源层之间，所述散射膜层表面为特定的不规则形状的表面形态。
  2. 根据权利要求1所述的阵列基板，其中，所述散射膜层的材料为氧化钼或其掺杂类金属氧化物材料。
  3. 根据权利要求2所述的阵列基板，其中，所述散射膜层的厚度为35nm~75nm。
  4. 一种阵列基板，包括：
    透明基板；
    位于所述透明基板一侧的栅极、栅极绝缘层、有源层、源极及漏极；
    散射膜层，设置于所述透明基板上，所述散射膜层包括第一散射膜层及第二散射膜层，所述第一散射膜层设置于所述透明基板与所述栅极之间，所述第二散射膜层设置于所述源极、漏极与所述有源层之间，所述散射膜层表面为特定的不规则形状的表面形态。
  5. 根据权利要求4所述的阵列基板，其中，所述散射膜层的材料为氧化钼或其掺杂类金属氧化物材料。
  6. 根据权利要求5所述的阵列基板，其中，所述散射膜层的厚度为35nm~75nm。
  7. 一种阵列基板的制造方法，包括以下步骤：
    S10：提供一透明基板；
    S20：在所述透明基板上制备第一散射膜层；
    S30：在所述第一散射膜层上依次形成栅极、栅极绝缘层及有源层；
    S40：在所述栅极绝缘层上制备第二散射膜层；
    S50：在所述第二散射膜层上形成源极及漏极。
    其中，所述第一散射膜层设置于所述透明基板与所述栅极之间，所述第二散射膜层设置于所述源极、漏极与所述有源层之间，所述第一散射膜层与所述第二散射膜层构成散射膜层，所述散射膜层表面为不规则形状的表面形态。
  8. 根据权利要求7所述的阵列基板的制造方法，其中，所述散射膜层的厚度为35nm~75nm。
  9. 根据权利要求7所述的阵列基板的制造方法，其中，所述制备第一散射膜层及制备第二散射膜层的步骤，具体包括：
    S201：在所述透明基板及所述栅极绝缘层表面分别形成一层薄膜；
    S202：在所述薄膜上均匀涂覆形成一层聚苯乙烯球膜层；
    S203：在所述薄膜表面形成特定的不规则形状的表面形态；
    S204：清除残余在所述薄膜表面的所述聚苯乙烯球膜层；
    S205：在所述形成的不规则形状表面涂覆石墨烯溶液，形成石墨烯膜层。
  10. 根据权利要求9所述的阵列基板的制造方法，其中，所述薄膜的厚度为35nm~75nm。
  11. 根据权利要求9所述的阵列基板的制造方法，其中，所述薄膜的材料为氧化钼或其掺杂类金属氧化物材料。
  12. 根据权利要求9所述的阵列基板的制造方法，其中，所述薄膜采用物理气相沉积法直接成膜。
  13. 根据权利要求9所述的阵列基板的制造方法，其中，利用干法刻蚀方法在所述薄膜表面形成特定的不规则形貌界面。
  14. 根据权利要求9所述的阵列基板的制造方法，其中，采用湿式化学清洗法清除残余在所述薄膜表面的所述聚苯乙烯球膜层。
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