WO2020037669A1 - 电熔丝及其制造方法、存储单元 - Google Patents

电熔丝及其制造方法、存储单元 Download PDF

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Publication number
WO2020037669A1
WO2020037669A1 PCT/CN2018/102311 CN2018102311W WO2020037669A1 WO 2020037669 A1 WO2020037669 A1 WO 2020037669A1 CN 2018102311 W CN2018102311 W CN 2018102311W WO 2020037669 A1 WO2020037669 A1 WO 2020037669A1
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WIPO (PCT)
Prior art keywords
isolation
fuse
active region
preset active
region
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PCT/CN2018/102311
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English (en)
French (fr)
Inventor
王文轩
沈健
王红超
Original Assignee
深圳市为通博科技有限责任公司
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Application filed by 深圳市为通博科技有限责任公司 filed Critical 深圳市为通博科技有限责任公司
Priority to EP18914944.6A priority Critical patent/EP3648160B1/en
Priority to PCT/CN2018/102311 priority patent/WO2020037669A1/zh
Priority to CN201880001204.3A priority patent/CN111095546B/zh
Priority to US16/664,787 priority patent/US10991655B2/en
Publication of WO2020037669A1 publication Critical patent/WO2020037669A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5228—Resistive arrangements or effects of, or between, wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/20—Programmable ROM [PROM] devices comprising field-effect components
    • H10B20/25—One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links

Definitions

  • Embodiments of the present application relate to the field of semiconductor technology, and in particular, to an electric fuse, a manufacturing method thereof, and a memory unit.
  • E-fuse Electrical fuse
  • MOS chips As an important part of a non-volatile programmable memory. For example, it is used to implement the redundancy function in the memory array and to permanently save information such as the chip ID.
  • the electric fuse can be programmed by switching between a low-resistance state and a high-resistance state.
  • the principle of programming is that by driving a certain amount of current, the fuse body included in the electric fuse undergoes electromigration, resulting in electric melting.
  • the wire changed from a low resistance state to a high resistance state, and the process was irreversible. Because the programming process is realized by current injection, it can be programmed after the chip is packaged, which greatly increases its application range.
  • the structure of the electric fuse specifically includes a yin-yang electrode and a fuse body electrically connected to the yin-yang electrode.
  • the width of the electric fuse is determined by the line width of the fuse.
  • the structure of the traditional electric fuse is limited by the limit line width of the semiconductor process.
  • the limit width of the fuse can not be less than the limit line width of the semiconductor process.
  • the actual line width will not be less than the limit line width of the semiconductor process, or the actual line width of the fuse body is greater than its theoretical line width.
  • the fuse current In the case of a certain process capability, due to the actual line width of the larger electric fuse, the fuse current must reach a certain size to completely fuse the electric fuse, thereby achieving the programming effect. Further, in order to provide an amount of current that can meet the requirements of the electric fuse, the size of the transistor structure as its control unit must also meet certain requirements, which ultimately leads to a larger area of a single memory cell including the electric fuse, which reduces the memory storage.
  • one of the technical problems solved by the embodiments of the present invention is to provide an electric fuse, a manufacturing method thereof, and a memory unit, which are used to overcome or alleviate the above-mentioned defects in the prior art.
  • An embodiment of the present application provides a method for manufacturing an electric fuse, which includes:
  • a fuse body for connecting the cathode electrode and the anode electrode is formed on the side wall.
  • An embodiment of the present application provides an electric fuse, which includes a semiconductor substrate, a cathode electrode, an anode electrode, and a fuse body electrically connecting the cathode electrode and the anode electrode; the semiconductor substrate includes a preset active region, The cathode electrode and the anode electrode are formed on the preset active area; an isolation area is formed on the semiconductor substrate, and a height difference between the isolation area and the preset active area passes through At least one side wall is connected, and the fuse body is formed on the side wall.
  • An embodiment of the present application provides a memory unit including the electric fuse described in any of the embodiments.
  • the electric fuse includes: a semiconductor substrate, a cathode electrode, an anode electrode, and a fuse body electrically connecting the cathode electrode and the anode electrode;
  • the semiconductor substrate includes a preset active region, and the cathode An electrode and the anode electrode are formed on the preset active region; an isolation region is formed on the semiconductor substrate, and a height difference between the isolation region and the preset active region passes through at least one side
  • the fuse body is connected to the wall, and the fuse body is formed on the side wall, so that the line width of the fuse body is separated from the limit line width limit of the semiconductor process, and the actual line width of the electric fuse can be smaller than the limit line width of the semiconductor process, especially in the same Under the semiconductor process platform, the limitation of its limit line width is achieved to achieve a smaller actual fuse line width, so that the fusing current required during fusing is smaller. Further, the transistor structure as its control unit is also smaller, thereby reducing The area occupied by a single storage unit is
  • FIG. 1A is a schematic plan structural view of an electric fuse according to the first embodiment of the present application.
  • FIG. 1B is a schematic structural cross-sectional view of the electric fuse in the X direction in the embodiment of FIG. 1A.
  • FIG. 1C is a schematic structural cross-sectional view of the electric fuse in the embodiment of FIG. 1A along the Y direction;
  • FIG. 2 is a schematic flowchart of an electric fuse manufacturing method in Embodiment 2 of the present application.
  • 3A is a schematic plan view of a planar structure of a groove and a preset active region formed in an embodiment of the present application;
  • 3B is a schematic structural cross-sectional view of the groove and the preset active region formed in the embodiment of the present application along the X direction;
  • 3C is a schematic structural cross-sectional view of the groove and the preset active region formed in the embodiment of the present application along the Y direction;
  • 3D is a schematic plan view of a planar structure after removing a part of the isolation medium in the groove in the embodiment of the present application;
  • FIG. 3E is a schematic cross-sectional structure view along the X direction after removing a part of the isolation medium in the groove in the embodiment of the present application;
  • FIG. 3F is a schematic cross-sectional structure view in the Y direction after a part of the isolation medium in the groove is removed in the embodiment of the present application;
  • 3G is a schematic plan view of a planar structure after an oxide layer is formed in an embodiment of the present application.
  • 3H is a schematic cross-sectional structure view along the X direction after an oxide layer is formed in an embodiment of the present application;
  • 3I is a schematic cross-sectional structure view along the Y direction after an oxide layer is formed in an embodiment of the present application
  • 3J is a schematic plan view of a planar structure after a parasitic polysilicon layer is formed in an embodiment of the present application
  • 3K is a schematic cross-sectional structure view along the X direction after a parasitic polysilicon layer is formed in an embodiment of the present application;
  • 3L is a schematic cross-sectional structure view along the Y direction of a parasitic polysilicon layer in an embodiment of the present application
  • FIG. 4A is a schematic plan structural view of an electric fuse in Embodiment 3 of the present application.
  • FIG. 4B is a schematic cross-sectional structure view of the electric fuse shown in FIG. 4A along the X1 direction;
  • 4C is a schematic cross-sectional structure view of the electric fuse shown in FIG. 4A along the X2 direction;
  • 4D is a schematic cross-sectional structure view of the electric fuse shown in FIG. 4A along the Y1 direction;
  • 4E is a schematic cross-sectional structure view of the electric fuse shown in FIG. 4A along the Y2 direction.
  • FIG. 5 is a schematic plan structural view of an electric fuse in Embodiment 4 of the present application.
  • FIG. 6 is a schematic plan view of the electric fuse in the fifth embodiment of the present application.
  • the electric fuse may include: a semiconductor substrate, a cathode electrode, an anode electrode, and a fuse body electrically connecting the cathode electrode and the anode electrode; the semiconductor substrate includes a preset active Region, the cathode electrode and the anode electrode are formed on the preset active region; an isolation region is formed on the semiconductor substrate, and there is a height difference between the isolation region and the preset active region And connected through at least one side wall, and the fuse body is formed on the side wall.
  • the fusing of the fuse body is not a physical fracture.
  • the fuse surface metal migration caused by the electromigration principle forms a state of high resistance.
  • the manufacturing method provided in the following embodiments of the present application may specifically include the following process steps: providing a semiconductor substrate, the semiconductor substrate including a preset active region Forming an isolation region on a semiconductor substrate, wherein a height difference between the isolation region and the preset active region is connected through at least one side wall; forming a cathode electrode on the preset active region and An anode electrode; and a fuse body for connecting the cathode electrode and the anode electrode is formed on the side wall.
  • FIG. 1A is a schematic plan view of the electrical fuse in the first embodiment of the present application
  • FIG. 1B is a schematic cross-sectional view of the electrical fuse in the X direction in the embodiment of FIG. 1A.
  • the fusing current is described along the X direction as an example.
  • FIG. 1A illustrates a specific structure of the electric fuse from a top perspective
  • FIG. 1B illustrates a specific structure of the electric fuse from a cross-sectional perspective of the X direction.
  • the semiconductor substrate 101 has an isolation region 102 and a preset active region 100.
  • a negative electrode 107 and a positive electrode 108 are formed on the preset active region 100. Due to the fusing current along Y Therefore, the cathode electrode 107 and the anode electrode 108 are located on the upper and lower sides as viewed from FIG. 1A; and a fuse body 109 is formed between the preset active region 100 and the isolation region 102.
  • the fuse body 109 may include an oxide layer 103, a polysilicon layer 104, and a metal silicide layer 105. The width of the fuse body 109 is along the X direction as shown by W in FIG. 1A.
  • the line width of the electric fuse is the width in the Y direction.
  • the cathode electrode 107 and the anode electrode 108 are located at the left and right sides shown in FIG. 1A. On both sides.
  • the electric fuse further includes a connection unit 106 for connecting the electric fuse with an external circuit.
  • the number of the connection units 106 is specifically determined according to a requirement for connection with an external circuit and a required amount of passing current. In this embodiment, for example, two connections are provided on the anode electrode 108.
  • the unit 106 is provided with four connection units 106 on the cathode electrode 107.
  • both left and right side walls A located between the preset active region 100 and the isolation region 102 are provided.
  • the metal silicide layer 105 is located on the upper surface of the polysilicon layer 104, or the metal silicide layer 105 covers the surface of the polysilicon layer 104.
  • the fuse body 109 is also formed at the boundary P between the isolation region 102 and the preset active region 100.
  • a height difference is formed between the preset active region 100 and the isolation region 102, or the upper surface (or the highest surface) of the preset active region 100 and the isolation region 102 are not in the same plane.
  • a sidewall A is formed between the preset active region 100 and the isolation region 102.
  • the height difference can cause a trapezoidal region to be formed between the preset active region 100 and the isolation region 102.
  • the fuse body has a near-vertical sharp angle, and will be here during the application of the fusing current.
  • the electric field concentration phenomenon occurs everywhere, which makes it easier to fuse here, and the magnitude of the required fuse current will be greatly reduced.
  • FIG. 1C is a schematic structural cross-sectional view of the electric fuse in the Y direction in the embodiment of FIG. 1A; as shown in FIG. 1C, in this embodiment, the cathode electrode 107, the anode electrode 108, and the fuse body 109 have the same material and the same layer Take the structure as an example, that is, from the perspective of FIG. 1C, the fuse body 109 extends from one end of the cathode electrode 107, the left and right boundaries P adjacent to the isolation region 102 and the preset active region 100 along the Y direction (that is, the direction of the fuse current). To one end of the anode electrode 108 to connect the cathode electrode 107 and the anode electrode 108 together.
  • the connection unit 106 may be disposed above the metal silicide layer 105 in the cathode electrode 107 and the anode electrode 108.
  • the preset active region 100 and the isolation region 102 have a height difference, the preset active region 100 and the isolation region 102 have a stepped region (active region- -Sidewall-isolation region-sidewall-active region), so that the fuse has a sharp angle close to vertical.
  • the cathode electrode 107, the anode electrode 108, and the fuse body 109 have the same material and form the same layer structure, specifically, they each include three layers: an oxide layer, a polysilicon layer, and a metal silicide layer.
  • the anode electrode 108 includes an oxide layer 103, a polysilicon layer 104, and a metal silicide layer 105
  • the metal silicide layer 105 is disposed on the upper surface of the polysilicon layer 104.
  • the cathode electrode 107 also includes the oxide layer 103 and the polysilicon layer 104.
  • the metal silicide layer 105 is disposed on the upper surface of the polysilicon layer 104.
  • the fuse body 109 also includes an oxide layer 103, a polysilicon layer 104, and a metal silicide layer 105.
  • the metal silicide layer 105 is disposed on the polysilicon layer 104
  • the cathode electrode 107 and the anode electrode 108 may be formed simultaneously using the same process when forming the fuse body 109, or the fuse body 109 may be formed simultaneously using the same process when forming the cathode electrode 107 and the anode electrode 108. In order to simplify the process steps and reduce production costs.
  • the cathode electrode 107, the anode electrode 108, and the fuse body 109 use different materials to form different layer structures
  • the cathode electrode 107, the anode electrode 108, and the fuse body The formation of 109 can be formed step by step using different processes. For example, after forming the grooves in which the isolation region 102 is formed, the cathode electrode 107 and the anode electrode 108 are formed in the preset active region 100, and then a fuse body is formed; or First, the fuse body 109 is formed, and then the cathode electrode 107 and the anode electrode 108 are formed.
  • the manufacturing method for forming the electric fuse shown in FIG. 1A to FIG. 1C described above is exemplarily explained by using the structural schematic diagram after each step in FIG. 2 and the following steps.
  • FIG. 2 is a schematic flowchart of an electric fuse manufacturing method in Embodiment 2 of the present application; as shown in FIG. 2, it includes the following steps S201-S204:
  • S201 Provide a semiconductor substrate, the semiconductor substrate including a preset active region;
  • the semiconductor substrate may be a non-doped single crystal silicon, a doped single crystal silicon, a silicon-on-insulator (SOI), silicon carbide, or a semiconductor substrate formed by other methods.
  • the semiconductor substrate selected in this embodiment is, for example, a P-type silicon substrate.
  • a groove is formed downward from an upper surface of the semiconductor substrate, a bottom surface of the groove forms the isolation region, and a sidewall of the groove is used to connect the isolation region.
  • a groove can be formed downward from the upper surface of the semiconductor substrate by photolithography and etching.
  • the isolation region may be first filled with an isolation medium such as an oxide in the groove; and then a portion of the isolation medium in the groove is removed to form the isolation region, and the isolation region and the isolation region are formed. There is a height difference between the predetermined active regions and they are connected by at least one sidewall.
  • the groove is a square-shaped groove, and the square-shaped groove is filled with an isolation medium to form an isolation region. Then, the isolation region and a preset active region, such as the isolation region, are formed. Surrounded by the preset active area.
  • the semiconductor substrate is filled with an isolation medium in the m-shaped groove by a standard MOS isolation region process.
  • the isolation medium may be a shallow trench isolation (Shallow Trench Isolation (STI) oxide), or a part of silicon
  • STI shallow Trench Isolation
  • An oxidation (Local Oxidation of Silicon, LOCOS for short) process generates an isolation medium such as a field oxide (Field Oxide), and then removes part of the oxide in the groove to form the isolation region.
  • the isolation region is a shallow trench isolation region.
  • a photoresist opening is opened in the area where the fuse body is formed, and then quantitative etching is performed until the remaining isolation medium has a thickness required to achieve isolation between devices on the same substrate. That is, removing a part of the isolation medium in the isolation region, so that the preset active region and the isolation region have a height difference directly, or the upper surface of the preset active region and the isolation region. Not on the same plane.
  • the area where the fuse is to be set during the etching is not covered by the photoresist layer. Therefore, only the area where the fuse is to be set is etched during the etching. Etching away, thereby forming an isolation region with a height difference and a preset active region, and a sidewall between the preset active region and the isolation region.
  • a wet oxide etching process can be specifically used, and a hydrofluoric acid solution (such as a concentration of 1%) or a buffered oxide etching solution (BOE) can be used for etching.
  • the buffer oxide etching solution may be specifically formed by mixing hydrofluoric acid (49%) with water or ammonium fluoride and water.
  • a hydrofluoric acid solution or a buffer oxide etching solution to perform wet oxide etching is merely an example and is not limited.
  • a fuse body for connecting the cathode electrode and the anode electrode is formed on the sidewall.
  • the fuse body includes the above-mentioned oxide layer, polysilicon layer, and metal silicide layer
  • an oxide layer, a polysilicon layer, and a metal silicide layer are sequentially formed on the sidewall to form the fuse body.
  • the residual or parasitic polysilicon layer is formed by etching the polysilicon layer, and a metal silicide layer is formed on the surface of the residual or parasitic polysilicon layer.
  • the metal silicide layer may include at least one of a titanium metal silicide, a cobalt metal silicide, and a tungsten metal silicide.
  • the cathode electrode, anode electrode and fuse body use the same material and have the same layer structure, that is, the above three-layer structure (that is, the above-mentioned oxide layer 103, polysilicon layer 104, and metal silicide layer). 105).
  • the cathode, anode and fuse are made of the same material.
  • the oxide layer 103, the polysilicon layer 104, and the metal silicide layer 105 constituting the cathode electrode and the anode electrode are simultaneously formed by using the same process.
  • the above fuse body, cathode electrode, and anode electrode can be formed synchronously by using a MOS manufacturing process.
  • the low pressure chemical vapor deposition method Low Pressure Chemical Vapor Deposition, LPCVD for short
  • LPCVD Low Pressure Chemical Vapor Deposition
  • An oxide layer 103 is formed on the sidewall
  • a polysilicon layer 104 is deposited on the oxide layer 103.
  • the thickness of the deposited polysilicon layer 104 can be adjusted by controlling the deposition time.
  • the deposited polysilicon layer 104 is etched by a MOS polysilicon lithography and etching process.
  • polysilicon that is not completely etched clean that is, residual Polysilicon layer
  • a parasitic polysilicon layer forming a polysilicon sidewall structure.
  • a metal silicide layer is formed on the surface of the residual or parasitic polysilicon layer. Forming a metal silicide layer can be achieved by metallizing polysilicon to finally form a low-resistance fuse. At the same time, positive and negative electrodes are formed simultaneously.
  • the metallization of polysilicon can specifically adopt a MOS standard polysilicon metallization process.
  • steps S203 and S204 are performed simultaneously.
  • steps S203 and S204 can be performed separately. For example, after forming a groove, a cathode is first formed in the active area. Electrodes, anode electrodes; or, after the fuse body is formed, a cathode electrode and an anode electrode are formed in the active region.
  • FIG. 3A a schematic plan view of a planar structure of the groove and the preset active region 100 formed in the embodiment of the present application; and referring to FIG. 3B, the groove and the preset active region 100 formed along the X in the embodiment of the present application Schematic cross-sectional view of the structure; see also FIG. 3C, which is a schematic cross-sectional view of the groove and the preset active area 100 formed in the embodiment of the present application along the Y direction;
  • the filling height of the isolation medium 200 may be higher than the upper surface of the preset active area 100.
  • the height of the filled isolation medium 200 and the preset active area 100 may be processed by a grinding process. The top surface is flush.
  • FIG. 3D a schematic plan view of a planar structure after removing a part of the isolation medium in the groove in the embodiment of the present application; and referring to FIG. 3E, a cross-sectional view along the X direction after removing the part of the isolation medium in the groove in the embodiment of the present application.
  • Part of the isolation medium 200 forms an isolation region 102, so that there is a height difference between the preset active region 100 and the isolation region 102, or the preset active region 100 and the isolation region 102.
  • the upper surfaces are not on the same plane.
  • FIG. 3G which is a schematic plan view of the planar structure after the oxide layer is formed in the embodiment of the present application; and then refer to FIG. 3H, which is a cross-sectional structure schematic diagram in the X direction after the oxide layer is formed in the embodiment of the present application; A schematic cross-sectional structure view in the Y direction after the oxide layer is formed in the embodiment of the application. As shown in FIGS.
  • An oxide layer 103 may be formed on the upper surface of the side wall A and the preset active region 100 through an oxidation generation process of silicon, including a part of the isolation region near the side wall A, that is, the above-mentioned boundary P.
  • the isolation medium of the isolation region 120 is formed by the oxidation process of silicon, the other surface regions on the isolation region other than this part of the region cannot continue to form an oxide layer by the oxidation process of silicon. 103.
  • the oxide layer 103 may be formed on a surface region other than this partial region on the isolation region by a deposition process.
  • FIG. 3J which is a schematic plan view of a planar structure after a parasitic polysilicon layer is formed in the embodiment of the present application; and then refer to FIG. 3K, which is a schematic cross-sectional structure view along the X direction after the parasitic polysilicon layer is formed in the embodiment of the present application; 3L is a schematic cross-sectional view of the parasitic polysilicon layer along the Y direction in the embodiment of the present application; as shown in FIG.
  • a parasitic polysilicon layer 104 is formed on the upper surface of the oxide layer 103, regardless of the combination of the Y direction from the X direction From the perspective view of the cross-sectional structure, the polysilicon layer 104 covers the boundary P of the isolation region 102 and the preset active region, the sidewall A, and the upper surface of the preset active region 100.
  • FIGS. 1B and 1C The cross-sectional structural diagrams in the X direction and the cross-sectional structural diagrams in the Y direction after the metal silicide layer 105 is formed on the upper surface of the polysilicon layer 104 are shown in the above-mentioned FIGS. 1B and 1C.
  • connection unit 106 for connecting to an external circuit is formed on the negative electrode and the positive electrode.
  • connection unit 106 is specifically a contact hole (in this case, the connection unit 106 is also called Contact in the industry), and the formation process thereof is specifically formed using a standard MOS interlayer contact hole manufacturing process, which specifically includes interlayers.
  • metal interconnection lines and interlayer dielectrics can also be formed through a standard MOS back-end process.
  • the standard MOS back-end process may specifically include a back-end intermetal dielectric layer deposition process (Inter Metal Dielectric), an inter-metal via (Via) process, a metal deposition process for forming a metal connection, Lithography and etching processes, and polishing processes.
  • Inter Metal Dielectric Inter Metal Dielectric
  • Via inter-metal via
  • metal deposition process for forming a metal connection Lithography and etching processes, and polishing processes.
  • connection unit 106 is further located between the adjacent upper and lower metal interconnection lines, and the connection unit 106 and the adjacent upper and lower metal interconnection lines form an electrical connection.
  • An upper metal interconnection line is formed over the connection unit 106 through metal deposition (such as AlCu alloy), photolithography, and etching processes.
  • first layer of metal interconnection lines that is, the lower layer metal interconnection lines
  • multiple layers of similar metal interconnection lines are generally formed as needed; for example, the first layer of metal interconnection lines A line (not shown in the figure) is directly formed on the upper surface of the metal polysilicon layer 105, and a connection unit 106 is formed on the first layer of metal interconnection line (in this case, the connection unit 106 is also called via in the industry), The periphery of the connection unit is surrounded by a dielectric layer.
  • the dielectric layer here is referred to as the above-mentioned interlayer dielectric (ie Inter metal Dielectric), and then a second layer of metal interconnection lines (ie, the upper layer) is generated by the same process above the connection unit.
  • Metal interconnection lines and so on, the specific generation of several layers of metal interconnection lines should be determined according to the needs of the circuit itself.
  • the line width of the electrical fuse is limited by the limit line width of the semiconductor process (also called the minimum line Width), that is, it cannot be less than the limit line width of the semiconductor process.
  • the preset active region and the isolation region have a height difference and a sidewall, a portion of the polysilicon layer or a parasitic portion of the polysilicon layer remains on the side during the polysilicon etching, and then metal is formed.
  • the polysilicon layer finally forms a fuse body, so that a special process is not required to form the fuse body, so that the line width of the fuse body is separated from the limit line width of the semiconductor process, and the actual line width of the electric fuse can be much smaller than the existing The line width of an electrical fuse as defined in the art by a normal lithographic process. Especially in the semiconductor process of the same platform, electric fuses smaller than the limit line width of the semiconductor process can be manufactured. Furthermore, the transistor structure as its control unit is also smaller, thereby reducing the area occupied by a single memory cell and improving Memory capacity.
  • FIG. 4A is a schematic plan view of the electrical fuse in the third embodiment of the present application
  • FIG. 4B is a schematic cross-sectional view of the electrical fuse shown in FIG. 4A along the X1 direction
  • FIG. 4C is a schematic view of the electrical fuse shown in FIG. 4D is a schematic cross-sectional structure diagram of the electric fuse shown in FIG. 4A along the Y1 direction
  • FIG. 4E is a schematic cross-sectional structure diagram of the electric fuse shown in FIG. 4A along the Y2 direction.
  • an isolation region is formed by filling an isolation medium in a slot with a zigzag pattern, and an isolation region formed by filling with an isolation medium in a slot with a zigzag pattern; Filling an isolation region formed by an isolation medium in a herringbone groove forms two of the isolation regions and two of the preset active regions, so there are two height differences, and the values of the two height differences can be The same or different.
  • the direction of the fusing current is still the Y direction.
  • another preset active region 100 (also referred to as a peripheral preset active region 100) is formed around the two isolation regions 102.
  • the intermediate preset active region 100 is specifically located between two isolation regions 102, and an oxide layer 103 of a fuse is formed on a sidewall A between the intermediate preset active region 100 and the two isolation regions 102 respectively.
  • the polysilicon layer 104, the metal 105, and the cathode electrode 107, the anode electrode 108, and the connection unit 106 are respectively formed on the preset active regions 100 located at the upper and lower ends of the electric fuse along the Y1 direction.
  • the manufacturing method of the electric fuse shown in FIG. 1A is formed according to the above FIG. 2.
  • the specific process in each step is similar to the corresponding step in FIG. 2. The differences are as follows:
  • two grooves are formed on the semiconductor substrate 101, a preset active region 100 is located between the two grooves, and an electric fuse is located along the Y1 direction
  • the preset active regions 100 at the upper and lower ends (as shown in FIG. 4A).
  • the isolation media filled in the grooves of the two isolation regions 102 to be formed are separately processed, so that the left and right isolation regions along the X1 direction are formed on the semiconductor substrate 101.
  • an oxide layer is formed on the sidewall A formed in the middle preset active region 100 and the left and right isolation regions 102 when viewed from the direction along X2. 103 (as shown in FIG. 4C), and polysilicon is formed at the boundary (as shown in FIG. 4E) adjacent to the left and right sides of the oxide layer 103, the middle preset active region 100, and the left and right isolation regions 102.
  • the fuse body of FIG. 4A when the fuse body of FIG. 4A is formed, the remaining polysilicon layer of the sidewall A in the middle preset active region 100 and the left and right isolation regions 102 is viewed from the direction of Y1.
  • a metal silicide layer 105 and an electrical connection unit 106 are sequentially formed on 104, so that the anode electrode, the cathode electrode, and the fuse body can be formed simultaneously in the same process.
  • FIG. 5 is a schematic diagram of a planar structure of an electric fuse in Embodiment 4 of the present application; as shown in FIG. 5, when viewed from the schematic diagram of the planar structure, compared with FIG. 1A, the difference is that along the Y direction of the electric fuse,
  • the upper and lower preset active regions 100 are respectively provided with two cathode electrodes 107 and two anode electrodes 108, each of the cathode electrodes 107 corresponds to four connection units 106, and each of the anode electrodes 108 corresponds to one connection unit 106.
  • the number of connection units 106 in the diagram is not specifically limited, and tens or dozens of connection units 106 may be put in the specific operation process, depending on the amount of the required fusing current.
  • FIG. 6 is a schematic diagram of a planar structure of an electric fuse in Embodiment 5 of the present application; as shown in FIG. 6, when viewed from the schematic diagram of the planar structure, compared with FIG. 4A, the difference is that along the Y direction of the electric fuse,
  • the upper and lower preset active regions 100 are respectively provided with two cathode electrodes 107 and two anode electrodes 108.
  • Each cathode electrode 107 corresponds to two connection units 106
  • each anode electrode 108 corresponds to two connection units 106.
  • FIG. 5 In order to form the electric fuse shown in FIG. 5, compared to the manufacturing method of the electric fuse shown in FIG.
  • FIGS. 1A and 2A since a pair of female and male electrodes correspond to the left and right fuses, only the left and right fuses can be fused to achieve program.
  • FIG. 5 and FIG. 6 since it is a pair of yin and yang electrodes corresponding to a fuse, as long as one of the fuses is fused, programming can be realized.
  • FIG. 5 and FIG. 6 can also be understood as the structure of two electric fuses.

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Abstract

本申请实施例提供了一种电熔丝及其制造方法、存储单元，方法包括：提供一半导体衬底，所述半导体衬底包括预设有源区；在半导体衬底上形成隔离区，其中，所述隔离区与所述预设有源区之间具有高度差并通过至少一侧壁相连；在所述预设有源区上形成阴电极和阳电极；以及在所述侧壁上形成用于连接所述阴电极和阳电极的熔断体，使得熔断体的线宽脱离半导体工艺的极限线宽限制，实现电熔丝的实际线宽可以小于半导体工艺的极限线宽，尤其在同一半导体工艺平台下摆脱其极限线宽的限制从而实现较小的电熔丝实际线宽，从而在熔断时需要的熔断电流较小，进一步地，作为其控制单元的晶体管结构也较小，从而减小了单一存储单元所占面积，提高了存储器的存储容量。

Description

电熔丝及其制造方法、存储单元 技术领域
本申请实施例涉及半导体技术领域，尤其涉及一种电熔丝及其制造方法、存储单元。
背景技术
电熔丝(Electrically programmable fuse，简称e-fuse)具有结构简洁、成本低、可靠性高的优点，因此被广泛应用于MOS芯片之中作为一种非易失性可编程存储器的重要组成部分，比如用作实现存储器阵列中的冗余功能以及用于永久保存芯片ID等信息。
电熔丝可以通过在低阻状态以及高阻状态之间转换而实现编程，其编程实现原理是通过在一定大小的电流驱动下，电熔丝所包含的熔断体发生电迁移现象，导致电熔丝从低阻态转变为高阻态，且过程不可逆。由于其编程过程是通过电流的注入实现，因此可以在芯片封装后进行编程，大大提高了其应用范围。
电熔丝的结构具体包括阴阳电极以及电连接阴阳电极的熔断体。电熔丝的宽度决定于熔断体的线宽，而传统电熔丝的结构受限于半导体工艺极限线宽的影响，熔断体的极限宽度不能小于半导体工艺的极限线宽，即电熔丝的实际线宽不会小于半导体工艺的极限线宽，或者又称熔断体的实际线宽要比其理论线宽要大。
在工艺能力一定的情况下，受限于较大的电熔丝实际线宽，其熔断电流要达到一定的大小才能完全熔断电熔丝，从而达到编程效果。进一步地，为了提供可满足电熔丝熔断要求的电流量，作为其控制单元的晶体管结构大小也要满足一定要求，最终导致包括电熔丝的单一存储单元所占面积较大，降低了存储器的存储容量。
发明内容
有鉴于此，本发明实施例所解决的技术问题之一在于提供一种电熔丝及其制造方法、存储单元，用以克服或者缓解现有技术中上述缺陷。
本申请实施例提供了一种电熔丝的制造方法，其包括：
提供一半导体衬底，所述半导体衬底包括预设有源区；
在半导体衬底上形成隔离区，其中，所述隔离区与所述预设有源区之间具有高度差并通过至少一侧壁相连；
在所述预设有源区上形成阴电极和阳电极；以及
在所述侧壁上形成用于连接所述阴电极和阳电极的熔断体。
本申请实施例提供了一种电熔丝，其包括：半导体衬底、阴电极、阳电极以及电连接所述阴电极和阳电极的熔断体；所述半导体衬底包括预设有源区，所述阴电极和所述阳电极形成在所述预设有源区上；所述半导体衬底上形成有隔离区，所述隔离区与所述预设有源区之间具有高度差并通过至少一侧壁相连，所述熔断体形成在所述侧壁上。
本申请实施例提供了一种存储单元，其包括任一实施例中所述的电熔丝。
本申请实施例中，由于电熔丝包括：半导体衬底、阴电极、阳电极以及电连接所述阴电极和阳电极的熔断体；所述半导体衬底包括预设有源区，所述阴电极和所述阳电极形成在所述预设有源区上；所述半导体衬底上形成有隔离区，所述隔离区与所述预设有源区之间具有高度差并通过至少一侧壁相连，所述熔断体形成在所述侧壁上，使得熔断体的线宽脱离半导体工艺的极限线宽限制，实现电熔丝的实际线宽可以小于半导体工艺的极限线宽，尤其在同一半导体工艺平台下摆脱其极限线宽的限制从而实现较小的电熔丝实际线宽，从而在熔断时需要的熔断电流较小，进一步地，作为其控制单元的晶体管结构也较小，从而减小了单一存储单元所占面积，提高了存储器的存储容量。
附图说明
后文将参照附图以示例性而非限制性的方式详细描述本申请实施例的一些具体实施例。附图中相同的附图标记标示了相同或类似的部件或部分。本领域技术人员应该理解，这些附图未必是按比例绘制的。附图中：
图1A为本申请实施例一的电熔丝的平面结构示意图；
图1B为图1A实施例中电熔丝沿X方向剖视结构示意图。
图1C为图1A实施例中电熔丝沿Y方向剖视结构示意图；
图2为本申请实施例二中电熔丝制造方法流程示意图；
图3A为本申请实施例中形成的凹槽与预设有源区的平面结构示意图；
图3B为本申请实施例中形成的凹槽与预设有源区沿X方向剖视结构示意图；
图3C为本申请实施例中形成的凹槽与预设有源区沿Y方向剖视结构示意图；
图3D为本申请实施例中去除掉凹槽中部分隔离介质后的平面结构示意图；
图3E为本申请实施例中去除掉凹槽中部分隔离介质后沿X方向的剖视结构示意图；
图3F为本申请实施例中去除掉凹槽中部分隔离介质后沿Y方向的剖视结构示意图；
图3G为本申请实施例中形成氧化层后的平面结构示意图；
图3H为本申请实施例中形成氧化层后沿X方向的剖视结构示意图；
图3I为本申请实施例中形成氧化层后沿Y方向的剖视结构示意图；
图3J为本申请实施例中形成寄生的多晶硅层后的平面结构示意图；
图3K为本申请实施例中形成寄生的多晶硅层后沿X方向的剖视结构示意图；
图3L为本申请实施例中寄生的多晶硅层后沿Y方向的剖视结构示意图；
图4A为本申请实施例三中电熔丝的平面结构示意图；
图4B为图4A所示电熔丝沿X1方向的剖视结构示意图；
图4C为图4A所示电熔丝沿X2方向的剖视结构示意图；
图4D为图4A所示电熔丝沿Y1方向的剖视结构示意图；
图4E为图4A所示电熔丝沿Y2方向的剖视结构示意图。
图5为本申请实施例四中电熔丝的平面结构示意图；
图6为本申请实施例五中电熔丝的平面结构示意图。
具体实施方式
实施本发明实施例的任一技术方案必不一定需要同时达到以上的所有优点。
为了使本领域的人员更好地理解本发明实施例中的技术方案，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅是本发明实施例一部分实施例，而不是全部的实施例。基于本发明实施例中的实施例，本领域普通技术人员所获得的所有其他实施例，都应当属于本发明实施例保护的范围。
下面结合本发明实施例附图进一步说明本发明实施例具体实现。
本申请下述实施例提供的电熔丝在结构上可以包括：半导体衬底、阴电极、 阳电极以及电连接所述阴电极和阳电极的熔断体；所述半导体衬底包括预设有源区，所述阴电极和所述阳电极形成在所述预设有源区上；所述半导体衬底上形成有隔离区，所述隔离区与所述预设有源区之间具有高度差并通过至少一侧壁相连，所述熔断体形成在所述侧壁上。
所述熔断体的熔断并非物理上的断裂，实际是利用电迁移原理造成的熔丝表层金属迁移形成高阻态的状态。
对应地，为制造出具有上述结构的电熔丝，本申请下述实施例中提供的制造方法，具体可包括如下流程步骤：提供一半导体衬底，所述半导体衬底包括预设有源区；在半导体衬底上形成隔离区，其中，所述隔离区与所述预设有源区之间具有高度差并通过至少一侧壁相连；在所述预设有源区上形成阴电极和阳电极；以及在所述侧壁上形成用于连接所述阴电极和阳电极的熔断体。
为了对本申请实施例中的电熔丝及其制造方法、存储单元作出清楚的示例性说明，下面将分别举例四种不同的电熔丝结构以及对应的制造方法。
图1A为本申请实施例一的电熔丝的平面结构示意图；图1B为图1A实施例中电熔丝沿X方向剖视结构示意图。本实施例中，以熔断电流沿着X方向为例进行说明。图1A从俯视角度对电熔丝的具体结构进行说明，图1B从X方向剖视角度对电熔丝的具体结构进行说明。
如图1A、1B所示，半导体衬底101上具有隔离区102以及预设有源区100，预设有源区100上形成有一个阴电极107、一个阳电极108，由于熔断电流沿着Y方向，因此，阴电极107、阳电极108从图1A上来看，位于上下两侧；而预设有源区100与隔离区102之间形成有熔断体109。如图1B所示，该熔断体109可以包括氧化层103、多晶硅层104、金属硅化物层105。熔断体109的宽度为如图1A中W所示沿着X方向。
在其他本实施例中，如果熔断电流是沿着X方向流动，则电熔丝的线宽为沿着Y方向的宽度，与此同时，阴电极107、阳电极108位于图1A所示的左右两侧。
进一步地，本实施例中，电熔丝还包括连接单元106，用于使得所述电熔丝与外部电路连接。本实施例中，连接单元106的数量具体根据与外部电路进行连接的需求，以及所需通过电流量而定，而在本实施例中，示例性地，在阳电极108上设置有两个连接单元106，在阴电极107上设置有四个连接单元106。
如图1B所示，由于熔断电流沿着Y方向，从X方向的剖视结构示意图上可看出，位于预设有源区100与隔离区102之间的左右两个侧壁A上均设置有 氧化层103、多晶硅层104、金属硅化物层105，金属硅化物层105位于多晶硅层104的上表面，或者说金属硅化物层105覆盖于多晶硅层104的表面。
本实施例中，沿着X方向，熔断体109也形成于隔离区102与预设有源区100的交界处P。
再参见图1B，预设有源区100与隔离区102之间形成高度差，或者称之为预设有源区100与隔离区102的上表面(或者又称最高的表面)不在同一平面内，且预设有源区100与隔离区102之间形成侧壁A。从X方向来看，该高度差可以使得所述预设有源区100与所述隔离区102之间形成梯形区域。如果沿着熔断电流的方向即Y方向来看，由于预设有源区100与隔离区102之间具有高度差，使得熔断体具有接近垂直的尖角，在施加熔断电流的过程中会在此处出现电场集中现象，导致熔断此处更加容易，所需熔断电流的大小也会大比例降低。
图1C为图1A实施例中电熔丝沿Y方向剖视结构示意图；如图1C所示，本实施例中，以阴电极107、阳电极108以及熔断体109具有同样的材质以及同样的层结构为例，即从图1C上来看，熔断体109沿着Y方向(即熔断电流的方向)从阴电极107的一端、隔离区102与预设有源区100相邻的左右两交界P延伸到阳电极108的一端，从而将阴电极107以及阳电极108连接起来。另外，连接单元106可以设置在阴电极107以及阳电极108中的金属硅化物层105上方。
本实施例中，由于预设有源区100与隔离区102具有高度差，所以，沿着熔断电流的方向来看，预设有源区100与隔离区102具有阶梯状区域(有源区--侧壁-隔离区--侧壁-有源区)，从而使得熔断体具有接近垂直的尖角。
本实施例中，如前所述，如果阴电极107、阳电极108以及熔断体109具有同样的材质且形成相同的层结构，具体如其均包括氧化层、多晶硅层、金属硅化物层这三层的话，即阳电极108包括氧化层103、多晶硅层104、金属硅化物层105，金属硅化物层105设置在多晶硅层104的上表面，类似的，阴电极107也包括氧化层103、多晶硅层104、金属硅化物层105，金属硅化物层105设置在多晶硅层104的上表面，熔断体109同样包括氧化层103、多晶硅层104、金属硅化物层105，金属硅化物层105设置在多晶硅层104的上表面时，可以在形成熔断体109的时候利用同一工艺同步形成所述阴电极107、阳电极108，或者，在形成所述阴电极107、阳电极108时利用同一工艺同步形成熔断体109，以简化工艺步骤，降低生产成本。
但是，在其他实施例中，对于本领域普通技术人员来说，如果阴电极107、阳电极108以及熔断体109使用不同的材质形成不同的层结构，则阴电极107、阳电极108以及熔断体109的形成可以采用不同的工艺分步形成，比如，在形成设置隔离区102的凹槽之后，就在预设有源区100形成阴电极107、阳电极108，之后，再形成熔断体；或者，先形成熔断体109，再形成阴电极107、阳电极108。
下述通过图2及各个步骤之后的结构示意图对形成上述图1A-图1C所示电熔丝的制造方法进行示例性解释。
图2为本申请实施例二中电熔丝制造方法流程示意图；如图2所示，其包括如下步骤S201-S204：
S201、提供一半导体衬底，所述半导体衬底包括预设有源区；
本实施例中，半导体衬底可以为未进行掺杂的单晶硅、掺杂过的单晶硅、绝缘体上硅(Silicon-on-insulator,SOI)、碳化硅或其他方式形成的半导体衬底。具体地，本实施例中所选用的半导体衬底比如为P型硅衬底。
S202、在半导体衬底上形成隔离区，其中，所述隔离区与所述预设有源区之间具有高度差并通过至少一侧壁相连；
具体地，本实施例中，自所述半导体衬底的上表面向下形成一凹槽，所述凹槽的底面形成所述隔离区，所述凹槽的侧壁用于连接所述隔离区与所述预设有源区。在一具体应用场景中，可以通过光刻以及刻蚀自所述半导体衬底的上表面向下形成一凹槽。在一具体应用场景中，可以首先通过在所述凹槽中填满隔离介质如氧化物；再去除所述凹槽中的部分隔离介质形成所述隔离区，并使得所述隔离区与所述预设有源区之间具有高度差并通过至少一侧壁相连。本实施例中，所述凹槽为口字型凹槽，在口字型凹槽中填充隔离介质形成隔离区，则形成一个所述隔离区以及一个预设有源区，比如所述隔离区被所述预设有源区环绕。
进一步地，在半导体衬底上通过标准MOS隔离区域工艺在口字型凹槽中填充隔离介质，该隔离介质可以是浅沟道隔离(Shallow Trench Isolation，简称STI)氧化物，或通过硅的局部氧化(Local Oxidation of Silicon，简称LOCOS)工艺生成场氧化物(Field Oxide)等隔离介质，再去除所述凹槽中的部分氧化物形成所述隔离区。具体地，本实施例中，隔离区为浅沟道隔离区。
具体地，在凹槽中填满隔离介质后，在形成熔断体的区域开设置光阻开口后进行定量蚀刻，直至剩下的隔离介质具有可实现同一衬底上器件之间隔离所 需的厚度，即去除所述隔离区中的部分隔离介质，使得所述预设有源区与所述隔离区直接具有高度差，或者又称之所述预设有源区与所述隔离区的上表面不在同一平面。
本实施例中，由于在凹槽中填满隔离介质后，在进行蚀刻时待设置熔断体的区域未被光阻层遮蔽，因此，在蚀刻时只有待设置熔断体的区域中隔离介质被刻蚀掉，从而可形成具有高度差的隔离区以及预设有源区，以及所述预设有源区与所述隔离区之间的侧壁。
在一具体应用场景中，可以具体采用湿法氧化物蚀刻工艺，可用设定浓度比例的氢氟酸溶液(如浓度1％)或缓冲氧化物刻蚀液(Buffered Oxide Etch，BOE)进行刻蚀。缓冲氧化物刻蚀液具体可由氢氟酸(49％)与水或氟化铵与水混合而成。此处使用氢氟酸溶液或缓冲氧化物刻蚀液进行湿法氧化物蚀刻仅是举例，并非限定。
但是，如果忽略工艺的局限性或不考虑工艺的成本，也可以直接在凹槽中填充部分氧化物，直接使得所述隔离区与所述预设有源区之间具有高度差并通过至少一侧壁相连。
S203、在所述预设有源区上形成阴电极和阳电极；
S204、在所述侧壁上形成用于连接所述阴电极和阳电极的熔断体。
当熔断体包括上述氧化层、多晶硅层、金属硅化物层时，在形成熔断时，依次在所述侧壁上形成氧化层、多晶硅层、金属硅化物层，以形成所述熔断体。其中，通过对所述多晶硅层进行刻蚀形成残留或者寄生的多晶硅层，在残留或者寄生的多晶硅层表面形成金属硅化物层。所述金属硅化物层可以包括钛金属硅化物、钴金属硅化物、钨金属硅化物中的至少一种。
如前所述，由于考虑的工艺成本，阴电极、阳电极和熔断体使用相同的材质、具有相同的层结构，即上述三层结构(即上述氧化层103、多晶硅层104、金属硅化物层105)，对于每层来说，阴电极、阳电极和熔断体由相同的材质组成。为此，在形成上述熔断体时，利用相同的工艺同步形成组成阴电极、阳电极的上述氧化层103、多晶硅层104、金属硅化物层105。
本实施例中，可以利用MOS制造工艺流程同步形成上述熔断体、阴电极、阳电极，比如具体利用低压力化学气相沉积法(Low Pressure Chemical Vapor Deposition，简称LPCVD)在有源区上表面以及所述侧壁上形成上述氧化层103，再在该氧化层103上沉积多晶硅层104，沉积的多晶硅层104的厚度可以通过控制沉积的时间来调整。之后，再通过MOS多晶硅光刻与刻蚀工艺对沉积的 多晶硅层104进行刻蚀。
本实施例中，由于预设有源区与隔离区之间具有侧壁，因此，在经过多晶硅光刻与刻蚀工艺之后，会在侧壁上残留未被完全刻蚀干净的多晶硅(即残留的多晶硅层)或者又称之形成寄生的多晶硅层，形成多晶硅边墙结构。最后，在残留或者寄生的多晶硅层表面形成金属硅化物层。形成金属硅化物层可以通过多晶硅的金属化来实现，以最终形成低阻态的熔断体。与此同时，同步形成阳电极、阴电极。多晶硅的金属化具体可以采用MOS标准多晶硅金属化工艺。
本实施例中，由于阴电极、阳电极和熔断体使用相同的材质、具有相同的层结构，上述步骤S203、S204是同步执行的。但是，如前所述，若阴电极、阳电极和熔断体使用不同的材质、具有不同的层结构，步骤S203、S204可以分开执行，比如在形成凹槽之后，就先在有源区形成阴电极、阳电极；或者，在形成熔断体之后，再在有源区形成阴电极、阳电极。
以下结合各个步骤处理后的结构示意图进行上述制造方法的解释。
参见图3A，为本申请实施例中形成的凹槽与预设有源区100的平面结构示意图；再参见图3B，为本申请实施例中形成的凹槽与预设有源区100沿X方向剖视结构示意图；再参见图3C，为本申请实施例中形成的凹槽与预设有源区100沿Y方向剖视结构示意图；参见3A-3C，凹槽中填充满隔离介质200，在实际工艺过程中，隔离介质200填充的高度可能会高出预设有源区100的上表面，此时，可以通过研磨工艺进行处理使得填充的隔离介质200的高度与预设有源区100的上表面齐平。
参见图3D，为本申请实施例中去除掉凹槽中部分隔离介质后的平面结构示意图；再参见图3E，为本申请实施例中去除掉凹槽中部分隔离介质后沿X方向的剖视结构示意图；再参见图3F，为本申请实施例中去除掉凹槽中部分隔离介质后沿Y方向的剖视结构示意图；参见3D-3F，通过蚀刻掉凹槽中的部分隔离介质200剩下部分隔离介质200以形成隔离区102，从而使得所述预设有源区100与所述隔离区102之间具有高度差，或者又称之所述预设有源区100与所述隔离区102的上表面不在同一平面。与此同时，所述预设有源区100与所述隔离区102之间梯形侧壁A。
参见图3G，为本申请实施例中形成氧化层后的平面结构示意图；再参见图3H，为本申请实施例中形成氧化层后沿X方向的剖视结构示意图；再参见图3I，为本申请实施例中形成氧化层后沿Y方向的剖视结构示意图；如图3G-3I所示，本实施例中，如前所述，由于阳电极、阴电极以及熔断均包括有氧化层， 因此，可以通过硅的氧化生成工艺在所述侧壁A、所述预设有源区100的上表面形成一层氧化层103，其中包括隔离区中靠近侧壁A的部分区域即上述交界P。
如前所述，由于隔离区120的隔离介质是通过硅的氧化生成工艺形成的，因此，在隔离区上除此部分区域之外的其他表面区域无法再继续通过硅的氧化生成工艺形成氧化层103。但是，在其他实施例中，可以通过沉积工艺在隔离区上除此部分区域之外的其他表面区域形成氧化层103。
参见图3J，为本申请实施例中形成寄生的多晶硅层后的平面结构示意图；再参见图3K，为本申请实施例中形成寄生的多晶硅层后沿X方向的剖视结构示意图；再参见图3L，为本申请实施例中寄生的多晶硅层后沿Y方向的剖视结构示意图；如图3J-3L所示，在氧化层103上表面形成寄生的多晶硅层104，无论从X方向结合Y方向的剖视结构来看，多晶硅层104覆盖隔离区102与预设有源区的交界P、侧壁A以及预设有源区100的上表面。
在多晶硅层104上表面形成金属硅化物层105后的X方向剖视结构图以及Y方向的剖视结构图如上述图1B和1C所示。
在形成所述阴电极和所述阳电极之后，在所述阴电极和所述阳电极上形成用于与外部电路连接的上述连接单元106。
本实施例中，上述连接单元106比如具体为接触孔(此种情形下该连接单元106业界又称之为Contact)，其形成工艺具体采用标准MOS层间接触孔制造工艺形成，具体包括层间介质(Inter Layer Dielectric)沉积工艺、接触孔(Contact)光刻工艺、刻蚀工艺、接触孔内金属沉积工艺、研磨(化学机械研磨)工艺等。
另外，还可以通过过标准MOS后段工艺形成各层金属互连线与层间介质(图中未示出)。
可选地，本实施例中，标准MOS后段工艺具体可包括后段金属间介电层沉积工艺(Inter Metal Dielectric)、金属间通孔(Via)工艺、形成金属连线的金属沉积工艺、光刻以及刻蚀工艺，以及研磨工艺等。
具体地，连接单元106进一步位于相邻的上下两层金属互连线之间，连接单元106与相邻上下两层的金属互连线形成电气连接。通过金属沉积(本比如AlCu合金)、光刻以及刻蚀工艺在连接单元106上方形成上层金属互连线。
具体地，从下到上形成了第一层金属互连线(即下层金属互连线)之后，一般根据需要，会再形成多层的类似金属互连线；比如，第一层金属互连线(图 中未示出)直接形成在金属多晶硅层105上表面，在第一层金属互连线之上再形成连接单元106(此种情形下该连接单元106业界又称之为via)，连接单元的外围被电介质层包围，此处的电介质层被称作上述层间介质(即Inter metal Dielectric)，然后在连接单元的上方再用相同的工艺产生第二层金属互连线(即上层金属互连线)，以此类推，具体产生几层金属互连线要根据电路本身的需求所决定。
与现有技术中由于预设有源区和隔离区处于同一水平面时进行标准的多晶硅刻蚀相比，电熔丝的线宽受限于半导体工艺的极限线宽(或又称之为最小线宽)，即不能小于半导体工艺的极限线宽。而本实施例中，由于预设有源区和隔离区具有高度差且具有侧壁，从而在进行多晶硅刻蚀时会在侧上残留部分多晶硅层或者又称寄生部分多晶硅层，之后再形成金属多晶硅层，最终形成熔断体，从而不需要专门的工艺去形成熔断体，使得熔断体的线宽脱离了半导体工艺的极限线宽的影响，可使得电熔丝的实际线宽远远小于现有技术中通过正常光刻工艺所定义的电熔丝的线宽。尤其在同一平台的半导体工艺下，可以制造出小于该半导体工艺极限线宽的电熔丝，进一步地，作为其控制单元的晶体管结构也较小，从而减小了单一存储单元所占面积，提高了存储器的存储容量。
图4A为本申请实施例三中电熔丝的平面结构示意图；图4B为图4A所示电熔丝沿X1方向的剖视结构示意图；图4C为图4A所示电熔丝沿X2方向的剖视结构示意图；图4D为图4A所示电熔丝沿Y1方向的剖视结构示意图；图4E为图4A所示电熔丝沿Y2方向的剖视结构示意图。如图4A-4E所示，本实施例中，通过在回字型凹槽中填充隔离介质形成隔离区，通过在回字型凹槽中填充隔离介质形成的隔离区；所述隔离区为通过在回字型凹槽中填充隔离介质形成的隔离区，则形成两个所述隔离区以及两个所述预设有源区，由此存在两个高度差，这两个高度差的数值可以相同，也可以不同。熔断电流的方向仍然为Y方向，与上述图1A及其对应的剖视结构示意图相比，图4A所示的电熔丝结构上，在两个隔离区102之间形成了一个中间的预设有源区100，在两个隔离区102外围形成有另外一个预设有源区100(又可称之为外围预设有源区100)。该中间的预设有源区100具体位于两个隔离区102之间，在该中间的预设有源区100分别与两个隔离区102之间的侧壁A上形成熔断体的氧化层103、多晶硅层104、金属105，而阴电极107、阳电极108以及连接单元106分别形成在沿着Y1方向位于电熔丝上下两端的预设有源区100上。
对照上述图2形成图1A所示电熔丝的制造方法，每个步骤中具体工艺类 似上述图2对应的步骤，其不同之处在于：
对照上述实施例，在半导体衬底101上形成两个凹槽(用于后续形成隔离区102)以及位于两个凹槽之间的预设有源区100，以及沿着Y1方向位于电熔丝上下两端的预设有源区100(如图4A所示)。
对照上述实施例，在形成图4A的隔离区时，对两个待形成隔离区102的凹槽中填充的隔离介质分别进行处理，从而在半导体衬底101上使得沿着X1方向的左右隔离区102与中间的预设有源区100之间分别具有高度差以及所述中间的预设有源区100与所述左右隔离区102之间分别具有侧壁A(如图4B所示)。
对照上述实施例，在形成图4A熔断体时，从沿着X2的方向来看，在所述中间的预设有源区100与左右所述隔离区102分别形成的侧壁A上形成氧化层103(如图4C所示)，并在所述氧化层103、所述中间的预设有源区100与所述左右隔离区102相邻的左右两交界(如图4E所示)处形成多晶硅层，并对所述对多晶硅层进行刻蚀得到残留的多晶硅层104，在残留的多晶硅层104上形成金属硅化物层105。
对照上述实施例，在形成图4A熔断体时，从沿着Y1方向上来看，在所述中间的预设有源区100与所述左右隔离区102分别具有的侧壁A的残留的多晶硅层104上依次形成金属硅化物层105以及电连接单元106(如图4D所示)，从而可以相同的工艺同步形成阳电极、阴电极以及熔断体。
图5为本申请实施例四中电熔丝的平面结构示意图；如图5所示，从平面结构示意图上来看，与图1A相比，区别之处在于，沿着电熔丝的Y方向，上下两端的预设有源区100上分别设置有两个阴电极107、两个阳电极108，每个阴电极107对应有四个连接单元106，每个阳电极108对应有一个连接单元106。示意图中的连接单元106的数量并非具体限定，具体操作过程中可能会放几十个或十几个连接单元106，具体要看所需熔断电流量的大小决定。
为形成具有图5所示的电熔丝，对照上述图2所示制造方法，只要改变多晶硅的沉积与刻蚀开口区域即可实现，具体的沉积与刻蚀参照对上述实施例的记载。
图6为本申请实施例五中电熔丝的平面结构示意图；如图6所示，从平面结构示意图上来看，与图4A相比，区别之处在于，沿着电熔丝的Y方向，上下两端的预设有源区100上分别设置有两个阴电极107、两个阳电极108，每个阴电极107对应有两个连接单元106，每个阳电极108对应有两个连接单元106。 为形成具有图5所示的电熔丝，对照上述图4A所示电熔丝的制造方法，只要改变多晶硅的沉积与开口区域即可实现。
本申请上述实施例中，从平面结构示意图上来看，对于图1A和图2A来说，由于是一对阴阳电极对应左右两条熔断体，因此，只有左右两条熔断体均被熔断方可实现编程。而对于图5和图6来说，由于是一对阴阳电极对应一条熔断体，只要其中一条熔断体被熔断即可实现编程。当然，如果图5和图6的结构也可以理解为是两个电熔丝的结构。
另外，由上述实施例可见，若所述侧壁为两个，则两个所述侧壁上共计设置有两个所述熔断体，两个所述熔断体用于连接在至少一个所述阴电极和至少一个所述阳电极之间。
最后应说明的是：以上实施例仅用以说明本申请实施例的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的精神和范围。

Claims (17)

  1. 一种电熔丝的制造方法，其特征在于，包括：
    提供一半导体衬底，所述半导体衬底包括预设有源区；
    在半导体衬底上形成隔离区，其中，所述隔离区与所述预设有源区之间具有高度差并通过至少一侧壁相连；
    在所述预设有源区上形成阴电极和阳电极；以及
    在所述侧壁上形成用于连接所述阴电极和阳电极的熔断体。
  2. 根据权利要求1所述的方法，其特征在于，所述在半导体衬底上形成隔离区包括：
    自所述半导体衬底的上表面向下形成一凹槽，所述凹槽的底面形成所述隔离区，所述凹槽的侧壁用于连接所述隔离区与所述预设有源区。
  3. 根据权利要求2所述的方法，其特征在于，自所述半导体衬底的上表面向下形成一凹槽包括：通过光刻以及刻蚀自所述半导体衬底的上表面向下形成一凹槽。
  4. 根据权利要求2所述的方法，其特征在于，所述凹槽的底面形成所述隔离区包括：
    在所述凹槽中填满隔离介质；
    去除所述凹槽中的部分隔离介质形成所述隔离区，并使得所述隔离区与所述预设有源区之间具有高度差并通过至少一侧壁相连。
  5. 根据权利要求1所述的方法，其特征在于，在所述侧壁上形成用于连接所述阴电极和阳电极的熔断体包括：
    依次在所述侧壁上形成氧化层、多晶硅层、金属硅化物层，以形成所述熔断体。
  6. 根据权利要求1所述的方法，其特征在于，在所述侧壁上形成氧化层、多晶硅层、金属硅化物层包括：对所述多晶硅层进行刻蚀形成残留或者寄生的多晶硅层，在残留或者寄生的多晶硅层表面形成金属硅化物层。
  7. 根据权利要求1所述的方法，其特征在于，在所述预设有源区分别形成阴电极和阳电极包括：在所述有源区形成氧化层、多晶硅层、金属硅化物层，以形成所述阴电极和所述阳电极。
  8. 根据权利要求1所述的方法，其特征在于，还包括：在所述阴电极和所述阳电极上形成用于与外部电路连接的连接单元。
  9. 根据权利要求5或7所述的方法，其特征在于，所述金属硅化物层包括钛金属硅化物、钴金属硅化物、钨金属硅化物中的至少一种。
  10. 一种电熔丝，其特征在于，包括：半导体衬底、阴电极、阳电极以及电连接所述阴电极和阳电极的熔断体；所述半导体衬底包括预设有源区，所述阴电极和所述阳电极形成在所述预设有源区上；所述半导体衬底上形成有隔离区，所述隔离区与所述预设有源区之间具有高度差并通过至少一侧壁相连，所述熔断体形成在所述侧壁上。
  11. 根据权利要求10所述的电熔丝，其特征在于，所述阴电极、所述阳电极以及所述熔断体均包括氧化层、多晶硅层、金属硅化物层。
  12. 根据权利要求10所述的电熔丝，其特征在于，所述隔离区为通过在口字型凹槽中填充隔离介质形成的隔离区，或者，通过在回字型凹槽中填充隔离介质形成的隔离区。
  13. 根据权利要求12所述的电熔丝，其特征在于，若所述隔离区为通过在口字型凹槽中填充隔离介质形成的隔离区，则形成一个所述隔离区以及一个个预设有源区。
  14. 根据权利要求12所述的电熔丝，其特征在于，所述隔离区为通过在回字型凹槽中填充隔离介质形成的隔离区，则形成两个所述隔离区以及两个所述预设有源区。
  15. 根据权利要求12所述的电熔丝，其特征在于，所述熔断体形成在沿着所述电熔丝的熔断电流方向的至少一侧壁上。
  16. 根据权利要求15所述的电熔丝，其特征在于，若所述侧壁为两个，则两个所述侧壁上共计设置有两个所述熔断体，两个所述熔断体用于连接在至少一个所述阴电极和至少一个所述阳电极之间。
  17. 一种存储单元，其特征在于，包括权利要求10-16任意一项所述的电熔丝。
PCT/CN2018/102311 2018-08-24 2018-08-24 电熔丝及其制造方法、存储单元 WO2020037669A1 (zh)

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