WO2020029226A1 - 场效应器件、反熔丝、随机数生成装置 - Google Patents

场效应器件、反熔丝、随机数生成装置 Download PDF

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WO2020029226A1
WO2020029226A1 PCT/CN2018/099859 CN2018099859W WO2020029226A1 WO 2020029226 A1 WO2020029226 A1 WO 2020029226A1 CN 2018099859 W CN2018099859 W CN 2018099859W WO 2020029226 A1 WO2020029226 A1 WO 2020029226A1
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doped region
field effect
effect device
region
dielectric layer
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PCT/CN2018/099859
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English (en)
French (fr)
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李运宁
沈健
王文轩
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深圳市为通博科技有限责任公司
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Priority to CN201880001135.6A priority Critical patent/CN109075203A/zh
Priority to PCT/CN2018/099859 priority patent/WO2020029226A1/zh
Publication of WO2020029226A1 publication Critical patent/WO2020029226A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions

Definitions

  • the embodiments of the present application relate to the field of semiconductor technology, and in particular, to a field effect device, an anti-fuse, and a random number generating device.
  • the signal conversion is difficult, further leading to higher implementation costs, and increasing the complexity of post-processing, such as the typical need for sensitivity
  • High amplifier circuits are used for digitization and additional error correction compensation circuits, and these circuits themselves are sensitive to environmental parameters, such as temperature, voltage noise, and electromagnetic interference, so it is likely to reduce the reliability of the output results.
  • one of the technical problems solved by the embodiments of the present invention is to provide a field effect device, an anti-fuse, and a random number generating device to overcome or alleviate technical defects in the prior art.
  • An embodiment of the present application provides a field effect device, which includes a dielectric layer, a source terminal doped region, a drain terminal doped region, a gate terminal doped region, and a substrate, wherein the dielectric layer is disposed on the substrate. And the gate terminal doped region; the source terminal doped region and the drain terminal doped region are disposed on the substrate, and the gate terminal doped region and the source terminal are doped respectively.
  • the region and the drain-end doped region form an overlapping region, the overlapping region corresponds to the dielectric layer, and the overlapping region exhibits a low resistance state after its corresponding dielectric layer is punctured.
  • An embodiment of the present application provides an antifuse, which includes a field effect device, and an overlapping area of the field effect device equivalently forms an antifuse capacitor, and each of the overlapping areas equivalently forms an antifuse capacitor,
  • the anti-fuse capacitor exhibits a low-resistance state after its corresponding dielectric layer is broken down to write a one-bit random number to the field effect device according to the low-resistance state.
  • An embodiment of the present application provides a random number generating device, which includes one or more field effect devices to generate one or more bit random numbers.
  • the dielectric layer is disposed between the substrate and the gate terminal doped region; the source terminal doped region and the drain terminal doped region are disposed in all On the substrate, and the gate terminal doped region forms an overlap region with the source terminal doped region and the drain terminal doped region, respectively, and the overlap region corresponds to the dielectric layer, the The overlapping region shows a low resistance state after its corresponding dielectric layer is broken down, so that an anti-fuse can be realized by a field effect device, and further a physical non-clonable technology based on a single-bit random number is simplified, thereby simplifying the implementation. Structure, and further reduced wafer area.
  • FIG. 1 is a schematic structural diagram of a field effect device according to an embodiment of the present application.
  • FIG. 2 is a schematic diagram of the electrical connection of a field effect device in use according to the second embodiment of the present application;
  • FIG. 3 is a schematic diagram of an equivalent circuit model of FIG. 2;
  • FIG. 4 is a schematic diagram of an equivalent circuit model of FIG. 3 when a dielectric layer of a first overlapping region is broken down;
  • FIG. 5 is a schematic diagram of an equivalent circuit model of FIG. 3 when a dielectric layer in a second overlapping region is broken down;
  • FIG. 6 is a schematic structural diagram of a random number generating device according to a third embodiment of the present application.
  • FIG. 7 is a schematic diagram of an equivalent circuit of the random number generating device shown in FIG. 6 in a read state
  • FIG. 8 is a schematic structural diagram of a random number generating device according to a fourth embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of a random number generating device according to a fifth embodiment of the present application.
  • FIG. 1 is a schematic structural diagram of a field effect device according to an embodiment of the present application. As shown in FIG. 1, in this embodiment, two overlapping regions (a first overlapping region and a second overlapping region described below) are formed as an example.
  • the field effect device includes a gate terminal doped region 101 and a dielectric layer. 102, source region 103, drain terminal 104 and a doped region of the substrate 105, the dielectric layer 102 may be a gate oxide layer, such as SiO 2.
  • the dielectric layer 102 is disposed between the substrate 105 and the gate-end doped region 101; the source-end doped region 103 and the drain-end doped region 104 are disposed on the substrate 105.
  • the gate-end doped region 101 and the source-end doped region 103 form a first overlap region A1
  • the gate-end doped region 101 and the drain-end doped region 104 form a second overlap Region A2
  • the first overlapping region A1 and the second overlapping region A2 each correspond to a portion of the dielectric layer 102.
  • the first overlap region A1 and the second overlap region A2 show a low resistance state after the corresponding dielectric layer 102 is broken down, and the first overlap region A1 and the second overlap region A2 Before its corresponding dielectric layer 102 is broken down, it shows a high resistance state.
  • the high-resistance state and the low-resistance state are relative states exhibited by the first overlapping region and the second overlapping region before and after breakdown, and are not absolutely limited.
  • the source-side doped region 103 and the drain-side doped region 104 have a symmetrical relationship with reference to the centerline of the substrate 105 in the vertical direction.
  • the symmetrical relationship between the source-side doped region 103 and the drain-side doped region 104 includes at least one of the following: size symmetry, doping concentration, and symmetry forming a connection relationship with an external circuit.
  • the first overlapping area A1 and the second overlapping area A2 have a symmetrical relationship.
  • the first overlapping area and the first overlapping area A2 have a symmetrical relationship.
  • the dielectric layers 102 corresponding to the two overlapping areas have different characteristic parameters, which are related to the randomness of the formation process, so that only one of the two overlapping areas can be penetrated.
  • the characteristic parameter includes at least one of a thickness characteristic, a dense characteristic, and a defect characteristic of the dielectric layer 102.
  • the dense feature is used to describe the density of the dielectric layer 102
  • the defect feature is used to describe the defects of the dielectric layer 102, such as impurities, uniformity, and the like.
  • the channel width is used to prevent or prevent a conductive channel from being formed between the source-side doped region 103 and the drain-side doped region 104, or only Form a weaker conductive channel.
  • a field effect device is NMOS, for example, if a positive voltage is applied to the gate terminal doped region, it is possible to avoid the formation of electron accumulation regions between the source terminal and drain terminal doped regions or to form fewer electrons.
  • the electron accumulation area is called conductive communication.
  • the width of the gate-end doped region 101 can be controlled during the manufacturing process, so that a set trench is provided between the source-end doped region 103 and the drain-end doped region 104.
  • the channel width further prevents a conductive channel from being formed between the source-side doped region 103 and the drain-side doped region 104 when the field effect device is in a programming mode, thereby avoiding the conductive channel and the gate 101 A strong electric field distribution is formed between them.
  • the electric field strength at the first overlapping area A1 and the second overlapping area A2 is greater than the electric field strength at the conductive channel, so that the The dielectric layer 102 at the first overlap region A1 or the second overlap region A2 is punctured before the dielectric layer 102 at the conductive channel.
  • the first overlapping region A1 shows a low resistance state after the corresponding dielectric layer 102 is broken down, and the second overlapping region A2 is in its The corresponding dielectric layer 102 is not penetrated.
  • the second overlapping region A2 exhibits a low-resistance state after the corresponding dielectric layer 102 is punctured, and the first overlapping region A2 is not punctured.
  • the second overlap region A2 is The strength of the electric field is reduced, so that the dielectric layer 102 corresponding to the second overlapping region A2 is not penetrated; or, after the dielectric layer 102 corresponding to the second overlapping region A2 is penetrated, The electric field strength of the first overlapping area A1 is reduced so that the corresponding dielectric layer 102 is not penetrated.
  • the triangular structures on both sides of the gate terminal doped region 101 are used for protecting the sidewalls of SiO 2 .
  • FIG. 2 is a schematic diagram of the electrical connection of a field effect device in use according to an embodiment of the present application; as shown in FIG. 2, for a gate end doped region 101, a source end doped region 103, and a drain end doped region in a field effect device 104.
  • the gate terminal doped region 101 is electrically connected to a first voltage
  • the source terminal doped region 103 is connected to a second voltage
  • the drain terminal doped region 104 is electrically connected to a third voltage GND.
  • the substrate 105 is electrically connected to a fourth voltage.
  • FIG. 2 is a schematic diagram of the electrical connection of a field effect device in use according to an embodiment of the present application; as shown in FIG. 2, for a gate end doped region 101, a source end doped region 103, and a drain end doped region in a field effect device 104.
  • the gate terminal doped region 101 is electrically connected to a first voltage
  • the source terminal doped region 103 is connected to a second voltage
  • the first voltage is provided by the voltage source V 1
  • the second voltage and the third voltage are multiplexed and connected to the same level, here is shared GND
  • the fourth voltage is provided by a voltage source V 2 .
  • the source voltage V and the voltage source is adjustable. 1, respectively, the voltage value V 2 according to the actual demand, to control the first overlapping area A1
  • the corresponding dielectric layer 102 is broken down, or the dielectric layer 102 corresponding to the second overlapping area A2 is controlled to be broken down.
  • the gate-end doped region 101 is connected to the gate end doped region 101 through a current limiting resistor R s or other current limiting device.
  • the first voltage connection when the dielectric layer 102 corresponding to one of the first overlapping region and the second overlapping region is broken down, the electric field intensity corresponding to the other overlapping region is rapidly reduced, thereby preventing the other overlapping region
  • the dielectric layer 102 corresponding to the overlap region is broken down, thereby better ensuring that only the dielectric layer 102 corresponding to the overlap region in the first overlap region and the second overlap region is broken down.
  • FIG. 3 is a schematic diagram of an equivalent circuit model of FIG. 2.
  • the first overlapping area and the second overlapping area are equivalently described as a capacitor
  • the equivalent circuit model is a capacitor-resistor network as a whole.
  • the gate-end doped region and the source-end doped region of the first overlapping region may be respectively equivalent to two electrode plates, and since the source terminal is doped at the source terminal, A dielectric layer such as a gate oxide layer is disposed between the doped region and the drain-end doped region. Therefore, the first overlapping region can be effectively equivalent to the first capacitor C gs ; similarly, the second overlapping region is equivalent to the second capacitor C gd , and the source terminal doped region 103 and the drain terminal are doped.
  • the conductive channel between the hetero-regions 104 is equivalent to a resistance R c .
  • the first capacitor C gs and the second capacitor C gd are parallel plate capacitors.
  • FIG. 4 is a schematic diagram of the equivalent circuit model of FIG. 3 when the dielectric layer of the first overlapping region is broken down.
  • the source terminal doped region 103 and drain terminal doped region 104 are applied.
  • the electric field strength of the first overlapping region and the second overlapping region is relatively strong, and relatively easy or can be preferentially broken down. Due to the randomness in the manufacturing process, the first overlap area A1 and the second overlap area A2 differ in feature parameters. As shown in FIG.
  • the first overlap area A1 The dielectric layer 102 is broken down, and the dielectric layer 102 in the second overlapping area A2 is not broken down, that is, the first capacitor C gs is broken down, so that the first capacitor C gs is equivalent to a short circuit.
  • the first overlapping area A1 is in a low-resistance state
  • the second overlapping area A2 is in a high-resistance state.
  • the dielectric layer 102 corresponding to the first overlap region is broken down, the source-side doped region 103 is grounded, so that the voltage of the gate-end doped region 101 is pulled down, which further attenuates the second overlap region A2.
  • the dielectric layer 102 in the second overlapping region is not broken down, that is, the second capacitor C gd is equivalent to an open circuit, and continues to be in a high-impedance state, thereby completing the programming operation of a single field effect device.
  • FIG. 5 is a schematic diagram of the equivalent circuit model of FIG. 3 when the dielectric layer of the second overlapping region is broken down.
  • the dielectric layer of the first overlapping area A1 is not penetrated, and the dielectric layer of the second overlapping area A2 is penetrated.
  • the first overlapping region A1 is in a high-resistance state, and the second overlapping region A2 is in a low-resistance state.
  • the second capacitor C gd is equivalent to a short circuit.
  • the second overlapping area A2 is in a low resistance state.
  • the voltage of the gate-end doped region 101 is pulled down, which further attenuates the electric field strength of the first overlapping region A1, and finally makes the dielectric of the first overlapping region A1.
  • the layer is not broken down, that is, the first capacitor C gs is equivalent to an open circuit and is in a high-impedance state, thereby completing the programming operation of a single field effect device.
  • FIG. 6 is a schematic structural diagram of a random number generating device according to Embodiment 3 of the present application.
  • the random number generating device includes a field effect device as shown in FIG. 1 as an example, and a corresponding one can be generated. One digit random number.
  • the source terminal of the field effect device M1 is electrically connected to the second voltage GND through the first switching unit S1, and the drain terminal of the field effect device M1 is electrically connected to the third voltage GND through the second switching unit S2.
  • the gate terminal of the field effect device M1 is electrically connected to the first voltage Vapply (equivalent to the above-mentioned V 1 ) through the third switching unit S3 to control the dielectric layer corresponding to the first overlapping region or the second overlapping region.
  • the second and third voltages to the ground GND according to the present embodiment, the first voltage is a voltage Vapply, the fourth voltage provided by the voltage source V 2.
  • the first switching unit S 1 is a first transistor
  • the second switching unit S 2 is a second transistor
  • the grid of the first transistor and the second transistor is
  • the source terminal of the first transistor and the source terminal of the second transistor are respectively connected to the second voltage GND and the third voltage GND, and the drains of the first transistor and the second transistor are connected to each other.
  • the terminals are respectively connected to the source terminal and the drain terminal of the field effect device M1.
  • a drain of the first transistor is further connected to a first output unit, and the first output unit is configured to output a voltage of the drain of the first transistor, and the second transistor
  • a second output unit is also connected to the drain end of the tube, and the second output unit is configured to output the voltage of the drain end of the second transistor.
  • the first output unit is a first inverter INV1 and the second output unit is a second inverter INV2 to output a voltage after the enhancement process.
  • the first output unit and the second output unit are not limited to being implemented by an inverter.
  • the third switching unit S 3 is a third transistor, and the third transistor is connected to the gate terminal of the field effect device M1.
  • a drain terminal of the third transistor is connected to the gate terminal of the field effect device M1, and a source terminal of the third transistor is connected to the first voltage.
  • a second control signal V SW2 is connected to the gate ends of the first transistor and the second transistor, respectively.
  • the gate terminal of the third transistor is connected to a first control signal V SW1 .
  • the first control signal V SW1 is at a high level, so that the first transistor and the second transistor work in a low-resistance state and behave as switches. That is, the first transistor can be controlled by controlling the first control signal V SW1 2.
  • the second transistor is turned on;
  • the second control signal V SW2 is at a low level, so that the third transistor is in a sub-threshold state and behaves as a resistor, which is functionally equivalent to the current-limiting resistor R S.
  • the two different state combinations with the second overlapping region can respectively represent 1 or 0, that is, the generation of a one-bit random number is completed, and the one-bit random number can be defined as 1 or 0 according to the needs used later.
  • the first triode and the second triode are operated in a sub-threshold state, and the high-resistance resistor is displayed;
  • the third transistor is turned on, which appears as a switch, and the third transistor is turned on.
  • FIG. 7 is a schematic diagram of an equivalent circuit of the random number generating device shown in FIG. 6 in a read state; as shown in FIG. 7, the first overlapped region corresponding to the dielectric layer to be penetrated is equivalent to a resistance R b without being hit.
  • the second overlapping region corresponding to the dielectric layer is equivalent to the resistance R o
  • R g is the equivalent resistance of the first triode and the second triode in a sub-threshold state
  • R s is the On-resistance, the resistance value is small enough, not considered. Since the resistance R o is close to infinity and approximates to an open circuit, and the value of the resistance R b is small, it exists in this equivalent circuit: R b ⁇ R g ⁇ R o .
  • the read voltage when the read voltage is based on the above assumptions, when the read voltage V read is V dd , the input of the first inverter INV1 is close to the voltage V dd , and its first output OUT is because the resistance R b is much smaller than R g . 1 was 0V; and because the resistance is much greater than R o R g, a second inverter INV2 input voltage is close to 0V, the second output OUT 2 is V dd. If the positions of Rb and Ro are exchanged, the first output OUT 1 is high and the second output OUT 2 is low.
  • the combination of OUT 1 and OUT 2 can be defined as random numbers 1 or 0 according to requirements.
  • the system uses more field effect devices and corresponding circuits, more random numbers can be generated.
  • FIG. 8 is a schematic diagram of an array form of the random number generating device according to the embodiment of the present application.
  • the random number generating device includes six field effect devices (M 11 , M 12 , M 21 , M 22 , M 32 , M 42 , M 52 , M 62 ), the six field effect devices are arranged in an array of two columns and three rows to generate a six-bit random number.
  • the size of the array in this embodiment is only for display purposes. The actual size of the array can be customized according to requirements.
  • the field effect devices in each column share a group of inverters, namely a first output unit and a second output unit, and share a group of transistors, namely a first transistor and a second transistor.
  • each of the field effect devices M11, M21, and M31 in the first column is connected to the source switch unit S11 (equivalent to the first switch unit), and the field effect device in the first column
  • the drain terminal of each field effect device in M11, M21, and M31 is connected to the drain switch unit S12 (equivalent to the above-mentioned second switch unit); each field effect device in the first column of field effect devices M11, M21, and M31
  • a gate terminal switching unit (equivalent to the above-mentioned third switching unit) is connected to the gate terminal, that is, a gate terminal switching unit S113 is connected to the gate terminal of the field effect device M11, and a gate terminal switching unit S213 is connected to the gate terminal of the field effect device M21.
  • a gate terminal of the field effect device M31 is connected to a gate terminal switching unit S313.
  • the source terminals of the field effect devices M12, M22, and M32 in the second column are all connected to the source switch unit Mb3 (equivalent to the above-mentioned first switch unit), and each of the field effect devices M12, M22, and M32 in the second column is connected.
  • the drain terminal of each field effect device is connected to the drain terminal switching unit Mb4 (equivalent to the above-mentioned second switching unit); the gate terminal of each field effect device in the second column of field effect devices M12, M22, and M32 is connected to a gate Terminal switching unit (equivalent to the above third switching unit), that is, the gate terminal of the field effect device M12 is connected to the gate terminal switching unit S123, the gate terminal of the field effect device M23 is connected to the gate terminal switching unit S223, and the gate of the field effect device M32 A gate terminal switching unit S323 is connected to the terminal.
  • the gate terminal switching units (S113 / S213 / S313 or S123 / S223 / S323) in the same column are triodes
  • the gate terminals of the triodes in the same column are electrically connected to the same gate terminal control signal (equivalent to the first A control signal) control, that is, the gate terminal of the gate terminal switching units S113 / S213 / S313 is controlled by the same gate terminal control signal Vgsw1
  • the gate terminal of the gate terminal switching units S123 / S223 / S323 is controlled by the same gate terminal control signal Vgsw2.
  • the substrates of all the field effect devices in the same row are electrically connected to the same fourth voltage. As shown in FIG. 8, the substrates of the field effect transistors M11 and M12 in the same row are all connected to the fourth voltage. Vb1, the substrates of the field effect tubes M21 and M22 in the same row are all connected to the fourth voltage Vb2, and the substrates of the field effect tubes M31 and M32 in the same row are all connected to the fourth voltage Vb3.
  • the source terminals of the gate-side switch units in the same row are electrically connected to the same first voltage.
  • the sources of the gate-side switch units S113 and S123 in the same row are electrically connected. Terminals are electrically connected to the first voltage Vg1, the source terminals of the gate terminal switch units S213 and S223 in the same row are electrically connected to the first voltage Vg2, and the source terminals of the gate terminal switch units S313 and S323 in the same row are all connected to the first voltage Vg3 is electrically connected.
  • FIG. 9 is another schematic diagram of an array structure of the random number generating device according to the embodiment of the present application. As shown in FIG. 9, in this embodiment, the random number generating device is also arranged in an array of two columns and three rows. The difference from FIG. 8 above is that in the above embodiment, the gate-end switch units in the same column are commonly connected to the same gate-end control signal; in this embodiment, the gate-end switch units in the same row are commonly connected to the same control signal.
  • the gate switch units S113 and S123 in the first row are connected to the same gate control signal Vgsw1
  • the gate switch units S213 and S223 in the second row are connected to the same gate control signal Vgsw2
  • the gate of the third row The terminal switching units S213 and S223 are connected to the same gate terminal control signal Vgsw3 control signal.
  • An embodiment of the present application further provides a method for manufacturing a field effect device, which includes the following steps:
  • an active region is formed by processes such as light irradiation, etching, and ion implantation, and the active region needs to be drawn out as a substrate electrode in a subsequent process to connect the fourth voltage.
  • the active area may be indicated by reference numeral 105 in FIG. 1.
  • the gate electrode in order to prevent the source terminal and the drain terminal from forming a conductive channel when the field effect device is in a programming mode, it is preferable that the width of the gate electrode meets this requirement.
  • the gate electrode is a conductive electrode formed on the gate terminal doped region 101.
  • an extension region is formed in a region where the source end and the drain end are located by using a technique of light irradiation and ion implantation.
  • the extension area is an area where the reference numeral 103/104 in FIG. 1 is located.
  • a source terminal and a drain terminal are formed, and the gate terminal doped region and the source terminal doped region and the drain terminal doped region form an overlapped region, respectively.
  • a source terminal and a drain terminal are formed by ion implantation in a large dose.
  • the source terminal (also referred to as S) includes at least a source electrode, a source terminal doped region, and the like
  • the drain terminal (also referred to as D) includes at least a drain electrode and a drain terminal doped region
  • the gate terminal also referred to as G includes at least a gate electrode Gate end doped region.
  • the first overlapping region can be understood as a region where the source-side doped region and the gate-side doped region overlap and a structure formed by the dielectric layer of the region.
  • the second overlapping region can be It is understood as the structure formed by the overlapped region between the drain-end doped region and the gate-end doped region and the dielectric layer of the region.
  • An embodiment of the present application further provides an antifuse, which includes a field effect device described in any one of the foregoing embodiments, and each of the overlapping regions is equivalent to form an antifuse capacitor, and the antifuse capacitor After the corresponding dielectric layer is broken down, it shows a low-resistance state to write a random number to the anti-fuse according to the low-resistance state.
  • an antifuse which includes a field effect device described in any one of the foregoing embodiments, and each of the overlapping regions is equivalent to form an antifuse capacitor, and the antifuse capacitor After the corresponding dielectric layer is broken down, it shows a low-resistance state to write a random number to the anti-fuse according to the low-resistance state.
  • the description is made by taking the formation of the first overlapping region and the second overlapping region simultaneously as an example.
  • the specific shape of the overlapping area can be flexibly set as required.
  • the dielectric layer of the field effect device is disposed between the substrate and the gate terminal doped region; the source terminal doped region and the drain terminal doped region are disposed.
  • the gate terminal doped region forms an overlap region with the source terminal doped region and the drain terminal doped region, respectively, and the overlap region corresponds to the dielectric layer,
  • the overlapped region exhibits a low-resistance state after its corresponding dielectric layer is broken down, so that anti-fuse can be realized through a MOSFET, further physical non-clonable technology, thereby simplifying the implementation structure and further reducing the crystal Round area.
  • the field effect device used is not limited to a specific type of MOSFET device, that is, both NMOS and PMOS may be used.
  • the device embodiments described above are only schematic, and the modules described as separate components may or may not be physically separated, and the components displayed as modules may or may not be physical modules, that is, may be located One place, or can be distributed to multiple network modules. Some or all of the modules may be selected according to actual needs to achieve the objective of the solution of this embodiment. Those of ordinary skill in the art can understand and implement without creative labor.
  • each embodiment can be implemented by means of software plus a necessary universal hardware platform, and of course, also by hardware.
  • the above-mentioned technical solution in essence or a part that contributes to the existing technology may be embodied in the form of a software product, and the computer software product may be stored in a computer-readable storage medium, the computer-readable record A medium includes any mechanism for storing or transmitting information in a form readable by a computer (eg, a computer).
  • machine-readable media include read-only memory (ROM), random-access memory (RAM), magnetic disk storage media, optical storage media, flash storage media, electrical, optical, acoustic, or other forms of propagation signals (e.g., carrier waves , Infrared signals, digital signals, etc.), the computer software product includes a number of instructions to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to execute various embodiments or certain parts of the embodiments Methods.
  • the embodiments of the embodiments of the present invention may be provided as a method, an apparatus (device), or a computer program product. Therefore, the embodiments of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Moreover, the embodiments of the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.
  • computer-usable storage media including but not limited to disk storage, CD-ROM, optical storage, etc.
  • Embodiments of the present invention are described with reference to flowcharts and / or block diagrams of methods, apparatuses (devices) and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowcharts and / or block diagrams, and combinations of processes and / or blocks in the flowcharts and / or block diagrams can be implemented by computer program instructions.
  • These computer program instructions may be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing device to produce a machine, so that the instructions generated by the processor of the computer or other programmable data processing device are used to generate instructions Means for implementing the functions specified in one or more flowcharts and / or one or more blocks of the block diagrams.
  • These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to work in a particular manner such that the instructions stored in the computer-readable memory produce a manufactured article including an instruction device, the instructions
  • the device implements the functions specified in one or more flowcharts and / or one or more blocks of the block diagram.
  • These computer program instructions can also be loaded on a computer or other programmable data processing device, so that a series of steps can be performed on the computer or other programmable device to produce a computer-implemented process, which can be executed on the computer or other programmable device.
  • the instructions provide steps for implementing the functions specified in one or more flowcharts and / or one or more blocks of the block diagrams.

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Abstract

本申请实施例提供了一种场效应器件、反熔丝、随机数生成装置，场效应器件包括介质层、源端掺杂区、漏端掺杂区、栅端掺杂区以及衬底，其中，所述介质层设置在所述衬底与所述栅端掺杂区之间；所述源端掺杂区及所述漏端掺杂区设置在所述衬底上，且所述栅端掺杂区分别与所述源端掺杂区和所述漏端掺杂区形成一交叠区，所述交叠区对应有所述介质层，所述交叠区在其对应的所述介质层被击穿后呈现低阻态，从而使得可通过一个场效应器件实现基于一位随机数的反熔丝，进一步实现物理不可克隆技术，从而简化了实现结构，以及进一步缩减了晶圆面积。

Description

场效应器件、反熔丝、随机数生成装置 技术领域
本申请实施例涉及半导体技术领域，尤其涉及一种场效应器件、反熔丝、随机数生成装置。
背景技术
在半导体制造过程中，利用器件在微观尺度上物理参数的随机性或制造工艺的波动来产生具有特征唯一性的产品，但是，由于这些随机特征的产生是不能被完全控制的，即使是原始的制造商也不能制造出具有同样特征的两个产品，简单描述为不可能被复制，或者物理不可克隆技术(Physical Unclonable Function，简称PUF)。虽然这种不可复制或者不可克隆现象在半导体制造中会被认为是一个缺陷，但是却可以作为一个优势应用于器件唯一性的身份识别信息。
随着物联网(Internet of Things，简称IoT)的快速发展，每天都有大量的不同类型的电子设备接入网络，而为每个设备提供一个唯一的、不可被复制的、不可预测的身份信息(ID)变得尤为重要，因此，信息安全成为亟待解决的技术问题。但是，对于解决信息安全的问题来说，上述物理不可克隆技术刚好可以产生具有特征唯一性的产品，使得产品具有“指纹”。
根据物理不可克隆技术的类型，一般会有一种或多种激励(challenges)方法来产生响应特征(responses)，对于同类型的产品，同样的物理不可克隆技术，同样的激励(challenge)，不同的产品，因为制造它们的工艺波动是不一样的，导致这些产品的响应特征(response)也是不一样的。在信号处理方面，这些响应特征是需要被转换成电路可识别的电信号，才能被进一步应用。但是，由于响应特征是基于微小的物理随机产生的，造成响应特征之间的差别也是微小的，由此造成信号转换存在一定的困难。例如早期的基于光学系统或静态存储(Static RAM，简称SRAM)结构的物理不可克隆技术，信号转换难度大，进一步导致实现成本较高，以及增加后处理的复杂度等问题，比如典型的需要灵敏度高的放大电路来进行数字化和额外的纠错补偿电路，而这些电路本身又是敏感于环境参数的，例如温度，电压噪声，电磁干扰，因此很大可能降低了 输出结果的可靠性。
为此，业界提出了基于反熔丝(anti-fuse)的物理不可克隆技术方案，但是由于一般的物理不可克隆技术至少需要三个MOSFET或是三个以上的MOSFET才能实现，由此导致物理不可克隆技术的实现结构较为复杂，进一步导致晶圆面积占用较大。
发明内容
有鉴于此，本发明实施例所解决的技术问题之一在于提供一种场效应器件、反熔丝、随机数生成装置，用以克服或者缓解现有技术中技术缺陷。
本申请实施例提供了一种场效应器件，其包括介质层、源端掺杂区、漏端掺杂区、栅端掺杂区以及衬底，其中，所述介质层设置在所述衬底与所述栅端掺杂区之间；所述源端掺杂区及所述漏端掺杂区设置在所述衬底上，且所述栅端掺杂区分别与所述源端掺杂区和所述漏端掺杂区形成一交叠区，所述交叠区对应有所述介质层，所述交叠区在其对应的所述介质层被击穿后呈现低阻态。
本申请实施例提供了一种反熔丝，其包括一个场效应器件，场效应器件的交叠区等效形成反熔丝电容，所述每一交叠区等效形成一反熔丝电容，所述反熔丝电容在其对应的介质层被击穿后呈现低阻态以根据所述低阻态向所述场效应器件写入一位随机数。
本申请实施例提供了一种随机数生成装置，其包括一个或多个场效应器件，以生成一位或者多位随机数。
本申请实施例提供的技术方案中，由于所述介质层设置在所述衬底与所述栅端掺杂区之间；所述源端掺杂区及所述漏端掺杂区设置在所述衬底上，且所述栅端掺杂区分别与所述源端掺杂区和所述漏端掺杂区形成一交叠区，所述交叠区对应有所述介质层，所述交叠区在其对应的所述介质层被击穿后呈现低阻态，从而使得可通过一个场效应器件实现反熔丝，进一步实现基于一位随机数的物理不可克隆技术，从而简化了实现结构，以及进一步缩减了晶圆面积。
附图说明
后文将参照附图以示例性而非限制性的方式详细描述本申请实施例的一些具体实施例。附图中相同的附图标记标示了相同或类似的部件或部分。本领域技术人员应该理解，这些附图未必是按比例绘制的。附图中：
图1为本申请实施例一场效应器件的结构示意图；
图2为本申请实施例二场效应器件在使用时的电气连接示意图；
图3为图2的等效电路模型示意图；
图4为第一交叠区的介质层被击穿时图3的等效电路模型示意图；
图5为第二交叠区的介质层被击穿时图3的等效电路模型示意图；
图6为本申请实施例三随机数生成装置的结构示意图；
图7为图6所示随机数生成装置在读取状态时的等效电路示意图；
图8为本申请实施例四随机数生成装置的结构示意图；
图9为本申请实施例五随机数生成装置的结构示意图。
具体实施方式
实施本发明实施例的任一技术方案必不一定需要同时达到以上的所有优点。
为了使本领域的人员更好地理解本发明实施例中的技术方案，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅是本发明实施例一部分实施例，而不是全部的实施例。基于本发明实施例中的实施例，本领域普通技术人员所获得的所有其他实施例，都应当属于本发明实施例保护的范围。
下面结合本发明实施例附图进一步说明本发明实施例具体实现。
图1为本申请实施例一场效应器件的结构示意图。如图1所示，本实施例中，以形成两个交叠区(下述第一交叠区、第二交叠区)为例，该场效应器件包括栅端掺杂区101、介质层102、源端掺杂区103、漏端掺杂区104以及衬底105，所述介质层102可以是栅氧化层，比如SiO 2。其中，所述介质层102设置在所述衬底105与所述栅端掺杂区101之间；所述源端掺杂区103及所述漏端掺杂区104设置在所述衬底105上，且所述栅端掺杂区101与所述源端掺杂区103形成第一交叠区A1，所述栅端掺杂区101与所述漏端掺杂区104形成第二交叠区A2，所述第一交叠区A1和第二交叠区A2各自对应有部分所述介质层102。所述第一交叠区A1和第二交叠区A2在其对应的所述介质层102被击穿后呈现低阻态，而在所述第一交叠区A1和第二交叠区A2在其对应的所述介质层102被击穿前呈现高阻态。
需要说明的是，本实施例中，高阻态、低阻态是第一交叠区、第二交叠区在被击穿前后表现出的相对状态，并非绝对限定。
本实施例中，所述源端掺杂区103与所述漏端掺杂区104以所述衬底105在竖直方向上的中心线为参考呈对称关系。具体地，所述源端掺杂区103与所述漏端掺杂区104之间的对称关系包括下述中的至少一种：尺寸对称、掺杂浓度、与外部电路形成连接关系的对称。
进一步地，本实施例中，理论上所述第一交叠区A1与所述第二交叠区A2呈对称关系，但是，由于制造过程中的随机性使得所述第一交叠区和第二交叠区各自对应的所述介质层102具有不同的特征参数，该特征参数又关联于形成工艺的随机性，从而使得两个交叠区中只有一个可被击穿。具体地，所述特征参数包括所述介质层102的厚度特征、致密特征、瑕疵特征中的至少一个。本实施例中，致密特征用于描述介质层102的密度大小，所述瑕疵特征用于描述介质层102的瑕疵，比如杂质，均匀性等。
本实施例中，所述源端掺杂区103与所述漏端掺杂区104之间具有设定的沟道宽度。具体地，在所述场效应器件处于编程模式时，所述沟道宽度用于避免或防止所述源端掺杂区103和所述漏端掺杂区104之间形成导电沟道，或只形成较弱的导电沟道，即比如以场效应器件为NMOS为例，若在栅端掺杂区加载正电压，避免源端和漏端掺杂区之间直接形成电子积累区或者形成较少的电子积累区，该电子积累区即称为导电沟通。在具体应用场景中，可以通过在制造过程中控制所述栅端掺杂区101的宽度，从而使得所述源端掺杂区103与所述漏端掺杂区104之间具有设定的沟道宽度，进一步防止在所述场效应器件处于编程模式时所述源端掺杂区103和所述漏端掺杂区104之间形成导电沟道，从而避免导电沟道与所述栅极101之间形成较强的电场分布。
本实施例中，当场效应器件要处于编程模式时，所述第一交叠区A1处和第二交叠区A2处的电场强度大于所述导电沟道处的电场强度，从而可以使得所述第一交叠区处A1或者第二交叠区处A2的介质层102先于导电沟道处的介质层102被击穿。
本实施例中，当场效应器件要处于编程模式时，所述第一交叠区A1在其对应的所述介质层102被击穿后呈现低阻态，所述第二交叠区A2在其对应的所述介质层102未被击穿。或者，所述第二交叠区A2在其对应的所述介质层102被击穿后呈现低阻态，所述第一交叠区在其对应的所述介质层102未被击穿。
具体地，在一应用场景中，当场效应器件要处于编程模式时，所述第一交叠区A1在其对应的所述介质层102被击穿后，使得所述第二交叠区A2的电场 强度降低，进而使所述第二交叠区A2对应的所述介质层102未被击穿；或者，所述第二交叠区A2在其对应的所述介质层102被击穿后，降低所述第一交叠区A1的电场强度使其对应的所述介质层102未被击穿。
上述图1中，栅端掺杂区101两侧的三角形结构为用于进行侧壁保护SiO 2。
图2为本申请实施例中场效应器件在使用时的电气连接示意图；如图2所示，对于场效应器件中的栅端掺杂区101、源端掺杂区103、漏端掺杂区104、衬底105来说，所述栅端掺杂区101电连接第一电压，所述源端掺杂区103连接至第二电压，所述漏端掺杂区104电连接第三电压GND，所述衬底105电连接第四电压。具体地，为实现本发明的PUF功能，如图2中所示，第一电压由电压源V 1提供，第二电压和第三电压为复用连接到同一电平，此处为共享GND，第四电压由电压源V 2提供。另外，为实现对栅端掺杂区101和衬底105的单独控制，所述电压源V 1与电压源V 2的电压值根据实际需求分别可调，以控制所述第一交叠区A1对应的所述介质层102被击穿，或者，控制所述第二交叠区A2对应的所述介质层102被击穿。
进一步地，为了实现第一交叠区A1对应的介质层102或者第二交叠区A2对应的介质层102被击穿，栅端掺杂区101通过限流电阻R s或其他限流器件与第一电压连接，当第一交叠区和第二交叠区其中之一对应的介质层102被击穿时，使得另一交叠区对应的电场强度较快降低，从而防止该另一交叠区对应的介质层102被击穿，从而较好的保证了所述第一交叠区和第二交叠区中只有一个交叠区对应的介质层102被击穿。
图3为图2的等效电路模型示意图。本实施例中，以将第一交叠区和第二交叠区等效为电容为例进行说明，该等效电路模型整体上为电容电阻网络。
参见图3所示，对于所述第一交叠区的所述栅端掺杂区和所述源端掺杂区来说，其可以分别相当于两个极板，而由于在所述源端掺杂区和所述漏端掺杂区之间设置有介质层如栅氧化层。因此，第一交叠区实际上可以等效为第一电容C gs；同样地，第二交叠区等效为第二电容C gd，所述源端掺杂区103和所述漏端掺杂区104之间的导电沟道等效为电阻R c。
本实施例中，第一电容C gs和第二电容C gd为平行板电容。
以下参考图4到图5对第一交叠区或者第二交叠区被击穿的情形分别进行说明。图4和图5中以制造工艺的随机性造成第一交叠区和第二交叠区在特征参数上存在随机差异，导致在各自对应的介质层被击穿时也同样存在随机性。
图4为第一交叠区的介质层被击穿时图3的等效电路模型示意图。再结合 上述图2所示，当栅端掺杂区101、源端掺杂区103、漏端掺杂区104加载上对应电压时，相对于源端掺杂区103和漏端掺杂区104之间的导电沟道来说，所述第一交叠区和第二交叠区的电场强度相对较强，相对来说，容易或者可被优先击穿。而由于制造工艺上的随机性，使得第一交叠区A1和第二交叠区A2在特征参数上存在差别，从而如图4所示，在一种随机情形下，第一交叠区A1的介质层102被击穿，而第二交叠区A2的介质层102未被击穿，即第一电容C gs被击穿，使得第一电容C gs相当于短路。此时，第一交叠区A1处于低阻状态，而第二交叠区A2处于高阻状态。
当第一交叠区对应的介质层102被击穿时，由于所述源端掺杂区103接地，从而使得栅端掺杂区101的电压被拉低，进一步衰减了第二交叠区A2的电场强度，最终使得所述第二交叠区的介质层102未被击穿，即第二电容C gd相当于断路，继续处于高阻状态，从而完成单个场效应器件的编程操作。
图5为第二交叠区的介质层被击穿时图3的等效电路模型示意图。结合上述图2以及图5所示，在另外一种情形下，第一交叠区A1的介质层未被击穿，而第二交叠区A2的介质层被击穿。此时，第一交叠区A1为高阻状态，而第二交叠区A2为低阻状态。
当第二交叠区A2对应的介质层被击穿时，使得第二电容C gd相当于短路，此时，第二交叠区A2处于低阻状态。由于所述漏端掺杂区104接地，从而使得栅端掺杂区101的电压被拉低，进一步衰减了第一交叠区A1的电场强度，最终使得所述第一交叠区A1的介质层未被击穿，即第一电容C gs相当于断路，处于高阻状态，从而完成单个场效应器件的编程操作。
图6为本申请实施例三随机数生成装置的结构示意图；如图6所示，本实施例中，以随机数生成装置包括一个上述图1所示的场效应器件为例，对应的可以生成一位随机数。
本实施例中，所述场效应器件M1的源端通过第一开关单元S1电连接第二电压GND，所述场效应器件M1的漏端通过第二开关单元S2电连接第三电压GND，所述场效应器件M1的栅端通过第三开关单元S3电连接第一电压Vapply(相当于上述V 1)，以在控制所述第一交叠区或者第二交叠区对应的所述介质层被击穿时，使得所述第一开关单元S1以及第二开关单元S2呈现低阻态，并对应地使得所述第三开关单元S3呈现高阻态，以作限流作用。
具体地，本实施例中，第二电压和第三电压为地GND，第一电压为电压 Vapply，第四电压由电压源V 2提供。
本实施例中，所述第一开关单元S 1为第一三极管，第二开关单元S 2为第二三极管，所述第一三极管与所述第二三极管的栅端互连且第一三极管的源端和第二三极管的源端分别连接所述第二电压GND和第三电压GND，所述第一三极管和第二三极管的漏端分别连接到所述场效应器件M1的源端和漏端。
本实施例中，所述第一三极管的漏端还连接有第一输出单元，所述第一输出单元用于输出所述第一三极管的漏端的电压，所述第二三极管的漏端还连接有第二输出单元，所述第二输出单元用于输出所述第二三极管的漏端的电压。
本实施例中，所述第一输出单元为第一反相器INV1，所述第二输出单元为第二反相器INV2，以输出增强处理后的电压。但是，需要说明的是，第一输出单元、第二输出单元并不限定为通过反相器来实现。
本实施例中，第三开关单元S 3为第三三极管，所述第三三极管与所述场效应器件M1的所述栅端连接。
本实施例中，所述第三三极管的漏端与所述场效应器件M1的所述栅端连接，所述第三三极管的源端连接所述第一电压。
为实现上述第一三极管、第二三极管、第三三极管的通断控制，分别在第一三极管、第二三极管的栅端连接有第二控制信号V SW2，第三三极管的栅端连接有第一控制信号V SW1。
在本实施例的上述电路基础上，对图1的随机数生成过程说明如下：
通过第一控制信号V SW1为高电平，使得第一三极管、第二三极管工作在低阻状态，表现为开关，即通过控制第一控制信号V SW1可使得第一三极管、第二三极管导通；
与此同时，通过第二控制信号V SW2为低电平，使得第三三极管处于亚阈值状态，表现为电阻，从而在功能上等效于上述限流电阻R S。
当上述图1所示的第一交叠区或者第二交叠区对应的介质层被击穿后，而另外一个交叠区对应的介质层未被击穿，对应的，第一交叠区和第二交叠区的两种不同的状态组合可分别对应代表1或者0，即完成一位随机数的生成，该一位随机数可根据后面使用的需要定义为1或是0。
当要从该随机数生成装置中读取数据时，与上述编程过程的控制相反：
通过加载对应的第一控制信号V SW1为低电平，使得第一三极管、第二三极管工作在亚阈值状态，表现为高阻值电阻；
与此同时，通过控制第二控制信号V SW2为高电平，使得第三三极管处于导通状态，表现为开关，第三三极管导通。
下面再结合图7对上述读取数据的原理进行说明。图7为图6所示随机数生成装置在读取状态时的等效电路示意图；如图7所示，被击穿介质层对应的第一交叠区等效为电阻R b，未被击穿介质层对应的第二交叠区等效为电阻R o，R g为处于亚阈值状态的第一三极管和第二三极管的等效电阻，R s为第三三极管的导通电阻，阻值足够小，不计入考虑。由于电阻R o接近于无穷大，近似于断路，而电阻R b的值很小，因此在此等效电路中存在：R b<<R g<<R o。
因此，当读取电压基于以上假设，在读取电压V read为V dd时，由于电阻R b远小于R g，所以第一反相器INV1的输入接近于电压V dd，其第一输出OUT 1则为0V；而由于电阻R o远大于R g，第二反相器INV2的输入电压接近于0V，则第二输出OUT 2为V dd。如果Rb和Ro的位置交换，则第一输出OUT 1为高电平，第二输出OUT 2为低电平。OUT 1和OUT 2的组合可根据需求定义为随机数1或者0。例如，OUT 1＝1，OUT 2＝0组合定义为1；OUT 1＝0，OUT 2＝1组合为0，即根据第一交叠区和第二交叠区的击穿状态的随机组合情况，可对应随机的输出一位数据1或者0。当系统采用更多的场效应器件和对应的电路时，可生成更多位的随机数。
图8为本申请实施例随机数生成装置的一种阵列形式示意图；如图8所示，本实施例中，随机数生成装置包括6个图1所示的场效应器件(M 11、M 12、M 21、M 22、M 32、M 42、M 52、M 62)，这6个场效应器件以2列3行的阵列形式布置，以生成六位随机数。本实施例中的阵列大小只作为展示作用，实际阵列大小可以根据需求定制。
如图8所示，每列的场效应器件共享一组反相器即第一输出单元以及第二输出单元，且共享一组三极管即第一三极管和第二三极管。
具体地，第一列的场效应器件M11、M21、M31中每个场效应器件的的源端均与源端开关单元S11(相当于上述第一开关单元)连接，第一列的场效应器件M11、M21、M31中每个场效应器件的漏端均与漏端开关单元S12(相当于上述第二开关单元)连接；第一列的场效应器件M11、M21、M31中每个场效应器件的栅端连接有一个栅端开关单元(相当于上述第三开关单元)，即场效应器件M11的栅端连接有栅端开关单元S113，场效应器件M21的栅端连接 有栅端开关单元S213，场效应器件M31的栅端连接有栅端开关单元S313。
类似地，第二列的场效应器件M12、M22、M32的源端均与源端开关单元Mb3(相当于上述第一开关单元)连接，第二列的场效应器件M12、M22、M32中每个场效应器件的漏端均与漏端开关单元Mb4(相当于上述第二开关单元)连接；第二列的场效应器件M12、M22、M32中每个场效应器件的栅端连接有一个栅端开关单元(相当于上述第三开关单元)，即场效应器件M12的栅端连接有栅端开关单元S123，场效应器件M23的栅端连接有栅端开关单元S223，场效应器件M32的栅端连接有栅端开关单元S323。
图8中，同一列的栅端开关单元(S113/S213/S313或者S123/S223/S323)为三极管时，同一列的这些三极管的栅端电连接有相同的栅端控制信号(相当于上述第一控制信号)控制，即栅端开关单元S113/S213/S313的栅端被同一栅端控制信号Vgsw1控制，栅端开关单元S123/S223/S323的栅端被同一栅端控制信号Vgsw2控制。
从行的方向来说，同一行的所有场效应器件的衬底电连接有相同的第四电压，如图8所示，同一行的场效应管M11、M12的衬底均连接到第四电压Vb1，同一行的场效应管M21、M22的衬底均连接到第四电压Vb2，同一行的场效应管M31、M32的衬底均连接到第四电压Vb3，。
对于同一行的栅端开关单元来说，该同一行中的栅端开关单元的源端电连接有相同的第一电压，如图8所示，同一行的栅端开关单元S113、S123的源端均与第一电压Vg1电连接，同一行的栅端开关单元S213、S223的源端均与第一电压Vg2电连接，同一行的栅端开关单元S313、S323的源端均与第一电压Vg3电连接。
图9为本申请实施例随机数生成装置的另一种阵列结构示意图；如图9所示，本实施例中，随机数生成装置同样以2列3行的阵列形式布置。与上述图8不同的是，上述实施例中，同一列的栅端开关单元共同连接到同一栅端控制信号；而在本实施例中而是同一行的栅端开关单元共同连接到同一控制信号；具体地，即第一行的栅端开关单元S113、S123连接到同一栅端控制信号Vgsw1，第二行的栅端开关单元S213、S223连接到同一栅端控制信号Vgsw2，第三行的栅端开关单元S213、S223连接到同一栅端控制信号Vgsw3控制信号。
本申请实施例还提供一种场效应器件的制造方法；其包括如下步骤：
S601、形成有源区；
具体地，本实施例中，通过光照，刻蚀，离子注入等工艺形成有源区，所述有源区在后续的工艺中需要被引出作为衬底电极，以连接第四电压。所述有源区可如图1中标号105所示。
S602、形成栅电极；
具体地，本实施例中，通过沉淀多晶硅，掺杂，光照和刻蚀等工艺形成。需要说明的是，在形成栅电极的时候，考虑到为了避免使得源端和漏端在场效应器件处于编程模式时形成导电通道，优选使得栅电极的宽度满足此要求。
本实施例中，栅电极即在栅端掺杂区101上形成的一导电电极。
S603、形成延伸区；
具体地，本实施例中，通过光照，离子注入技术，在源端和漏端所在的区域形成延伸区。
本实施例中，所述延伸区即图1中标号103/104所在的区域。
S604、参照该延伸区形成源端和漏端，且使得所述栅端掺杂区分别与所述源端掺杂区和所述漏端掺杂区分别形成一交叠区。
具体地，本实施例中，通过大剂量的离子注入形成源端和漏端。
源端(又称为S)至少包括源电极、源端掺杂区等，漏端(又称为D)包括至少漏电极、漏端掺杂区，栅端(又称G)至少包括栅电极、栅端掺杂区。
另外，上述实施例中，第一交叠区可以理解为源端掺杂区与栅端掺杂区之间重合的区域以及该区域的介质层形成的结构，同样地，第二交叠区可以理解为漏端掺杂区与栅端掺杂区之间重合的区域以及该区域的介质层形成的结构。
本申请实施例还提供一种反熔丝，其包括上述任一实施例中所述的一个场效应器件，所述每一交叠区等效形成一反熔丝电容，所述反熔丝电容在其对应的所述介质层被击穿后呈现低阻态以根据所述低阻态向所述反熔丝写入一位随机数。
本申请的上述实施例中，以同时形成第一交叠区和第二交叠区为例进行说明。但是，对于本领域普通技术人员来说，也可以有选择只形成第一交叠区或者第二交叠区。交叠区的具体形态可以根据需要进行灵活设置。
本申请实施例提供的技术方案中，由于场效应器件的介质层设置在所述衬底与所述栅端掺杂区之间；所述源端掺杂区及所述漏端掺杂区设置在所述衬底上，且所述栅端掺杂区分别与所述源端掺杂区和所述漏端掺杂区形成一交叠区，所述交叠区对应有所述介质层，所述交叠区在其对应的所述介质层被击穿后呈 现低阻态，从而使得可通过一个MOSFET实现反熔丝，进一步物理不可克隆技术，从而简化了实现结构，以及进一步缩减了晶圆面积。
本申请上述实施例的方案可以被广泛应用于各种需要生成具有唯一性和不可复制性的ID情景，例如RFID，物联网设备的身份授权和电子钥匙生成。
本申请实施例提供的技术方案中，所用到的场效应器件并不局限于特定类型的MOSFET器件，即NMOS和PMOS皆可。
以上所描述的装置实施例仅是示意性的，其中所述作为分离部件说明的模块可以是或者也可以不是物理上分开的，作为模块显示的部件可以是或者也可以不是物理模块，即可以位于一个地方，或者也可以分布到多个网络模块上。可以根据实际的需要选择其中的部分或者全部模块来实现本实施例方案的目的。本领域普通技术人员在不付出创造性的劳动的情况下，即可以理解并实施。
通过以上的实施方式的描述，本领域的技术人员可以清楚地了解到各实施方式可借助软件加必需的通用硬件平台的方式来实现，当然也可以通过硬件。基于这样的理解，上述技术方案本质上或者说对现有技术做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品可以存储在计算机可读存储介质中，所述计算机可读记录介质包括用于以计算机(例如计算机)可读的形式存储或传送信息的任何机制。例如，机器可读介质包括只读存储器(ROM)、随机存取存储器(RAM)、磁盘存储介质、光存储介质、闪速存储介质、电、光、声或其他形式的传播信号(例如，载波、红外信号、数字信号等)等，该计算机软件产品包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行各个实施例或者实施例的某些部分所述的方法。
本领域的技术人员应明白，本发明实施例的实施例可提供为方法、装置(设备)、或计算机程序产品。因此，本发明实施例可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且，本发明实施例可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器、CD-ROM、光学存储器等)上实施的计算机程序产品的形式。
本发明实施例是参照根据本发明实施例的方法、装置(设备)和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理 机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
最后应说明的是：以上实施例仅用以说明本申请实施例的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的精神和范围。

Claims (22)

  1. 一种场效应器件，其特征在于，包括介质层、源端掺杂区、漏端掺杂区、栅端掺杂区以及衬底，其中，所述介质层设置在所述衬底与所述栅端掺杂区之间；所述源端掺杂区及所述漏端掺杂区设置在所述衬底上，且所述栅端掺杂区分别与所述源端掺杂区和所述漏端掺杂区形成一交叠区，所述交叠区对应有所述介质层，所述交叠区在其对应的所述介质层被击穿后呈现低阻态。
  2. 根据权利要求1所述的场效应器件，其特征在于，所述栅端掺杂区与所述源端掺杂区形成第一交叠区，所述栅端掺杂区与所述漏端掺杂区形成第二交叠区。
  3. 根据权利要求2所述的场效应器件，其特征在于，所述第一交叠区在其对应的所述介质层被击穿后呈现低阻态，所述第二交叠区在其对应的所述介质层未被击穿；或者，所述第二交叠区在其对应的所述介质层被击穿后呈现低阻态，所述第一交叠区在其对应的所述介质层未被击穿。
  4. 根据权利要求3所述的场效应器件，其特征在于，所述第一交叠区在其对应的所述介质层被击穿后，降低所述第二交叠区的电场强度使其对应的所述介质层未被击穿；或者，所述第二交叠区在其对应的所述介质层被击穿后，降低所述第一交叠区的电场强度使其对应的所述介质层未被击穿。
  5. 根据权利要求3所述的场效应器件，其特征在于，所述栅端掺杂区电连接第一电压，所述源端掺杂区电连接第二电压，所述漏端掺杂区电连接第三电压，所述衬底电连接第四电压，以控制所述第一交叠区或者第二交叠区对应的所述介质层被击穿。
  6. 根据权利要求5所述的场效应器件，其特征在于，所述源端掺杂区通过第一开关单元电连接所述第二电压，所述漏端掺杂区通过第二开关单元电连接所述第三电压，所述栅端掺杂区通过第三开关单元电连接所述第一电压，以在控制所述第一交叠区或者第二交叠区对应的所述介质层被击穿时，使得所述第一开关单元以及第二开关单元呈现高阻态，并对应地使得所述第三开关单元呈现低阻态。
  7. 根据权利要求6所述的场效应器件，其特征在于，所述第一开关单元为第一三极管，所述第二开关单元为第二三极管，所述第一三极管与所述第二三极管的栅端互连并第一三极管的源端和第二三极管的源端分别连接所述第二电压和第三电压，所述第一三极管和第二三极管的漏端分别连接到所述场效应器 件的源端和漏端掺杂区，所述第一三极管和第二三极管的源端分别连接到地或设定的电位。
  8. 根据权利要求7所述的场效应器件，其特征在于，所述第一三极管的漏端还连接有第一输出单元，所述第一输出单元用于输出所述第一三极管的漏端的电压，所述第二三极管的漏端还连接有第二输出单元，所述第二输出单元用于输出所述第二三极管的漏端的电压。
  9. 根据权利要求8所述的场效应器件，其特征在于，所述第一输出单元为第一反相器，所述第二输出单元为第二反相器。
  10. 根据权利要求6所述的场效应器件，其特征在于，所述第三开关单元为第三三极管，所述第三三极管与所述场效应器件的栅端连接。
  11. 根据权利要求10所述的场效应器件，其特征在于，所述第三三极管的漏端与所述场效应器件的栅端连接，所述第三三极管的源端连接所述第一电压。
  12. 根据权利要求1所述的场效应器件，其特征在于，所述源端掺杂区与所述漏端掺杂区以所述衬底在竖直方向上的中心线为参考呈对称关系。
  13. 根据权利要求12所述的场效应器件，其特征在于，所述对称关系包括下述中的至少一种：尺寸对称、掺杂浓度、与外部电路形成连接关系的对称。
  14. 根据权利要求1所述的场效应器件，其特征在于，所述源端掺杂区与所述漏端掺杂区之间形成沟道，所述交叠区处的电场强度大于所述沟道处的电场强度。
  15. 根据权利要求1所述的场效应器件，其特征在于，所述交叠区对应的所述介质层具有关联于形成工艺随机性的特征参数。
  16. 根据权利要求15所述的场效应器件，其特征在于，所述特征参数包括所述介质层的厚度特征、致密特征、瑕疵特征中的至少一个。
  17. 根据权利要求1-16任一项所述的场效应器件，其特征在于，所述栅端掺杂区分别与所述源端掺杂区和所述漏端掺杂区形成的交叠区等效为两个容抗元件。
  18. 根据权利要求17所述的场效应器件，其特征在于，所述交叠区在其对应的所述介质层被击穿前呈现高阻态。
  19. 一种反熔丝，其特征在于，包括权利要求1-18任一项所述的一个场效应器件，所述每一交叠区等效形成一反熔丝电容，所述反熔丝电容在其对应的所述介质层被击穿后呈现低阻态以根据所述低阻态向所述反熔丝写入一位随 机数。
  20. 一种随机数生成装置，其特征在于，包括一个或多个权利要求1-18任一项所述的场效应器件，以生成一位或者多位随机数。
  21. 根据权利要求20所述的装置，其特征在于，若包括多个所述场效应器件，则多个场效应器件以阵列形式排布。
  22. 根据权利要求21所述的装置，其特征在于，所述场效应器件为NMOS或PMOS管。
PCT/CN2018/099859 2018-08-10 2018-08-10 场效应器件、反熔丝、随机数生成装置 WO2020029226A1 (zh)

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