WO2020015016A1 - 薄膜晶体管及其制作方法 - Google Patents

薄膜晶体管及其制作方法 Download PDF

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WO2020015016A1
WO2020015016A1 PCT/CN2018/098004 CN2018098004W WO2020015016A1 WO 2020015016 A1 WO2020015016 A1 WO 2020015016A1 CN 2018098004 W CN2018098004 W CN 2018098004W WO 2020015016 A1 WO2020015016 A1 WO 2020015016A1
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electrode
metal layer
layer
semiconductor active
active layer
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PCT/CN2018/098004
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English (en)
French (fr)
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夏慧
谭志威
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深圳市华星光电半导体显示技术有限公司
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Priority to US16/080,596 priority Critical patent/US11056577B2/en
Publication of WO2020015016A1 publication Critical patent/WO2020015016A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
    • H01L29/78648—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate arranged on opposing sides of the channel

Definitions

  • the invention belongs to the field of display technology, and in particular, relates to a thin film transistor and a manufacturing method thereof.
  • liquid crystal displays Liquid Crystal Display, LCD for short
  • other flat display devices have been widely used in mobile phones, TVs, etc. due to their advantages such as high picture quality, power saving, thin body, and wide application range.
  • Various consumer electronic products such as personal digital assistants, digital cameras, notebook computers, and desktop computers, have become mainstream in display devices.
  • the display panel In the liquid crystal display, the display panel is used to control the working state of the liquid crystal layer.
  • the manufacturing process of the display panel the production of thin film transistors is a very critical step.
  • the traditional thin film transistor manufacturing process at least three photolithography processes and lift-off processes are required to form the source electrode, the drain electrode, the gate electrode, and the active layer. The overall process is more complicated and the manufacturing cost is higher.
  • an object of the present invention is to provide a thin film transistor manufactured by using two photolithography processes, a manufacturing method thereof, and a display panel having the same.
  • a manufacturing method of a thin film transistor includes:
  • Step 1 deposit a first metal layer on the substrate
  • Step 2 depositing a semiconductor material layer on the first metal layer, and patterning the semiconductor material layer using a first photolithography process to form a semiconductor active layer;
  • Step 3 depositing a second metal layer on the first metal layer and the semiconductor active layer, and patterning the first metal layer and the second metal layer using a second photolithography process, A first electrode, a second electrode, and a third electrode are obtained, wherein the first electrode is disposed at a distance from the second electrode, the first electrode is disposed on the substrate, and the second electrode is disposed on the substrate. Between the substrate and the semiconductor active layer, the third electrode is disposed on the semiconductor active layer, the second electrode and the third electrode overlap in a horizontal plane projection, and the first electrode is formed by The first metal layer and the second metal layer are configured.
  • the method further includes:
  • An insulating layer is formed on the substrate, the first electrode, and the third electrode.
  • the first electrode is composed of a first metal layer and a second metal layer.
  • the thickness of the third electrode is greater than the thickness of the semiconductor active layer.
  • the thickness of the third electrode is different from the thickness of the semiconductor active layer by 500 angstroms.
  • a semiconductor material layer is deposited on the first metal layer, and the semiconductor material layer is patterned by using a first photolithography process.
  • the step of forming a semiconductor active layer includes:
  • the first photoresist block is peeled off.
  • a second metal layer is deposited on the first metal layer and the semiconductor active layer, and the second metal layer is patterned by using a second photolithography process to obtain The steps of the first electrode, the second electrode, and the third electrode include:
  • the second photoresist block and the third photoresist block are peeled off.
  • the first electrode is a gate electrode
  • the second electrode and the third electrode are source and drain electrodes.
  • the invention also discloses a thin film transistor, which is manufactured by using the above manufacturing method.
  • the thin film transistor includes:
  • a first electrode and a second electrode provided on a substrate, a semiconductor active layer provided on the second electrode, a third electrode provided on the semiconductor active layer, and a covering of the first electrode and the second electrode A second electrode, the semiconductor active layer, and an insulating layer of the third electrode; wherein the first electrode is spaced from the second electrode, and the first electrode is composed of a first metal layer and a second metal layer;
  • the second electrode is composed of a first metal layer
  • the third electrode is composed of a second metal layer
  • the second electrode overlaps with the projection of the third electrode on a horizontal plane.
  • the thickness of the third electrode is greater than the thickness of the semiconductor active layer.
  • a thin film transistor and a manufacturing method thereof disclosed in the present invention can complete the fabrication of a first electrode, a second electrode, a third electrode, and an active layer through two photolithography processes, reducing process steps and reducing cost.
  • FIG. 1 is a flowchart of a method for manufacturing a thin film transistor according to the first embodiment of the present invention
  • FIGS. 2A to 2N are process diagrams of a thin film transistor according to a first embodiment of the present invention.
  • FIG. 1 shows a flowchart of a manufacturing method of a thin film transistor according to an embodiment of the present invention.
  • the manufacturing method includes steps 1 to 4:
  • step 1 Referring to FIG. 2A, a first metal layer 20 is deposited on the substrate 10.
  • the substrate 10 is a glass substrate, and a physical vapor deposition (Physical Vapor Deposition (PVD)) process is used to deposit a first metal layer 20 on the substrate 10, and the first metal layer 20 covers the substrate 10 over the entire surface.
  • PVD Physical Vapor Deposition
  • the material of the metal layer 20 may be molybdenum copper alloy or molybdenum aluminum alloy.
  • Step 2 Referring to FIGS. 2B to 2E, a semiconductor material layer 30 is deposited on the first metal layer 20, and the semiconductor material layer 30 is patterned by using a first photolithography process to form a semiconductor active layer 30 a.
  • the step 2 includes steps 21 to 25:
  • Step 21 Referring to FIG. 2B, a semiconductor material layer 30 is formed on the first metal layer 20.
  • a semiconductor material layer 30 is formed on the first metal layer 20 by using a physical vapor deposition process, and the entire surface of the semiconductor material layer 30 covers the first metal layer 20.
  • the semiconductor material layer 30 is preferably made of indium gallium zinc. Oxide.
  • Step 22 Referring to FIG. 2C, a first photoresist material layer 40 is deposited on the semiconductor material layer 30.
  • Step 23 Referring to FIG. 2D and FIG. 2E, the first photoresist material layer 40 is exposed by using the first photomask 50, and then developed to obtain the first photoresist block 40a. Specifically, the exposed first photoresist material layer 40 is subjected to a development process to form a first photoresist block 40a opposite to the active layer 30a to be formed.
  • the first photomask 50 is a half-tone mask with a predetermined pattern. In this embodiment, the half-tone mask includes an opaque region, a partially transparent region, and a completely transparent region.
  • the exposure energy is controlled so that a part of the first photoresist material layer 40 under the partially transparent area and the fully transparent area is fully exposed, so that after the first photoresist material layer 40 is processed for development, The first photoresist material layer 40 corresponding to the completely transparent region is completely etched away, and only a portion corresponding to the opaque region is left, thereby forming a first photoresist block 40a.
  • the thickness of the first photoresist block 40a is
  • Step 24 Referring to FIG. 2F, the semiconductor material layer 30 not covered by the first photoresist block 40a is etched to obtain a semiconductor active layer 30a.
  • the semiconductor material layer 30 not covered by the first photoresist block 40a is dry-etched by using a plasma gas to form an active layer 30a.
  • the semiconductor material layer 30 not covered by the first photoresist block 40a may be wet-etched by using an etching solution.
  • Step 25 Referring to FIG. 2G, the first photoresist block 40a is peeled off.
  • Step 3 Referring to FIGS. 2H to 2M, a second metal layer 60 is deposited on the first metal layer 20 and the semiconductor active layer 30a, and the first metal layer 20 and the second metal layer 60 are subjected to a second photolithography process.
  • the patterning process obtains a first electrode 61, a second electrode 63, and a third electrode 62.
  • the first electrode 61 and the second electrode 63 are disposed at intervals, the first electrode 61 is disposed on the substrate 10, the second electrode 63 is disposed between the substrate 10 and the semiconductor active layer 30a, and the third electrode 62 is disposed on the semiconductor active Above the layer 30a, the projections of the second electrode 63 and the third electrode 62 on the horizontal plane overlap.
  • the step 3 includes steps 31 to 35:
  • Step 31 Referring to FIG. 2H, a second metal layer 60 is deposited on the first metal layer 20 and the active layer 30a.
  • a second metal layer 60 is formed on the substrate 10 by a physical vapor deposition process, and the second metal layer 60 covers the first metal layer 20 and the active layer 30a on the entire surface.
  • the material of the second metal layer 60 may be Use molybdenum copper alloy or molybdenum aluminum alloy.
  • Step 32 Referring to FIG. 2I, a second photoresist material layer 70 is formed on the second metal layer 60.
  • Step 33 Referring to FIG. 2J and FIG. 2K, the second photoresist material layer 70 is exposed by using the second photomask 90, and then developed to obtain the second photoresist block 70a and the third photoresist block 70b spaced apart from each other.
  • the second photoresist block 70a is opposite to the active layer 30a
  • the third photoresist block 70b is opposite to the first electrode 61 to be formed.
  • the second mask 90 is a half-tone mask having a predetermined pattern.
  • the half-tone mask in this embodiment includes an opaque region, a partially transparent region, and a completely transparent region. Control the exposure energy so that a portion of the second photoresist material layer 70 under the fully transparent area is fully exposed, and a portion of the second photoresist material layer 70 under the partially transparent area is partially exposed, so that the second photoresist material layer After the development process of 70, a portion of the second photoresist material layer 70 corresponding to the completely transparent region is completely etched away, and a portion corresponding to the opaque region and the partially transparent region remains, thereby forming a second photoresist block 70a. And a third photoresist block 70b.
  • the thickness of the second photoresist block 70a is The thickness of the third photoresist block 70b is
  • the second photomask 90 and the first photomask 50 use the same half-tone mask.
  • different patterns are generated by using the same half-tone mask, so that a second photolithography process is performed. In this case, there is no need to replace the new photomask, and the same photomask can be used, which reduces the production cost.
  • Step 34 Referring to FIG. 2L, the first metal layer 20 and the second metal layer 60 are etched to obtain a first electrode 61, a second electrode 63, and a third electrode 62.
  • the first electrode 61 includes a first metal layer and a second metal layer.
  • a portion of the first metal layer 20 and a portion of the second metal layer 60 that are not covered by the second and third photoresist blocks 70a and 70b are removed by etching.
  • Step 35 Referring to FIG. 2M, the second photoresist block 70a and the third photoresist block 70b are peeled off to form a third conductive electrode 61, a first conductive electrode 63, and a second conductive electrode 62.
  • the first electrode 61 is used as a gate, and the first metal layer 20 and the second metal layer 60 on the upper and lower surfaces of the active layer 30a form a second electrode 63 and a third electrode 62, respectively.
  • the three electrodes 62 are used as a source and a drain, respectively, or the second electrode 63 and the third electrode 62 are used as a drain and a source, respectively, and the second electrode 63, the active layer 30a, and the third electrode 62 are sequentially stacked. It is provided on the substrate 10.
  • the thickness of the third electrode 62 is greater than the thickness of the active layer 30a.
  • the difference between the thickness of the third electrode 62 and the thickness of the active layer 30a is greater than or equal to In this way, the active control of the active layer 30a by the first electrode 61 can be realized, and the function of the vertical TFT switch can be realized.
  • Step 4 Referring to FIG. 2N, an insulating layer 80 is formed on the first electrode 61, the third electrode 62, and the substrate 10.
  • the material of the insulating layer 80 is preferably silicon nitride.
  • the invention discloses a method for manufacturing a thin film transistor, which can complete the production of a first electrode, a second electrode, a third electrode, and a semiconductor active layer through two photolithography processes, reducing process steps and reducing costs.
  • the thin film transistor according to the second embodiment of the present invention includes a first electrode 61, a second electrode 63 provided on the substrate 10, a semiconductor active layer 30a provided on the second electrode 63, and a semiconductor
  • the first electrode 61 and the second electrode 63 are spaced apart from each other.
  • the first electrode 61 is composed of the first metal layer 20 and the second metal layer 60
  • the second electrode 63 is composed of the first metal layer 20
  • the third electrode 62 is composed of the first
  • the two metal layers 60 are formed, and the projections of the second electrode 63 and the third electrode 62 on the horizontal plane overlap.
  • the thickness of the first electrode 61 is larger than the thickness of the active layer 30a.
  • the difference between the thickness of the first electrode 61 and the thickness of the active layer 30a is greater than or equal to In this way, the gate electrode 61 can effectively control the active layer 30a and realize the function of a vertical TFT switch.

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Abstract

一种薄膜晶体管及其制作方法，该方法包括：在基板（10）上沉积第一金属层（20）；在第一金属层上沉积半导体材料层（30），利用第一道光刻工艺对半导体材料层进行图案化处理，形成半导体有源层（30a）；在第一金属层及半导体有源层上沉积第二金属层（60），采用第二道光刻工艺对第一金属层及第二金属层进行图案化处理，得到第一电极（61）、第二电极（63）和第三电极（62），第一电极与第二电极间隔设置，第三电极设置在半导体有源层之上，第二电极与第三电极在水平面的投影重叠。通过该方法减少了工艺步骤，降低了成本。

Description

薄膜晶体管及其制作方法 技术领域
本发明属于显示技术领域，具体地讲，涉及一种薄膜晶体管及其制作方法。
背景技术
随着显示技术的发展，液晶显示器(Liquid Crystal Display，简称LCD)等平板显示装置因具有高画质、省电、机身薄以及应用范围广等优点，而被广泛地应用于手机、电视、个人数字助理、数字相机、笔记本电脑、台式计算机等各种消费型电子产品，成为显示装置中的主流。
在液晶显示器中，显示面板用于控制液晶层的工作状态，在显示面板的制作过程中，薄膜晶体管的制作是非常关键的步骤。传统的薄膜晶体管在制作过程中，至少需要三道光刻工艺接合lift-off工艺来制作形成源电极、漏电极、栅电极以及有源层，整体的工艺过程比较复杂，制作成本也较高。
发明内容
为了解决上述现有技术存在的不足，本发明的目的在于提供一种利用两道光刻工艺制作形成的薄膜晶体管及其制作方法以及具有该薄膜晶体管的显示面板。
为了实现上述的目的，本发明采用了如下的技术方案：
一种薄膜晶体管的制作方法，所述制作方法包括：
步骤一：在基板上沉积第一金属层；
步骤二：在所述第一金属层上沉积半导体材料层，利用第一道光刻工艺对所述半导体材料层进行图案化处理，形成半导体有源层；
步骤三：在所述第一金属层及所述半导体有源层上沉积第二金属层，采用 第二道光刻工艺对所述第一金属层及所述第二金属层进行图案化处理，得到第一电极、第二电极和第三电极，其中，所述第一电极与所述第二电极间隔设置，所述第一电极设置在所述基板上，所述第二电极设置在所述基板与所述半导体有源层之间，所述第三电极设置在所述半导体有源层之上，所述第二电极与所述第三电极在水平面的投影重叠，所述第一电极由第一金属层和第二金属层构成。
可选地，在步骤三之后，所述方法还包括：
在所述基板、所述第一电极和所述第三电极上形成绝缘层。
可选地，所述第一电极由第一金属层和第二金属层构成。
可选地，所述第三电极的厚度大于所述半导体有源层的厚度。
可选地，所述第三电极的厚度与所述半导体有源层的厚度相差500埃。
可选地，在所述第一金属层上沉积半导体材料层，利用第一道光刻工艺对所述半导体材料层进行图案化处理，形成半导体有源层的步骤包括：
在所述第一金属层沉积半导体材料层；
在所述半导体材料层上沉积第一光阻材料层；
采用第一道光罩对所述第一光阻材料层进行曝光、显影，得到第一光阻块；
对未被所述第一光阻块覆盖的半导体材料层进行蚀刻，得到所述半导体有源层；
剥离所述第一光阻块。
可选地，在所述第一金属层及所述半导体有源层上沉积第二金属层，采用第二道光刻工艺对所述第一金属层及第二金属层进行图案化处理，得到第一电极、第二电极和第三电极的步骤包括：
在所述第一金属层及所述半导体有源层上沉积第二金属层；
在所述第二金属层上沉积第二光阻材料层；
采用第二道光罩对所述第二光阻材料层进行曝光、显影，得到相互间隔的第二光阻块和第三光阻块；
对所述第一金属层和所述第二金属层进行蚀刻，得到第一电极、第二电极 和第三电极；
剥离所述第二光阻块和所述第三光阻块。
可选地，所述第一电极为栅极，所述第二电极和第三电极为源漏极。
本发明还公开了一种薄膜晶体管，采用上述的制作方法制成，薄膜晶体管包括：
设置在基板上的第一电极、第二电极，设置在所述第二电极上的半导体有源层，设置在所述半导体有源层上的第三电极以及覆盖所述第一电极、所述第二电极、所述半导体有源层、所述第三电极的绝缘层；其中，所述第一电极与所述第二电极间隔设置，第一电极由第一金属层和第二金属层构成，所述第二电极由第一金属层构成，所述第三电极由第二金属层构成，所述第二电极与所述第三电极在水平面的投影重叠。
可选地，所述第三电极的厚度大于所述半导体有源层的厚度。
有益效果：本发明公开的一种薄膜晶体管及其制作方法，通过两道光刻工艺即可完成第一电极、第二电极、第三电极以及有源层的制作，减少了工艺步骤，降低了成本。
附图说明
图1为本发明的实施例一的薄膜晶体管的制作方法的流程图；
图2A至图2N为本发明的实施例一的薄膜晶体管的制程图。
具体实施方式
为了使本发明的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本发明进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
实施例一
图1示出了根据本发明的实施例的薄膜晶体管的制作方法的流程图，该制作方法包括步骤一至步骤四：
具体地，步骤一：参照图2A，在基板10上沉积第一金属层20。
作为优选实施例，基板10选用玻璃基底，采用物理气相沉积(Physical Vapor Deposition，简称PVD)工艺在基板10上沉积形成第一金属层20，第一金属层20整面覆盖基板10，其中第一金属层20的材料可选用钼铜合金或者钼铝合金。
步骤二：参照图2B至图2E，在第一金属层20上沉积半导体材料层30，利用第一道光刻工艺对半导体材料层30进行图案化处理，形成半导体有源层30a。
作为优选实施例，该步骤二包括步骤二一至步骤二五：
步骤二一：参照图2B，在第一金属层20上形成半导体材料层30。作为优选实施例，采用物理气相沉积工艺在第一金属层20上沉积形成半导体材料层30，半导体材料层30整面覆盖第一金属层20，其中，半导体材料层30的材料优选采用铟镓锌氧化物。
步骤二二：参照图2C，在半导体材料层30上沉积第一光阻材料层40。
步骤二三：参照图2D和图2E，采用第一光罩50对第一光阻材料层40进行曝光，再经过显影得到第一光阻块40a。具体地，对曝光后的第一光阻材料层40进行显影处理，以形成与将形成的有源层30a相对的第一光阻块40a。其中第一光罩50为具有预定图案的半色调掩膜，本实施例中半色调掩膜包括不透光区域、部分透光区域和完全透光区域。
进一步地，控制曝光能量，使得部分透光区域和完全透光区域下方的第一光阻材料层40的部分进行充分曝光，使得第一光阻材料层40显影处理后，与部分透光区域、完全透光区域对应的第一光阻材料层40被完全刻蚀掉，只保留与不透光区域对应的部分，从而形成第一光阻块40a，其中第一光阻块40a的厚度为
Figure PCTCN2018098004-appb-000001
步骤二四：参照图2F，对未被第一光阻块40a覆盖的半导体材料层30进行蚀刻，得到半导体有源层30a。
作为优选实施例，采用等离子气体对未被第一光阻块40a覆盖的半导体材料层30干刻蚀，以形成有源层30a。当然在其他实施方式中，还可以采用刻蚀液对未被第一光阻块40a覆盖的半导体材料层30湿刻蚀。
步骤二五：参照图2G，剥离第一光阻块40a。
步骤三：参照图2H至图2M，在第一金属层20及半导体有源层30a上沉积第二金属层60，采用第二道光刻工艺对第一金属层20及第二金属层60进行图案化处理，得到第一电极61、第二电极63和第三电极62。其中，第一电极61与第二电极63间隔设置，第一电极61设置在基板10上，第二电极63设置在基板10与半导体有源层30a之间，第三电极62设置在半导体有源层30a之上，第二电极63与第三电极62在水平面的投影重叠。
作为优选实施例，该步骤三包括步骤三一至步骤三五：
步骤三一：参照图2H，在第一金属层20和有源层30a上沉积第二金属层60。
作为优选实施例，采用物理气相沉积工艺在基板10上沉积形成第二金属层60，第二金属层60整面覆盖第一金属层20和有源层30a，其中第二金属层60的材料可选用钼铜合金或者钼铝合金。
步骤三二：参照图2I，在第二金属层60上形成第二光阻材料层70。
步骤三三：参照图2J和图2K利用第二光罩90对第二光阻材料层70进行曝光，然后显影得到相互间隔的第二光阻块70a和第三光阻块70b。其中，第二光阻块70a与有源层30a相对，第三光阻块70b与将形成的第一电极61相对。
进一步地，第二光罩90为具有预定图案的半色调掩膜本实施例中半色调掩膜包括不透光区域、部分透光区域和完全透光区域。控制曝光能量，使得完全透光区域下方的第二光阻材料层70的部分进行充分曝光，部分透光区域下方的第二光阻材料层70的部分进行部分曝光，使得第二光阻材料层70经过显影处理后，与完全透光区域对应的第二光阻材料层70部分被完全刻蚀掉，保留与不透光区域、部分透光区域对应的部分，从而形成第二光阻块70a和第三光阻块70b。其中，第二光阻块70a的厚度为
Figure PCTCN2018098004-appb-000002
第三光阻块70b的厚度为
Figure PCTCN2018098004-appb-000003
作为优选实施例，第二光罩90与第一光罩50采用相同的半色调掩膜，通过控制曝光强度，利用同一个半色调掩膜产生不同的图案，这样在进行第二道光刻工艺时，不需要更换新的光罩，利用同一个光罩即可，降低了生产成本。
步骤三四：参照图2L，对第一金属层20和第二金属层60进行蚀刻，得到第一电极61、第二电极63和第三电极62。其中，第一电极61由第一金属层和第二金属层构成。
具体地，将未被第二光阻块70a和第三光阻块70b覆盖的第一金属层20的部分和第二金属层60的部分刻蚀去除。
步骤三五：参照图2M，将第二光阻块70a和第三光阻块70b剥离去除，以形成第三导电极61、第一导电极63和第二导电极62。
其中，第一电极61用作栅极，位于有源层30a上下两个表面的第一金属层20和第二金属层60分别形成第二电极63和第三电极62，第二电极63和第三电极62分别用作源极和漏极，或者第二电极63和第三电极62分别用作漏极和源极，第二电极63、有源层30a和第三电极62三者依序层叠设置在基板10上。
进一步地，第三电极62的厚度大于有源层30a的厚度。作为优选实施例，第三电极62的厚度和有源层30a的厚度之差大于或等于
Figure PCTCN2018098004-appb-000004
这样能实现第一电极61对有源层30a的有效控制，实现垂直TFT开关的作用。
步骤四：参照图2N，在第一电极61、第三电极62以及基板10上形成绝缘层80。其中绝缘层80的材料优选为氮化硅。
本发明公开的一种薄膜晶体管的制作方法，通过两道光刻工艺即可完成第一电极、第二电极、第三电极以及半导体有源层的制作，减少了工艺步骤，降低了成本。
实施例二
如图2N所示，根据本发明的实施例二的薄膜晶体管包括设置在基板10上的第一电极61、第二电极63，设置在第二电极63上的半导体有源层30a，设置在半导体有源层30a上的第三电极62以及覆盖第一电极61、第二电极63、半导体有源层30a、第三电极62的绝缘层80。其中，第一电极61与第二电极63间隔设置，第一电极61由第一金属层20和第二金属层60构成，第二电极63由第一金属层20构成，第三电极62由第二金属层60构成，第二电极63与第三电极62在水平面的投影重叠。
进一步地，第一电极61的厚度大于有源层30a的厚度。作为优选实施例，第一电极61的厚度和有源层30a的厚度之差大于或等于
Figure PCTCN2018098004-appb-000005
这样能实现栅电极61对有源层30a的有效控制，实现垂直TFT开关的作用。
上面对本发明的具体实施方式进行了详细描述，虽然已表示和描述了一些实施例，但本领域技术人员应该理解，在不脱离由权利要求及其等同物限定其范围的本发明的原理和精神的情况下，可以对这些实施例进行修改和完善，这些修改和完善也应在本发明的保护范围内。

Claims (12)

  1. 一种薄膜晶体管的制作方法，其中，所述制作方法包括：
    步骤一：在基板上沉积第一金属层；
    步骤二：在所述第一金属层上沉积半导体材料层，利用第一道光刻工艺对所述半导体材料层进行图案化处理，形成半导体有源层；
    步骤三：在所述第一金属层及所述半导体有源层上沉积第二金属层，采用第二道光刻工艺对所述第一金属层及所述第二金属层进行图案化处理，得到第一电极、第二电极和第三电极，其中，所述第一电极与所述第二电极间隔设置，所述第一电极设置在所述基板上，所述第二电极设置在所述基板与所述半导体有源层之间，所述第三电极设置在所述半导体有源层之上，所述第二电极与所述第三电极在水平面的投影重叠；所述第一电极由第一金属层和第二金属层构成。
  2. 根据权利要求1所述的制作方法，其中，在步骤三之后，所述方法还包括：
    在所述基板、所述第一电极和所述第三电极上形成绝缘层。
  3. 根据权利要求1所述的制作方法，其中，所述第一电极由第一金属层和第二金属层构成。
  4. 根据权利要求1所述的制作方法，其中，所述第三电极的厚度大于所述半导体有源层的厚度。
  5. 根据权利要求4所述的制作方法，其中，所述第三电极的厚度与所述半导体有源层的厚度相差500埃。
  6. 如权利要求1所述的制作方法，其中，在所述第一金属层上沉积半导体材料层，利用第一道光刻工艺对所述半导体材料层进行图案化处理，形成半 导体有源层的步骤包括：
    在所述第一金属层沉积半导体材料层；
    在所述半导体材料层上沉积第一光阻材料层；
    采用第一道光罩对所述第一光阻材料层进行曝光、显影，得到第一光阻块；
    对未被所述第一光阻块覆盖的半导体材料层进行蚀刻，得到所述半导体有源层；
    剥离所述第一光阻块。
  7. 如权利要求1所述的制作方法，其中，在所述第一金属层及所述半导体有源层上沉积第二金属层，采用第二道光刻工艺对所述第一金属层及第二金属层进行图案化处理，得到第一电极、第二电极和第三电极的步骤包括：
    在所述第一金属层及所述半导体有源层上沉积第二金属层；
    在所述第二金属层上沉积第二光阻材料层；
    采用第二道光罩对所述第二光阻材料层进行曝光、显影，得到相互间隔的第二光阻块和第三光阻块；
    对所述第一金属层和所述第二金属层进行蚀刻，得到第一电极、第二电极和第三电极；
    剥离所述第二光阻块和所述第三光阻块。
  8. 如权利要求1所述的制作方法，其中，所述第一电极为栅极，所述第二电极和第三电极为源漏极。
  9. 一种薄膜晶体管，采用如权利要求1所述的制作方法制成；其中，所述薄膜晶体管包括：
    设置在基板上的第一电极、第二电极，设置在所述第二电极上的半导体有源层，设置在所述半导体有源层上的第三电极以及覆盖所述第一电极、所述第二电极、所述半导体有源层、所述第三电极的绝缘层；其中，所述第一电极与 所述第二电极间隔设置，第一电极由第一金属层和第二金属层构成，所述第二电极由第一金属层构成，所述第三电极由第二金属层构成，所述第二电极与所述第三电极在水平面的投影重叠。
  10. 根据权利要求9所述的薄膜晶体管，其中，所述第三电极的厚度大于所述半导体有源层的厚度。
  11. 根据权利要求10所述的薄膜晶体管，其中，所述第三电极的厚度与所述半导体有源层的厚度相差500埃。
  12. 根据权利要求9所述的薄膜晶体管，其中，所述第一电极为栅极，所述第二电极和第三电极为源漏极。
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