WO2020011285A2 - 图像传感器的半导体结构、芯片及电子装置 - Google Patents

图像传感器的半导体结构、芯片及电子装置 Download PDF

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WO2020011285A2
WO2020011285A2 PCT/CN2019/109426 CN2019109426W WO2020011285A2 WO 2020011285 A2 WO2020011285 A2 WO 2020011285A2 CN 2019109426 W CN2019109426 W CN 2019109426W WO 2020011285 A2 WO2020011285 A2 WO 2020011285A2
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pixel
pixels
image sensor
semiconductor structure
transistor
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PCT/CN2019/109426
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English (en)
French (fr)
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WO2020011285A3 (zh
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陈经纬
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深圳市汇顶科技股份有限公司
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Priority to EP19834065.5A priority Critical patent/EP3651200B1/en
Priority to CN201980002392.6A priority patent/CN110809823B/zh
Priority to PCT/CN2019/109426 priority patent/WO2020011285A2/zh
Priority to KR1020207002764A priority patent/KR102358599B1/ko
Priority to JP2020513731A priority patent/JP6891340B2/ja
Publication of WO2020011285A2 publication Critical patent/WO2020011285A2/zh
Priority to US16/749,754 priority patent/US11233086B2/en
Publication of WO2020011285A3 publication Critical patent/WO2020011285A3/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
    • H01L27/14616—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor characterised by the channel of the transistor, e.g. channel having a doping gradient
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
    • H01L27/14605—Structural or functional details relating to the position of the pixel elements, e.g. smaller pixel elements in the center of the imager compared to pixel elements at the periphery
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14636—Interconnect structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14641—Electronic components shared by two or more pixel-elements, e.g. one amplifier shared by two pixel elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14643—Photodiode arrays; MOS imagers
    • H01L27/14645—Colour imagers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/10—Circuitry of solid-state image sensors [SSIS]; Control thereof for transforming different wavelengths into image signals
    • H04N25/11—Arrangement of colour filter arrays [CFA]; Filter mosaics
    • H04N25/13—Arrangement of colour filter arrays [CFA]; Filter mosaics characterised by the spectral characteristics of the filter elements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
    • H04N25/618—Noise processing, e.g. detecting, correcting, reducing or removing noise for random or high-frequency noise
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
    • H04N25/65—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
    • H04N25/778—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself

Definitions

  • the present application relates to a semiconductor structure of an image sensor and related chips and electronic devices, and in particular to a semiconductor structure of an image sensor capable of increasing the channel length of a source follower transistor, and related chips and electronic devices.
  • CMOS image sensors have been mass-produced and applied. With the improvement of image quality requirements, the number of pixels is also getting larger. In order to increase the number of pixels in a limited area as much as possible, the size of a unit pixel must be reduced as much as possible In other words, the size of the photosensitive sensor and the output circuit in the unit pixel must be reduced accordingly.
  • One of the purposes of this application is to disclose a semiconductor structure of an image sensor and related chips and electronic devices to solve the above problems.
  • An embodiment of the present application discloses a semiconductor structure of an image sensor.
  • the semiconductor structure of the image sensor includes a semiconductor substrate and a plurality of pixel groups disposed on the semiconductor substrate.
  • Each pixel group includes: The first and second pixels adjacent to each other in a row are located in the third and fourth pixels adjacent to each other in a row and the first and third pixels are diagonally misaligned and the first pixel And the third pixel is a pixel of the same color; each of the first pixel, the second pixel, the third pixel, and the fourth pixel includes four sub-pixels arranged in two rows and two columns, and four in each pixel A plurality of sub-pixels share a floating diffusion region and the floating diffusion region is surrounded by the four sub-pixels' photosensitive sensors, which are used to convert light into electric charges; the outputs of the first and third pixels Circuit sharing, the output circuit shared by the first pixel and the third pixel is located between the first pixel and the third pixel and extends to the left / right side of the
  • the output circuit is used to A pixel output is generated according to the charge, and the output circuit includes a first source follower transistor, wherein a portion of the first source follower transistor is located on a side of a boundary between the first pixel and the third pixel as viewed from a top view. , And is at least adjacent to the left / right side of the first pixel, and another part of the first source follower transistor is located on the other side of the boundary between the first pixel and the third pixel And at least adjacent to the right / left side of the third pixel.
  • An embodiment of the present application discloses a chip including the semiconductor structure of the image sensor described above.
  • An embodiment of the present application discloses an electronic device including the semiconductor structure of the image sensor described above.
  • the embodiments of the present application improve the configuration of the output circuit of the semiconductor structure of the image sensor, which can reduce the area and improve the performance of the output circuit.
  • FIG. 1 is a plan view of an embodiment of a semiconductor structure of an image sensor of the present application.
  • FIG. 2 is a circuit diagram of a pixel of the image sensor of FIG. 1.
  • FIG. 3 is a plan view of a first embodiment of a Bayer pixel group based on the semiconductor structure of the image sensor of FIG. 1.
  • FIG. 4 is a plan view of a second embodiment of a Bayer pixel group based on the semiconductor structure of the image sensor of FIG. 1.
  • FIG. 5 is a schematic diagram of an embodiment in which an image sensor is applied to an electronic device.
  • first and second features are in direct contact with each other; and may also include additional components are formed between the first and second features, so that the first and second features may not be in direct contact.
  • contents of this application may reuse component symbols and / or reference numerals in multiple embodiments. Such reuse is for brevity and clarity, and does not in itself represent the relationship between the different embodiments and / or configurations discussed.
  • spatially relative terms such as “below”, “below”, “below”, “above”, “above” and similar are used here for the convenience of illustration Shows the relationship between one component or feature relative to another or more components or features.
  • these spatially relative words also cover a variety of different orientations of the device in use or operation. The device may be placed in other orientations (eg, rotated 90 degrees or in other orientations), and these spatially relative description words should be interpreted accordingly.
  • the application and demand of high-resolution and even ultra-high-resolution CMOS image sensors are becoming more and more extensive.
  • the size of the unit pixel must be reduced accordingly. That is, the size of the photosensitive sensor and the output circuit in the unit pixel must be reduced. Inevitably, there will be some impact on the effectiveness. For example, when the channel length of the source follower transistor in the output circuit is reduced, the random telegraph signal noise will become larger.
  • the semiconductor structure of the image sensor of the present application can reduce the area of the pixel and increase the output by changing the configuration of the output circuit. The source in the circuit follows the channel length of the transistor, thereby reducing random telegraph signal noise.
  • the application can also enable pixels with the same color in the same pixel group to share the same reading circuit, so as to improve the problem of inconsistent output of pixels of the same color.
  • the present application may also use the same reading circuit for the green pixels Gr and Gb in the same pixel group with a Bayer array arrangement, so as to prevent the green pixels Gr and Gb from being caused between the green pixels Gr and Gb due to different reading circuits. Image misalignment problem.
  • FIG. 1 is a plan view of an embodiment of a semiconductor structure of an image sensor of the present application.
  • the image sensor 600 in FIG. 1 includes a shared pixel P5 ′ based on 2 ⁇ 2 and a shared pixel P6 based on 2 ⁇ 2, and the pixels P5 ′ and P6 collectively form a unit pixel group. It should be noted that although the image sensor 600 in FIG. 1 only shows the pixels P5 ′ and P6, the image sensor 600 may include a plurality of the unit pixel groups.
  • FIG. 2 is a circuit diagram of the image sensor 600 of FIG. 1.
  • the image sensor 600 includes a semiconductor substrate 101, and a pixel P5 ′ and a pixel P6 are provided on the semiconductor substrate 101.
  • the semiconductor substrate 101 may be a bulk semiconductor substrate, such as a silicon substrate or a silicon-on-insulator (SOI) substrate.
  • SOI silicon-on-insulator
  • the pixel P5 ′ and the pixel P6 respectively include four sub-pixels to form a 2 ⁇ 2 shared pixel P5 and P6, and the pixel P5 ′ includes four photo sensors 502_1, 504_1, 506_1, and 508_1 corresponding to the pixel P5 ′.
  • the pixel P6 includes four photosensitive pixels 502_2, 504_2, 506_2, and 508_2 corresponding to the four subpixels of the pixel P6.
  • the pixel P5 'and the pixel P6 also include an output circuit 116, that is, the output circuit 518 is composed of the pixel P5'.
  • pixel P5 ' has four transmission gates 510_1, 512_1, 514_1, and 516_1 to correspond to the four photosensors 502_1, 504_1, 506_1, and 508_1;
  • pixel P6 has four transmission gates 510_2, 512_2, 514_2, and 516_2 to correspond Four photosensors 502_2, 504_2, 506_2, and 508_2.
  • the anodes of the photosensitive sensors 502_1, 504_1, 506_1, 508_1, 502_2, 504_2, 506_2, and 508_2 are electrically connected to the first voltage VSS.
  • the photosensitive sensors 502_1, 504_1, 506_1, 508_1, 502_2, 504_2, 506_2, and 508_2 are used to convert light into Charge.
  • the range of the output circuit 518 is not shown in FIG. 1 for brevity, and the output circuit 518 is only shown in FIG. 2.
  • the output circuit 518 is used to generate the pixel output according to the charge generated by the photosensitive sensors 502_1, 504_1, 506_1, 508_1, 502_2, 504_2, 506_2, and 508_2.
  • the output circuit 518 includes transmission gates 510_1, 512_1, 514_1, 516_1, 510_2, 512_2, 514_2, and 516_2, a reset transistor 106, a source follower transistor 108, and a row selection transistor 110. As shown in FIG. 1, there is a boundary between the pixel P5 ′ and the pixel P6, that is, the boundary between the lower boundary of the pixel P5 ′ and the upper boundary of the pixel P6.
  • An output circuit 518 (ie, transmission gates 510_1, 512_1, 514_1, 516_1, 510_2, 512_2, 514_2, and 516_2, a reset transistor 106, a source follower transistor 108, and a row selection transistor 110) spans the boundary between the pixel P5 'and the pixel P6, and
  • the photo sensor 502_1, 504_1, 506_1, 508_1 of the adjacent pixel P5 'of the output circuit 518 and the photo sensors 502_2, 504_2, 506_2, and 508_2 of the adjacent pixel P6 of the output circuit 518 are provided.
  • the transmission gates 510_1, 512_1, 514_1, 516_1, 510_2, 512_2, 514_2, and 516_2 include a gate and two sources / drains, and the gates of the transmission gates 510_1, 512_1, 514_1, 516_1, 510_2, 512_2, 514_2, and 516_2 correspond to the gates, respectively.
  • 516_1, 510_2, 512_2, 514_2, and 516_2 are turned on or off.
  • Each transmission gate 510_1, 512_1, 514_1, 516_1, 510_2, 512_2, 514_2, and 516_2 are two sources /
  • the drain is electrically connected between the photosensitive sensors 502_1, 504_1, 506_1, 508_1, 502_2, 504_2, 506_2, and 508_2 and the floating diffusion regions FD1 and FD2.
  • the source follower transistor 108 is disposed between the reset transistor 106 and the row selection transistor 110.
  • the row selection transistor 110 and the first reset transistor 106 are symmetrically arranged along the first source follower transistor 108.
  • the transmission gates 510_1, 512_1, 514_1, 516_1 are uniformly distributed in the pixel P5 '; the transmission gates 510_2, 512_2, 514_2, and 516_2 in the pixel P6 are uniformly distributed in the pixel P6.
  • the gate of the source follower transistor 108 and one source / drain of the reset transistor 106 are electrically connected to the floating diffusion regions FD1 and FD2, and the other source / drain of the reset transistor 106 is electrically connected to the second The voltage VDD and the second voltage VDD are different from the first voltage VSS.
  • the gate of the reset transistor 106 determines whether to be turned on according to the control of the reset signal RST.
  • the source follower transistor 108 is connected in series to the row select transistor 110.
  • a source / drain of the source follower transistor 108 is electrically connected to a row select transistor 110.
  • Source / drain, another source / drain of the source follower transistor 108 is electrically connected to the second voltage VDD.
  • the other source / drain of the row selection transistor 110 is used as an output terminal POUT of the pixel output and is electrically connected to the bit line BL.
  • the gate of the row selection transistor 110 is controlled according to the row selection signal RSEL on the word line WL.
  • the pixel output is output from the output terminal POUT to the bit line BL.
  • the row selection transistor 110, the source follower transistor 108, and the reset transistor 106 are arranged in a row to form a transistor column.
  • each of the pixel P5 ′ and the pixel P6 has a range, and the pixel P5 ′ and the pixel P6 are adjacent to each other to form a boundary between the pixel P5 ′ and the pixel P6.
  • the source following transistor 108 crosses between the pixel P5 'and the pixel P6, that is, the source following transistor 108 is disposed across the boundary between the pixel P5' and the pixel P6, and extends to the pixel P5 'and the pixel P6.
  • a part of the source follower transistor 108 that is, an upper part of the source follower transistor 108, is located on one side of the boundary between the pixel P5 'and the pixel P6, and is at least adjacent (ie, left and right adjacent) to the pixel P5'.
  • Photosensitive sensors 502_1, 504_1, 506_1, 508_1, the other part of the source following transistor 108, that is, the lower part of the source following transistor 108, are located on the other side of the boundary between the pixel P5 'and the pixel P6, and are at least adjacent (i.e. left and right) Adjacent) photosensitive sensors 502_2, 504_2, 506_2, and 508_2 of the pixel P6.
  • the reset transistor 106 is disposed on the pixel P5 ', and the photosensors 502_1, 504_1, 506_1, and 508_1 of the reset transistor 106 adjacent to the pixel P5', the row selection transistor 110 is disposed on the pixel P6, and the row selection transistor 110 is adjacent to the photosensitive of the pixel P6.
  • the pixel P5 'and the pixel P6 share an output terminal POUT.
  • this application configures pixel P5 'and pixel P6 as a group, so that pixel P5' and pixel P6 share the output circuit 116, and break the boundary between pixel P5 'and pixel P6, and cross the output circuit 116.
  • the source follower transistor 108 which originally needs to be limited to the range of the pixel P5' or the pixel P6 can cross the boundary between the pixel P5 'and the pixel P6, which is bound to increase the design Elasticity, that is, extra space can be obtained to increase the length of the source follower transistor 108, because the channel length L of the source follower transistor 108 is directly related to the length of the source follower transistor 108, which means that the application can increase the source follower transistor
  • the channel length L of 108 is used to achieve the purpose of reducing the area of the pixels P5 'and the pixels P6 and reducing the random telegraph signal noise.
  • the row selection transistor 110, the source follower transistor 108, and the reset transistor 106 are arranged in a row to form a transistor column, and the pixel
  • the photosensors 502_1, 504_1, 506_1, 508_1 of P5 'and the photosensors 502_2, 504_2, 506_2, and 508_2 of the pixel P6 are disposed on different sides of the transistor column.
  • a color filter is disposed above the pixels P5 ′ and the pixels P6, and is arranged as a pixel group according to the Bayer array. It is further illustrated in FIG. 3, which is based on the semiconductor structure of the image sensor of FIG. 1.
  • FIG. 3 is based on the semiconductor structure of the image sensor of FIG. 1.
  • the Bayer pixel group 800 in FIG. 3 includes two unit pixel groups shown in FIG. 1, that is, a unit pixel group composed of pixels P5 ′ and P6 and a unit pixel group composed of pixels P7 ′ and P8.
  • a green Gb color filter is provided above the photosensors 502_1, 504_1, 506_1, and 508_1 of the pixel P5 ', and a green Gr color filter is provided above the photosensors 502_2, 504_2, 506_2, and 508_2 of the pixel P6, and a photosensor of the pixel P7'
  • a blue B color filter is disposed above 502_1, 504_1, 506_1, and 508_1, and a red R color filter is disposed above the photosensitive sensors 502_2, 504_2, 506_2, and 508_2 of the pixel P8.
  • the green Gb filter overlaps the pixel P5 '
  • the green Gr filter overlaps the pixel P6
  • the blue B filter overlaps the pixel P7'
  • the red R filter is superimposed on the pixel P8.
  • Pixels P5 'and P6 are diagonally misaligned; pixels P7' and P8 are diagonally misaligned.
  • each of the above color filters may completely overlap the corresponding pixels; or each color filter may partially overlap the corresponding pixels; or each color filter may cover its corresponding The pixel, that is, the area of the color filter is larger than the area of the pixel, so that the color filter completely covers the corresponding pixel.
  • green Gb and Gr color filters are provided above the pixels P5 'and P6, and the pixels P5' and P6 share an output terminal POUT, and blue is provided above the pixels P7 'and P8. B and red R color filters, and the pixels P7 'and P8 share the output terminal POUT, that is, the pixels P5' and P6 will enter the same reading circuit through the same bit line BL.
  • the advantage is to avoid the green pixels Gr and Gb enters different reading circuits and causes image misalignment between green pixels Gr and Gb. It should be noted that in reality there is a deviation between reading circuits. Therefore, if the green pixels Gr and Gb is read into different reading circuits, which will cause the above-mentioned image misalignment problem. Therefore, the Bayer pixel group 800 in FIG. 3 can improve the image misregistration problem described above.
  • FIG. 4 is a plan view of a second embodiment of a Bayer pixel group based on the semiconductor structure of the image sensor of FIG. 1. Similar to 3, the Bayer pixel group 900 in FIG. 4 includes two unit pixel groups shown in FIG. 1, that is, a unit pixel group composed of pixels P5 ′ and P6 and a unit pixel group composed of pixels P7 ′ and P8.
  • a green Gr color filter is provided above the photosensitive sensors 502_1, 504_1, 506_1, and 508_1 of the pixel P5 ', and a green GB color filter is provided above the photosensitive sensors 502_2, 504_2, 506_2, and 508_2 of the pixel P6, and the pixel P7'
  • a red R color filter is disposed above the photosensitive sensors 502_1, 504_1, 506_1, and 508_1, and a blue B color filter is disposed above the photosensitive sensors 502_2, 504_2, 506_2, and 508_2 of the pixel P8.
  • the green Gr filter overlaps the pixel P5 '
  • the green Gb filter overlaps the pixel P6
  • the red R filter overlaps the pixel P7'.
  • the blue B filter is superimposed on the pixel P8. Pixels P5 'and P6 are diagonally misaligned; pixels P7' and P8 are diagonally misaligned.
  • the color configuration of the Bayer pixel group 900 in FIG. 4 is slightly different from the Bayer pixel group 800 in FIG.
  • the pixel P5 ′ and the pixel P6 enter the same reading circuit through the same bit line BL, which can avoid The green pixels Gr and Gb enter into different reading circuits and cause image misalignment between the green pixels Gr and Gb.
  • the above-mentioned pixel group setting method can be used to combine the diagonally dislocated pixels Gr and Gb of the same color to share the output circuit, so that the output of the first pixel Gr and the third pixel Gb, which are also green pixels, are consistent. Improve the image quality.
  • the area of the pixel can be reduced.
  • the source follower transistor By extending the source follower transistor in the output circuit to the PD of the first pixel and the third pixel, the source follower transistor can be increased in a limited semiconductor area. The channel length can further reduce the pixel size and reduce noise interference.
  • the output circuit is shared between the first pixel Gr and the third pixel Gb to improve the consistency of the pixel output and the quality of the image.
  • the output circuit sharing can reduce the The output circuit occupies space, and a larger PD can be set in a limited space to increase the amount of light.
  • the source follows the transistor across the two pixels of the PD. The source can be further increased without affecting the space occupied by the PD.
  • FIG. 5 is a schematic diagram of an embodiment in which the image sensor is applied to the electronic device 1100.
  • the electronic device 1100 includes a display screen assembly 1104 and an image sensor 800/900.
  • the electronic device 1100 may be any electronic device such as a smart phone, a personal digital assistant, a handheld computer system, a tablet computer, or a digital camera.

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  • Solid State Image Pick-Up Elements (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)
  • Color Television Image Signal Generators (AREA)

Abstract

本申请公开了一种图像传感器的半导体结构及相关芯片和电子装置。半导体结构包括半导体衬底和设置于半导体衬底的若干个像素组，每个像素组包括：位于同一行且相邻的第一像素及第二像素，位于另一行且相邻的第三像素及第四像素，第一像素及第三像素为对角错位设置，每个像素各自均包括四个子像素，每个像素里的四个子像素共用浮置扩散区且浮置扩散区被四个子像素的光敏传感器包围，第一像素和第三像素的输出电路共享，第一像素和第三像素共享的输出电路位于第一像素及第三像素之间且延伸至第一像素的左侧/右侧和第三像素的右侧/左侧，本申请可提高图像传感器的图像质量并改善输出电路的效能。

Description

图像传感器的半导体结构、芯片及电子装置 技术领域
本申请涉及一种图像传感器的半导体结构及相关芯片和电子装置，尤其涉及一种能增加源跟随晶体管的沟道长度的图像传感器的半导体结构及相关芯片和电子装置。
背景技术
CMOS图像传感器已经得到大规模生产和应用，随著画质要求的提升，像素的数目也越来越大，为了尽量在有限的面积中增加像素的数目，单位像素的尺寸要尽可能地缩小，也就是说，单位像素中的光敏传感器和输出电路的尺寸都要跟著缩小。
然而，将输出电路的尺寸缩小，往往会影响到输出电路的效能，因此，如何兼顾面积与效能，已成为本领域的一个重要的工作项目。而且，现有技术中的CMOS图像传感器易出现影像失调的问题。
发明内容
本申请的目的之一在于公开一种图像传感器的半导体结构及相关芯片和电子装置，来解决上述问题。
本申请的一实施例公开了一种图像传感器的半导体结构，所述图像传感器的半导体结构包括：半导体衬底和设置于所述半导体衬底的若干个像素组，每个像素组包括：位于同一行且相邻的第一像素及第二像素，位于另一行且相邻的第三像素及第四像素，所述第一像素及所述第三像素为对角错位设置且所述第一像素及所述第三像素为相同颜色的像素；所述第一像素、第二像素、第三像素及第四像素各自均包括四个按照两行两列排列的子像 素，每个像素里的四个子像素共用浮置扩散区且所述浮置扩散区被所述四个子像素的光敏传感器包围，所述光敏传感器用来将光线转换为电荷；所述第一像素和所述第三像素的输出电路共享，所述第一像素和所述第三像素共享的所述输出电路位于所述第一像素及第三像素之间且延伸至所述第一像素的左侧/右侧和所述第三像素的右侧/左侧，所述输出电路的一部分相邻所述第一像素的光敏传感器，所述输出电路的另一部分相邻所述第三像素的光敏传感器，所述输出电路用来依据所述电荷产生像素输出，所述输出电路包括第一源跟随晶体管；其中，从俯视图来看，所述第一源跟随晶体管的一部分位于所述第一像素及第三像素的分界的一侧，并至少与所述第一像素的左侧/右侧的光敏传感器相邻，且所述第一源跟随晶体管的另一部分位于所述第一像素及第三像素的所述分界的另一侧，并至少与所述第三像素的右侧/左侧的光敏传感器相邻。
本申请的一实施例公开了一种芯片，包括上述的图像传感器的半导体结构。
本申请的一实施例公开了一种电子装置，包括上述的图像传感器的半导体结构。
本申请实施例针对图像传感器的半导体结构的输出电路之配置方式进行改良，可降低面积并改善输出电路的效能。
附图说明
图1为本申请的图像传感器的半导体结构的实施例的俯视图。
图2为图1的图像传感器的像素的电路图。
图3为基于图1的图像传感器的半导体结构的拜耳像素组的第一实施例的俯视图。
图4为基于图1的图像传感器的半导体结构的拜耳像素组的第二实施例的俯视图。
图5为本申请的图像传感器应用于电子装置中的实施例的示意图。
具体实施方式
以下揭示内容提供了多种实施方式或示例，其能用以实现本申请内容的不同特征。下文所述之组件与配置的具体例子系用以简化本申请内容。当可想见，这些叙述仅为例示，其本意并非用于限制本申请内容。举例来说，在下文的描述中，将一第一特征形成于一第二特征上或之上，可能包括某些实施例其中所述的第一与第二特征彼此直接接触；且也可能包括某些实施例其中还有额外的组件形成于上述第一与第二特征之间，而使得第一与第二特征可能没有直接接触。此外，本申请内容可能会在多个实施例中重复使用组件符号和/或标号。此种重复使用乃是基于简洁与清楚的目的，且其本身不代表所讨论的不同实施例和/或组态之间的关系。
再者，在此处使用空间上相对的词汇，譬如「之下」、「下方」、「低于」、「之上」、「上方」及与其相似者，可能是为了方便说明图中所绘示的一组件或特征相对于另一或多个组件或特征之间的关系。这些空间上相对的词汇其本意除了图中所绘示的方位之外，还涵盖了装置在使用或操作中所处的多种不同方位。可能将所述设备放置于其他方位(如，旋转90度或处于其他方位)，而这些空间上相对的描述词汇就应该做相应的解释。
虽然用以界定本申请较广范围的数值范围与参数皆是约略的数值，此处已尽可能精确地呈现具体实施例中的相关数值。然而，任何数值本质上不可避免地含有因个别测试方法所致的标准偏差。在此处，「约」通常系指实际数值在一特定数值或范围的正负10％、5％、1％或0.5％之内。或者是，「约」一词代表实际数值落在平均值的可接受标准误差之内，视本申请所属技术领域中具有通常知识者的考虑而定。当可理解，除了实验例之外，或除非另有明确的说明，此处所用的所有范围、数量、数值与百分比(例如用以描述材料用量、时间长短、温度、操作条件、数量比例及其他相似者)均经过 「约」的修饰。因此，除非另有相反的说明，本说明书与附随申请专利范围所揭示的数值参数皆为约略的数值，且可视需求而更动。至少应将这些数值参数理解为所指出的有效位数与套用一般进位法所得到的数值。在此处，将数值范围表示成由一端点至另一端点或介于二端点之间；除非另有说明，此处所述的数值范围皆包括端点。
高分辨率甚至超高分辨率CMOS图像传感器的应用和需求越来越广泛，单位像素的尺寸必须跟著缩小，也就是说，单位像素中的光敏传感器和输出电路的尺寸都要跟著缩小，输出电路的效能不可避免地会遭遇一些影响。例如当输出电路中的源跟随晶体管的沟道长度缩小时，随机电报信号噪声会变大，本申请的图像传感器的半导体结构可藉由改变输出电路的配置，来减少像素的面积，并增加输出电路中的源跟随晶体管的沟道长度，因而降低随机电报信号噪声。此外，藉由改变输出电路的配置，本申请亦可使同一像素组中具有相同颜色的像素共享同一读取电路，以改善相同颜色的像素输出不一致的问题。例如：本申请亦可使具有拜耳阵列排列的同一像素组中的绿色像素Gr和Gb使用同一读取电路，达到避免绿色像素Gr和Gb因读取电路的不同而造成绿色像素Gr和Gb之间的影像失调问题。
图1为本申请的图像传感器的半导体结构的实施例的俯视图。图1中的图像传感器600包括2×2为基础的共享像素P5'和2×2为基础的共享像素P6，且像素P5'和像素P6共同形成单位像素组。应注意的是，尽管图1中的图像传感器600仅绘示了像素P5'和像素P6，但图像传感器600可包括多个所述单位像素组。图2为图1的图像传感器600的电路图。
请同时参阅图1和图2。图像传感器600包括半导体衬底101，且像素P5'和像素P6设置于半导体衬底101。其中半导体衬底101可以是块状半导体衬底，诸如硅衬底或绝缘体上硅(SOI)衬底。具体来说，像素P5'和像素P6分别包括四个子像素以形成2×2为基础的共享像素P5和P6，像素P5'包括四个光敏传感器502_1、504_1、 506_1和508_1对应像素P5'的所述四个子像素；像素P6包括四个光敏传感器502_2、504_2、506_2和508_2对应像素P6的所述四个子像素，像素P5'和像素P6另共同包括输出电路116，即输出电路518由像素P5'和像素P6共享，像素P5'具有四个传输门510_1、512_1、514_1和516_1以对应四个光敏传感器502_1、504_1、506_1和508_1；像素P6具有四个传输门510_2、512_2、514_2和516_2以对应四个光敏传感器502_2、504_2、506_2和508_2。光敏传感器502_1、504_1、506_1、508_1、502_2、504_2、506_2和508_2的阳极电连接至第一电压VSS，光敏传感器502_1、504_1、506_1、508_1、502_2、504_2、506_2和508_2用来将光线转换为电荷。请注意，图1为了简洁并未另标示出输出电路518的范围，输出电路518仅标示于图2。
输出电路518用来依据光敏传感器502_1、504_1、506_1、508_1、502_2、504_2、506_2和508_2产生的所述电荷产生所述像素输出，输出电路518包括传输门510_1、512_1、514_1、516_1、510_2、512_2、514_2和516_2、重置晶体管106、源跟随晶体管108以及行选择晶体管110。如图1所示，像素P5'和像素P6之间具有分界，即像素P5'的下方边界和像素P6的上方边界的交界处。输出电路518(即传输门510_1、512_1、514_1、516_1、510_2、512_2、514_2和516_2、重置晶体管106、源跟随晶体管108以及行选择晶体管110)跨越像素P5'和像素P6的所述分界而设置，使输出电路518的一部分相邻像素P5'的光敏传感器502_1、504_1、506_1、508_1，输出电路518的另一部分相邻像素P6的光敏传感器502_2、504_2、506_2和508_2。其中传输门510_1、512_1、514_1、516_1、510_2、512_2、514_2和516_2包括闸极和两源/漏极，传输门510_1、512_1、514_1、516_1、510_2、512_2、514_2和516_2的闸极分别对应光敏传感器502_1、504_1、506_1、508_1、502_2、504_2、506_2和508_2，并分别依据传输门控制信号TX1_1、TX2_1、TX3_1、TX4_1、TX1_2、TX2_2、TX3_2、和TX4_2决定传输门510_1、512_1、514_1、516_1、510_2、512_2、514_2和516_2开启或关闭。
像素P5'的所述四个子像素共用浮置扩散区FD1且浮置扩散区FD1被所述四个子像素的光敏传感器502_1、504_1、506_1、508_1包围，像素P6的所述四个子像素共用浮置扩散区FD2且浮置扩散区FD2被所述四个子像素的光敏传感器502_2、504_2、506_2、508_2包围，每一传输门510_1、512_1、514_1、516_1、510_2、512_2、514_2和516_2的两源/漏极电连接于光敏传感器502_1、504_1、506_1、508_1、502_2、504_2、506_2和508_2和浮置扩散区FD1、FD2之间。源跟随晶体管108设置于重置晶体管106和行选择晶体管110之间，行选择晶体管110及第一重置晶体管106沿第一源跟随晶体管108对称设置，像素P5'里的传输门510_1、512_1、514_1、516_1均匀分布于像素P5'中；像素P6里的传输门510_2、512_2、514_2、516_2均匀分布于像素P6中。
具体来说，源跟随晶体管108的闸极和重置晶体管106的一源/漏极都电连接至浮置扩散区FD1及FD2，重置晶体管106的另一源/漏极电连接至第二电压VDD，第二电压VDD不同于第一电压VSS。重置晶体管106的闸极依据重置信号RST的控制决定是否导通，源跟随晶体管108串接于行选择晶体管110，源跟随晶体管108的一源/漏极电连接至行选择晶体管110的一源/漏极，源跟随晶体管108的另一源/漏极电连接至第二电压VDD。行选择晶体管110的另一源/漏极作为所述像素输出的输出端POUT并电连接至位线BL，行选择晶体管110的闸极依据字线WL上的行选择信号RSEL控制决定是否导通并将所述像素输出从输出端POUT输出至位线BL。
从像素P5'和像素P6的半导体结构的俯视图来看，在某些实施例中，行选择晶体管110、源跟随晶体管108和重置晶体管106排成一列形成晶体管列。具体来说，图1中像素P5'和像素P6各具有一个范围，且像素P5'和像素P6彼此相邻接处形成像素P5'和像素P6的界线。源跟随晶体管108跨于像素P5'和像素P6之间，即源跟随晶体管108跨越像素P5'和像素P6的所述分界而设置，并延伸至像素P5'和像素P6。从俯视图来看，源跟随晶体管108的一部分，即源跟随晶体管108的上方部分，位于像素P5'和像素P6的所述分 界的一侧，并至少相邻(即左右相邻)像素P5'的光敏传感器502_1、504_1、506_1、508_1，源跟随晶体管108的另一部分，即源跟随晶体管108的下方部分，位于像素P5'和像素P6的所述分界的另一侧，并至少相邻(即左右相邻)像素P6的光敏传感器502_2、504_2、506_2和508_2。重置晶体管106设置于像素P5'，且重置晶体管106相邻像素P5'的光敏传感器502_1、504_1、506_1、508_1，行选择晶体管110设置于像素P6，且行选择晶体管110相邻像素P6的光敏传感器502_2、504_2、506_2和508_2。像素P5'和像素P6共享输出端POUT。和传统的像素设置相比，本申请将像素P5'和像素P6配置为一组，使像素P5'和像素P6共享输出电路116，并打破像素P5'和像素P6的界线，将输出电路116跨于像素P5'和像素P6之间来设置，使原本需要局限在像素P5'或像素P6的范围内的源跟随晶体管108可跨越像素P5'和像素P6的所述分界，势必可增加设计上的弹性，也就是说，可以争取到额外的空间来增加源跟随晶体管108的长度，由于源跟随晶体管108的沟道长度L直接和源跟随晶体管108的长度有关，也就是本申请得以增加源跟随晶体管108的沟道长度L，以达到减少像素P5'和像素P6的面积和降低随机电报信号噪声的目的。
如前所述，从像素P5'和像素P6的半导体结构的俯视图来看，在某些实施例中，行选择晶体管110、源跟随晶体管108和重置晶体管106排成一列形成晶体管列，且像素P5'的光敏传感器502_1、504_1、506_1、508_1和像素P6的光敏传感器502_2、504_2、506_2和508_2设置在所述晶体管列的不同一侧。
在本实施例中，像素P5'和像素P6的上方设置有滤色片，并依照拜耳阵列排列为像素组，其进一步绘示如图3，图3为基于图1的图像传感器的半导体结构的拜耳像素组的第一实施例的俯视图。图3中的拜耳像素组800包括两个图1所示的单位像素组，即像素P5'、P6所构成的单位像素组和像素P7'、P8所构成的单位像素组。像素P5'的光敏传感器502_1、504_1、506_1、508_1上方设置有绿色Gb滤色片，以及像素P6的光敏传感器502_2、504_2、506_2和 508_2上方设置有绿色Gr滤色片，像素P7'的光敏传感器502_1、504_1、506_1、508_1上方设置有蓝色B滤色片，以及像素P8的光敏传感器502_2、504_2、506_2和508_2上方设置有红色R滤色片。换句话说，若从俯视图来看，所述绿色Gb滤色片重叠于像素P5'，所述绿色Gr滤色片重叠于像素P6，所述蓝色B滤色片重叠于像素P7'，所述红色R滤色片重叠于像素P8。像素P5'和像素P6为对角错位设置；像素P7'和像素P8为对角错位设置。
值得说明的是，从俯视图来看，上述各滤色片可以是与对应的像素完全重叠；也可以是各滤色片与对应的像素部分重叠；还可以是各滤色片罩住与其对应的像素，即滤色片的面积大于像素的面积，使滤色片完全盖住与其对应的像素。
图3的拜耳像素组800中，像素P5'和像素P6的上方皆设置绿色Gb和Gr滤色片，并且像素P5'和像素P6共享输出端POUT，像素P7'和像素P8的上方设置蓝色B和红色R滤色片，并且像素P7'和像素P8共享输出端POUT，也就是说，像素P5'和像素P6会通过同一条位线BL进入同一读取电路，好处在于避免绿色像素Gr和Gb因进入不同的读取电路而造成绿色像素Gr和Gb之间的影像失调问题，应注意的是，实际上读取电路之间难免存在偏差，因此若同一拜耳像素组中的绿色像素Gr和Gb进入不同的读取电路被读取，会造成上述的影像失调问题。因此图3的拜耳像素组800可改善上述的影像失调问题。
图4为基于图1的图像传感器的半导体结构的拜耳像素组的第二实施例的俯视图。和同3类似，图4中的拜耳像素组900包括两个图1所示的单位像素组，即像素P5'、P6所构成的单位像素组和像素P7'、P8所构成的单位像素组。差别在于像素P5'的光敏传感器502_1、504_1、506_1、508_1上方设置有绿色Gr滤色片，以及像素P6的光敏传感器502_2、504_2、506_2和508_2上方设置有绿色GB滤色片，像素P7'的光敏传感器502_1、504_1、506_1、508_1上方设置有红色R滤色片，以及像素P8的光敏传感器502_2、504_2、 506_2和508_2上方设置有蓝色B滤色片。换句话说，若从俯视图来看，所述绿色Gr滤色片重叠于像素P5'，所述绿色Gb滤色片重叠于像素P6，所述红色R滤色片重叠于像素P7'，所述蓝色B滤色片重叠于像素P8。像素P5'和像素P6为对角错位设置；像素P7'和像素P8为对角错位设置。图4的拜耳像素组900的颜色配置和图3的拜耳像素组800稍有不同，但具备相同的优点，即像素P5'和像素P6会通过同一条位线BL进入同一读取电路，可避免绿色像素Gr和Gb因进入不同的读取电路而造成绿色像素Gr和Gb之间的影像失调问题。
综上，本申请可以通过上述像素组的设置方式结合将相同颜色的像素Gr和Gb对角错位设置以共享输出电路，实现使得同样为绿色像素的第一像素Gr和第三像素Gb输出一致以提高影像质量，在输出电路共享的基础上可以减少像素的面积且通过将输出电路中的源跟随晶体管延伸至第一像素及第三像素的PD旁边以在有限的半导体面积上增加源跟随晶体管的沟道长度，进而可以缩小像素的尺寸及减少杂讯干扰。即在对角错位设置的在第一像素Gr和第三像素Gb共享输出电路以提高像素输出的一致性及图像的质量的同时，在单个像素组较小的情况下，通过输出电路共享可以减少输出电路占用空间，进而在有限的空间可以设置更大的PD，以提高进光量，且源跟随晶体管跨越到两个像素的PD旁边，在不影响PD占用的空间的情况下可以进一步的增加源跟随晶体管的沟通长度，以改善杂讯，所以本申请可以使图像传感器在有限的空间里集成更多更高的像素以进一步实现高质量的图像输出。
本申请还提供了一种芯片，其包括图像传感器800/900。本申请还提供了一种电子装置，图5为本申请的图像传感器应用于电子装置1100中的实施例的示意图，如图5所示，电子装置1100包括显示屏组件1104和图像传感器800/900。其中，电子装置1100可为例如智能型手机、个人数字助理、手持式计算机系统、平板计算机或数码相机等任何电子装置。
上文的叙述简要地提出了本申请某些实施例之特征，而使得本申请所属技术领域具有通常知识者能够更全面地理解本申请内容的多种态样。本申请所属技术领域具有通常知识者当可明了，其可轻易地利用本申请内容作为基础，来设计或更动其他工艺与结构，以实现与此处所述之实施方式相同的目的和/或达到相同的优点。本申请所属技术领域具有通常知识者应当明白，这些均等的实施方式仍属于本申请内容之精神与范围，且其可进行各种变更、替代与更动，而不会悖离本申请内容之精神与范围。

Claims (20)

  1. 一种图像传感器的半导体结构，其特征在于：
    所述图像传感器的半导体结构包括：半导体衬底和设置于所述半导体衬底的若干个像素组，每个像素组包括：位于同一行且相邻的第一像素及第二像素，位于另一行且相邻的第三像素及第四像素，所述第一像素及所述第三像素为对角错位设置且所述第一像素及所述第三像素为相同颜色的像素；
    所述第一像素、第二像素、第三像素及第四像素各自均包括四个按照两行两列排列的子像素，每个像素里的四个子像素共用浮置扩散区且所述浮置扩散区被所述四个子像素的光敏传感器包围，所述光敏传感器用来将光线转换为电荷；
    所述第一像素和所述第三像素的输出电路共享，所述第一像素和所述第三像素共享的所述输出电路跨越所述第一像素及所述第三像素的分界且延伸至所述第一像素的左侧/右侧和所述第三像素的右侧/左侧，所述输出电路用来依据所述电荷产生像素输出，所述输出电路包括第一源跟随晶体管；
    其中，从俯视图来看，所述第一源跟随晶体管的一部分位于所述第一像素及第三像素的所述分界的一侧，并至少与所述第一像素的左侧/右侧的光敏传感器相邻，且所述第一源跟随晶体管的另一部分位于所述第一像素及第三像素的所述分界的另一侧，并至少与所述第三像素的右侧/左侧的光敏传感器相邻。
  2. 如权利要求1所述的图像传感器的半导体结构，其中所述第一像素及所述第三像素均为绿色像素。
  3. 如权利要求2所述的图像传感器的半导体结构，其中所述输出电路另包括设置于第三像素的第一行选择晶体管，且所述第一行选择晶体管相邻所述第三像素的光敏传感器。
  4. 如权利要求3所述的图像传感器的半导体结构，其中所述输出电路另包括设置于第一像素的第一重置晶体管，且所述第一重置晶体管相邻所述第一像素的光敏传感器。
  5. 如权利要求4所述的图像传感器的半导体结构，其中从俯视图来看，所述第一行选择晶体管、所述第一源跟随晶体管和所述第一重置晶体管排成一列形成晶体管列。
  6. 如权利要求3所述的图像传感器的半导体结构，其中所述输出电路通过将所述第一行选择晶体管的一源/漏极作为输出端，来输出所述像素输出。
  7. 如权利要求4所述的图像传感器的半导体结构，其中从俯视图来看，所述第一源跟随晶体管设置于所述第一重置晶体管和所述第一行选择晶体管之间。
  8. 如权利要求7所述的图像传感器的半导体结构，其中，所述第一行选择晶体管及所述第一重置晶体管沿所述第一源跟随晶体管对称设置。
  9. 如权利要求2所述的图像传感器的半导体结构，其中所述每个像素里的四个子像素均包括传输门，且所述传输门位于其所在的子像素的光敏传感器所在的区域。
  10. 如权利要求9所述的图像传感器的半导体结构，其中从俯视图来看，所述第一像素、第二像素、第三像素及第四像素里的传输门都均匀分布于其所在的像素中。
  11. 如权利要求1至10中任一项所述的图像传感器的半导体结构，其中所述第二像素及第四像素为对角错位设置且所述第二像素及第四像素的输出电路共享。
  12. 如权利要求11所述的图像传感器的半导体结构，其中所述第二像素及第四像素共享的输出电路位于所述第二像素及第四像素之间且延伸至所述第二像素的左侧/右侧和所述第四像素的右侧/左侧。
  13. 如权利要求12所述的图像传感器的半导体结构，其中，所述第二像素及第四像素共享的输出电路包括第二源跟随晶体管，所述第二源跟随晶体管跨越所述第二像素及第四像素的分界并至少 延伸至与所述第二像素的左侧/右侧的光敏传感器相邻，且至少延伸至与所述第四像素的右侧/左侧的光敏传感器相邻。
  14. 如权利要求13所述的图像传感器的半导体结构，其中，所述第二像素及第四像素共享的输出电路还包括第二行选择晶体管及第二重置晶体管，所述第二行选择晶体管设置于第四像素，且所述第二行选择晶体管相邻所述第四像素的光敏传感器；第二重置晶体管设置于第二像素，且所述第二重置晶体管相邻所述第二像素的光敏传感器。
  15. 如权利要求14所述的图像传感器的半导体结构，其中从俯视图来看，所述第二行选择晶体管、所述第二源跟随晶体管和所述第二重置晶体管排成一列形成晶体管列。
  16. 如权利要求15所述的图像传感器的半导体结构，其中从俯视图来看，所述第二源跟随晶体管设置于所述第二重置晶体管和所述第二行选择晶体管之间。
  17. 如权利要求16所述的图像传感器的半导体结构，其中，所述每个像素里的四个子像素的颜色均相同。
  18. 如权利要求17所述的图像传感器的半导体结构，其中，所述第二像素为蓝色像素，所述第四像素为红色，且所述第一像素、第二像素、第三像素及第四像素形成拜耳阵列。
  19. 一种芯片，其特征在于，包括：
    如权利要求1-18中任一项所述的图像传感器的半导体结构。
  20. 一种电子装置，其特征在于，包括：
    如权利要求1-18中任一项所述的图像传感器的半导体结构。
PCT/CN2019/109426 2019-09-30 2019-09-30 图像传感器的半导体结构、芯片及电子装置 WO2020011285A2 (zh)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11233086B2 (en) 2019-09-30 2022-01-25 Shenzhen GOODIX Technology Co., Ltd. Semiconductor structure of image sensor, chip and electronic apparatus

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11527569B2 (en) * 2020-05-18 2022-12-13 Omnivision Technologies, Inc. High dynamic range split pixel CMOS image sensor with low color crosstalk
CN112367482B (zh) * 2020-10-26 2022-08-09 Oppo广东移动通信有限公司 一种感光器件及飞行时间测距系统
KR20220103282A (ko) * 2021-01-15 2022-07-22 에스케이하이닉스 주식회사 이미지 센싱 장치

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7916195B2 (en) * 2006-10-13 2011-03-29 Sony Corporation Solid-state imaging device, imaging apparatus and camera
KR20100080172A (ko) * 2008-12-31 2010-07-08 주식회사 동부하이텍 이미지 센서 및 그 제조 방법
JP5564874B2 (ja) * 2009-09-25 2014-08-06 ソニー株式会社 固体撮像装置、及び電子機器
JP5644177B2 (ja) * 2010-05-07 2014-12-24 ソニー株式会社 固体撮像装置、および、その製造方法、電子機器
US9165959B2 (en) * 2013-02-25 2015-10-20 Omnivision Technologies, Inc. Image sensor with pixel units having mirrored transistor layout
JP2015012303A (ja) * 2013-06-26 2015-01-19 ソニー株式会社 固体撮像装置および電子機器
US9305949B2 (en) * 2013-11-01 2016-04-05 Omnivision Technologies, Inc. Big-small pixel scheme for image sensors
JP6334203B2 (ja) * 2014-02-28 2018-05-30 ソニー株式会社 固体撮像装置、および電子機器
JP2016042557A (ja) * 2014-08-19 2016-03-31 ソニー株式会社 固体撮像素子および電子機器
US9774801B2 (en) * 2014-12-05 2017-09-26 Qualcomm Incorporated Solid state image sensor with enhanced charge capacity and dynamic range
TWI696278B (zh) * 2015-03-31 2020-06-11 日商新力股份有限公司 影像感測器、攝像裝置及電子機器
KR102473154B1 (ko) * 2016-01-11 2022-12-02 에스케이하이닉스 주식회사 이미지 센서
US11201186B2 (en) * 2016-01-20 2021-12-14 Sony Corporation Solid-state imaging device, driving method therefor, and electronic apparatus
JP6789653B2 (ja) * 2016-03-31 2020-11-25 キヤノン株式会社 光電変換装置およびカメラ
CN108242449B (zh) * 2016-12-27 2023-12-22 三星电子株式会社 图像传感器及包括其的电子装置
KR102551862B1 (ko) * 2018-01-29 2023-07-06 에스케이하이닉스 주식회사 이미지 센서
KR102560775B1 (ko) * 2018-12-20 2023-07-28 삼성전자주식회사 이미지 센서
CN209729909U (zh) * 2019-09-30 2019-12-03 深圳市汇顶科技股份有限公司 图像传感器的半导体结构、芯片及电子装置
KR102358599B1 (ko) 2019-09-30 2022-02-08 선전 구딕스 테크놀로지 컴퍼니, 리미티드 이미지 센서의 반도체 구조, 칩 및 전자 장치

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11233086B2 (en) 2019-09-30 2022-01-25 Shenzhen GOODIX Technology Co., Ltd. Semiconductor structure of image sensor, chip and electronic apparatus

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