WO2020006649A1 - 多位元触发器及电子设备 - Google Patents

多位元触发器及电子设备 Download PDF

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Publication number
WO2020006649A1
WO2020006649A1 PCT/CN2018/000242 CN2018000242W WO2020006649A1 WO 2020006649 A1 WO2020006649 A1 WO 2020006649A1 CN 2018000242 W CN2018000242 W CN 2018000242W WO 2020006649 A1 WO2020006649 A1 WO 2020006649A1
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Prior art keywords
oxide
effect transistor
type metal
coupled
node
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PCT/CN2018/000242
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English (en)
French (fr)
Inventor
吴敬杰
杨智文
谢文斌
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崛智科技有限公司
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Application filed by 崛智科技有限公司 filed Critical 崛智科技有限公司
Priority to CN201880038967.5A priority Critical patent/CN111183586B/zh
Priority to PCT/CN2018/000242 priority patent/WO2020006649A1/zh
Priority to US16/626,894 priority patent/US10958252B2/en
Publication of WO2020006649A1 publication Critical patent/WO2020006649A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356—Bistable circuits
    • H03K3/356104—Bistable circuits using complementary field-effect transistors

Definitions

  • the invention relates to a flip-flop (FF), in particular to a multi-bit flip-flop capable of sharing a clock and an electronic device.
  • FF flip-flop
  • Triggers can store only one bit of data. When you want to store multi-bit data, you must combine multiple triggers together, and they are collectively referred to as multi-bit triggers.
  • the clock path is one of the most complicated parts of the overall circuit design. Therefore, how to improve the clock path of the multi-bit flip-flops while effectively reducing the clock Amplitude is an important subject in this technical field.
  • An embodiment of the present invention provides a multi-bit flip-flop.
  • the multi-bit flip-flop includes a clock input pin, a clock buffer circuit, and a plurality of flip-flops.
  • the clock input pin is configured to receive a first clock signal.
  • the clock buffer circuit is coupled to the clock input pin, and is used to receive the first clock signal, and provides a second clock signal and a third clock signal according to the first clock signal.
  • the clock buffer circuit includes the first clock signal.
  • An inverter and a second inverter The first inverter is coupled to the clock input pin via the first node, and is used to receive and invert the first clock signal, and output the inverted first clock signal as the second clock via the second node. signal.
  • the second inverter is coupled to the second node via the third node, and is configured to receive and invert the second clock signal, and output the inverted second clock signal as the third clock signal via the fourth node.
  • Each flip-flop has a corresponding data input terminal and a data output terminal, and each flip-flop is coupled to the third node and the fourth node for receiving the second clock signal and the third clock signal, and Data is stored based on the second clock signal and the third clock signal.
  • An embodiment of the present invention further provides a multi-bit flip-flop.
  • the multi-bit flip-flop includes a clock input pin, a clock buffer circuit, and a plurality of flip-flops.
  • the clock input pin is configured to receive a first clock signal.
  • the clock buffer circuit is coupled to the clock input pin, and is used to receive the first clock signal, and provides a second clock signal and a third clock signal according to the first clock signal.
  • the clock buffer circuit includes the first clock signal.
  • An inverter, a second inverter, and a transistor string The first inverter is coupled to the clock input pin via the first node, and is used to receive and invert the first clock signal, and output the inverted first clock signal as the fourth clock via the second node. signal.
  • the second inverter is coupled to the second node via the third node, and is configured to receive and invert the fourth clock signal, and output the inverted fourth clock signal as the fifth clock signal via the fourth node.
  • the transistor string is coupled to the third node and the fourth node, and is used for receiving the fourth clock signal and the fifth clock signal, and according to the fourth clock signal and the fifth clock signal, the fifth node and the sixth clock
  • the node provides a second clock signal and a third clock signal.
  • Each of the flip-flops has a corresponding data input terminal and a data output terminal, and each of the flip-flops is coupled to the fifth node and the sixth node for receiving the second clock signal and the third clock signal. And store data according to the second clock signal and the third clock signal.
  • FIG. 1 is a schematic circuit diagram of a multi-bit flip-flop according to an embodiment of the present invention.
  • FIG. 2 is a timing diagram of the multi-bit flip-flop of FIG. 1.
  • FIG. 3 is a schematic circuit diagram of a multi-bit flip-flop according to another embodiment of the present invention.
  • FIG. 4 is a schematic circuit diagram of a multi-bit flip-flop according to another embodiment of the present invention.
  • FIG. 5 is a timing diagram of the multi-bit flip-flop of FIG. 4.
  • FIG. 6 is a schematic circuit diagram of a multi-bit flip-flop according to another embodiment of the present invention.
  • FIG. 7 is a timing diagram of the multi-bit flip-flop of FIG. 6.
  • FIG. 8 is a circuit diagram of a multi-bit flip-flop according to another embodiment of the present invention.
  • FIG. 9 is a schematic circuit diagram of a flip-flop in the multi-bit flip-flop of FIG. 1.
  • the multi-bit trigger provided by the embodiment of the present invention may be applicable to any electronic device having a computing function, such as a smart phone, a game machine, a router, or a tablet computer.
  • the present invention does not limit the specific implementation of the multi-bit flip-flop of the embodiment included in the electronic device, and those with ordinary knowledge in the technical field should be able to make related designs based on actual needs or applications.
  • FIG. 1 is a schematic circuit diagram of a multi-bit flip-flop according to an embodiment of the present invention.
  • the multi-bit flip-flop 1 includes a clock input pin PIN1, a clock buffer circuit 110, and a plurality of flip-flops, such as a flip-flop 121 to a flip-flop 128.
  • the clock input pin PIN1 is configured to receive the clock signal CP.
  • the clock buffer circuit 110 is coupled to the clock input pin PIN1 to receive the clock signal CP, and provides the clock signal CKB and the clock signal CCK according to the clock signal CP.
  • the clock buffer circuit 110 may include a first inverter 111 and a second inverter 112.
  • the first inverter 111 is coupled to the clock input pin PIN1 via a node T11 to receive and invert the clock signal CP, and outputs the inverted clock signal CP as a clock signal CKB via a node T12.
  • the second inverter 112 is coupled to the node T12 via the node T13, and is configured to receive and invert the clock signal CKB, and output the inverted clock signal CKB as the clock signal CCK via the node T14.
  • each of the flip-flops 121 to 128 has a corresponding data input terminal and data output terminal.
  • the flip-flop 121 has a data input terminal D1 and a data output terminal Q1
  • the flip-flop 122 has a data input terminal D2 and a data output terminal Q2.
  • the flip-flop 127 has a data input terminal D7 and a data output terminal Q7
  • the flip-flop 128 has a data input terminal D8 and a data output terminal Q8, and each of the flip-flops 121 to 128 is coupled to the node T13 and the node T14. Is used to receive the clock signal CKB and the clock signal CKD, and store data according to the clock signal CKB and the clock signal CCK.
  • the nodes T11 and T12 can refer to the input and output terminals of the first inverter 111, respectively, and the nodes T13 and T14 also refer to the second inverters, respectively.
  • the multi-bit flip-flop 1 provided in this embodiment is designed so that each flip-flop 121-128 is coupled to the nodes T13 and The node T14 therefore enables each of the flip-flops 121 to 128 to share the same clock signal CKB and the same clock signal CCK.
  • each of the triggers 121 to 128 in this embodiment may be a static trigger, a dynamic trigger, or any type of trigger.
  • the present invention does not limit the specific implementation manner of each of the triggers 121 to 128.
  • Those with ordinary knowledge in the technical field should be able to make related designs based on actual needs or applications.
  • the operation principle of storing data according to the clock signal CKB and the clock signal CKD of each flip-flop 121-128 is well known to those having ordinary knowledge in the technical field, the above-mentioned each flip-flop 121-128 The details of 128 will not be repeated here.
  • the first inverter 111 may include a P-type metal-oxide-semiconductor field-effect transistor (PMOSFET) P11 and an N-type metal-oxide-semiconductor field-effect transistor (NMOSFET) N11 connected in series with each other, but the present invention is not limited thereto. Connections and transistor types are limited.
  • the source of the P-type metal-oxide-semiconductor field-effect transistor P11 is coupled to the power supply voltage VDD
  • the source of the N-type metal-oxide-semiconductor field-effect transistor N11 is coupled to the ground voltage VSS.
  • the drain of the half field-effect transistor P11 and the N-type metal-oxide-semiconductor half-field transistor N11 are coupled to the node T12.
  • the gate of the P-type metal-oxide-semiconductor half-effect transistor P11 and the N-type metal-oxide semiconductor The gate of the field effect transistor N11 is commonly coupled to the node T11.
  • the second inverter 112 may include a P-type metal-oxide-semiconductor half-effect transistor P12 and an N-type metal-oxide-semiconductor half-effect transistor N12 connected in series with each other, but the present invention also does not use this connection relationship and the transistor type is limit.
  • the source of the P-type metal-oxide-semiconductor field-effect transistor P12 is coupled to the power supply voltage VDD
  • the source of the N-type metal-oxide-semiconductor half-field-effect transistor N12 is coupled to the ground voltage VSS.
  • the drain of the half field effect transistor P12 and the drain of the N-type metal-oxide-semiconductor N12 are coupled to the node T14.
  • the gate of the P-type metal-oxide-semiconductor half-effect transistor P12 and the N-type metal-oxide-semiconductor is commonly coupled to the node T13.
  • FIG. 2 is a timing diagram of the multi-bit flip-flop of FIG. 1.
  • the i-th flip-flop 12i since at the first rising edge of the clock signal CCK (that is, at the first rising edge of the clock signal CKB), the i-th flip-flop 12i (where i is 1 to 8) The data signal input from the data input terminal Di of the i) has a logic "high” level, so the data signal output from the data output terminal Qi of the i-th flip-flop 12i can be changed from the logic "low” level to Logic "high” level.
  • the data signal input to the data input terminal Di of the i-th flip-flop 12i has The logic "low” level, so the data signal output from the data output terminal Qi of the i-th flip-flop 12i can be changed from the logic "high” level to the logic "low” level.
  • the i-th flip-flop 12i can latch the data input terminal Di only by the rising edge of the clock signal CKD (or the falling edge of the clock signal CKD). Data signal. Since the principle of the data signal latched by the flip-flop 12i is also known to those having ordinary knowledge in the technical field, the details of the above-mentioned details will not be repeated here.
  • the P-type metal-oxide-semiconductor half-effect transistors P11, P12, and N-type metal-oxide-semiconductor half-effect transistors N11, N12 can be ultra-low threshold voltage (uLVT) metal-oxide
  • uLVT ultra-low threshold voltage
  • a half field effect transistor is used for implementation, but the invention is not limited to this type of transistor. Therefore, when the uLVT metal-oxide half field effect transistor is used in this embodiment, the i-th flip-flop 12i only needs to perform the lock according to the relatively small level change on the clock signal CKB and the clock signal CKD. Save action.
  • FIG. 3 is a schematic circuit diagram of a multi-bit flip-flop according to another embodiment of the present invention. Among them, some of the elements in FIG. 3 that are the same as or similar to those in FIG. 1 are marked with the same or similar drawing numbers, so details are not described in detail here.
  • the clock buffer circuit 310 of the multi-bit flip-flop 3 may include a first inverter 111, a second inverter 112, a P-type MOSFET and an N-type MOSFET. Field effect transistor N33.
  • the P-type metal-oxide-semiconductor field-effect transistor P33 is connected in series between the P-type metal-oxide-semiconductor field-effect transistor P11 and the power supply voltage VDD, and the source of the P-type metal-oxide-semiconductor half-field effect transistor P33 is coupled At the power supply voltage VDD, the drain and gate of the P-type metal-oxide-semiconductor field-effect transistor P33 are coupled to the source of the P-type metal-oxide-semiconductor field-effect transistor P11.
  • the N-type metal-oxide-semiconductor FET N33 is connected in series between the N-type metal-oxide-semiconductor FET N12 and the ground voltage VSS, where the source of the N-type metal-oxide-semiconductor FET N33 is Coupled to the ground voltage VSS, the drain and gate of the N-type metal-oxide-semiconductor field-effect transistor N33 are commonly coupled to the source of the N-type metal-oxide-semiconductor field-effect transistor N12. Therefore, compared with the clock signal CKB and the clock signal CKD in FIG. 1, the clock signal CKB and the clock signal CCK in FIG.
  • FIG. 4 is a schematic circuit diagram of a multi-bit flip-flop according to another embodiment of the present invention. Among them, some elements in FIG. 4 that are the same as or similar to those in FIG. 1 are marked with the same or similar drawing numbers, and therefore details are not described in detail here.
  • the clock buffer circuit 410 of FIG. 4 is used to receive the clock signal CP and provide the clock signal according to the clock signal CP. CKN and clock signal CKP.
  • the clock buffer circuit 410 may include a first inverter 111, a second inverter 112, and a transistor string 313.
  • the transistor string 313 is coupled to the nodes T13 and T14, and is used to receive the clock signal CKB and the clock signal CKD, and according to the clock signal CKB and the clock signal CKD, the clock signal CKN and Clock signal CKP.
  • the transistor string 313 may include a P-type metal-oxide-semiconductor field-effect transistor P43 and an N-type metal-oxide-semiconductor field-effect transistor N43, N44 connected in series with each other.
  • the source of the P-type metal-oxide-semiconductor field-effect transistor P43 is coupled to the power supply voltage VDD, the drain of the P-type metal-oxide-semiconductor field-effect transistor P43 and the N-type metal-oxide-semiconductor field-effect transistor N43.
  • the drain of the N-type metal-oxide-semiconductor field-effect transistor N43 and the drain of the N-type metal-oxide-semiconductor field-effect transistor N44 are commonly coupled to the node T46, and the N-type metal-oxide-semiconductor half-field transistor N43
  • the source of the effect transistor N44 is coupled to the ground voltage VSS
  • the gate of the P-type metal-oxide-semiconductor field-effect transistor P43 is coupled to the node T13, N together with the gate of the N-type metal-oxide-semiconductor field-effect transistor N43.
  • the gate electrode of the NMOS transistor N44 is coupled to the node T14.
  • the nodes T45 and T46 can also refer to the two output ends of the clock buffer circuit 410, and the node T45 is used to provide the clock signal CKN, and the node T46 is used to Provides clock signal CKP.
  • the clock buffer circuit 410 may further include a P-type metal-oxide-semiconductor field-effect transistor P44 and capacitors C1 and C2.
  • the source of the P-type metal-oxide-semiconductor field-effect transistor P44 is coupled to the node T45
  • the drain of the P-type metal-oxide-semiconductor field-effect transistor P44 is coupled to the node T46.
  • the gate of the effect transistor P44 is coupled to the node T14 together with the gate of the N-type metal-oxide-semiconductor half field effect transistor N44.
  • FIG. 5 is a timing diagram of the multi-bit flip-flop of FIG. 4. According to the teachings of the above content, those with ordinary knowledge in the technical field should understand that, compared to the embodiments of FIG. 1 and FIG. 3, the i-th flip-flop 12i of FIG. 4 will only pass the clock signal CKN. The rising edge (or the falling edge of the clock signal CKP) is used to latch the data signal input to its data input terminal Di.
  • FIG. 6 is another aspect of the present invention.
  • a circuit diagram of a multi-bit flip-flop provided by an embodiment. Among them, some of the elements in FIG. 6 that are the same as or similar to those in FIG. 1 are marked with the same or similar drawing numbers, and therefore no further details are given here. As shown in FIG.
  • the clock buffer circuit 610 is further configured to provide the power conversion signal SW1 and the power conversion signal SW2 via the node T65 and the node T66 according to the clock signal CKB and the clock signal CKD, and each flip-flop 121 to 128 Both are coupled to the node T65 and the node T66, and are used to receive the power conversion signal SW1 and the power conversion signal SW2. It can be understood that, in this embodiment, the node T65 is used to provide the power conversion signal SW1, and the node T66 is used to provide the power conversion signal SW2.
  • the clock buffer circuit 610 of FIG. 6 may include a first inverter 111, a second inverter 112, a P-type metal-oxide-semiconductor field-effect transistor P63, P64, and an N-type metal-oxide-semiconductor half-field-effect transistor. N63, N64.
  • the source of the P-type metal-oxide-semiconductor field-effect transistor P63 is coupled to the power supply voltage VDD
  • the drain of the P-type metal-oxide-semiconductor field-effect transistor P63 is coupled to the node T65.
  • the gate of the field effect transistor P63 is coupled to the node T13 together with the flip-flops 121-128.
  • the source of the N-type metal-oxide-semiconductor field-effect transistor N63 is coupled to the node T65, and the drain of the N-type metal-oxide-semiconductor field-effect transistor N63 is coupled to the power supply voltage VDD.
  • the gate of N63 is coupled to the node T13 together with the gate of the P-type CMOS half field effect transistor P63.
  • the source of the P-type metal-oxide-semiconductor field-effect transistor P64 is coupled to the node T66, and the drain of the P-type metal-oxide-semiconductor field-effect transistor P64 is coupled to the ground voltage VSS.
  • the gate of the crystal P64 is coupled to the node T14 together with the flip-flops 121 to 128.
  • the source of the N-type metal-oxide-semiconductor field-effect transistor N64 is coupled to the ground voltage VSS, and the drain of the N-type metal-oxide-semiconductor field-effect transistor N64 is coupled to the node T66.
  • the gate of N64 is coupled to the node T14 together with the gate of the P-type metal-oxide-semiconductor field-effect transistor P64.
  • FIG. 7 is a timing diagram of the multi-bit flip-flop of FIG. 6.
  • the P-type metal-oxide-semiconductor FETs P63, P64 and N-type metal-oxide-semiconductor MOSFETs N63, N64 can be viewed as a whole.
  • the multi-bit flip-flop 6 provided in this embodiment is designed to use this weak hold circuit as a power conversion when the clock signal CP is at a logic low level.
  • the strong hold circuit and the weak hold circuit are usually distinguished by designing different threshold voltages or channel lengths.
  • FIG. 8 is a schematic circuit diagram of a multi-bit flip-flop according to another embodiment of the present invention. Among them, some elements in FIG. 8 that are the same as or similar to those in FIG. 6 are marked with the same or similar drawing numbers, and therefore details thereof will not be described in detail here. As shown in FIG. 8, compared to the clock buffer circuit 610 of FIG. 6, the clock buffer circuit 810 of FIG.
  • the 8 may include a first inverter 111, a second inverter 112, and a P-type metal-oxide half-field-effect power generator. Crystals P83, P84, P85 and N-type metal-oxide half field effect transistors N83, N84, N85.
  • the source of the P-type metal-oxide-semiconductor field-effect transistor P83 is coupled to the power supply voltage VDD
  • the drain of the P-type metal-oxide-semiconductor field-effect transistor P83 is coupled to the node T65.
  • the gate of the field effect transistor P83 is coupled to the node T13 together with the flip-flops 121-128.
  • the source of the P-type metal-oxide-semiconductor field-effect transistor P84 is coupled to the power supply voltage VDD, and the drain and gate of the P-type metal-oxide-semiconductor field-effect transistor P84 are coupled to the P-type metal-oxide-semiconductor half-field-effect transistor.
  • the source of the crystal P85, the drain of the P-type metal-oxide-semiconductor field-effect transistor P85 is coupled to the node T65, and the gate of the P-type metal-oxide-semiconductor field-effect transistor P85 is coupled to the node with the flip-flops 121 to 128. T14.
  • the source of the N-type metal-oxide-semiconductor field-effect transistor N83 is coupled to the ground voltage VSS, and the drain of the N-type metal-oxide-semiconductor field-effect transistor N83 is coupled to the node T66.
  • the gate of the crystal N83 is coupled to the node T14 together with the flip-flops 121-128.
  • the source of the N-type metal-oxide-semiconductor field-effect transistor N84 is coupled to the ground voltage VSS, and the drain and gate of the N-type metal-oxide-semiconductor field-effect transistor N84 are coupled to the N-type metal-oxide-semiconductor FET N85.
  • the source of the N-type metal-oxide-semiconductor field-effect transistor N85 is coupled to the node T66, and the gate of the N-type metal-oxide-semiconductor field-effect transistor N85 is coupled to the node T13 together with the flip-flops 121-128. Therefore, compared to the power conversion signal SW1 and the power conversion signal SW2 in FIG. 6, the power conversion signal SW1 and the power conversion signal SW2 in FIG. 8 can reduce their amplitudes by 1Vt, for example, the logic “high” bit of the power conversion signal SW1 1Vt has been reduced, and the logic "low” bit criterion of the power conversion signal SW2 has been increased by 1Vt, but the present invention does not limit the specific implementation of Vt. Since the operation details are also as described in the previous embodiment, they will not be repeated here.
  • each of the flip-flops 121 to 128 can be a dynamic flip-flop. Therefore, please refer to FIG. 9, which is a schematic circuit diagram of the flip-flop in the multi-bit flip-flop of FIG. 1. Among them, some of the elements in FIG. 9 that are the same as or similar to those in FIG. 1 are marked with the same or similar drawing numbers, so the details are not described in detail here. It is worth mentioning that, in order to facilitate the following description, this embodiment will be described by using only an example of the trigger 121. As shown in FIG. 9, the trigger 121 includes a transmission gate 901, a third inverter 902, a fourth inverter 903, a pull-up transistor 904, and a pull-down transistor 905.
  • the transmission gate 901 is coupled to the data input terminal D1 of the flip-flop 121, and is configured to receive a first data signal (not shown), and output the first data signal to the child node A1 according to the clock signal CKB and the clock signal CKD.
  • the third inverter 902 is coupled to the transmission gate 901 via the child node A1, and is used for inverting the first data signal, and outputs the inverted first data signal to the child node A2.
  • the fourth inverter 903 is coupled between the child node A2 and the data output terminal Q1 of the flip-flop 121, and is used to invert the inverted first data signal to generate a second data signal (not shown in the figure), and output the first data signal.
  • the pull-up transistor 904 is coupled between the child node A2 and the power supply voltage VDD, and is used to pull up the voltage of the child node A2 to the power supply voltage VDD.
  • the pull-down transistor 905 is coupled between the child node A2 and the ground voltage VSS, and is used to pull down the voltage of the child node A2 to the ground voltage VSS.
  • the "child node A1" in this embodiment can refer to the node where the transmission gate 901 is connected to the third inverter 902, and the "child node A2" also refers to the third inverter 902 is a node connected to the fourth inverter 903.
  • the transmission gate 901 includes an N-type metal-oxide-semiconductor half-field-effect transistor N93 and a P-type metal-oxide-semiconductor half-field-effect transistor P93, and a drain and P of the N-type metal-oxide-semiconductor half-field-effect transistor N93.
  • the drain of the P-type metal-oxide-semiconductor half field-effect transistor P93 is coupled to the data input D1 of the flip-flop 121 via the node A3.
  • the source of the transistor P93 is commonly coupled to the node A1 via the child node A4.
  • the gate of the N-type metal-oxide-semiconductor field-effect transistor N93 is used to receive the clock signal CKB.
  • the gate is used to receive the clock signal CKD.
  • the "child node A3" in this embodiment can refer to a node where the drain of the N-type metal-oxide-semiconductor N93 and the drain of the P-type metal-oxide-semiconductor half-effect transistor P93 are connected.
  • child node A4 also refers to a node where the source of the N-type metal-oxide-semiconductor field-effect transistor N93 is connected to the source of the P-type metal-oxide-semiconductor field-effect transistor P93.
  • the third inverter 902 is a tri-state inverter, and includes P-type metal-oxide-semiconductor half-effect transistors P94, P95 and N-type metal-oxide-semiconductor half-effect transistors N94,
  • the source of N95, P-type metal-oxide-semiconductor half-effect transistor P94 is coupled to the power supply voltage VDD
  • the source of N-type metal-oxide-semiconductor half-effect transistor N95 is coupled to ground voltage VSS
  • the P-type metal-oxide-semiconductor half-effect transistor is connected to ground voltage VSS.
  • the gate of the crystal P94 and the gate of the N-type CMOS half-effect transistor N95 are respectively coupled to the sub-node A1 to receive the first data signal.
  • the drain of the oxygen half field effect transistor P95 and the drain of the N-type metal oxide half field effect transistor N94 are coupled to the child node A2 through the child node A5.
  • the gate of the P type metal oxide half field effect transistor P95 is used for the gate.
  • the clock signal CKB is received, and the gate of the N-type metal-oxide-semiconductor field effect transistor N94 is used to receive the clock signal CKD.
  • the fourth inverter 903 includes a P-type metal-oxide-semiconductor half-effect transistor P96 and an N-type metal-oxide-semiconductor half-effect transistor N96.
  • the source of the P-type metal-oxide semi-effect transistor P96 is coupled to the power supply voltage.
  • N-type metal-oxide-semiconductor field-effect transistor N96 is coupled to the ground voltage VSS, the drain of P-type metal-oxide-semiconductor field-effect transistor P96 and the drain of N-type metal-oxide-semiconductor field-effect transistor N96 Coupled to data output Q1 of flip-flop 121 via sub-node A6, the gate of P-type metal-oxide-semiconductor half-effect transistor P96 and the gate of N-type metal-oxide-semiconductor half-effect transistor N96 are coupled via sub-node A7 Connected to the child node A2 to receive the inverted first data signal.
  • the pull-up transistor 904 is a P-type metal-oxide-semiconductor half-field-effect transistor P97
  • the pull-down transistor 905 is an N-type metal-oxide-semiconductor half-field-effect transistor N97
  • the P-type metal-oxide-semiconductor half-field-effect transistor P97 is source-coupled.
  • the source of the N-type MOSFET half-effect transistor N97 is coupled to the ground voltage VSS, the drain of the P-type MOSFET half-effect transistor P97 and the N-type MOSFET half-effect transistor N97
  • the drain electrodes are respectively coupled to the sub-node A2, and the gates of the P-type metal-oxide-semiconductor field-effect transistor P97 and the N-type metal-oxide-semiconductor field-effect transistor N97 are respectively coupled to the data of the trigger 121
  • the output terminal Q1 is used for receiving a second data signal.
  • the pull-up transistor 904 and the pull-down transistor 905 constitute a feedback inverter 906, and compared to the third inverter 902, the feedback inverter is configured as Weak hold circuit.
  • the third inverter 902 and the feedback inverter 906 will easily have data conflicts on the child node A2, so the signal output capability of the third inverter 902 must be It must be stronger than the signal output capability of the feedback inverter 906, so that the data on the child node A2 can be forcibly updated. Therefore, compared to the third inverter 902, the feedback inverter 906 must be configured as a weak holding circuit.
  • the multi-bit flip-flops provided in the embodiments of the present invention are designed so that each flip-flop can share the same clock, thereby improving the clock path of the multi-bit flip-flop.
  • the multi-bit flip-flop provided by the embodiment of the present invention is also designed to be capable of reducing the clock amplitude and having the advantages of clock control power conversion function.

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Abstract

一种多位元触发器(1)，所述多位元触发器(1)包括时脉输入引脚(PIN1)、时脉缓冲电路(110)及多个触发器(121～128)。时脉缓冲电路(110)用来接收自时脉输入引脚(PIN1)所收到的第一时脉信号(CP)，并且根据第一时脉信号(CP)提供第二时脉信号与第三时脉信号。而每一触发器(121～128)均用来接收第二时脉信号与第三时脉信号，并且根据第二时脉信号与第三时脉信号来存储数据。因此，所述多位元触发器(1)是设计让每一触发器(121～128)均能共用同一时脉。另提出一种包括所述的多位元触发器(1)的电子设备。

Description

多位元触发器及电子设备 技术领域
本发明涉及一种触发器(flip flop，FF)，尤其涉及一种能够共用时脉的多位元(multi-bit)触发器及电子设备。
背景技术
触发器只能存储一个位元的数据。当想要存储多位元的数据时，就必须将多个触发器合并起来使用，且其即统称为多位元触发器。由于在现有的多位元触发器中，时脉路径(clock path)为整体电路设计最复杂的部份之一，因此，如何改进多位元触发器的时脉路径，同时有效降低时脉振幅，是本技术领域的重要课题。
发明内容
本发明实施例提供一种多位元触发器。所述多位元触发器包括时脉输入引脚、时脉缓冲电路及多个触发器。时脉输入引脚被配置为接收第一时脉信号。时脉缓冲电路耦接于时脉输入引脚，用来接收第一时脉信号，并且根据第一时脉信号提供第二时脉信号与第三时脉信号，其中时脉缓冲电路包括第一逆变器(inverter)及第二逆变器。第一逆变器经由第一节点耦接于时脉输入引脚，用来接收与反相第一时脉信号，并且经由第二节点输出已反相的第一时脉信号作为第二时脉信号。第二逆变器经由第三节点耦接于第二节点，用来接收与反相第二时脉信号，并且经由第四节点输出已反相的第二时脉信号作为第三时脉信号。而每一触发器均具有相应的数据输入端与数据输出端，且每一触发器均耦接于第三节点与第四节点，用来接收第二时脉信号与第三时脉信号，并且根据第二时脉信号与第三时脉信号来存储数据。
本发明实施例另提供一种多位元触发器。所述多位元触发器包括时脉输入引脚、时脉缓冲电路及多个触发器。时脉输入引脚被配置为接收第一时脉信号。时脉缓冲电路耦接于时脉输入引脚，用来接收第一时脉信号，并且根据第一时脉信号提供第二时脉信号与第三时脉信号，其中时脉缓冲电路包括第一逆变器、第二逆变器及一电晶体串。第一逆变器经由第一节点耦接于时脉输入引脚，用来接收与反相第一时脉信号，并且经由第二节点输出已反相的第一时脉信号作为第四时脉信号。第二逆变器经由第三节点耦接于第二节点，用来接收与反相第四时脉信号，并且经由第四节点输出已反相的第四时脉信号作为第五时脉信号。电晶体串耦接于第三节点与第四节点，用来接收第四时脉信号与第五时脉信号，并且根据第四时脉信号与第五时脉信号，经由第五节点与第六节点提供第二时脉信号与第三时脉信号。而每一所述触发器均具有相应的数据输入端与数据输出端，且每一触发器均耦接于第五节点与第六节点，用来接收第二时脉信号与第三时脉信号，并且根据第二时脉信号与第三时脉信号来存储数据。
为使能更进一步了解本发明的特征及技术内容，请参阅以下有关本发明的详细说明与附图，但是此等说明与附图仅仅是用来说明本发明，而不是对本发明的权利范围作任何的限制。
附图概述
图1是本发明实施例所提供的多位元触发器的电路示意图。
图2是图1的多位元触发器的时序示意图。
图3是本发明另一实施例所提供的多位元触发器的电路示意图。
图4是本发明另一实施例所提供的多位元触发器的电路示意图。
图5是图4的多位元触发器的时序示意图。
图6是本发明另一实施例所提供的多位元触发器的电路示意图。
图7是图6的多位元触发器的时序示意图。
图8是本发明另一实施例所提供的多位元触发器的电路示意图。
图9是图1的多位元触发器中的触发器的电路示意图。
本发明的较佳实施方式
在下文中，将通过附图说明本发明的各种实施例来详细描述本发明。然而，本发明概念可能以许多不同形式来体现，且不应解释为限于本文中所阐述的例示性实施例。此外，在附图中相同参考数字可用以表示类似的元件。
详细地说，本发明实施例所提供的多位元触发器，可以是适用于任何具有计算功能的电子设备中，例如智能手机、游戏机、路由器或平板电脑等。总而言之，本发明并不限制所述电子设备所包含本实施例的多位元触发器的具体实现方式，本技术领域中具有通常知识者应可依据实际需求或应用来进行相关设计。请参阅图1，图1是本发明实施例所提供的多位元触发器的电路示意图。多位元触发器1包括时脉输入引脚PIN1、时脉缓冲电路110及多个触发器，例如触发器121到触发器128。值得一提的是，为了方便以下说明，图1的多个触发器则是仅先采用数量为8个的例子来进行说明，但其数量并不是用以限制本发明。在本实施例中，时脉输入引脚PIN1被配置为接收时脉信号CP。时脉缓冲电路110耦接于时脉输入引脚PIN1，用来接收时脉信号CP，并且根据时脉信号CP提供时脉信号CKB与时脉信号CKD。
如图1所示，时脉缓冲电路110可包括第一逆变器111及第二逆变器112。第一逆变器111经由节点T11耦接于时脉输入引脚PIN1，用来接收与反相时脉信号CP，并且经由节点T12输出已反相的时脉信号CP作为时脉信号CKB。第二逆变器112经由节点T13耦接于节点T12，用来接收与反相时脉信号CKB，并且经由节点T14输出已反相的时脉信号CKB作为时脉信号CKD。另外，每一触发器121～128均具有相应的数据输入端与数据输出端， 例如触发器121具有数据输入端D1与数据输出端Q1，触发器122具有数据输入端D2与数据输出端Q2，以此类推，触发器127具有数据输入端D7与数据输出端Q7，触发器128则具有数据输入端D8与数据输出端Q8，且每一触发器121～128均耦接于节点T13与节点T14，用来接收时脉信号CKB与时脉信号CKD，并且根据时脉信号CKB与时脉信号CKD来存储数据。
可以理解的是，在本实施例中，节点T11与节点T12即能分别指的是第一逆变器111的输入端与输出端，且节点T13与节点T14也就分别指的是第二逆变器112的输入端与输出端。另外，根据以上内容的教示，本技术领域中具有通常知识者应可理解到，本实施例所提供的多位元触发器1是设计让每一触发器121～128均耦接于节点T13与节点T14，因此，使得每一触发器121～128均能共用同一时脉信号CKB与同一时脉信号CKD。需要说明的是，本实施例的每一触发器121～128可以是静态(static)触发器、动态(dynamic)触发器或任何类型的触发器。总而言之，本发明并不限制每一触发器121～128的具体实现方式，本技术领域中具有通常知识者应可依据实际需求或应用来进行相关设计。然而，由于每一触发器121～128所根据时脉信号CKB与时脉信号CKD来存储数据的运作原理已是本技术领域中具有通常知识者所习知，因此有关上述每一触发器121～128的细部内容在此就不再多加赘述。
进一步来说，第一逆变器111可包括相互串联的P型金氧半场效电晶体(PMOSFET)P11及N型金氧半场效电晶体(NMOSFET)N11，但本发明并不以此连接关系及电晶体类型为限制。在本实施例中，P型金氧半场效电晶体P11的源极耦接于电源电压VDD，N型金氧半场效电晶体N11的源极耦接于接地电压VSS，P型金氧半场效电晶体P11的汲极及N型金氧半场效电晶体N11的汲极则共同耦接于节点T12，P型金氧半场效电晶体P11的闸极及N型金氧半场效电晶体N11的闸极则共同耦接于节点T11。类似地，第 二逆变器112可包括相互串联的P型金氧半场效电晶体P12及N型金氧半场效电晶体N12，但本发明也不以此连接关系及电晶体类型为限制。在本实施例中，P型金氧半场效电晶体P12的源极耦接于电源电压VDD，N型金氧半场效电晶体N12的源极耦接于接地电压VSS，P型金氧半场效电晶体P12的汲极及N型金氧半场效电晶体N12的汲极则共同耦接于节点T14，P型金氧半场效电晶体P12的闸极及N型金氧半场效电晶体N12的闸极则共同耦接于节点T13。
更仔细地说，请一并参阅图2，图2是图1的多位元触发器的时序示意图。如图2所示，由于在时脉信号CKD的第一上升边缘时(也即，在时脉信号CKB的第一下升边缘时)，第i个触发器12i(其中，i为1至8的任整数)的数据输入端Di所输入的数据信号具有逻辑「高」位准，因此第i个触发器12i的数据输出端Qi所输出的数据信号即可自逻辑「低」位准变至逻辑「高」位准。接下来，由于在时脉信号CKD的第二上升边缘时(也即，在时脉信号CKB的第二下升边缘时)，第i个触发器12i的数据输入端Di所输入的数据信号具有逻辑「低」位准，因此第i个触发器12i的数据输出端Qi所输出的数据信号则可自逻辑「高」位准变至逻辑「低」位准。
这也就是说，在本实施例中，第i个触发器12i将可仅通过在时脉信号CKD的上升边缘(或时脉信号CKD的下升边缘)来锁存其数据输入端Di所输入的数据信号。由于触发器12i所锁存数据信号的原理也已是本技术领域中具有通常知识者所习知，因此有关上述细部内容在此就不再多加赘述。必须了解的是，上述P型金氧半场效电晶体P11、P12及N型金氧半场效电晶体N11、N12更可以是以超低临限电压(ultra low voltage trigger，uLVT)金氧半场效电晶体来实现，但本发明也不以此电晶体类型为限制。因此，当本实施例是使用uLVT金氧半场效电晶体时，第i个触发器12i就只须要根据时脉信号CKB与时脉信号CKD上的相对较小准位变化而来执行上述锁存 动作。
另一方面，若再考量到降低时脉信号CKB与时脉信号CKD的振幅的话，因此，请参阅图3，图3是本发明另一实施例所提供的多位元触发器的电路示意图。其中，图3中部分与图1相同或相似的元件以相同或相似的图号标示，因此在此不再多加详述其细节。如图3所示，多位元触发器3的时脉缓冲电路310可包括第一逆变器111、第二逆变器112、P型金氧半场效电晶体P33与N型金氧半场效电晶体N33。在本实施例中，P型金氧半场效电晶体P33串联于P型金氧半场效电晶体P11及电源电压VDD间，其中P型金氧半场效电晶体P33的源极耦接于电源电压VDD，P型金氧半场效电晶体P33的汲极与闸极共同耦接于P型金氧半场效电晶体P11的源极。另外，在本实施例中，N型金氧半场效电晶体N33串联于N型金氧半场效电晶体N12及接地电压VSS间，其中N型金氧半场效电晶体N33的源极耦接于接地电压VSS，N型金氧半场效电晶体N33的汲极与闸极共同耦接于N型金氧半场效电晶体N12的源极。因此，相较于图1的时脉信号CKB与时脉信号CKD，图3的时脉信号CKB与时脉信号CKD则均可降低其振幅达1Vt，例如时脉信号CKB的逻辑「高」位准减少了1Vt，且时脉信号CKD的逻辑「低」位准则增加了1Vt，但本发明并不限制Vt的具体实现方式。由于详尽细节也如同前述实施例所述，因此在此就不再多加赘述。
类似地，请参阅图4，图4也是本发明另一实施例所提供的多位元触发器的电路示意图。其中，图4中部分与图1相同或相似的元件以相同或相似的图号标示，因此在此不再多加详述其细节。如图4所示，相较于图1及图3的时脉缓冲电路110及310，图4的时脉缓冲电路410则用来接收时脉信号CP，并且根据时脉信号CP提供时脉信号CKN与时脉信号CKP。另外，图4的每一触发器121～128则改均耦接于节点T45与节点T46，用来接收时脉信号CKN与时脉信号CKP，并且根据时脉信号CKN与时脉信号CKP 来存储数据。在本实施例中，时脉缓冲电路410可包括第一逆变器111、第二逆变器112及电晶体串313。电晶体串313耦接于节点T13与节点T14，用来接收时脉信号CKB与时脉信号CKD，并且根据时脉信号CKB与时脉信号CKD，经由节点T45与节点T46提供时脉信号CKN与时脉信号CKP。
进一步来说，电晶体串313可包括相互串联的P型金氧半场效电晶体P43及N型金氧半场效电晶体N43、N44。在本实施例中，P型金氧半场效电晶体P43的源极耦接于电源电压VDD，P型金氧半场效电晶体P43的汲极与N型金氧半场效电晶体N43的汲极共同耦接于节点T45，N型金氧半场效电晶体N43的源极与N型金氧半场效电晶体N44的汲极共同耦接于节点T46，N型金氧半场效电晶体N44的源极耦接于接地电压VSS，P型金氧半场效电晶体P43的闸极则与N型金氧半场效电晶体N43的闸极共同耦接于节点T13，N型金氧半场效电晶体N44的闸极耦接于节点T14。可以理解的是，在本实施例中，节点T45与节点T46也就能分别指的是时脉缓冲电路410的两输出端，且节点T45即用来提供时脉信号CKN，节点T46则用来提供时脉信号CKP。
另外，如图4所示，时脉缓冲电路410更可包括P型金氧半场效电晶体P44及电容C1、C2。在本实施例中，P型金氧半场效电晶体P44的源极耦接于节点T45，P型金氧半场效电晶体P44的汲极耦接于节点T46，P型金氧半场效电晶体P44的闸极则与N型金氧半场效电晶体N44的闸极共同耦接于节点T14。电容C1的第一端耦接于电源电压VDD，电容C1的第二端则耦接于节点T45。而电容C2的第一端耦接于接地电压VSS，电容C2的第二端则耦接于节点T46。接着，请一并参阅图5，图5是图4的多位元触发器的时序示意图。根据以上内容的教示，本技术领域中具有通常知识者应可理解到，相较于图1及图3的实施例，图4的第i个触发器12i将可仅通过在时脉信号CKN的上升边缘(或时脉信号CKP的下升边缘)来锁存其数据输入 端Di所输入的数据信号。必须了解的是，由于本实施例用到了P型金氧半场效电晶体P43、P44及N型金氧半场效电晶体N43、N44，因此，相较于图1的时脉信号CKB与时脉信号CKD，图4的时脉信号CKN与时脉信号CKP则均可降低其振幅达高准位的一半，如图5所示。由于详尽细节也如同前述实施例所述，因此在此就不再多加赘述。
另一方面，若考量到让图1中的多位元触发器1也能够具有时脉控制功率转换(clock-controled power switch)功能，因此，请一并参阅图6，图6是本发明另一实施例所提供的多位元触发器的电路示意图。其中，图6中部分与图1相同或相似的元件以相同或相似的图号标示，因此在此不再多加详述其细节。如图6所示，时脉缓冲电路610更用来根据时脉信号CKB与时脉信号CKD，经由节点T65与节点T66提供功率转换信号SW1与功率转换信号SW2，且每一触发器121～128更均耦接于节点T65与节点T66，用来接收功率转换信号SW1与功率转换信号SW2。可以理解的是，在本实施例中，节点T65即用来提供功率转换信号SW1，且节点T66则用来提供功率转换信号SW2。
进一步来说，图6的时脉缓冲电路610可包括第一逆变器111、第二逆变器112、P型金氧半场效电晶体P63、P64及N型金氧半场效电晶体N63、N64。在本实施例中，P型金氧半场效电晶体P63的源极耦接于电源电压VDD，P型金氧半场效电晶体P63的汲极耦接于节点T65，P型金氧半场效电晶体P63的闸极则与触发器121～128共同耦接于节点T13。另外，N型金氧半场效电晶体N63的源极耦接于节点T65，N型金氧半场效电晶体N63的汲极耦接于电源电压VDD，N型金氧半场效电晶体N63的闸极则与P型金氧半场效电晶体P63的闸极共同耦接于节点T13。类似地，P型金氧半场效电晶体P64的源极耦接于节点T66，P型金氧半场效电晶体P64的汲极耦接于接地电压VSS，P型金氧半场效电晶体P64的闸极则与触发器121～128 共同耦接于节点T14。另外，N型金氧半场效电晶体N64的源极耦接于接地电压VSS，N型金氧半场效电晶体N64的汲极耦接于节点T66，N型金氧半场效电晶体N64的闸极则与P型金氧半场效电晶体P64的闸极共同耦接于节点T14。
接着，请一并参阅图7，图7是图6的多位元触发器的时序示意图。根据以上内容的教示，本技术领域中具有通常知识者应可理解到，上述P型金氧半场效电晶体P63、P64及N型金氧半场效电晶体N63、N64即可被整体视作为一个弱保持电路(weak keeper circuit)。也就是说，本实施例所提供的多位元触发器6是设计让在时脉信号CP为逻辑低位准时，使用此弱保持电路来作为功率转换。一般而言，通常是通过设计不同的临界电压或通道长度来区分强保持电路及弱保持电路。总而言之，本发明并不限制此弱保持电路的具体实现方式，本技术领域中具有通常知识者应可依据实际需求或应用来进行相关设计。需要说明的是，由于具有功率转换功能的触发器的运作原理也已是本技术领域中具有通常知识者所习知，因此有关上述细部内容在此就不再多加赘述。
另一方面，若除了考量到让图1中的多位元触发器1也能够具有时脉控制功率转换功能外，同时再考量到降低如图6中的功率转换信号SW1与功率转换信号SW2振幅的话，因此，请参阅图8，图8是本发明另一实施例所提供的多位元触发器的电路示意图。其中，图8中部分与图6相同或相似的元件以相同或相似的图号标示，因此在此不再多加详述其细节。如图8所示，相较于图6的时脉缓冲电路610，图8的时脉缓冲电路810可包括第一逆变器111、第二逆变器112、P型金氧半场效电晶体P83、P84、P85及N型金氧半场效电晶体N83、N84、N85。在本实施例中，P型金氧半场效电晶体P83的源极耦接于电源电压VDD，P型金氧半场效电晶体P83的汲极耦接于节点T65，P型金氧半场效电晶体P83的闸极则与触发器121～128共同耦接 于节点T13。另外，P型金氧半场效电晶体P84的源极耦接于电源电压VDD，P型金氧半场效电晶体P84的汲极与闸极共同耦接于P型金氧半场效电晶体P85的源极，P型金氧半场效电晶体P85的汲极耦接于节点T65，P型金氧半场效电晶体P85的闸极则与触发器121～128共同耦接于节点T14。
类似地，N型金氧半场效电晶体N83的源极耦接于接地电压VSS，N型金氧半场效电晶体N83的汲极耦接于节点T66，N型金氧半场效电晶体N83的闸极则与触发器121～128共同耦接于节点T14。N型金氧半场效电晶体N84的源极耦接于接地电压VSS，N型金氧半场效电晶体N84的汲极与闸极共同耦接于N型金氧半场效电晶体N85的源极，N型金氧半场效电晶体N85的汲极耦接于节点T66，N型金氧半场效电晶体N85的闸极则与触发器121～128共同耦接于节点T13。因此，相较于图6的功率转换信号SW1与功率转换信号SW2，图8的功率转换信号SW1与功率转换信号SW2则均可降低其振幅达1Vt，例如功率转换信号SW1的逻辑「高」位准减少了1Vt，且功率转换信号SW2的逻辑「低」位准则增加了1Vt，但本发明并不限制Vt的具体实现方式。由于操作细节也如同前述实施例所述，因此在此就不再多加赘述。
最后，如同前面内容所述，每一触发器121～128可以是动态触发器，因此，请参阅图9，图9是图1的多位元触发器中的触发器的电路示意图。其中，图9中部分与图1相同或相似的元件以相同或相似的图号标示，因此在此不再多加详述其细节。值得一提的是，为了方便以下说明，本实施例将是仅以触发器121的例子来进行说明。如图9所示，触发器121包括传输闸901、第三逆变器902、第四逆变器903、上拉电晶体904及下拉电晶体905。传输闸901耦接于触发器121的数据输入端D1，用来接收第一数据信号(图未示)，并且根据时脉信号CKB与时脉信号CKD输出第一数据信号到子节点A1。第三逆变器902经由子节点A1耦接于传输闸901，用来反相第一数 据信号，并且输出已反相的第一数据信号到子节点A2。第四逆变器903耦接于子节点A2与触发器121的数据输出端Q1间，用来反相已反相的第一数据信号以产生第二数据信号(图未示)，并且输出第二数据信号到触发器121的数据输出端Q1。上拉电晶体904耦接于子节点A2与电源电压VDD间，用来上拉子节点A2的电压到电源电压VDD。下拉电晶体905耦接于子节点A2与接地电压VSS间，用来下拉子节点A2的电压到接地电压VSS。可以理解的是，本实施例的「子节点A1」即能指的是传输闸901与第三逆变器902相连接的节点，且「子节点A2」也就指的是第三逆变器902与第四逆变器903相连接的节点。
在本实施例中，传输闸901包括相互并联的N型金氧半场效电晶体N93及P型金氧半场效电晶体P93，N型金氧半场效电晶体N93的汲极及P型金氧半场效电晶体P93的汲极共同经由子节点A3耦接于触发器121的数据输入端D1，N型金氧半场效电晶体N93的源极及P型金氧半场效电晶体P93的源极共同经由子节点A4耦接于子节点A1，N型金氧半场效电晶体N93的闸极用来接收时脉信号CKB，P型金氧半场效电晶体P93的闸极则用来接收时脉信号CKD。可以理解的是，本实施例的「子节点A3」即能指的是N型金氧半场效电晶体N93的汲极与P型金氧半场效电晶体P93的汲极相连接的节点，且「子节点A4」也就指的是N型金氧半场效电晶体N93的源极与P型金氧半场效电晶体P93的源极相连接的节点。
另外，第三逆变器902为三态(tri-state)逆变器，且其包括相互串联的P型金氧半场效电晶体P94、P95及N型金氧半场效电晶体N94、N95，P型金氧半场效电晶体P94的源极耦接于电源电压VDD，N型金氧半场效电晶体N95的源极耦接于接地电压VSS，P型金氧半场效电晶体P94的闸极及N型金氧半场效电晶体N95的闸极均分别耦接于子节点A1，以用来接收第一数据信号，P型金氧半场效电晶体P95的源极耦接于P型金氧半场效电晶体 P94的汲极，N型金氧半场效电晶体N94的源极耦接于N型金氧半场效电晶体N95的汲极，P型金氧半场效电晶体P95的汲极及N型金氧半场效电晶体N94的汲极共同经由子节点A5耦接于子节点A2，P型金氧半场效电晶体P95的闸极用来接收时脉信号CKB，N型金氧半场效电晶体N94的闸极则用来接收所述时脉信号CKD。
第四逆变器903包括相互串联的P型金氧半场效电晶体P96及N型金氧半场效电晶体N96，P型金氧半场效电晶体P96的源极耦接于电源电压VDD，N型金氧半场效电晶体N96的源极耦接于接地电压VSS，P型金氧半场效电晶体P96的汲极及N型金氧半场效电晶体N96的汲极共同经由子节点A6耦接于触发器121的数据输出端Q1，P型金氧半场效电晶体P96的闸极及N型金氧半场效电晶体N96的闸极则共同经由子节点A7耦接于所述子节点A2，以用来接收已反相的第一数据信号。再者，上拉电晶体904是P型金氧半场效电晶体P97，下拉电晶体905是N型金氧半场效电晶体N97，P型金氧半场效电晶体P97的源极耦接于电源电压VDD，N型金氧半场效电晶体N97的源极耦接于接地电压VSS，P型金氧半场效电晶体P97的汲极及N型金氧半场效电晶体N97的汲极均分别耦接于子节点A2，P型金氧半场效电晶体P97的闸极及N型金氧半场效电晶体N97的闸极则均分别耦接于触发器121的数据输出端Q1，以用来接收第二数据信号。
需要说明的是，在本实施例中，上拉电晶体904及下拉电晶体905即组构成一反馈逆变器906，且相较于第三逆变器902，此反馈逆变器被配置为弱保持电路。也就是说，当下一笔新的数据要写入时，第三逆变器902和反馈逆变器906会容易在子节点A2上发生数据冲突，所以第三逆变器902的信号输出能力要必须比反馈逆变器906的信号输出能力来得较强，这样才能强制更新子节点A2上的数据。因此，相较于第三逆变器902，反馈逆变器906必须被配置为弱保持电路。由于P型金氧半场效电晶体P93、P94、P95、 P96、P97及N型金氧半场效电晶体N93、N94、N95、N96、N97的运作原理也已是本技术领域中具有通常知识者所习知，因此有关上述触发器121的细部内容在此就不再多加赘述。
综上所述，本发明实施例所提供的多位元触发器，是设计让每一触发器均能共用同一时脉，借此改进多位元触发器的时脉路径。除此之外，本发明实施例所提供的多位元触发器，还设计到能够降低时脉振幅，以及能够具有时脉控制功率转换功能的优点。
以上所述仅仅是本发明的实施例，其并不是用以局限本发明的专利范围。

Claims (19)

  1. 一种多位元触发器，其特征在于，包括：
    一时脉输入引脚，被配置为接收一第一时脉信号；
    一时脉缓冲电路，耦接于所述时脉输入引脚，用来接收所述第一时脉信号，并且根据所述第一时脉信号提供一第二时脉信号与一第三时脉信号，其中所述时脉缓冲电路包括：
    一第一逆变器，经由一第一节点耦接于所述时脉输入引脚，用来接收与反相所述第一时脉信号，并且经由一第二节点输出已反相的所述第一时脉信号作为所述第二时脉信号；以及
    一第二逆变器，经由一第三节点耦接于所述第二节点，用来接收与反相所述第二时脉信号，并且经由一第四节点输出已反相的所述第二时脉信号作为所述第三时脉信号；以及
    多个触发器，其中每一所述触发器均具有相应的一数据输入端与一数据输出端，且每一所述触发器均耦接于所述第三节点与所述第四节点，用来接收所述第二时脉信号与所述第三时脉信号，并且根据所述第二时脉信号与所述第三时脉信号来存储数据。
  2. 如权利要求1所述的多位元触发器，其特征在于，所述第一逆变器包括相互串联的一第一P型金氧半场效电晶体及一第一N型金氧半场效电晶体，其中所述第一P型金氧半场效电晶体的源极耦接于一电源电压，所述第一N型金氧半场效电晶体的源极耦接于一接地电压，所述第一P型金氧半场效电晶体的汲极及所述第一N型金氧半场效电晶体的汲极则共同耦接于所述第二节点，所述第一P型金氧半场效电晶体的闸极及所述第一N型金氧半场效电晶体的闸极则共同耦接于所述第一节点。
  3. 如权利要求2所述的多位元触发器，其特征在于，所述第二逆变器包括相互串联的一第二P型金氧半场效电晶体及一第二N型金氧半场效电晶 体，其中所述第二P型金氧半场效电晶体的源极耦接于所述电源电压，所述第二N型金氧半场效电晶体的源极耦接于所述接地电压，所述第二P型金氧半场效电晶体的汲极及所述第二N型金氧半场效电晶体的汲极则共同耦接于所述第四节点，所述第二P型金氧半场效电晶体的闸极及所述第二N型金氧半场效电晶体的闸极则共同耦接于所述第三节点。
  4. 如权利要求3所述的多位元触发器，其特征在于，所述时脉缓冲电路更包括：
    一第三P型金氧半场效电晶体，串联于所述第一P型金氧半场效电晶体及所述电源电压间，其中所述第三P型金氧半场效电晶体的源极耦接于所述电源电压，所述第三P型金氧半场效电晶体的汲极与闸极共同耦接于所述第一P型金氧半场效电晶体的源极；以及
    一第三N型金氧半场效电晶体，串联于所述第二N型金氧半场效电晶体及所述接地电压间，其中所述三N型金氧半场效电晶体的源极耦接于所述接地电压，所述第三N型金氧半场效电晶体的汲极与闸极共同耦接于所述第二N型金氧半场效电晶体的源极。
  5. 如权利要求3所述的多位元触发器，其特征在于，所述时脉缓冲电路更用来根据所述第二时脉信号与所述第三时脉信号，经由一第五节点与一第六节点提供一第一功率转换信号与一第二功率转换信号，且每一所述触发器更均耦接于所述第五节点与所述第六节点，用来接收所述第一功率转换信号与所述第二功率转换信号。
  6. 如权利要求5所述的多位元触发器，其特征在于，所述时脉缓冲电路更包括：
    一第三P型金氧半场效电晶体，所述第三P型金氧半场效电晶体的源极耦接于所述电源电压，所述第三P型金氧半场效电晶体的汲极耦接于所述第五节点，所述第三P型金氧半场效电晶体的闸极则与所述触发器共同耦接于 所述第三节点；
    一第三N型金氧半场效电晶体，所述三N型金氧半场效电晶体的源极耦接于所述第五节点，所述第三N型金氧半场效电晶体的汲极耦接于所述电源电压，所述第三N型金氧半场效电晶体的闸极则与所述第三P型金氧半场效电晶体的闸极共同耦接于所述第三节点；
    一第四P型金氧半场效电晶体，所述第四P型金氧半场效电晶体的源极耦接于所述第六节点，所述第四P型金氧半场效电晶体的汲极耦接于所述接地电压，所述第四P型金氧半场效电晶体的闸极则与所述触发器共同耦接于所述第四节点；以及
    一第四N型金氧半场效电晶体，所述四N型金氧半场效电晶体的源极耦接于所述接地电压，所述第四N型金氧半场效电晶体的汲极耦接于所述第六节点，所述第四N型金氧半场效电晶体的闸极则与所述第四P型金氧半场效电晶体的闸极共同耦接于所述第四节点。
  7. 如权利要求6所述的多位元触发器，其特征在于，所述时脉缓冲电路更包括：
    一第三P型金氧半场效电晶体，所述第三P型金氧半场效电晶体的源极耦接于所述电源电压，所述第三P型金氧半场效电晶体的汲极耦接于所述第五节点，所述第三P型金氧半场效电晶体的闸极则与所述触发器共同耦接于所述第三节点；
    一第四至一第五P型金氧半场效电晶体，所述第四P型金氧半场效电晶体的源极耦接于所述电源电压，所述第四P型金氧半场效电晶体的汲极与闸极共同耦接于所述第五P型金氧半场效电晶体的源极，所述第五P型金氧半场效电晶体的汲极耦接于所述第五节点，所述第五P型金氧半场效电晶体的闸极则与所述触发器共同耦接于所述第四节点；
    一第三N型金氧半场效电晶体，所述三N型金氧半场效电晶体的源极 耦接于所述接地电压，所述第三N型金氧半场效电晶体的汲极耦接于所述第六节点，所述第三N型金氧半场效电晶体的闸极则与所述触发器共同耦接于所述第四节点；以及
    一第四至一第五N型金氧半场效电晶体，所述四N型金氧半场效电晶体的源极耦接于所述接地电压，所述第四N型金氧半场效电晶体的汲极与闸极共同耦接于所述第五N型金氧半场效电晶体的源极，所述第五N型金氧半场效电晶体的汲极耦接于所述第六节点，所述第五N型金氧半场效电晶体的闸极则与所述触发器共同耦接于所述第三节点。
  8. 如权利要求3所述的多位元触发器，其特征在于，每一所述触发器均是一动态触发器，且其包括：
    一传输闸，耦接于所述触发器的所述数据输入端，用来接收一第一数据信号，并且根据所述第二时脉信号与所述第三时脉信号输出所述第一数据信号到一第一子节点；
    一第三逆变器，经由所述第一子节点耦接于所述传输闸，用来反相所述第一数据信号，并且输出已反相的所述第一数据信号到一第二子节点；
    一第四逆变器，耦接于所述第二子节点与所述触发器的所述数据输出端间，用来反相已反相的所述第一数据信号以产生一第二数据信号，并且输出所述第二数据信号到所述触发器的所述数据输出端；
    一上拉电晶体，耦接于所述第二子节点与所述电源电压间，用来上拉所述二子节点的电压到所述电源电压；以及
    一下拉电晶体，耦接于所述第二子节点与所述接地电压间，用来下拉所述二子节点的电压到所述接地电压。
  9. 如权利要求8所述的多位元触发器，其特征在于，所述传输闸包括相互并联的一第三N型金氧半场效电晶体及一第三P型金氧半场效电晶体，所述第三N型金氧半场效电晶体的汲极及所述第三P型金氧半场效电晶体的汲 极共同经由一第三子节点耦接于所述触发器的所述数据输入端，所述第三N型金氧半场效电晶体的源极及所述第三P型金氧半场效电晶体的源极共同经由一第四子节点耦接于所述第一子节点，所述第三N型金氧半场效电晶体的闸极用来接收所述第二时脉信号，所述第三P型金氧半场效电晶体的闸极则用来接收所述第三时脉信号。
  10. 如权利要求9所述的多位元触发器，其特征在于，所述第三逆变器是一三态逆变器，且其包括相互串联的一第四P型金氧半场效电晶体、一第五P型金氧半场效电晶体、一第四N型金氧半场效电晶体及一第五N型金氧半场效电晶体，所述第四P型金氧半场效电晶体的源极耦接于所述电源电压，所述第五N型金氧半场效电晶体的源极耦接于所述接地电压，所述第四P型金氧半场效电晶体的闸极及所述第五N型金氧半场效电晶体的闸极均分别耦接于所述第一子节点，以用来接收所述第一数据信号，所述第五P型金氧半场效电晶体的源极耦接于所述第四P型金氧半场效电晶体的汲极，所述第四N型金氧半场效电晶体的源极耦接于所述第五N型金氧半场效电晶体的汲极，所述第五P型金氧半场效电晶体的汲极及所述第四N型金氧半场效电晶体的汲极共同经由一第五子节点耦接于所述第二子节点，所述第五P型金氧半场效电晶体的闸极用来接收所述第二时脉信号，所述第四N型金氧半场效电晶体的闸极则用来接收所述第三时脉信号。
  11. 如权利要求10所述的多位元触发器，其特征在于，所述第四逆变器包括相互串联的一第六P型金氧半场效电晶体及一第六N型金氧半场效电晶体，所述第六P型金氧半场效电晶体的源极耦接于所述电源电压，所述第六N型金氧半场效电晶体的源极耦接于所述接地电压，所述第六P型金氧半场效电晶体的汲极及所述第六N型金氧半场效电晶体的汲极共同经由一第六子节点耦接于所述触发器的所述数据输出端，所述第六P型金氧半场效电晶体的闸极及所述第六N型金氧半场效电晶体的闸极则共同经由一第七子节 点耦接于所述第二子节点，以用来接收已反相的所述第一数据信号。
  12. 如权利要求11所述的多位元触发器，其特征在于，所述上拉电晶体是一第七P型金氧半场效电晶体，所述下拉电晶体是一第七N型金氧半场效电晶体，所述第七P型金氧半场效电晶体的源极耦接于所述电源电压，所述第七N型金氧半场效电晶体的源极耦接于所述接地电压，所述第七P型金氧半场效电晶体的汲极及所述第七N型金氧半场效电晶体的汲极均分别耦接于所述第二子节点，所述第七P型金氧半场效电晶体的闸极及所述第七N型金氧半场效电晶体的闸极则均分别耦接于所述触发器的所述数据输出端，以用来接收所述第二数据信号。
  13. 如权利要求12所述的多位元触发器，其特征在于，所述上拉电晶体及所述下拉电晶体组构成一反馈逆变器，且相较于所述第三逆变器，所述反馈逆变器被配置为一弱保持电路。
  14. 一种多位元触发器，其特征在于，包括：
    一时脉输入引脚，被配置为接收一第一时脉信号；
    一时脉缓冲电路，耦接于所述时脉输入引脚，用来接收所述第一时脉信号，并且根据所述第一时脉信号提供一第二时脉信号与一第三时脉信号，其中所述时脉缓冲电路包括：
    一第一逆变器，经由一第一节点耦接于所述时脉输入引脚，用来接收与反相所述第一时脉信号，并且经由一第二节点输出已反相的所述第一时脉信号作为一第四时脉信号；
    一第二逆变器，经由一第三节点耦接于所述第二节点，用来接收与反相所述第四时脉信号，并且经由一第四节点输出已反相的所述第四时脉信号作为一第五时脉信号；以及
    一电晶体串，耦接于所述第三节点与所述第四节点，用来接收所述第四时脉信号与所述第五时脉信号，并且根据所述第四时脉信号与所述第五时脉 信号，经由一第五节点与一第六节点提供所述第二时脉信号与所述第三时脉信号；以及
    多个触发器，其中每一所述触发器均具有相应的一数据输入端与一数据输出端，且每一所述触发器均耦接于所述第五节点与所述第六节点，用来接收所述第二时脉信号与所述第三时脉信号，并且根据所述第二时脉信号与所述第三时脉信号来存储数据。
  15. 如权利要求14所述的多位元触发器，其特征在于，所述第一逆变器包括相互串联的一第一P型金氧半场效电晶体及一第一N型金氧半场效电晶体，所述第一P型金氧半场效电晶体的源极耦接于一电源电压，所述第一N型金氧半场效电晶体的源极耦接于一接地电压，所述第一P型金氧半场效电晶体的汲极及所述第一N型金氧半场效电晶体的汲极则共同耦接于所述第二节点，所述第一P型金氧半场效电晶体的闸极及所述第一N型金氧半场效电晶体的闸极则共同耦接于所述第一节点。
  16. 如权利要求15所述的多位元触发器，其特征在于，所述第二逆变器包括相互串联的一第二P型金氧半场效电晶体及一第二N型金氧半场效电晶体，所述第二P型金氧半场效电晶体的源极耦接于所述电源电压，所述第二N型金氧半场效电晶体的源极耦接于所述接地电压，所述第二P型金氧半场效电晶体的汲极及所述第二N型金氧半场效电晶体的汲极则共同耦接于所述第四节点，所述第二P型金氧半场效电晶体的闸极及所述第二N型金氧半场效电晶体的闸极则共同耦接于所述第三节点。
  17. 如权利要求16所述的多位元触发器，其特征在于，所述电晶体串包括相互串联的一第三P型金氧半场效电晶体、一第三N型金氧半场效电晶体及一第四N型金氧半场效电晶体，其中所述第三P型金氧半场效电晶体的源极耦接于所述电源电压，所述第三P型金氧半场效电晶体的汲极与所述第三N型金氧半场效电晶体的汲极共同耦接于所述第五节点，所述第三N型金氧 半场效电晶体的源极与所述第四N型金氧半场效电晶体的汲极共同耦接于所述第六节点，所述第四N型金氧半场效电晶体的源极耦接于所述接地电压，所述第三P型金氧半场效电晶体的闸极则与所述第三N型金氧半场效电晶体的闸极共同耦接于所述第三节点，所述第四N型金氧半场效电晶体的闸极耦接于所述第四节点。
  18. 如权利要求17所述的多位元触发器，其特征在于，所述时脉缓冲电路更包括：
    一第四P型金氧半场效电晶体，所述第四P型金氧半场效电晶体的源极耦接于所述第五节点，所述第四P型金氧半场效电晶体的汲极耦接于所述第六节点，所述第四P型金氧半场效电晶体的闸极则与所述第四N型金氧半场效电晶体的闸极共同耦接于所述第四节点；
    一第一电容，所述第一电容的第一端耦接于所述电源电压，所述第一电容的第二端耦接于所述第五节点；以及
    一第二电容，所述第二电容的第一端耦接于所述接地电压，所述第二电容的第二端耦接于所述第六节点。
  19. 一种电子设备，其特征在于，包括如权利要求1～18中任一项所述的多位元触发器。
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