WO2020057138A1 - 全摆幅电压转换电路及应用其的运算单元、芯片、算力板和计算设备 - Google Patents

全摆幅电压转换电路及应用其的运算单元、芯片、算力板和计算设备 Download PDF

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Publication number
WO2020057138A1
WO2020057138A1 PCT/CN2019/085894 CN2019085894W WO2020057138A1 WO 2020057138 A1 WO2020057138 A1 WO 2020057138A1 CN 2019085894 W CN2019085894 W CN 2019085894W WO 2020057138 A1 WO2020057138 A1 WO 2020057138A1
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Prior art keywords
voltage
unit
full
voltage conversion
conversion circuit
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PCT/CN2019/085894
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English (en)
French (fr)
Inventor
刘杰尧
张楠赓
吴敬杰
马晟厚
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北京嘉楠捷思信息技术有限公司
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Priority to US17/095,545 priority Critical patent/US11409314B2/en
Publication of WO2020057138A1 publication Critical patent/WO2020057138A1/zh

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/575—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0016—Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
    • H03K19/018528—Interface arrangements of complementary type, e.g. CMOS with at least one differential stage

Definitions

  • the invention relates to a voltage converter (LVL, Level-Shifter), in particular to a full swing voltage conversion circuit (Full Swing, Level-Shifter) applied in a computing device, and an arithmetic unit, chip, and computing power using the Board and computing equipment.
  • a voltage converter (LVL, Level-Shifter)
  • Full swing voltage conversion circuit (Full Swing, Level-Shifter) applied in a computing device, and an arithmetic unit, chip, and computing power using the Board and computing equipment.
  • Multi-supply voltage power supply technology is more and more widely used in System-on-chip (SoC) and multi-processor computing structures.
  • SoC System-on-chip
  • the chip In a chip using multi-voltage domain technology, the chip usually contains multiple independent voltage domains or voltage islands, and the modules in each voltage domain work at the appropriate power supply voltage according to their timing requirements.
  • VDDH high power voltage
  • VDDL low power voltage
  • the voltage converter is an indispensable circuit in a multi-voltage system. It provides different power supplies for different voltage domains and ensures the transmission of signals between the voltage domains. Under normal circumstances, the signal is converted from the high-voltage domain to the low-voltage domain, and ordinary buffers can be implemented. However, if the signal is converted from the low-voltage domain to the high-voltage domain, especially from the sub-threshold voltage domain to the high-voltage domain, a more complicated circuit is required.
  • CN104506183A discloses a voltage converter. As shown in FIG. 1, it is composed of a pair of cross-coupled PMOS tubes, a pair of pull-down NMOS tubes, and a low-voltage inverter providing a differential input.
  • the M1 tube pulls down the voltage at the node OUTB to "0", and then pre-charges the output OUT to a high level VDDH through a cross-coupled PMOS pair.
  • the pull-down current provided by the NMOS tube operating in the low-voltage region is several orders of magnitude smaller than the pull-up current provided by the PMOS operating in the high-voltage region, resulting in extremely fierce competition between the pull-up network and the pull-down network, making traditional voltage converters impossible. It realizes the conversion of low-threshold signals, and has the problems of large power leakage, narrow input voltage range, and long delay time from low voltage to high voltage conversion.
  • CN107707246A discloses a sub-threshold voltage converter. As shown in FIG. 2, a first normal threshold voltage PMOS transistor MP1, a second normal threshold voltage PMOS transistor MP2, a first high threshold voltage PMOS transistor MP3, and the first normal threshold value.
  • the sources of the voltage PMOS transistor MP1 and the second normal threshold voltage PMOS transistor MP2 are respectively connected to a high supply voltage, and the drain of the first normal threshold voltage PMOS transistor MP1 is connected to the source of the first high threshold voltage PMOS transistor MP3.
  • the gate of is connected to the drain of the first normal threshold voltage PMOS transistor MP1, and the gate of the first high threshold voltage PMOS transistor MP3 is connected to the second normal The drain of the threshold voltage PMOS transistor MP2; at the same time, the gate of the first low threshold voltage NMOS transistor MN1 is used as the first input terminal of the current mirror to one end of an input buffer, and the second low threshold voltage is The gate of the NMOS transistor MN2 is used as the second input terminal of the current mirror to be connected to the other end of the input buffer; the drain of the first normal threshold voltage PMOS transistor MP1 is used as the first output terminal of the current mirror, and The drain of the second normal threshold voltage PMOS transistor MP2 serves as a second output terminal of the current mirror.
  • CMOS level conversion circuit of the level shifter proposed in this embodiment is shown in Figure 2.
  • multi-threshold device (MTCMOS) technology can be preferably used to optimize the propagation delay and reduce energy consumption.
  • the design of the CMOS level conversion circuit is further optimized.
  • this type of sub-threshold voltage converter can achieve voltage conversion in a low input voltage range, the circuit design and production process requires the use of multiple threshold transistors, which is extremely difficult to design and produce.
  • the present invention provides a full-swing voltage conversion circuit.
  • the above circuit can realize the conversion from a low input voltage to a high output voltage.
  • the present invention provides a full-swing voltage conversion circuit, including:
  • a differential input unit configured to invert the first level signal of the input terminal and output a differential input signal
  • a conversion unit configured to convert a first level of the differential input signal into a second level signal
  • An output driving unit configured to output the second level signal to the output terminal
  • auxiliary pull-down unit provided between the input terminal and the conversion unit, and the auxiliary pull-down unit receives a feedback signal of the output driving unit.
  • the ability of the conversion unit to identify the differential input signal is achieved by turning on the auxiliary pull-down unit to form an auxiliary pull-down unit path of the conversion unit.
  • the auxiliary pull-down unit includes two or more transistors, and the two or more transistors are connected in series in sequence.
  • the auxiliary pull-down unit includes a first NMOS transistor and a second NMOS transistor, and the first NMOS transistor and the second NMOS transistor are connected in series.
  • a gate of the first NMOS transistor is connected to an input signal, and a gate of the second NMOS transistor is connected to the output driving unit.
  • the output driving unit includes a first inverter and a second inverter, the first inverter and the second inverter are connected in series, and the first inverter The output terminal of the phaser outputs the feedback signal.
  • the present invention further provides a data operation unit, which includes an interconnected control circuit, an operation circuit, a storage circuit, and a plurality of full-swing voltage conversion circuits.
  • the plurality of full-swing voltage conversion circuits are: The full-swing voltage conversion circuit according to any one of the above.
  • the present invention further provides a chip, wherein the chip includes any one of the foregoing data operation units.
  • the present invention also provides a computing board for use in a computing device, wherein the computing board includes a plurality of any of the chips described above.
  • the present invention further provides a computing device including a power board, a control board, a connection board, a radiator, and a plurality of computing boards.
  • the control board is connected to the computing board through the connection board.
  • the heat sink is provided around the computing power board, and the power board is used to provide power to the connection board, the control board, the heat sink, and the computing board, wherein the computing power
  • the board is any one of the computing boards described above.
  • FIG. 1 is a schematic diagram of a conventional voltage converter circuit
  • FIG. 2 is a schematic diagram of a conventional sub-threshold voltage converter circuit
  • FIG. 3 is a schematic diagram of a full-swing voltage conversion circuit according to the present invention.
  • FIG. 4 is a schematic circuit diagram of a full-swing voltage conversion circuit according to the present invention.
  • FIG. 5 is a schematic diagram of a data operation unit according to the present invention.
  • FIG. 6 is a schematic diagram of a chip of the present invention.
  • FIG. 7 is a schematic diagram of a computing board according to the present invention.
  • FIG. 8 is a schematic diagram of a computing device of the present invention.
  • FIG. 3 is a schematic diagram of a full-swing voltage conversion circuit according to the present invention.
  • the full-swing voltage conversion circuit 10 includes a differential input unit 11, a conversion unit 12, an auxiliary pull-down unit 13, an output driving unit 14, an input terminal 15, and an output terminal 16, and the input terminals 15 respectively pass through the differential input unit.
  • the auxiliary pull-down unit 13 is directly connected to the conversion unit 12, the conversion unit 12 is connected to the output drive unit 14, the auxiliary pull-down unit 13 receives a feedback signal from the output drive unit 14, and the output drive unit 14 is connected to the output terminal 16.
  • FIG. 4 is a circuit diagram of a full-swing voltage conversion circuit according to the present invention.
  • the full-swing voltage conversion circuit 10 includes an input terminal 15, an output terminal 16, a high-voltage power terminal 103, a low-voltage power terminal 104, a high-voltage ground terminal 122, and a low-voltage terminal. Voltage ground terminal 123.
  • the high-voltage power supply terminal 103 is connected to a high-voltage power supply VDDH, such as 0-1.8V, specifically 1.2V, 1.8V, etc.
  • the low-voltage power supply terminal 104 is connected to a low-voltage power supply VDDL, such as 0-0.4V, specifically 0.3 V, 0.4V, etc.
  • VDDH high-voltage power supply
  • VDDL low-voltage power supply
  • the differential input unit 11 of the full-swing voltage conversion circuit 10 is an inverter 105.
  • the inverter 105 operates in a low power voltage region.
  • the power of the inverter 105 is connected to the low voltage power terminal 104, and power is provided by the low voltage source VDDL. ;
  • the low-voltage ground terminal 123 of the inverter 105 is directly grounded to GND.
  • the input terminal of the inverter 105 is connected to the input terminal 15 of the full-swing voltage conversion circuit 10.
  • a low-level signal VIN is input.
  • the output terminal generates a low-level signal NVIN which is inverse to the input terminal 15.
  • the flat signal VIN and the low-level signal NVIN output inverted by the inverter 105 together form a differential input signal.
  • the conversion unit 12 of the full-swing voltage conversion circuit 10 includes PMOS transistors 106, 107, and 111, and NMOS transistors 108, 112.
  • the PMOS transistors 106 and 111 constitute a current mirror structure
  • the PMOS transistor 107 plays a role of leakage protection
  • the NMOS transistors 108 and 112 serve as differential input transistors and receive differential input signals provided by the differential input unit 11.
  • the source terminals of the PMOS transistors 106 and 111 are connected to the high-voltage power supply terminal 103, and power is provided by the high-voltage power supply VDDH.
  • the drain of the PMOS transistor 106 is connected to the source of the PMOS transistor 107, and the drain of the PMOS transistor 107 is connected to the drain of the NMOS transistor 108 to form a node 118.
  • the source of the NMOS transistor 108 is connected to the high-voltage ground terminal 122.
  • the drain of the PMOS transistor 111 is connected to the drain of the NMOS transistor 112 to form a node 119, which serves as an output terminal of the conversion unit 12 and outputs a high-level signal.
  • the source of the NMOS transistor 112 is connected to the high-voltage ground terminal 122.
  • the gates of the PMOS transistor 106 and the PMOS transistor 111 are connected together to form a node 121, and are connected to the drain of the PMOS transistor 106.
  • the gate of the PMOS transistor 107 is connected to a node 119.
  • the gate of the NMOS transistor 108 is connected to the input terminal 15 of the full-swing voltage conversion circuit 10 and receives an input signal VIN.
  • the gate of the NMOS transistor 112 is connected to the output terminal of the inverter 105 and receives a signal NVIN which is inverted from the input signal.
  • the output driving unit 14 of the full-swing voltage conversion circuit 10 is formed by cascading a two-stage inverter composed of a PMOS transistor 113, an NMOS transistor 114, a PMOS transistor 115, and an NMOS transistor 116.
  • the input terminal of the output driving unit 14 is connected to the converter.
  • the output of unit 12 is node 19.
  • a node 120 is formed between the two-stage inverters, and the output terminal of the output driving unit 14 is connected to the output terminal 16 of the full-swing voltage conversion circuit 10 as an output of the entire circuit.
  • the auxiliary pull-down unit 13 of the full-swing voltage conversion circuit 10 is composed of NMOS transistors 109 and 110 connected in series.
  • the source of the NMOS transistor 110 is connected to the high-voltage ground terminal 122, the drain terminal is connected to the source of the NMOS transistor 109, and the drain of the NMOS transistor 109 is connected to the node 121.
  • the gate of the NMOS transistor 109 is connected to the input terminal 15 of the full-swing voltage conversion circuit 10 and receives an input signal VIN.
  • the gate of the NMOS transistor 110 is connected to the node 120.
  • the working principle of the full-swing voltage conversion circuit 10 in this embodiment is as follows:
  • the input terminal 15 of the full-swing voltage conversion circuit 10 inputs a VIN signal, and VIN may be “0”, indicating a low level, or may be “1”, indicating a high level.
  • the inverter 105 inverts the input VIN signal to generate an NVIN signal.
  • VIN is connected to the gate of the NMOS transistor 108 as one of the inputs of the conversion unit 12;
  • NVIN is connected to the gate of the NMOS transistor 112 as the other input of the conversion unit 12. Because VIN and NVIN are inverted signals, when VIN is "0", NVIN is "1", and when VIN is "1", NVIN is "0". Therefore, one of the NMOS transistor 108 and the NMOS transistor 112 is always on.
  • the differential input unit 11 is an inverter 105.
  • the inverter 105 operates in a low power supply voltage region, and the power supply of the inverter 105 is connected to the low voltage power supply terminal 104. Therefore, when the high-level signal "1" is input to the input terminal 15, it actually refers to the VDDL level.
  • the conversion unit 12 of the full-swing voltage conversion circuit 10 operates in a high power supply voltage region, and power is provided by a high voltage power supply VDDH. In the high power supply voltage region VDDH, the VDDL input in the low power supply voltage region can only achieve a "half-on” or "weak-on” effect on the differential input NMOS transistor 108 and NMOS transistor 112.
  • NMOS transistor 108 When the VIN input is “0”, NVIN is "1", NMOS transistor 108 is turned off, node 118 is at a high level, and the state remains unchanged.
  • the NMOS transistor 112 is turned on, a pull-down path is formed between the node 119 and the ground, and the node 119 is at a low level “0”.
  • the existing full-swing voltage conversion circuit 10 does not include the auxiliary pull-down unit 13.
  • VIN input changes from “0” to “1”
  • NVIN changes from “1” to "0”
  • NMOS transistor 108 changes from off to weakly on
  • NMOS transistor 112 turns off, and a current path is formed between NMOS transistor 108 and ground
  • the voltage at node 118 is pulled down.
  • the previous state at node 119 is low-level "0". Due to the effect of circuit delay, the level at node 119 remains at "0", so that the PMOS transistor 107 is on, and the voltage at node 121 will follow The PMOS transistor 107 and the NMOS transistor 108 are turned on to form a pull-down trend.
  • the voltage at the node 121 is affected by the pull-up of the PMOS transistor 106. Since the NMOS transistor 108 operates in a sub-threshold on-state, it will seriously affect the pull-down effect, and may even be pulled up and clamped by the PMOS transistor 106, and the output cannot be inverted.
  • the NMOS transistor 112 is turned off, the level at the node 119 is high, and the PMOS transistor 107 is turned off, thereby blocking the DC path where the PMOS transistor 106 and the NMOS transistor 108 are turned on at the same time. Furthermore, the power consumption of the full-swing voltage conversion circuit 10 can be reduced.
  • the inverter 105 Since the inverter 105 operates on the low-voltage power supply VDDL, the high level when VIN is “1” is also VDDL. When VDDL is too low, the NMOS transistor 108 and the NMOS transistor 112 work in a sub-threshold state. At this time, it is necessary to improve the ability of the conversion unit 12 to distinguish between the differential signals at the two input terminals.
  • auxiliary pull-down unit 13 After the auxiliary pull-down unit 13 is introduced, when the VIN input changes from “0" to “1", NVIN changes from “1” to “0". Due to the effect of circuit delay, the level at node 120 remains at “1” ", So that the NMOS transistor 110 in the auxiliary pull-down unit 13 is turned on, and the NMOS transistor 109 is also turned on weakly simultaneously, and two pull-down paths are generated for the voltage at the node 121, which are the PMOS transistor 107, the NMOS transistor 108, and the NMOS transistor 109 and the NMOS transistor. 110 two pull-down paths. When the node 121 is pulled down, the PMOS transistor 111 is turned on and the NMOS transistor 112 is turned off, so that the voltage at the node 119 is pulled up to VDDH, and finally the output transition is achieved.
  • the NMOS transistors 109 and 110 are low threshold voltage transistors, and the number of NMOS transistors can also be multiple. Multiple NMOS transistors are connected in series and are turned on simultaneously when the input changes from "0" to "1".
  • a pull-down path is formed between the node 121 and the ground not only through the NMOS transistor 108 and the PMOS transistor 107, but also through the NMOS transistors 109 and 110 in the auxiliary pull-down unit 13. Therefore, the level at the node 119 is rapidly raised to "1", and the level at the node 119 is changed from the ground level to the high-voltage power supply VDDH level.
  • the full-swing voltage conversion circuit 10 of the present invention when the input terminal 15 is changed from “0” to “1”, that is, when the ground level is changed to the low-voltage power supply VDDL level, the output terminal 16 is changed from the ground voltage. The level is changed to the high-voltage power supply VDDH level, and the low-voltage VDDL is converted to the high-voltage VDDH.
  • VIN When the VIN input changes from “1” to “0”, NVIN changes from “0” to “1”, the level at node 119 is “1” in the previous state, and PMOS transistor 107 is turned off; The level is “0” in the previous state, and the NMOS transistor 110 is turned off; the voltage at the node 121 has no pull-down path, and its potential is stable in the diode connection mode of the PMOS transistor 106, that is, one threshold voltage lower than the VDDH of the PMOS transistor 106. That is, VDDH-Vth.
  • Vds of the PMOS transistor 111 is 0, Vgs is Vth, the PMOS transistor 111 is in the off state, and the weak turn-on of the NMOS transistor 112 is enough to pull down the voltage at the node 119 to the circuit output to invert.
  • FIG. 4 is a circuit diagram of a full-swing voltage conversion circuit according to the present invention.
  • the full-swing voltage conversion circuit 10 includes an input terminal 15, an output terminal 16, a high-voltage power terminal 103, a low-voltage power terminal 104, a high-voltage ground terminal 122, and a low-voltage terminal. Voltage ground terminal 123.
  • the low-voltage power supply terminal 104 is connected to the low-voltage power supply VDDL, for example, 0.4-0.8V, 0.8-1.2V, and specifically, 0.7V, 0.8V, 1.1V, 1.2V, and the low-voltage ground terminal 123 Connect low-voltage ground VSSL, such as 0-0.4V, 0.4-0.8V, specifically 0.3V, 0.4V, 0.7V, 0.8V.
  • VDDL low-voltage power supply
  • the working principle of the full-swing voltage conversion circuit 10 in this embodiment is as follows:
  • VIN may be “0”, which indicates a low-level VSSL, or may be “1”, which indicates a high-level VDDL.
  • the inverter 105 inverts the input VIN signal to generate an NVIN signal.
  • the NMOS transistor 108 when the VIN input is "0", which is VSSL, the NVIN is "1," which is VDDL, the NMOS transistor 108 is turned off, and the state of the node 118 remains unchanged; the NMOS transistor 112 is turned on, and the node 119 and ground A pull-down path is formed between them, and the node 119 is "0".
  • VIN input changes from “0” to “1”, that is, from VSSL to VDDL
  • NVIN changes from "1” to “0”, that is, from VDDL to VSSL
  • the level at node 119 changes from ground GND. It is the high-voltage power supply VDDH level.
  • the full-swing voltage conversion circuit 200 of this embodiment when the input terminal 15 is changed from low-level VSSL to high-level VDDL, the output terminal 16 is changed from the ground level GND to the high-voltage power supply VDDH level. Realize the conversion from low voltage VSSL-VDDL to high voltage GND-VDDH.
  • FIG. 5 is a schematic diagram of the data operation unit of the present invention.
  • the data operation unit 700 includes a control circuit 701, an operation circuit 702, a storage circuit 703, and a plurality of full-swing voltage conversion circuits 10.
  • the control circuit 701 performs voltage conversion on the data read from the storage circuit 703 through the full-swing voltage conversion circuit 10, the operation circuit 702 performs operation on the read data, and the control circuit 701 outputs the operation result.
  • FIG. 6 is a schematic diagram of the chip of the present invention.
  • the chip 800 includes a control unit 801 and one or more data operation units 700.
  • the control unit 801 inputs data to the data operation unit 700 and processes the data output by the data operation unit 700.
  • FIG. 7 is a schematic diagram of the computing board of the present invention. As shown in FIG. 7, each hash board 900 includes one or more chips 800 to perform a hash operation on the work data issued by the mining pool.
  • each computing device 1000 includes a connection board 1001, a control board 1002, a radiator 1003, a power board 1004, and one or more computing boards 900.
  • the control board 1002 is connected to the computing board 900 through a connection board 1001, and the radiator 1003 is disposed around the computing board 900.
  • the power board 1004 is used to provide power to the connection board 1001, the control board 1002, the radiator 1003, and the computing board 900.
  • the present invention may have other various embodiments. Without departing from the spirit and essence of the present invention, those skilled in the art can make various corresponding changes and modifications according to the present invention, but these corresponding Changes and modifications should fall within the protection scope of the claims attached to the present invention.
  • the ability of the voltage conversion circuit to identify the differential input signal can be improved, so that the full-swing voltage conversion circuit of the present invention can realize the conversion from a low input voltage to a high output voltage.

Abstract

一种全摆幅电压转换电路(10)及应用其的运算单元(700)、芯片(800)、算力板(900)和计算设备(1000)。全摆幅电压转换电路(10)包括输入端(15)，用于第一电平信号的输入；输出端(16)，用于第二电平信号的输出；差分输入单元(11)，用于反相输入端(15)的第一电平信号，并输出差分输入信号；转换单元(12)，用于将差分输入信号的第一电平转换成第二电平信号；输出驱动单元(14)，用于将第二电平信号输出至输出端(16)；还包括设置在输入端(15)与转换单元(12)之间的辅助下拉单元(13)，辅助下拉单元(13)接收输出驱动单元(14)的反馈信号，以提高转换单元(12)识别差分输入信号的能力，从而使得全摆幅电压转换电路(10)能够实现从输入低电压到输出高电压的转换。

Description

全摆幅电压转换电路及应用其的运算单元、芯片、算力板和计算设备 技术领域
本发明涉及一种电压转换器(LVL，Level-Shifter)，特别涉及一种在计算设备中应用的全摆幅电压转换电路(Full Swing Level-Shifter)及应用其的运算单元、芯片、算力板和计算设备。
背景技术
多电压域(Multi-supply voltage domain)供电技术越来越广泛的应用于片上芯片系统(System-on-chip，SoC)及多处理器计算结构中。在应用了多电压域技术的芯片中，该芯片通常含有多个独立的电压域或电压岛，并且每个电压域下的模块根据其时序的要求工作在恰当的电源电压下。通常，对于时序比较关键的模块，它通常工作在高的电源电压下(VDDH)下，以满足芯片对速度性能的要求；而对于非关键的电路模块，它则工作在低的电源电压(VDDL)甚至亚阈值电源电压下，以降低芯片的功耗消耗和能量消耗。
电压转换器是多电压系统中一个必不可少的电路，它为各个不同的电压域提供不同的电源供应，保证信号在各个电压域之间的传输。正常情况下，信号从高压域转换到低压域，普通的缓冲器(buffer)便可实现。但是，如果信号是从低压域转换到高压域，尤其是从亚阈值电压域转换到高压域，则需要更为复杂的电路。
CN104506183A公开了一种电压转换器，如图1所示，它由一对交叉耦合的PMOS管，一对下拉NMOS管及提供差分输入的低压反相器构成。当输入IN从“0”跳变到VDDL时，M1管将节点OUTB电压下拉至“0”，再通过交叉耦合的PMOS对将输出OUT预充为高电平VDDH。由于低电压区工作的NMOS管提供的下拉电流，比高电压区工作的PMOS提供的上拉电流小几个数量级，导致上拉网络与下拉网络的竞争异常激烈，从而使得传统的电压转换器无法实现低阈值信号的转换，并且存在功率泄漏比较大、输入电压范围窄以及从低电压到高电压转换的延迟时间较长的问题。
CN107707246A公开了一种亚阈值电压转换器，如图2所示，第一正常阈值电压PMOS晶体管MP1、第二正常阈值电压PMOS晶体管MP2、第一高阈值电 压PMOS晶体管MP3，所述第一正常阈值电压PMOS晶体管MP1和第二正常阈值电压PMOS晶体管MP2的源极分别接高供电电压，所述第一正常阈值电压PMOS晶体管MP1的漏极接所述第一高阈值电压PMOS晶体管MP3的源极，还包括：第一低阈值电压NMOS晶体管MN1、第二低阈值电压NMOS晶体管MN2，所述第一低阈值电压NMOS晶体管MN1的源极接地，所述第二正常阈值电压PMOS晶体管MP2的漏极接所述第二低阈值电压NMOS晶体管MN2的漏极，所述第二低阈值电压NMOS晶体管MN2的源极接地，所述第一正常阈值电压PMOS晶体管MP1和所述第二正常阈值电压PMOS晶体管MP2的栅极接所述第一正常阈值电压PMOS晶体管MP1的漏极，所述第一高阈值电压PMOS晶体管MP3的栅极接所述第二正常阈值电压PMOS晶体管MP2的漏极；同时，将所述第一低阈值电压NMOS晶体管MN1的栅极作为所述电流镜的第一输入端接输入缓冲器的一端，将所述第二低阈值电压NMOS晶体管MN2的栅极作为所述电流镜的第二输入端接输入缓冲器的另一端；将所述第一正常阈值电压PMOS晶体管MP1的漏极作为所述电流镜的第一输出端，将所述第二正常阈值电压PMOS晶体管MP2的漏极作为所述电流镜的第二输出端。本实施例中提出的电平转换器的CMOS电平转换电路实现如图2所示，同时优选地可以采用多阈值器件(MTCMOS)技术优化传播延迟和降低能量消耗，采用多阈值器件的配合使用进一步优化了CMOS电平转换电路的设计。此种亚阈值电压转换器虽然能实现在低输入电压范围内的电压转换，但是，电路设计和生产过程中需要使用多种阈值的晶体管，设计和生产难度极大。
发明公开
为了解决上述问题，本发明提供一种全摆幅电压转换电路，上述电路能够实现从输入低电压到输出高电压的转换。
为了实现上述目的，本发明提供了一种全摆幅电压转换电路，包括：
输入端，用于第一电平信号的输入；
输出端，用于第二电平信号的输出；
差分输入单元，用于反相所述输入端的第一电平信号，并输出差分输入信号；
转换单元，用于将所述差分输入信号的第一电平转换成第二电平信号；
输出驱动单元，用于将所述第二电平信号输出至所述输出端；
其中，还包括设置在所述输入端与所述转换单元之间的辅助下拉单元，所述辅助下拉单元接收所述输出驱动单元的反馈信号。
上述的全摆幅电压转换电路，其中，所述转换单元提高识别所述差分输入信号的能力是通过所述辅助下拉单元导通形成所述转换单元的辅助下拉单元通路实现。
上述的全摆幅电压转换电路，其中，所述辅助下拉单元包括两个或两个以上的晶体管，所述两个或两个以上的晶体管依次串联连接。
上述的全摆幅电压转换电路，其中，所述辅助下拉单元包括第一NMOS晶体管以及第二NMOS晶体管，所述第一NMOS晶体管以及所述第二NMOS晶体管串联连接。
上述的全摆幅电压转换电路，其中，所述第一NMOS晶体管的栅极与输入信号连接，所述第二NMOS晶体管的栅极与所述输出驱动单元连接。
上述的全摆幅电压转换电路，其中，所述输出驱动单元包括第一反相器以及第二反相器，所述第一反相器与第二反相器串联连接，所述第一反相器的输出端输出所述反馈信号。
为了实现上述目的，本发明还提供一种数据运算单元，包括互联连接的控制电路、运算电路、存储电路以及多个全摆幅电压转换电路，其中，所述多个全摆幅电压转换电路为上述任意一种所述的全摆幅电压转换电路。
为了实现上述目的，本发明还提供一种芯片，其中，所述芯片包括上述任意一种数据运算单元。
为了实现上述目的，本发明还提供一种用于计算设备中的算力板，其中，所述算力板包括多个上述的任意一种所述芯片。
为了实现上述目的，本发明还提供一种计算设备，包括电源板、控制板、连接板、散热器以及多个算力板，所述控制板通过所述连接板与所述算力板连接，所述散热器设置在所述算力板的周围，所述电源板用于向所述连接板、所述控制板、所述散热器以及所述算力板提供电源，其中，所述算力板为上述任意一种所述算力板。
以下结合附图和具体实施例对本发明进行详细描述，但不作为对本发明的限定。
附图简要说明
图1为现有电压转换器电路示意图；
图2为现有亚阈值电压转换器电路示意图；
图3为本发明全摆幅电压转换电路示意图；
图4为本发明全摆幅电压转换电路的电路示意图；
图5为本发明数据运算单元示意图；
图6为本发明芯片示意图；
图7为本发明算力板示意图；
图8为本发明计算设备示意图。
其中，附图标记：
10-全摆幅电压转换电路
11-差分输入单元
12-转换单元
13-辅助下拉单元
14-输出驱动单元
15-输入端
16-输出端
103-高电压电源端
104-低电压电源端
105-反相器
106、107、111、113、115-PMOS晶体管
108、109、110、112、114、116-NMOS晶体管
118、119、120、121-节点
122-高电压地端
123-低电压地端
700-数据运算单元
701-控制电路
702-运算电路
703-存储电路
800-芯片
801-控制单元
900-算力板
1000-计算设备
1001-连接板
1002-控制板
1003-散热器
1004-电源板
实现本发明的最佳方式
下面结合附图对本发明的结构原理和工作原理作具体的描述：
在说明书及后续的权利要求当中使用了某些词汇来指称特定组件。所属领域中具有通常知识者应可理解，制造商可能会用不同的名词来称呼同一个组件。本说明书及后续的权利要求并不以名称的差异来作为区分组件的方式，而是以组件在功能上的差异来作为区分的准则。在整个说明书中，相同的附图标记表示相同的元件。
在通篇说明书及后续的权利要求当中所提及的“包括”和“包含”为一开放式的用语，故应解释成“包含但不限定于”。以外，“连接”一词在此为包含任何直接及间接的电性连接手段。间接的电性连接手段包括通过其它装置进行连接。
图3是本发明全摆幅电压转换电路的示意图。如图3所示，全摆幅电压转换电路10包括差分输入单元11、转换单元12、辅助下拉单元13、输出驱动单元14、输入端15以及输出端16，该输入端15分别通过差分输入单元11、辅助下拉单元13或直接与转换单元12连接，转换单元12连接输出驱动单元14，辅助下拉单元13接收输出驱动单元14的反馈信号，输出驱动单元14连接输出端16。
实施例一
图4是本发明全摆幅电压转换电路的电路示意图。在实施例一中，结合图3、图4所示，全摆幅电压转换电路10包括输入端15、输出端16、高电压电源端103、低电压电源端104、高电压地端122以及低电压地端123。其中， 高电压电源端103连接高电压电源VDDH，例如0-1.8V，具体可为1.2V、1.8V等，低电压电源端104连接低电压电源VDDL，例如0-0.4V，具体可为0.3V、0.4V等，高电压地端122以及低电压地端123均接地GND。
全摆幅电压转换电路10的差分输入单元11为反相器105，反相器105工作在低电源电压区域，反相器105的电源连接至低电压电源端104，由低电压源VDDL提供电源；反相器105的低电压地端123直接接地GND。反相器105的输入端与全摆幅电压转换电路10的输入端15连接，输入低电平信号VIN，输出端产生与输入端15反相的低电平信号NVIN，输入端15的低电平信号VIN以及经反相器105反相输出的低电平信号NVIN共同构成差分输入信号。
全摆幅电压转换电路10的转换单元12包括PMOS晶体管106、107、111以及NMOS晶体管108、112。其中，PMOS晶体管106、111构成电流镜结构，PMOS晶体管107起到漏电保护的作用，NMOS晶体管108、112作为差分输入晶体管，接收差分输入单元11提供的差分输入信号。PMOS晶体管106、111的源极端连接高电压电源端103，由高电压电源VDDH提供电源。PMOS晶体管106的漏极连接至PMOS晶体管107的源极，PMOS晶体管107的漏极与NMOS晶体管108的漏极连接，形成节点118。NMOS晶体管108的源极接高电压地端122。PMOS晶体管111的漏极与NMOS晶体管112的漏极连接，形成节点119，作为转换单元12的输出端，输出高电平信号。NMOS晶体管112的源极接高电压地端122。
PMOS晶体管106和PMOS晶体管111的栅极连接在一起，形成节点121，并连接至PMOS晶体管106的漏极。PMOS晶体管107的栅极连接至节点119。NMOS晶体管108的栅极连接全摆幅电压转换电路10的输入端15，接收输入信号VIN。NMOS晶体管112的栅极连接反相器105的输出端，接收与输入信号反相的信号NVIN。
全摆幅电压转换电路10的输出驱动单元14为由PMOS晶体管113、NMOS晶体管114以及PMOS晶体管115、NMOS晶体管116构成的两级反相器级联形成，输出驱动单元14的输入端连接至转换单元12的输出端，即节点19。两级反相器之间形成节点120，输出驱动单元14的输出端与全摆幅电压转换电路10的输出端16连接，作为整个电路的输出。
全摆幅电压转换电路10的辅助下拉单元13由串联连接的NMOS晶体管 109、110构成。NMOS晶体管110源极连接至高电压地端122，漏极端与NMOS晶体管109的源极连接，NMOS晶体管109的漏极连接至节点121。NMOS晶体管109的栅极连接至全摆幅电压转换电路10的输入端15，接收输入信号VIN。NMOS晶体管110的栅极连接至节点120。
本实施例全摆幅电压转换电路10的工作原理如下：
结合图4所示，全摆幅电压转换电路10的输入端15输入VIN信号，VIN可以为“0”，表示低电平，也可以是“1”，表示高电平。反相器105将输入VIN信号进行反相，产生NVIN信号。其中，VIN连接NMOS晶体管108的栅极，作为转换单元12的其中一个输入；NVIN连接NMOS晶体管112的栅极，作为转换单元12的另外一个输入。由于VIN、NVIN之间为反相信号，当VIN为“0”时，NVIN为“1”，当VIN为“1”时，NVIN为“0”。因此，NMOS晶体管108与NMOS晶体管112之中总有一个处于导通状态。
需要说明的是，差分输入单元11为反相器105，反相器105工作在低电源电压区域，反相器105的电源连接至低电压电源端104。因此，输入端15输入高电平信号“1”时，实际指VDDL电平。全摆幅电压转换电路10的转换单元12工作在高电源电压区域，由高电压电源VDDH提供电源。在高电源电压区域VDDH下，低电源电压区域的VDDL输入只能对差分输入的NMOS晶体管108及NMOS晶体管112实现“半开启”或“弱开启”的效果。
当VIN输入为“0”时，NVIN为“1”，NMOS晶体管108截止，节点118处于高电平，状态保持不变。NMOS晶体管112导通，节点119与地之间形成下拉通路，节点119为低电平“0”。
现有的全摆幅电压转换电路10不包括辅助下拉单元13。当VIN输入由“0”变为“1”时，NVIN由“1”变为“0”，NMOS晶体管108由截止变为弱开启，NMOS晶体管112截止，NMOS晶体管108与地之间形成电流通路，节点118处的电压被下拉。节点119处的前一状态是低电平“0”，由于电路延迟的作用，节点119处的电平仍保持为“0”，使得PMOS晶体管107处于开启状态，节点121处的电压会随着PMOS晶体管107、NMOS晶体管108的导通形成下拉趋势。
然而，由于PMOS晶体管106的栅极、漏极连接在一起，形成二极管连接方式，节点121处的电压会受到PMOS晶体管106的上拉影响。由于NMOS晶体管108工作在亚阈值导通状态下，会严重影响下拉效果，甚至可能会被PMOS 晶体管106上拉并形成钳位，无法达到输出的翻转。
另外，VIN输入为“1”时，NMOS晶体管112截止，节点119处的电平为高电平，PMOS晶体管107截止，从而阻断PMOS晶体管106及NMOS晶体管108同时开启的直流通路。进而可以降低全摆幅电压转换电路10的功耗。
由于反相器105工作在低电压电源VDDL下，因此，VIN为“1”时的高电平也就是VDDL。当VDDL过低时，NMOS晶体管108以及NMOS晶体管112工作在亚阈值状态下，此时，需要提高转换单元12对于两个输入端的差分信号的区别能力。
在引入辅助下拉单元13后，当VIN输入由“0”变为“1”时，NVIN由“1”变为“0”，由于电路延迟的作用，节点120处的电平仍保持为“1”，使得辅助下拉单元13中的NMOS晶体管110开启，NMOS晶体管109也同步弱开启，对节点121处的电压产生两条下拉通路，分别是PMOS晶体管107、NMOS晶体管108以及NMOS晶体管109、NMOS晶体管110形成的两条下拉通路。当节点121被下拉后，PMOS晶体管111导通，NMOS晶体管112截止，使得节点119处的电压被上拉至VDDH，最终实现输出跳变。
当节点119处的电平变成“1”后，PMOS晶体管107截止，关闭了PMOS晶体管107、NMOS晶体管108形成的下拉通路；此时，节点120处的电平变成“0”，NMOS晶体管110截止，关闭了NMOS晶体管109、NMOS晶体管110的下拉通路，由此关断了直流通路，防止直流串通。
其中，NMOS晶体管109、110为低阈值电压晶体管，NMOS晶体管的数量也可为多个，多个NMOS晶体管串联连接，并在输入由“0”变为“1”时同时导通。
由此可见，在引入辅助下拉单元13之后，节点121与地之间不仅通过NMOS晶体管108和PMOS晶体管107形成了下拉通路，还通过辅助下拉单元13中的NMOS晶体管109、110形成下拉通路。从而，将节点119处的电平迅速拉升至“1”，节点119处的电平则由地电平变为高电压电源VDDH电平。
因此，通过本发明的全摆幅电压转换电路10，可以实现输入端15由“0”变为“1”时，即由地电平变为低电压电源VDDL电平时，输出端16由地电平变为高电压电源VDDH电平，实现低电压VDDL向高电压VDDH的转换。
当VIN输入由“1”变为“0”时，NVIN由“0”变为“1”，节点119处 的电平在前一状态下为“1”，PMOS晶体管107关闭；节点120处的电平在前一状态下为“0”，NMOS晶体管110关闭；节点121处的电压没有下拉通路，其电位稳定于PMOS晶体管106的二极管连接方式，即比VDDH低一个PMOS晶体管106的阈值电压，即VDDH-Vth，而此时PMOS晶体管111的Vds为0，Vgs为Vth，PMOS晶体管111处于截止状态，NMOS晶体管112的弱开启足够将节点119处的电压下拉至电路输出翻转。
实施例二
图4是本发明全摆幅电压转换电路的电路示意图。在实施例二中，结合图3、图4所示，全摆幅电压转换电路10包括输入端15、输出端16、高电压电源端103、低电压电源端104、高电压地端122以及低电压地端123。与实施例一不同的仅仅在于低电压电源端104连接低电压电源VDDL，例如0.4-0.8V、0.8-1.2V，具体可为0.7V、0.8V，1.1V、1.2V，低电压地端123接低电压地VSSL，例如0-0.4V、0.4-0.8V，具体可为0.3V、0.4V，0.7V、0.8V。其他的电路结构及连接关系均与实施例一相同，在此不再赘述。
本实施例全摆幅电压转换电路10的工作原理如下：
结合图4所示，全摆幅电压转换电路10的输入端15输入VIN信号，VIN可以为“0”，表示低电平VSSL，也可以是“1”，表示高电平VDDL。反相器105将输入VIN信号进行反相，产生NVIN信号。
与实施例一相同，当VIN输入为“0”即为VSSL时，NVIN为“1”即为VDDL，NMOS晶体管108截止，节点118的状态保持不变；NMOS晶体管112导通，节点119与地之间形成下拉通路，节点119为“0”。
当VIN输入由“0”变为“1”即由VSSL变为VDDL时，NVIN由“1”变为“0”即由VDDL变为VSSL，节点119处的电平则由地电平GND变为高电压电源VDDH电平。
因此，通过本实施例的全摆幅电压转换电路200，可以实现输入端15由低电平VSSL变为高电平VDDL时，输出端16由地电平GND变为高电压电源VDDH电平，实现低电压VSSL-VDDL向高电压GND-VDDH的转换。
本发明还提供一种数据运算单元，图5为本发明数据运算单元示意图。如图5所示，数据运算单元700包括控制电路701、运算电路702、存储电路703以及多个全摆幅电压转换电路10。控制电路701对从存储电路703中读出的 数据通过全摆幅电压转换电路10进行电压转换，运算电路702对读取的数据进行运算，再由控制电路701将运算结果输出。
本发明还提供一种芯片，图6为本发明芯片示意图。如图6所示，芯片800包括控制单元801，以及一个或多个数据运算单元700。控制单元801向数据运算单元700输入数据并将数据运算单元700输出的数据进行处理。
本发明还提供一种算力板，图7为本发明算力板示意图。如图7所示，每一个算力板900上包括一个或多个芯片800，对矿池下发的工作数据进行哈希运算。
本发明还提供一种计算设备，所述计算设备优选用于挖掘虚拟数字货币的运算，当然所述计算设备也可以用于其他任何海量运算，图8为本发明计算设备示意图。如图8所示，每一个计算设备1000包括连接板1001、控制板1002、散热器1003、电源板1004，以及一个或多个算力板900。控制板1002通过连接板1001与算力板900连接，散热器1003设置在算力板900的周围。电源板1004用于向所述连接板1001、控制板1002、散热器1003以及算力板900提供电源。
需要说明的是，在本发明的描述中，术语“横向”、“纵向”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本发明和简化描述，并不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。
尽管本发明的实施方案已公开如上，但其并不仅仅限于说明书和实施方式中所列运用，它完全可以被适用于各种适合本发明的领域，对于熟悉本领域的人员而言，可容易地实现另外的修改，因此在不背离权利要求及等同范围所限定的一般概念下，本发明并不限于特定的细节和这里示出与描述的图例。
换言之，本发明还可有其它多种实施例，在不背离本发明精神及其实质的情况下，熟悉本领域的技术人员当可根据本发明作出各种相应的改变和变形，但这些相应的改变和变形都应属于本发明所附的权利要求的保护范围。
工业应用性
采用本发明的全摆幅电压转换电路及应用其的运算单元、芯片、算力板和计算设备，具有以下有益效果：
能够提高电压转换电路识别差分输入信号的能力，从而使得本发明的全摆幅电压转换电路能够实现从输入低电压到输出高电压的转换。

Claims (10)

  1. 一种全摆幅电压转换电路，包括：
    输入端，用于第一电平信号的输入；
    输出端，用于第二电平信号的输出；
    差分输入单元，用于反相所述输入端的第一电平信号，并输出差分输入信号；
    转换单元，用于将所述差分输入信号的第一电平转换成第二电平信号；
    输出驱动单元，用于将所述第二电平信号输出至所述输出端；
    其特征在于，还包括设置在所述输入端与所述转换单元之间的辅助下拉单元，所述辅助下拉单元接收所述输出驱动单元的反馈信号。
  2. 如权利要求1所述的全摆幅电压转换电路，其特征在于：所述转换单元提高识别所述差分输入信号的能力是通过所述辅助下拉单元导通形成所述转换单元的辅助下拉通路实现。
  3. 如权利要求2所述的全摆幅电压转换电路，其特征在于：所述辅助下拉单元包括两个或两个以上的晶体管，所述两个或两个以上的晶体管依次串联连接。
  4. 如权利要求3所述的全摆幅电压转换电路，其特征在于：所述辅助下拉单元包括第一NMOS晶体管以及第二NMOS晶体管，所述第一NMOS晶体管以及所述第二NMOS晶体管串联连接。
  5. 如权利要求4所述的全摆幅电压转换电路，其特征在于：所述第一NMOS晶体管的栅极与所述输入端的所述第一电平信号连接，所述第二NMOS晶体管的栅极与所述输出驱动单元的所述反馈信号连接。
  6. 如权利要求5所述的全摆幅电压转换电路，其特征在于：所述输出驱动单元包括第一反相器以及第二反相器，所述第一反相器与第二反相器串联连接，所述第一反相器的输出端输出所述反馈信号。
  7. 一种数据运算单元，包括互联连接的控制电路、运算电路、存储电路以及多个全摆幅电压转换电路，其特征在于：所述多个全摆幅电压转换电路为权利要求1-6中任意一种所述的全摆幅电压转换电路。
  8. 一种芯片，其特征在于，包括权利要求7中所述的任意一种数据运算 单元。
  9. 一种用于计算设备中的算力板，其特征在于，包括多个权利要求8中所述的任意一种所述芯片。
  10. 一种计算设备，包括电源板、控制板、连接板、散热器以及多个算力板，所述控制板通过所述连接板与所述算力板连接，所述散热器设置在所述算力板的周围，所述电源板用于向所述连接板、所述控制板、所述散热器以及所述算力板提供电源，其特征在于：所述算力板为权利要求9中所述的任意一种所述算力板。
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