WO2020004422A1 - Dispositif de formation d'image - Google Patents

Dispositif de formation d'image Download PDF

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Publication number
WO2020004422A1
WO2020004422A1 PCT/JP2019/025242 JP2019025242W WO2020004422A1 WO 2020004422 A1 WO2020004422 A1 WO 2020004422A1 JP 2019025242 W JP2019025242 W JP 2019025242W WO 2020004422 A1 WO2020004422 A1 WO 2020004422A1
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WIPO (PCT)
Prior art keywords
light emitting
data
emitting element
magnification
line
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Application number
PCT/JP2019/025242
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English (en)
Japanese (ja)
Inventor
広高 関
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キヤノン株式会社
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Publication of WO2020004422A1 publication Critical patent/WO2020004422A1/fr

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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
    • B41J2/435—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of radiation to a printing material or impression-transfer material
    • B41J2/447—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of radiation to a printing material or impression-transfer material using arrays of radiation sources
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41J—TYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J2/00—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
    • B41J2/435—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of radiation to a printing material or impression-transfer material
    • B41J2/447—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of radiation to a printing material or impression-transfer material using arrays of radiation sources
    • B41J2/45—Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by selective application of radiation to a printing material or impression-transfer material using arrays of radiation sources using light-emitting diode [LED] or laser arrays
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/20—Exposure; Apparatus therefor
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03G—ELECTROGRAPHY; ELECTROPHOTOGRAPHY; MAGNETOGRAPHY
    • G03G15/00—Apparatus for electrographic processes using a charge pattern
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03G—ELECTROGRAPHY; ELECTROPHOTOGRAPHY; MAGNETOGRAPHY
    • G03G15/00—Apparatus for electrographic processes using a charge pattern
    • G03G15/04—Apparatus for electrographic processes using a charge pattern for exposing, i.e. imagewise exposure by optically projecting the original image on a photoconductive recording material
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03G—ELECTROGRAPHY; ELECTROPHOTOGRAPHY; MAGNETOGRAPHY
    • G03G21/00—Arrangements not provided for by groups G03G13/00 - G03G19/00, e.g. cleaning, elimination of residual charge
    • G03G21/14—Electronic sequencing control
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof

Definitions

  • the present invention relates to an electrophotographic image forming apparatus.
  • a method of exposing a photosensitive drum using an exposure head using an LED (Light Emitting Diode) or an organic EL (Organic Electro Luminescence) to form a latent image is generally used.
  • the exposure head includes a light emitting element array arranged in the longitudinal direction of the photosensitive drum, and a rod lens array for forming an image of light from the light emitting element array on the photosensitive drum.
  • an LED or an organic EL has a surface emission shape in which a light irradiation direction from a light emission surface is the same as that of a rod lens array.
  • the length of the light emitting element row is determined according to the image area width on the photosensitive drum, and the interval between the light emitting elements is determined according to the resolution of the printer. For example, in the case of a 1200 dpi printer, the interval between pixels is 21.16 ⁇ m, which is an interval corresponding to resolution, and therefore, the interval between light emitting elements is also an interval corresponding to 21.16 ⁇ m. Since a printer using such an exposure head uses a smaller number of parts than a laser scanning printer that scans a photosensitive drum with a laser beam deflected by a rotating polygon mirror, the apparatus is downsized. It is easy to reduce the cost. Further, in a printer using an exposure head, the sound generated by the rotation of the rotary polygon mirror is reduced.
  • a shift may occur in the magnification in the sub-scanning direction.
  • a deviation occurs between the rotation speed of the photosensitive drum and the light emission cycle of the exposure head, and a deviation occurs due to thermal contraction of the sheet by nipping and conveying the sheet by a fixing device after forming an image on the sheet. Therefore, in order to correct the magnification in the sub-scanning direction, for example, in Japanese Patent Application Laid-Open No. H10-157, the image data is divided into a plurality of regions in the sub-scanning direction, and the printing rate is calculated for each of the divided regions.
  • the entire correction amount which is a correction amount for correcting the magnification of the image data in the sub-scanning direction based on the calculated printing rate, is distributed to a plurality of regions, and the partial correction amount, which is the correction amount distributed for each region, is calculated.
  • the light emission cycle of the exposure head is changed to satisfy the condition.
  • magnification correction in the sub-scanning direction can be accurately performed on image data including an area with a low printing rate, but sub-scanning can be performed on image data with an overall high printing rate. Performing magnification correction in the direction changes the density of image data. Conversely, if priority is given to suppressing density fluctuation of image data, there is a problem that magnification correction in the sub-scanning direction cannot be performed with high accuracy.
  • the present invention has been made under such circumstances, and has as its object to accurately correct magnification in the sub-scanning direction.
  • an image forming apparatus has the following configuration.
  • a rotatable photoreceptor a plurality of light emitting elements arranged at mutually different positions in an intersecting direction intersecting with the rotation direction of the photoreceptor, and a driving unit for driving the plurality of light emitting elements exposing the photoreceptor
  • an exposure head comprising: an image forming apparatus that forms an image having a resolution corresponding to an arrangement interval of the plurality of light emitting elements in the cross direction, wherein the image data is driven in synchronization with a clock signal.
  • An output unit that outputs the clock signal; a first generation unit that generates the clock signal; a second generation unit that generates a one-line periodic signal corresponding to the resolution of the photoconductor in the rotation direction; Control means for controlling a cycle of the clock signal and a cycle of the periodic signal in accordance with a magnification of an image to be output in the rotation direction of the photoconductor.
  • the magnification in the sub-scanning direction can be accurately corrected.
  • FIG. 1 is a schematic sectional view illustrating a configuration of an image forming apparatus according to first and second embodiments.
  • FIG. 3 is a diagram illustrating a positional relationship between an exposure head and a photosensitive drum according to the first and second embodiments.
  • FIG. 3 is a diagram illustrating a configuration of an exposure head.
  • FIG. 4 is a schematic view of a surface of the drive substrate according to the first and second embodiments on which a surface light emitting element array element group is mounted.
  • FIG. 4 is a schematic view of a surface of the driving substrate opposite to a surface on which the surface light emitting element array element group is mounted.
  • FIG. 2 illustrates a structure of a surface-emitting element array chip.
  • FIG. 3 is a control block diagram of a control board and an exposure head according to the first and second embodiments.
  • FIG. 6 is a diagram illustrating a relationship between the presence or absence of magnification correction and a clock cycle according to the first embodiment.
  • FIG. 3 is a control block diagram of a chip data conversion unit according to the first and second embodiments. 6 is a timing chart illustrating input / output timing of line data in a chip data conversion unit.
  • FIG. 4 is a diagram for describing processing of image data by a chip data conversion unit according to the first and second embodiments.
  • FIG. 3 is a diagram illustrating a circuit of the surface emitting element array chip according to the first and second embodiments.
  • FIG. 4 is a diagram for explaining a distribution state of a gate potential of the shift thyristors of the first and second embodiments.
  • FIG. 4 is a diagram for explaining a distribution state of a gate potential of the shift thyristors of the first and second embodiments.
  • FIG. 4 is a diagram for explaining a distribution state of a gate potential of the shift thyristors of the first and second embodiments.
  • FIG. 4 is a diagram showing a drive signal waveform of the surface emitting element array chips of the first and second embodiments.
  • FIG. 4 is a plan view of a plurality of light-emitting elements having a mesa structure.
  • FIG. 11B is a cross-sectional view of the light-emitting element having a mesa structure, taken along line XIB-XIB in FIG. 11A.
  • 5 is a time chart showing the presence / absence of magnification correction, a Line synchronization signal, and image data according to the first embodiment.
  • FIG. 3 is a diagram illustrating a dot shape formed on the photosensitive drum according to the first embodiment.
  • FIG. 9 is a diagram illustrating a relationship between a clock cycle and a light amount according to the second embodiment.
  • FIG. 9 is a diagram illustrating a relationship between the presence or absence of a magnification in the sub-scanning direction and the light amount according to the second embodiment.
  • FIG. 10 is a block diagram of another embodiment.
  • FIG. 10 is a block diagram of another embodiment.
  • FIG. 10 is a block diagram of another embodiment.
  • FIG. 4 is a diagram illustrating a lookup table according to the first and second embodiments.
  • FIG. 4 is a diagram illustrating a lookup table according to the first and second embodiments.
  • FIG. 4 is a diagram illustrating a lookup table according to the first and second embodiments.
  • FIG. 1 is a schematic cross-sectional view illustrating a configuration of an electrophotographic image forming apparatus 10 according to the first embodiment.
  • An image forming apparatus 10 shown in FIG. 1 is a multifunction peripheral (MFP) having a scanner function and a printer function, and controls a scanner unit 100, an image forming unit 103, a fixing unit 104, a feeding / transporting unit 105, and these units. It comprises a printer control unit (not shown).
  • the scanner unit 100 illuminates a document placed on a document table, optically reads a document image, converts the read image into an electric signal, and creates image data.
  • MFP multifunction peripheral
  • the image forming unit 103 is arranged in the order of cyan (C), magenta (M), yellow (Y), and black (K) along the rotation direction (counterclockwise direction) of the endless transport belt 111. It has a series of image forming stations. The four image forming stations have the same configuration, and each image forming station includes a photosensitive drum 102, which is a photosensitive member that rotates in the direction of an arrow (clockwise), an exposure head 106, a charger 107, and a developing device 108. I have.
  • the suffixes a, b, c, and d of the photosensitive drum 102, the exposure head 106, the charger 107, and the developing device 108 are black (K), yellow (Y), magenta (M), and cyan ( C).
  • K black
  • Y yellow
  • M magenta
  • C cyan
  • the photosensitive drum 102 is rotated, and the photosensitive drum 102 is charged by the charger 107.
  • An exposure head 106 serving as an exposure unit emits light from the arranged LED array according to image data, and condenses light emitted from the chip surface of the LED array onto the photosensitive drum 102 (photosensitive member) by a rod lens array.
  • the developing device 108 develops the electrostatic latent image formed on the photosensitive drum 102 with toner.
  • the developed toner image is transferred to a recording sheet on a transport belt 111 that transports the recording sheet.
  • Such a series of electrophotographic processes is executed in each image forming station.
  • each of the magenta (M), yellow (Y), and black (K) image forming stations is sequentially performed. Then, the image forming operation is executed.
  • the image forming apparatus 10 illustrated in FIG. 1 includes, as units for feeding recording paper, internal feeding units 109a and 109b included in the feeding / conveying unit 105, an external feeding unit 109c that is a large-capacity feeding unit, And a manual feed unit 109d.
  • the recording paper is fed from a feeding unit designated in advance, and the fed recording paper is conveyed to the registration roller 110.
  • the registration roller 110 conveys the recording paper to the conveyance belt 111 at the timing when the toner image formed in the image forming unit 103 is transferred onto the recording paper.
  • the toner images formed on the photosensitive drums 102 of the respective image forming stations are sequentially transferred onto the recording paper transported by the transport belt 111.
  • the recording paper to which the unfixed toner image has been transferred is conveyed to the fixing unit 104.
  • the fixing unit 104 has a built-in heat source such as a halogen heater, and fixes the toner image on the recording paper to the recording paper by heating and pressing with two rollers.
  • the recording paper on which the toner image has been fixed by the fixing unit 104 is discharged to the outside of the image forming apparatus 10 by the discharge roller 112.
  • An optical sensor 113 serving as a detection unit is disposed at a position facing the transport belt 111 downstream of the black (K) image forming station in the recording paper transport direction.
  • the optical sensor 113 detects the position of the test image formed on the transport belt 111 to derive the amount of color shift of the toner image between the image forming stations.
  • the color shift amount derived by the optical sensor 113 is notified to a control board 415 (see FIG. 4) described later, and the image position of each color is corrected so that a full-color toner image without color shift is transferred onto the recording paper.
  • a printer control unit controls the above-described scanner unit 100, image forming unit 103, fixing unit 104, and supply unit in accordance with an instruction from an MFP control unit (not shown) that controls the entire multifunction peripheral (MFP).
  • MFP control unit controls the entire multifunction peripheral (MFP).
  • the image forming operation is executed while controlling the feeding / conveying unit 105 and the like.
  • the image forming apparatus 10 of the type that directly transfers the toner image formed on the photosensitive drum 102 of each image forming station to the recording paper on the transport belt 111 has been described.
  • the present invention is not limited to such a printer that directly transfers the toner image on the photosensitive drum 102 to recording paper.
  • the present invention is also applicable to an image forming apparatus including a primary transfer unit that transfers the toner image on the photosensitive drum 102 to the intermediate transfer belt and a secondary transfer unit that transfers the toner image on the intermediate transfer belt to recording paper. can do.
  • FIG. 2A is a perspective view showing a positional relationship between the exposure head 106 and the photosensitive drum 102.
  • FIG. 2B is a perspective view showing the internal configuration of the exposure head 106 and a light beam 205 from the exposure head 106 being formed by the rod lens array 203.
  • FIG. 2A the exposure head 106 is mounted on the image forming apparatus 10 by a mounting member (not shown) at a position above the photosensitive drum 102 rotating in the direction of the arrow and facing the photosensitive drum 102 (see FIG. 2A). (Fig. 1).
  • the exposure head 106 includes a driving substrate 202, a surface light emitting element array element group 201 mounted on the driving substrate 202, a rod lens array 203, and a housing 204.
  • the rod lens array 203 and the drive board 202 are attached to the housing 204.
  • the rod lens array 203 focuses the light flux 205 from the surface light emitting element array element group 201 on the photosensitive drum 102.
  • the assembling and adjusting work is performed with the exposure head 106 alone, and the focus adjustment and the light amount adjustment of each spot are performed.
  • the assembly and adjustment are performed so that the distance between the photosensitive drum 102 and the rod lens array 203 and the distance between the rod lens array 203 and the surface light emitting element array element group 201 are at predetermined intervals.
  • the mounting position of the rod lens array 203 is adjusted so that the distance between the rod lens array 203 and the surface light emitting element array element group 201 becomes a predetermined value.
  • each light emitting element of the surface light emitting element array element group 201 is sequentially caused to emit light so that the light collected on the photosensitive drum 102 via the rod lens array 203 has a predetermined light quantity. Then, the drive current of each light emitting element is adjusted.
  • FIG. 3A is a schematic diagram illustrating the configuration of the surface of the drive substrate 202 on which the surface light emitting element array element group 201 is mounted
  • FIG. 3B is the surface of the drive substrate 202 on which the surface light emitting element array element group 201 is mounted ( It is a schematic diagram which shows the structure of the surface (2nd surface) opposite to (1st surface).
  • the surface light emitting element array element group 201 mounted on the driving substrate 202 includes 29 surface light emitting element array chips 1 to 29 in a staggered manner along the longitudinal direction of the driving substrate 202. It has a configuration arranged in rows.
  • the vertical direction indicates the sub-scanning direction (the rotation direction of the photosensitive drum 102) which is the first direction
  • the horizontal direction indicates the main scanning direction which is the second direction orthogonal to the sub-scanning direction.
  • the main scanning direction is also an intersecting direction that intersects the rotation direction of the photosensitive drum 102.
  • each element of the surface light emitting element array chip having a total of 516 light emitting points is arranged at a predetermined resolution pitch in the longitudinal direction of the surface light emitting element array chip.
  • the pitch of each element of the surface emitting element array chip is about 21.16 ⁇ m ( ⁇ 2.54 cm / 1200 dots), which is the pitch of the first resolution of 1200 dpi.
  • the arrangement interval from end to end of the 516 light emitting points in one surface light emitting element array chip is about 10.9 mm ( ⁇ 21.16 ⁇ m ⁇ 516).
  • the surface light emitting element array element group 201 is composed of 29 surface light emitting element array chips.
  • FIG. 3C is a diagram showing a state of a boundary portion between the surface light emitting element array chips arranged in two rows in the longitudinal direction.
  • the horizontal direction is the longitudinal direction of the surface light emitting element array element group 201 in FIG. 3A. is there.
  • a wire bonding pad to which a control signal is input is disposed at an end of the surface light emitting element array chip, and the transfer unit and the light emitting element are driven by a signal input from the wire bonding pad. Is done.
  • the surface light emitting element array chip has a plurality of light emitting elements.
  • the pitch in the longitudinal direction of the light emitting elements is about 21.16 ⁇ m, which is the pitch of the resolution of 1200 dpi. .
  • the distance between the light emitting points of the upper and lower surface light emitting element array chips is about 84 ⁇ m (4 pixels at 1200 dpi and 8 pixels at 2400 dpi). (A distance of an integral multiple of each minute).
  • driving units 303 a and 303 b and a connector 305 are mounted on the surface of the driving substrate 202 opposite to the surface on which the surface light emitting element array element group 201 is mounted.
  • the driving units 303a and 303b are driver ICs.
  • the driving units 303a and 303b disposed on both sides of the connector 305 drive the surface light emitting element array chips 1 to 15 and the surface light emitting element array chips 16 to 29, respectively.
  • the driving units 303a and 303b are connected to the connector 305 via the patterns 304a and 304b, respectively.
  • the connector 305 is connected to a signal line for controlling the driving units 303a and 303b from a control board 415 (see FIG.
  • a power supply voltage and a ground, and is connected to the driving units 303a and 303b.
  • wiring for driving the surface light emitting element array element group 201 passes through the inner layer of the driving substrate 202, and the surface light emitting element array chips 1 to 15 and the surface light emitting element array chips 16 to 29 It is connected to the.
  • FIG. 4 is a control block of a control board 415 as an output unit that processes image data and outputs the processed data to the exposure head 106, and a control block of a drive board 202 that exposes the photosensitive drum 102 based on the image data input from the control board 415.
  • FIG. Each of the blocks 401 to 414 described below indicates a module inside the IC.
  • the drive substrate 202 surface light emitting element array chips 1 to 15 controlled by the drive unit 303a shown in FIG. 4 will be described.
  • the surface emitting element array chips 16 to 29 controlled by the driving unit 303b (not shown in FIG. 4) perform the same operation as the surface emitting element array chips 1 to 15 controlled by the driving unit 303a.
  • the control board 415 shown in FIG. 4 has a connector 416 for transmitting a signal for controlling the exposure head 106. From the connector 416, image data, a Line synchronization signal described later, and a control signal from the CPU 400 of the control board 415 are transmitted via cables 417 and 418 connected to the connector 305 of the exposure head 106, respectively.
  • the control board 415 transmits a signal for controlling the exposure head 106 to the exposure head 106.
  • This signal is a signal obtained by parallel-serial conversion of a clock signal, image data, and a line synchronization signal.
  • This signal is input to the connector 305 on the exposure head side via a cable 417 for transmitting a signal from the connector 416 on the control board 415 side.
  • a communication signal of the CPU 400 is input to the connector 305 on the exposure head 106 side via the transmission cable 418.
  • the control board 415 the CPU 400 performs processing of image data and processing of print timing.
  • the control board 415 includes functional blocks of an image data generation unit 401, a line data shift unit 402, a chip data conversion unit 403, a chip data shift unit 404, a data transmission unit 405, and a synchronization signal generation unit 406.
  • processing in each functional block will be described in the order in which image data is processed in the control board 415.
  • An image data generation unit 401 serving as a data generation unit performs dithering processing on image data received from the scanner unit 100 or an external computer connected to the image forming apparatus 10 at a resolution instructed by the CPU 400, and performs print output. Generate image data for In the present embodiment, the image data generation unit 401 performs dithering processing at a resolution of 2400 dpi, which is the second resolution. That is, the image data generated by the image data generation unit 401 is pixel data equivalent to 2400 dpi.
  • the pixel data corresponding to 2400 dpi in this embodiment is one bit, but one pixel may be represented by a plurality of bits.
  • the pixel data generated by the image data generation unit 401 is line data corresponding to a line corresponding to 2400 dpi in the sub-scanning direction. Note that the image data generation unit 401 is one integrated circuit 401A.
  • the CPU 400 determines the main scanning direction (the longitudinal direction of the exposure head 106) and the sub-scanning direction (the rotation direction of the photosensitive drum 102 and the recording paper conveyance direction) based on the color misregistration amount detected by the optical sensor 113. Are determined in units of 2400 dpi.
  • the image shift amount is determined by the CPU 400 based on, for example, a relative color shift amount between colors calculated based on a detection result of the color shift detection pattern image by the optical sensor 113. Then, the CPU 400 instructs the line data shift unit 402, which is a correction unit, on the image shift amount.
  • the line data shift unit 402 shifts the image data input from the image data generation unit 401 in units of 2400 dpi over the entire image area within one page of the recording paper based on the image shift amount specified by the CPU 400. .
  • the line data shift unit 402 may divide the image area in one page of the recording paper into a plurality of areas, and execute the shift process for each of the plurality of divided image areas.
  • a synchronization signal generation unit 406 which is a second generation unit, is a signal synchronized with the rotation speed of the photosensitive drum 102, and is a periodic signal (hereinafter, Line) corresponding to one line of the resolution of an output image in the rotation direction of the photosensitive drum 102. Synchronization signal).
  • the CPU 400 instructs the synchronization signal generation unit 406 to set the pixel size (approximately 10 pixels) of the surface of the photosensitive drum 102 in the rotation direction (sub-scanning direction) to the cycle of the Line synchronization signal, that is, the predetermined rotation speed of the photosensitive drum 102. .5 ⁇ m) Indicate the time to move.
  • the CPU 400 when printing at a speed of 200 mm / sec in the sub-scanning direction, the CPU 400 sets the cycle of the Line synchronization signal (the cycle of one line in the sub-scanning direction) to about 52.9 ⁇ s ( ⁇ (25.4 mm / 2400 dots). ) / 200 mm) to the synchronization signal generation unit 406.
  • the image forming apparatus 10 includes a detection unit (for example, an encoder installed on the rotation shaft of the photosensitive drum) that detects the rotation speed of the photosensitive drum 102
  • the CPU 400 determines a result of the detection unit (a signal output from the encoder).
  • the rotation speed of the photosensitive drum 102 in the sub-scanning direction is calculated based on the generation cycle, and the cycle of the Line synchronization signal is determined based on the calculation result.
  • the CPU 400 inputs information on the paper type such as the sheet basis weight (g / m 2 ) and the sheet size input by the user from the operation unit. , The cycle of the Line synchronization signal is determined.
  • the clock generation unit 422 serving as the first generation unit transmits the data to the data transmission unit 405 based on a correction value for correcting the magnification in the sub-scanning direction stored in the ROM 421 (hereinafter, referred to as a sub-scanning magnification correction value).
  • the cycle (frequency) of the clock signal to be generated is determined before the start of image formation.
  • FIG. 5 shows the relationship between the clock signal generated based on the sub-scanning magnification correction value and the Line synchronization signal.
  • FIG. 5 shows a waveform of a clock signal, a line synchronization signal generated based on the clock signal, and image data (D0, D1,..., Etc.), and the horizontal axis shows time.
  • FIG. 5A shows the case where the magnification correction in the sub-scanning direction is not performed
  • FIG. 5B shows the case where the magnification in the sub-scanning direction is enlarged
  • FIG. 5C shows the case where the magnification in the sub-scanning direction is reduced.
  • Tn_clk the clock cycle dclk
  • Tm_clk the clock cycle dclk
  • the clock cycle dclk (Tr_clk), which is the second cycle when reducing the magnification in the sub-scanning direction, becomes shorter.
  • One pulse output (for example, D0) of the clock cycle dclk corresponds to one block (“0” or “1”) of PWM data.
  • the chip data conversion unit 403 reads line data from the line data shift unit 402 one line at a time in the sub-scanning direction of the photosensitive drum 102 in synchronization with the Line synchronization signal. Then, the chip data conversion unit 403 executes data processing for dividing the read line data into line data for each chip.
  • FIG. 6A is a block diagram showing a configuration of the chip data conversion unit 403. 6A, the Line synchronization signal output from the synchronization signal generation unit 406 is input to the counter 530.
  • the counter 530 includes a frequency modulation circuit that modulates the input Line synchronization signal to generate a CLK signal having a higher frequency than the Line synchronization signal.
  • the counter 530 may include an oscillator that generates a clock signal (CLK) having a higher frequency than the Line synchronization signal instead of the frequency modulation circuit.
  • CLK clock signal
  • a configuration in which the chip data conversion unit 403 reads line data from the line data shift unit 402 will be described as an example, but the embodiment is not limited thereto. That is, the Line data shift unit 402 supplies the Line synchronization signal to the line data shift unit 402 and internally generates the CLK signal, so that the line data shift unit 402 It may be configured to transmit line data.
  • the counter 530 When the Line synchronization signal is input, the counter 530 resets the count value to 0, and then increments the counter value in synchronization with the number of pulses of the clock signal (CLK) (see FIG. 6B).
  • the frequency of the CLK signal generated by the counter 530 includes the capacity (the number of bits) of pixel data that the chip data conversion unit 403 should read within one cycle of the Line synchronization signal, the data processing speed of the chip data conversion unit 403 described later, Is determined at the design stage based on For example, as described above, the surface light emitting element array element group 201 has 14,964 light emitting elements (1200 dpi conversion) that expose one line in the sub-scanning direction.
  • the chip data conversion unit 403 reads out one line of image data in the sub-scanning direction and writes it to a line memory 500 described later, and writes image data to memories 501 to 529 described later during the Line synchronization signal. . Therefore, the counter 530 performs a count operation of twice (59, 856) the number of pixels (29, 928) included in one line of line data. A period in which the count value of the counter 530 is from 1 to 29,928 is Tm1, and a period in which the count value is from 29,929 to 59,856 is Tm2 (see FIG. 6B).
  • the READ control unit 531 reads line data from the line data shift unit 402 according to the count value of the counter 530. That is, the READ control unit 531 stores the line data (29,928 pixels) for one line in the main scanning direction in the line memory 500 during the period Tm1 in which the count value of the counter 530 is 1 to 29,928.
  • the WR control unit 532 divides the line data for one line in the sub-scanning direction stored in the line memory 500 into the memories 501 to 529 during the period Tm2 in which the count value of the counter 530 is 29,929 to 59,856. Write.
  • the memories 501 to 529 are memories having a smaller storage capacity than the line memory 500, and store line data (divided line data) divided for each chip.
  • the memories 501 to 529 are FIFO (First In First First Out) memories provided corresponding to the surface light emitting element array chips 1 to 29. That is, the memory 501 stores line data corresponding to the surface light emitting element array chip 1, the memory 502 stores line data corresponding to the surface light emitting element array chip 2,. Is stored.
  • FIFO First In First First Out
  • FIG. 6B is a time chart illustrating the input / output timing of the line data in the chip data conversion unit 403.
  • a Line synchronization signal indicates a pulse signal output from the synchronization signal generation unit 406.
  • TL1, TL2,... TL10 indicate the cycle numbers of one line in the sub-scanning direction.
  • One cycle of the Line synchronization signal is divided into a period Tm1 and a period Tm2 according to the counter value of the counter 530.
  • the input data to the line memory 500 indicates image data from the line data shift unit 402, and is input from the line data shift unit 402 during a period Tm1 of the periods TL1, TL2,.
  • the first line data in FIG. 5B indicates line data of the first line in the sub-scanning direction (for one line in the main scanning direction).
  • the second line data,..., The tenth line data are the line data of the second line in the sub-scanning direction,. Minute).
  • the “input data to the memory 501” shown in FIG. 5B is the line data corresponding to the surface emitting element array chip 1 among the line data for one line in the main scanning direction stored in the line memory 500. Indicates the timing at which is written to the memory 501.
  • the input data to the memory 502, the input data to the memory 503,..., The input data to the memory 529 are line data corresponding to the surface light emitting element array chips 2, 3,. , 503,... 529 are shown. Note that the first line data of the input data to the memory 501 is not line data of one line in the main scanning direction, but line data (divided line data) in the main scanning direction corresponding to the surface emitting element array chip 1. The same applies to the input data of the memories 502 to 529.
  • the “output data from the memory 501” shown in FIG. 5B indicates the timing at which the line data written in the memory 501 is read out to be output to the surface emitting element array chip 1.
  • “output data from the memory 502”,..., “Output data from the memory 529” shown in FIG. 5B correspond to the surface light emitting element array chip 2,.
  • the timing for reading to output the data is shown in FIG. Note that the first line data of the output data from the memory 501 is not line data of one line in the main scanning direction but line data (divided line data) in the main scanning direction corresponding to the surface emitting element array chip 1. The same applies to output data from the memories 502 to 529.
  • line data for one line in the main scanning direction is sequentially read from the line memory 500, and first, writing to the memory 501 for storing the line data of the surface emitting element array chip 1 is performed. Next, writing to the memory 502 for storing the image data of the surface light emitting element array chip 2 is performed, and thereafter, writing to the memory 529 for storing the image data of the surface light emitting element array chip 29 is sequentially performed. .
  • the chip data shift unit 404 at the subsequent stage of the chip data conversion unit 403 data shift processing in the sub-scanning direction is performed for each surface light emitting element array chip. Therefore, it is assumed that the memories 501 to 529 store line data for 10 lines in the sub-scanning direction.
  • the line data stored in the memories 501 to 529 includes the line data for one chip corresponding to each surface light emitting element array chip and the pixel data obtained by copying the pixel data at the end of the adjacent surface light emitting element array chip. Data is also stored together.
  • the following pixel data is stored in the memory 502. That is, in the memory 502, at both ends of the line data corresponding to the surface light emitting element array chip 2, the pixel data of the end part on the surface light emitting element array chip 2 side of the surface light emitting element array chip 1 and the surface light emitting element array The pixel data at the end of the chip 3 on the surface light emitting element array chip 2 side is added and stored.
  • FIG. 7 is a diagram illustrating the relationship between line data stored in the line memory 500 and image data stored in the memories 501 to 529.
  • FIG. 7A is a diagram showing line data for each surface light emitting element array chip stored in the line memory 500, and shows an image of the arrangement of the line data before the arrangement is changed in the memories 501 to 529. I have.
  • the line memory 500 includes line data of the surface emitting element array chip (N-1) (hatched display), line data of the surface emitting element array chip N (open display), and line data of the surface emitting element array chip (N + 1). (Hatched display) is stored.
  • FIG. 7B shows an image of line data of a memory corresponding to the surface emitting element array chip N.
  • the memories 502 to 528 corresponding to the surface emitting element array chips store the line data of the corresponding surface emitting element array chip with the pixel data of the end of the adjacent surface emitting element array chip added. Is done.
  • the leftmost pixel data is assigned to the surface emitting element array chip N included in the line data of the surface emitting element array chip (N-1). This is the pixel data of the adjacent end (see the arrow in the figure).
  • the rightmost pixel data is assigned to the surface emitting element array chip N of the line data of the surface emitting element array chip (N + 1). This is the pixel data of the adjacent end (see the arrow in the figure).
  • the end of the line data corresponding to the surface light emitting element array chip 1 is added with pixel data of the end of the surface light emitting element array chip 2 on the side of the surface light emitting element array chip 1 and stored.
  • pixel data at the end of the surface light emitting element array chip 28 on the side of the surface light emitting element array chip 29 is added to the end of the line data corresponding to the surface light emitting element array chip 29 and stored.
  • the pixel data at the end of the adjacent surface emitting element array chip is added to both ends of the line data of the corresponding surface emitting element array chip for each of the surface emitting element array chips. 529.
  • the line data for one line in the main scanning direction is stored in the memories 501 to 529 provided corresponding to the surface light emitting element array chips 1 to 29 and the adjacent surface light emitting element array. It is stored together with the pixel data at the end of the chip.
  • the pixel data at the end of the adjacent surface light emitting element array chip is used in a filter processing unit 408 described later.
  • the chip data shift unit 404 which is a correction unit, converts line data from the memories 501 to 529 based on data (2400 dpi units) relating to the image shift amount in the sub-scanning direction for each surface light emitting element array chip specified in advance by the CPU 400. Control relative read timing.
  • the image shift processing in the sub-scanning direction performed by the chip data shift unit 404 will be specifically described.
  • each even-numbered surface light emitting element array chip in the longitudinal direction of the exposure head.
  • the mounting positions of the odd-numbered surface emitting element array chips do not shift.
  • the mounting positional relationship between the even-numbered surface light-emitting element array chips and the odd-numbered surface light-emitting element array chips in the sub-scanning direction is equivalent to 2400 dpi and is a predetermined number of pixels (for example, 8 pixels). preferable.
  • the arrangement positions of the light emitting element rows in the sub-scanning direction in each surface light emitting element array chip are constant without any individual difference.
  • these mounting positions and the arrangement positions of the light emitting element rows include errors, and these errors may cause deterioration in the image quality of the output image.
  • the memory 430 (ROM) shown in FIG. 4 has a correction calculated from the relative positional relationship in the sub-scanning direction of each light emitting element array of the surface light emitting element array chips 1 to 29 mounted in a staggered manner on the drive substrate 202. Data is stored. For example, in the memory 430, each light emitting element array of the other surface light emitting element array chips 2 to 29 is arranged in the sub scanning direction with respect to the light emitting element array of the surface light emitting element array chip 1 which is a reference of the position in the sub scanning direction. Correction data based on measurement data of how many pixels are shifted on the drive substrate 202 corresponding to 2400 dpi is stored.
  • the measurement data is obtained by mounting the surface light emitting element array chips 2 to 29 on the drive substrate 202, turning on the light emitting elements of each surface light emitting element array chip with a measuring device, and measuring the light receiving result.
  • CPU 400 sets the correction data read from memory 430 in the internal register of chip data shift unit 404 in response to the power on of image forming apparatus 10 being turned on.
  • the chip data shift unit 404 shifts line data for forming the same line stored in the memories 501 to 529 based on the correction data set in the internal register.
  • the unit 404 delays the output timing of the line data corresponding to the surface light emitting element array chip 2 forming the same line by eight pixels with respect to the output timing of the line data corresponding to the surface light emitting element array chip 1 to the drive substrate 202. All the line data corresponding to the surface light emitting element array chip 2 is shifted with respect to the line data corresponding to the surface light emitting element array chip 1.
  • the data transmission unit 405 transmits, to the drive substrate 202, the line data after performing the data processing on the series of line data described above with respect to the exposure head 106.
  • the transmission timing of the image data will be described with reference to FIG. 6B described above.
  • the odd numbered surface light emitting element array chips 1, 3, 5,... 29 are arranged on the upstream side in the sub-scanning direction, and the even numbered surface light emitting elements
  • the element array chips 2, 4, 6, ... 28 are arranged on the downstream side in the sub-scanning direction.
  • writing of image data to the memories 501 and 529 corresponding to the odd-numbered surface light emitting element array chips 1 and 29 is performed during the period of the first Line synchronization signal (TL1 and TL10 in the figure).
  • the period of the next Line synchronization signal (TL2 in the figure) data of the first line in the sub-scanning direction is read out from the memories 501 and 529 corresponding to the odd-numbered surface emitting element array chips 1 and 29. Be done.
  • data of the second line in the sub-scanning direction is read from the memories 501 and 529 corresponding to the odd-numbered surface emitting element array chips 1 and 29.
  • the data of the ninth line in the sub-scanning direction is read from the memories 501 and 529 corresponding to the odd-numbered surface emitting element array chips 1 and 29. Done.
  • the memory 502 corresponding to the even-numbered surface light emitting element array chip 2 has a period (TL10 in the figure) after nine pulses of the Line synchronization signal 424 from the period TL1 in which image data is written to the memory 502. Then, reading of image data from the memory 502 is performed.
  • the data transmission unit 405 transmits the line data processed by the chip data shift unit 404 to the drive substrate 202.
  • the counter 530 includes, instead of an oscillator, a frequency modulation circuit that modulates an input Line synchronization signal to generate a CLK signal having a higher frequency than the Line synchronization signal.
  • the counter 530 may include an oscillator that generates a clock signal (CLK) having a higher frequency than the Line synchronization signal instead of the frequency modulation circuit.
  • the frequency of the clock signal (CLK in FIG. 6B) is determined so that the count value is 59,856 (two times the number of pixel data in one line) or more within one cycle of the Line synchronization signal. ing.
  • image data can be input (written) to the line memory 500 and image data can be output (written) from the line memory 500 to the memories 501 to 529 within one cycle of the line synchronization signal.
  • reading of data from the memories 501 to 529 is performed within one period of the line synchronizing signal, by the image of one line in the main scanning direction corresponding to each surface light emitting element array chip from the 29 memories 501 to 529. Output data in parallel. Therefore, the reading speed of the image data from the memories 501 to 529 may be lower than the writing speed to the memory. For example, in the present embodiment, it is assumed that image data is read from the memories 501 to 529 at a long cycle that is 58 times longer than the number of pulses at the time of writing image data to the memories 501 to 529.
  • the line data shift unit 402, the chip data conversion unit 403, the chip data shift unit 404, the data transmission unit 405, and the synchronization signal generation unit 406 are an integrated circuit 402A different from the integrated circuit 401A.
  • the CPU 400 is an integrated circuit different from the integrated circuits 401A and 402A.
  • the data receiving unit 407 receives the data transmitted from the data transmitting unit 405 of the control board 415, and separates the clock signal 420, the line synchronization signal 424, and the image data 423, respectively.
  • the data receiving unit 407 and the data transmitting unit 405 may use generally known parallel-serial conversion.
  • the clock signal 420, the Line synchronization signal 424, and the image data 423 are transmitted to the drive unit 303a by parallel-serial conversion, but may be transmitted in parallel.
  • the driving unit 303a operates based on the clock signal received by the data receiving unit 407. This is because it is possible to eliminate the need for a clock oscillator or a crystal oscillator in the driving unit 303a.
  • the data receiving unit 407 and the data transmitting unit 405 transmit and receive image data in line units in the sub-scanning direction in synchronization with the Line synchronization signal.
  • the chip data conversion unit 403 arranges data for each of the surface emitting element array chips 1 to 29, and the subsequent processing blocks process the data of the surface emitting element array chips 1 to 29 in parallel.
  • the filter processing unit 408 which is a conversion unit, performs interpolation processing by filter processing in the main scanning direction on image data for each of the surface light emitting element array chips 1 to 29, and converts resolution in the main scanning direction from 2400 dpi to 1200 dpi. .
  • the chip data conversion unit 403 of the control board 415 adds the pixel data on the end side of the adjacent surface light emitting element array chip and arranges the image data so that the image is not lost. Filter processing can be performed (see FIG. 7).
  • the subsequent LUT 410 performs data conversion of the image data value (density data value) for each pixel corresponding to the light emitting element in the surface light emitting element array chip with reference to a look-up table (Look Up Table).
  • the LUT 410 converts the data value of each pixel based on the response characteristic of the light emitting time of the surface light emitting element array chip so that the integrated light amount when the pulse light is emitted becomes a predetermined value. For example, when the response of the light emitting time of the surface light emitting element array chip is slow and the integrated light amount is smaller than the target value, data conversion is performed so that the data value increases.
  • the CPU 400 sets the value of the conversion table set in the lookup table to a predetermined value based on the response characteristics of the light emitting element array obtained experimentally before starting the image formation. Shall be.
  • FIGS. 17A, 17B and 17C are diagrams showing examples of the look-up table.
  • the LUT 410 converts pixel data equivalent to 1200 dpi into a PWM signal using any of the look-up tables in FIGS. 17A, 17B, and 17C.
  • 17A, 17B and 17C are tables for converting pixel data corresponding to 1200 dpi into 8-bit PWM data.
  • “000,001,010,011,100” is pixel data corresponding to 1200 dpi indicating “density 0%, density 25%, density 50%, density 75%, density 100%”, respectively.
  • “1” of the PWM data is LED ON data (light emission data), and “0” indicates OFF data (non-light emission data).
  • PWM data corresponds to ⁇ W1 to ⁇ W4.
  • the PWM signal generation unit 411 generates a pulse width signal (hereinafter, referred to as a PWM signal) corresponding to a light emission time during which the surface light emitting element array chip emits light within one pixel section according to the data value of each pixel.
  • the timing of outputting the PWM signal is controlled by the timing control unit 412.
  • the timing control unit 412 generates a synchronization signal corresponding to the pixel section of each pixel from the Line synchronization signal generated by the synchronization signal generation unit 406 of the control board 415, and outputs the synchronization signal to the PWM signal generation unit 411.
  • the drive voltage generator 414 generates a drive voltage for driving the surface light emitting element array chip in synchronization with the PWM signal.
  • the drive voltage generation unit 414 has a configuration in which the CPU 400 can adjust the voltage level of the output signal around 5 V so that a predetermined light amount is obtained.
  • each surface light emitting element array chip has a configuration in which four light emitting elements can be simultaneously driven independently.
  • Drive signals supplied to each surface light emitting element array chip are ⁇ W1 to ⁇ W4 (see FIG. 8).
  • the surface light emitting element array chips are sequentially driven by the operation of a shift thyristor (see FIG. 8) described later.
  • the control signal generator 413 generates control signals ⁇ s, ⁇ 1, and ⁇ 2 for transferring the shift thyristor for each pixel from the synchronization signal corresponding to the pixel section generated by the timing controller 412 (see FIG. 8).
  • FIG. 8 is an equivalent circuit extracted from a part of a self-scanning light emitting element (Self-Scanning LED: SLED) array chip of the present embodiment.
  • Ra and Rg are an anode resistance and a gate resistance, respectively
  • Tn is a shift thyristor
  • Dn is a transfer diode
  • Ln is a light emitting thyristor.
  • Gn represents the corresponding shift thyristor Tn and the common gate of the light emitting thyristor Ln connected to the shift thyristor Tn.
  • n is an integer of 2 or more.
  • ⁇ 1 is a transfer line of the odd-numbered shift thyristor T
  • ⁇ 2 is a transfer line of the even-numbered shift thyristor T
  • ⁇ W1 to ⁇ W4 are lighting signal lines of the light emitting thyristor L, and are connected to the resistors RW1 to RW4, respectively.
  • VGK is a gate line
  • ⁇ s is a start pulse line.
  • four light-emitting thyristors L4n-3 to L4n are connected to one shift thyristor Tn, and four light-emitting thyristors L4n-3 to L4n can be turned on at the same time. It has become.
  • the common gate Gn of the light emitting thyristor Ln and the common gate Gn + 1 of the light emitting thyristor Ln + 1 are connected by the coupling diode Dn, a potential difference substantially equal to the diffusion potential of the coupling diode Dn occurs.
  • the diffusion potential of the coupling diode Dn is about 1.5 V
  • the potential after the common gate Gn + 4 of the light emitting thyristor Ln + 4 is 5 V since the voltage of the gate line VGK is 5 V and does not become higher than this.
  • the potential of the common gate Gn-1 before the common gate Gn of the light emitting thyristor Ln since the coupling diode Dn-1 is in the reverse bias state, the gate line The voltage of VGK is applied as it is, and becomes 5V.
  • FIG. 9A is a diagram showing the distribution of the gate potential of the common gate Gn of each light emitting thyristor Ln when the above-mentioned shift thyristor Tn is in the ON state.
  • the vertical axis in FIG. 9A indicates the gate potential.
  • the voltage required to turn on each shift thyristor Tn (hereinafter referred to as a threshold voltage) is obtained by adding a diffusion potential (1.5 V) to the gate potential of the common gate Gn of each light emitting thyristor Ln; The potentials are almost the same.
  • the shift thyristor Tn + 2 When the shift thyristor Tn is on, the shift thyristor Tn + 2 has the lowest gate potential of the common gate among the shift thyristors connected to the transfer line ⁇ 2 of the same shift thyristor Tn.
  • the shift thyristor Tn since the shift thyristor Tn is on, the potential of the transfer line ⁇ 2 is pulled to about 1.5 V (diffusion potential), and is lower than the threshold voltage of the shift thyristor Tn + 2, so that the shift thyristor Tn + 2 is on. Can not do it.
  • the other shift thyristors connected to the same transfer line ⁇ 2 cannot be turned on similarly because the threshold voltage is higher than the shift thyristor Tn + 2, and only the shift thyristor Tn can be kept on.
  • shift thyristor Tn and shift thyristor Tn + 1 are simultaneously turned on.
  • FIG. 9B is a diagram showing the gate voltage distribution of each of the common gates Gn-1 to Gn + 4 at this time, and the vertical axis indicates the gate potential.
  • FIG. 9C is a diagram showing the gate voltage distribution at this time, and the vertical axis shows the gate potential.
  • the potential of the common gate Gn + 1 of the shift thyristor Tn + 1 adjacent to the shift thyristor Tn is 1.7 V
  • the threshold voltages of the light emitting thyristors L4n-3 to L4n are lower, when a lighting signal is input from the lighting signal lines ⁇ W1 to ⁇ W4, the light emitting thyristors L4n + 1 to L4n + 4 are turned on earlier. Once the light emitting thyristors L4n-3 to L4n are turned on, the connected lighting signal lines ⁇ W1 to ⁇ W4 are lowered to about 1.5V (diffusion potential).
  • the potentials of the lighting signal lines ⁇ W1 to ⁇ W4 become lower than the threshold voltages of the light emitting thyristors L4n + 1 to L4n + 4, so that the light emitting thyristors L4n + 1 to L4n + 4 cannot be turned on.
  • a plurality of light emitting thyristors L can be simultaneously turned on.
  • FIG. 10 is a timing chart of the driving signals of the SLED circuit shown in FIG.
  • the voltage waveforms of the driving signals of the gate line VGK, the start pulse line ⁇ s, the transfer lines ⁇ 1 and ⁇ 2 of the odd-numbered and even-numbered thyristors, and the lighting signal lines ⁇ W1 to ⁇ W4 of the light-emitting thyristor are shown in order from the top.
  • Each drive signal has an on-state voltage of 5 V and an off-state voltage of 0 V.
  • the horizontal axis in FIG. 10 indicates time.
  • 5 V is always supplied to the gate line VGK.
  • a clock signal ⁇ 1 for the odd-numbered shift thyristor and a clock signal ⁇ 2 for the even-numbered shift thyristor are input at the same cycle Tc, and 5 V is supplied to the signal ⁇ s of the start pulse line.
  • the signal ⁇ s of the start pulse line is dropped to 0V in order to give a potential difference to the gate line VGK.
  • the gate potential of the first shift thyristor Tn-1 is pulled down from 5 V to 1.7 V, the threshold voltage becomes 3.2 V, and the shift thyristor Tn-1 is turned on by a signal from the transfer line ⁇ 1.
  • 5 V is applied to the transfer line ⁇ 1 and 5 V is supplied to the start pulse line ⁇ s a little after the first shift thyristor Tn-1 transitions to the ON state, and thereafter 5 V is supplied to the start pulse line ⁇ s. to continue.
  • the transfer line ⁇ 1 and the transfer line ⁇ 2 have a time Tov in which their ON states (here, 5V) overlap, and are configured to have a substantially complementary relationship.
  • the light-emitting thyristor lighting signal lines ⁇ W1 to ⁇ W4 are transmitted at a half cycle of the transfer lines ⁇ 1 and ⁇ 2.
  • the corresponding shift thyristor is in the ON state, it is lit when 5V is applied.
  • a period a all four light-emitting thyristors connected to the same shift thyristor are in a lighting state, and in a period b, three light-emitting thyristors are simultaneously turned on.
  • the number of light-emitting thyristors connected to one shift thyristor is four.
  • the number is not limited to four and may be smaller or larger than four depending on the application.
  • a circuit in which the cathode of each thyristor is common has been described.
  • an anode common circuit can be applied by appropriately inverting the polarity.
  • FIG. 11A and FIG. 11B are schematic diagrams of the surface-emitting thyristor unit of the present embodiment.
  • FIG. 11A is a plan view (schematic diagram) of a light emitting element array in which a plurality of light emitting elements formed in a mesa (trapezoidal) structure 922 are arranged.
  • FIG. 11B is a schematic cross-sectional view when the light emitting element formed in the mesa structure 922 is cut along the line XIB-XIB shown in FIG. 11A.
  • the mesa structures 922 on which the light emitting elements are formed are arranged at a predetermined pitch (interval between the light emitting elements) (for example, about 21.16 ⁇ m in the case of a resolution of 1200 dpi). 924 separate from each other.
  • reference numeral 900 denotes a first conductivity type compound semiconductor substrate
  • 902 denotes a buffer layer of the same first conductivity type as the substrate 900
  • 904 denotes a distributed Bragg reflection formed by stacking two types of semiconductor layers of the first conductivity type. (DBR) layer.
  • 906 is a first first conductivity type semiconductor layer
  • 908 is a first second conductivity type semiconductor layer different from the first conductivity type
  • 910 is a second first conductivity type semiconductor layer
  • 912 is a second first conductivity type semiconductor layer. It is a second conductivity type semiconductor layer. As shown in FIG.
  • a pnpn-type (or npnp-type) thyristor structure is formed by alternately stacking semiconductors having different conductivity types of the semiconductor layers 906, 908, 910, and 912.
  • an n-type GaAs substrate is used for the substrate 900
  • n-type GaAs or n-type AlGaAs layer is used for the buffer layer 902
  • n-type AlGaAs having a high Al composition and a low Al composition are used for the DBR layer 904.
  • a stacked structure of AlGaAs is used.
  • the first first conductivity type semiconductor layer 906 on the DBR layer is n-type AlGaAs
  • the first second conductivity type semiconductor layer 908 is p-type AlGaAs
  • the second first conductivity type semiconductor layer 910 is n-type AlGaAs.
  • the p-type AlGaAs is used for the type AlGaAs and the second second conductivity type semiconductor layer 912.
  • a p-type GaP layer 914 is formed on a p-type AlGaAs which is a second second conductivity type semiconductor layer 912, and an n-type transparent conductor is further formed thereon. Is formed.
  • the p-type GaP layer 914 is formed to have a sufficiently high impurity concentration in a portion in contact with the transparent conductor ITO layer 918.
  • the p-type GaP layer 914 When a forward bias is applied to the light-emitting thyristor (for example, when the back electrode 926 is grounded and a positive voltage is applied to the front electrode 920), the p-type GaP layer 914 is formed in a portion in contact with the transparent conductor ITO layer 918. Since the impurity concentration is sufficiently high, a tunnel junction is formed. As a result, current flows. With such a structure, the p-type GaP layer 914 concentrates a current at a portion in contact with the n-type transparent conductor ITO layer 918, thereby forming a current confinement mechanism. In this embodiment, an interlayer insulating layer 916 is provided between the ITO layer 918 and the p-type AlGaAs layer 912.
  • the attached diode formed by the n-type ITO layer 918 and the p-type AlGaAs layer 912 is reverse-biased with respect to the forward bias of the light emitting thyristor. No current flows through Therefore, if the attached diode formed of the n-type ITO layer 918 and the p-type AlGaAs layer 912 is sufficient for applications requiring a reverse breakdown voltage, it can be omitted.
  • the lower part of the semiconductor lamination portion substantially equivalent to the portion where the p-type GaP layer 914 and the n-type transparent conductor ITO layer 918 are in contact emits light, and the DBR layer 904 causes most of the light emission to occur on the substrate. It is reflected on the side opposite to 900.
  • the density of light emitting points is determined according to the resolution.
  • Each light emitting element in the surface light emitting element array chip is separated into a mesa structure 922 by an element separating groove 924.
  • a distance between element centers of adjacent light emitting elements are arranged to be 21.16 ⁇ m.
  • FIG. 12 is a diagram illustrating a relationship between a Line synchronization signal output from the data receiving unit 407 and image data.
  • FIG. 12A shows a case where magnification correction in the sub-scanning direction is not performed
  • FIG. 12B shows a case where magnification in the sub-scanning direction is enlarged
  • FIG. The case where the magnification is reduced is shown.
  • FIG. 12A shows a waveform of the Line synchronization signal and image data.
  • the horizontal axis indicates time.
  • the cycle Tn of the Line synchronization signal when no correction is performed is Tn_clk ⁇ 15000
  • the cycle Tm of the Line synchronization signal when the magnification is enlarged is Tm_clk ⁇ 15000
  • the cycle Tr of the Line synchronization signal when the magnification is reduced is Tr_clk ⁇ 15000.
  • the clock frequency output from the data receiving unit 407 differs between (a), (b), and (c) in FIG.
  • the clock cycle is Tn_clk in (a), Tm_clk in (b), and Tr_clk in (c) (Tm_clk> Tn_clk> Tr_clk).
  • the number of pulses between Line synchronization signals is the same (15000). In the first embodiment, the number of clocks required for one line is 15,000 pulses.
  • the clock frequency is low (the clock cycle is long), so that the cycle of the Line synchronization signal is longer than that in the case where the magnification correction is not performed in the sub-scanning direction.
  • the clock frequency becomes higher (clock period becomes shorter), so that the period of the Line synchronization signal is shorter than that in the case where magnification correction is not performed in the sub-scanning direction.
  • the line interval formed on the photosensitive drum 102 is increased, and the sub-scanning direction of the image data is enlarged as a whole.
  • the line interval formed on the photosensitive drum 102 is reduced, and the overall sub-scanning direction of image data is reduced.
  • the control board 415 as a control unit corrects the cycle of the clock signal and the cycle of the Line synchronization signal to 1 / N times, respectively, when performing the magnification correction in which the magnification in the rotation direction of the photosensitive drum 102 is, for example, N times. .
  • FIG. 13 shows the relationship between dots formed on the photosensitive drum 102 when magnification correction in the sub-scanning direction is not performed and when magnification correction is performed.
  • 13A shows a case where the magnification in the sub-scanning direction is enlarged
  • FIG. 13B shows a case where the magnification correction in the sub-scanning direction is not performed (reference)
  • FIG. 13C shows a magnification in the sub-scanning direction. Shows the case of reducing.
  • FIG. 13 shows the first and second lines in the sub-scanning direction.
  • the line interval formed on the photosensitive drum 102 increases, but the dots formed on the photosensitive drum 102 also increase. For this reason, the density of the image data is maintained at the same density as when no magnification correction is performed in the sub-scanning direction. Also, when the magnification in the sub-scanning direction is reduced, the line interval formed on the photosensitive drum 102 is reduced, but the dots formed on the photosensitive drum 102 are also smaller. For this reason, the density of the image data is maintained at the same density as when no magnification correction is performed in the sub-scanning direction.
  • the magnification of the sub-scanning direction can be corrected by changing the cycle of the clock signal generated by the clock generation unit 422. For this reason, it is possible to suppress the density fluctuation of the image data together with the expansion or contraction of the line interval, and it is possible to provide the image forming apparatus 10 capable of forming a high quality image.
  • the example in which the surface light emitting element array chips are arranged in a staggered manner is described.
  • the same effect can be obtained by performing the same processing.
  • the CPU 400, the integrated circuit 401A, and the integrated circuit 402A may be included in one integrated circuit. Further, the CPU 400 and the integrated circuits 401A and 402A may be different integrated circuits.
  • the magnification in the sub-scanning direction can be accurately corrected.
  • the second embodiment a part different from the first embodiment will be described in detail with reference to FIGS. 14A and 14B.
  • the clock cycle and the light amount of the surface emitting element array chip may not be linear. I do. In that case, it is necessary to adjust the density of the image data by changing the light amount of the surface light emitting element array chip in accordance with the magnification correction.
  • FIG. 14A is a diagram showing the relationship between the clock cycle and the light intensity of the surface emitting element array chip.
  • (a) is a graph when the magnification in the sub-scanning direction is enlarged, and is a graph when the light amount is insufficient.
  • (B) is a graph when the magnification in the sub-scanning direction is reduced, and is a graph when the light amount becomes excessive.
  • (C) shows a graph when the light amount is corrected in the second embodiment, respectively.
  • the horizontal axis indicates the clock cycle [nanosecond (ns)], and the vertical axis indicates the light intensity of the surface emitting element array chip.
  • 14B is a diagram illustrating a light amount according to the second embodiment when magnification correction in the sub-scanning direction is performed.
  • the horizontal axis indicates the light amount
  • the vertical axis indicates the sub-scanning direction.
  • 14B (a) is a graph when the magnification in the sub-scanning direction is enlarged, (b) is a graph when magnification correction in the sub-scanning direction is not performed (reference), and (c) is a graph when the sub-scanning is performed. It is a graph at the time of reducing the magnification of a direction.
  • the line interval formed on the photosensitive drum 102 is increased, so that the dot interval of the first and second lines is increased.
  • the clock cycle (Tm_clk) is long, the clock cycle and the light quantity of the surface emitting element array chip are not linear, so that the light quantity is insufficient ((a) in FIG. 14A).
  • the size of the dots formed on the photosensitive drum 102 is increased.
  • the drive voltage of each light emitting element is increased by a drive voltage generation unit 414, which is a drive unit for increasing the amount of light, from a reference drive voltage when magnification correction is not performed, and is set as a first drive voltage (first drive voltage). 1 drive voltage> reference drive voltage).
  • the line interval formed on the photosensitive drum 102 in the sub-scanning direction is extended, but is formed on the photosensitive drum 102.
  • the size of the dot becomes larger. Further, by performing light quantity correction of each light emitting element, more accurate correction can be performed.
  • the drive voltage generation unit 414 lowers the drive voltage of each light emitting element from the reference drive voltage when magnification correction is not performed, and sets the drive voltage as the second drive voltage. Good (second drive voltage ⁇ reference drive voltage).
  • the drive voltage of each light emitting element is reduced by the drive voltage generation unit 414 in order to reduce the size of the dots formed on the photosensitive drum 102 and further reduce the amount of light.
  • the drive voltage of each light emitting element may be increased by the drive voltage generation unit 414.
  • the light amount correction data of the surface emitting element array chip corresponding to the magnification adjustment data in the sub-scanning direction in the second embodiment is stored in the ROM 421 in advance, and the CPU 400 reads the light amount correction data from the ROM 421.
  • the CPU 400 sets the light quantity correction data of the surface light emitting element array chip read from the ROM 421 in the drive voltage generation unit 414, and controls the light quantity of the surface light emitting element array chip.
  • the magnification in the sub-scanning direction when the magnification in the sub-scanning direction is enlarged or reduced, the magnification in the sub-scanning direction can be corrected by changing the period of the clock signal generated by the clock generation unit 422. Further, the drive voltage generator 414 changes the drive voltage of each light emitting element to change the amount of light, thereby changing the dot size formed on the photosensitive drum 102. This makes it possible to suppress a change in the density of the image data. As a result, it is possible to provide the image forming apparatus 10 capable of forming a high-quality image. As described above, according to the second embodiment, it is possible to accurately correct the magnification in the sub-scanning direction.
  • the filter processing unit 408 may be provided between the chip data shift unit 404 and the data transmission unit 405.
  • the filter processing unit 408 may be provided between the line data shift unit 402 and the chip data conversion unit 403.
  • Photosensitive drum 106 Exposure head 201 Surface light emitting element array element group 303 Drive section 415 Control board 422 Clock generation section

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Toxicology (AREA)
  • General Health & Medical Sciences (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Optics & Photonics (AREA)
  • Printers Or Recording Devices Using Electromagnetic And Radiation Means (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Control Or Security For Electrophotography (AREA)
  • Led Devices (AREA)
  • Exposure Or Original Feeding In Electrophotography (AREA)

Abstract

L'invention concerne un dispositif de formation d'image (10) qui est pourvu d'un tableau de commande (415) qui délivre en sortie des données d'image vers une unité de commande (303) de manière synchrone avec un signal d'horloge, d'une unité de génération d'horloge (422) qui génère le signal d'horloge, d'une unité de génération de signal de synchronisation (406) qui génère un signal de synchronisation de ligne pour une ligne correspondant à la résolution, dans une direction de rotation, d'un tambour photosensible (102), et du tableau de commande (415), qui commande la période du signal d'horloge et la période du signal de synchronisation de ligne conformément à un grossissement, dans la direction de rotation du tambour photosensible (102), d'une image devant être délivrée en sortie, ce qui permet ainsi d'ajuster de manière précise le grossissement dans une direction de sous-balayage.
PCT/JP2019/025242 2018-06-27 2019-06-25 Dispositif de formation d'image WO2020004422A1 (fr)

Applications Claiming Priority (2)

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JP2018-121818 2018-06-27
JP2018121818A JP2020001240A (ja) 2018-06-27 2018-06-27 画像形成装置

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WO2020004422A1 true WO2020004422A1 (fr) 2020-01-02

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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001239698A (ja) * 2000-03-01 2001-09-04 Nippon Sheet Glass Co Ltd 自己走査型発光装置
JP2003127462A (ja) * 2001-10-29 2003-05-08 Nippon Sheet Glass Co Ltd 光書込みヘッドの光量補正方法
JP2006159851A (ja) * 2004-12-10 2006-06-22 Konica Minolta Business Technologies Inc 画像形成装置
JP2007130963A (ja) * 2005-11-14 2007-05-31 Seiko Epson Corp 発光装置、駆動回路、駆動方法、電子機器および画像形成装置
US20120314014A1 (en) * 2011-06-10 2012-12-13 Xerox Corporation Led print-head driver with integrated process direction compensation
JP2014008743A (ja) * 2012-07-02 2014-01-20 Ricoh Co Ltd 光書き込み制御装置、画像形成装置及び光書き込み制御方法
JP2015030128A (ja) * 2013-07-31 2015-02-16 株式会社リコー 光書き込み制御装置、画像形成装置及び光書き込み制御方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06286213A (ja) * 1993-03-30 1994-10-11 Olympus Optical Co Ltd 記録装置
JP2003241610A (ja) * 2002-02-14 2003-08-29 Canon Inc 画像形成装置

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001239698A (ja) * 2000-03-01 2001-09-04 Nippon Sheet Glass Co Ltd 自己走査型発光装置
JP2003127462A (ja) * 2001-10-29 2003-05-08 Nippon Sheet Glass Co Ltd 光書込みヘッドの光量補正方法
JP2006159851A (ja) * 2004-12-10 2006-06-22 Konica Minolta Business Technologies Inc 画像形成装置
JP2007130963A (ja) * 2005-11-14 2007-05-31 Seiko Epson Corp 発光装置、駆動回路、駆動方法、電子機器および画像形成装置
US20120314014A1 (en) * 2011-06-10 2012-12-13 Xerox Corporation Led print-head driver with integrated process direction compensation
JP2014008743A (ja) * 2012-07-02 2014-01-20 Ricoh Co Ltd 光書き込み制御装置、画像形成装置及び光書き込み制御方法
JP2015030128A (ja) * 2013-07-31 2015-02-16 株式会社リコー 光書き込み制御装置、画像形成装置及び光書き込み制御方法

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