WO2020000549A1 - 一种阵列基板、显示面板及显示设备 - Google Patents

一种阵列基板、显示面板及显示设备 Download PDF

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Publication number
WO2020000549A1
WO2020000549A1 PCT/CN2018/096923 CN2018096923W WO2020000549A1 WO 2020000549 A1 WO2020000549 A1 WO 2020000549A1 CN 2018096923 W CN2018096923 W CN 2018096923W WO 2020000549 A1 WO2020000549 A1 WO 2020000549A1
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WO
WIPO (PCT)
Prior art keywords
potential
alignment
low
traces
area
Prior art date
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Ceased
Application number
PCT/CN2018/096923
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English (en)
French (fr)
Inventor
任维
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Original Assignee
Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Application filed by Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority to US16/235,458 priority Critical patent/US10824038B2/en
Publication of WO2020000549A1 publication Critical patent/WO2020000549A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/911—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using passive elements as protective elements
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1337—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133388—Constructional arrangements; Manufacturing methods with constructional differences between the display region and the peripheral region
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13452—Conductors connecting driver circuitry and terminals of panels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/13629—Multilayer wirings
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel

Definitions

  • the present application relates to the field of display technology, and in particular, to an array substrate, a display panel, and a display device.
  • HVA High Vertically The aligned
  • liquid crystal display panel of the VA mode When the liquid crystal display panel of the VA mode is aligned by a polymer-stable alignment method, a predetermined curing voltage is required to be applied to the liquid crystal layer, and light is irradiated at the voltage to polymerize and cure the reactive monomer in the liquid crystal layer.
  • a polymer layer is simultaneously formed on the substrates on both sides of the liquid crystal layer, so that the liquid crystal cell generates a certain deflection angle, thereby completing the liquid crystal light alignment process.
  • a light alignment line needs to be formed in advance around the liquid crystal display panel in order to implement an application operation such as curing a predetermined voltage.
  • an application operation such as curing a predetermined voltage.
  • FIG. 1 is a schematic diagram of peripheral alignment routing of an array substrate in the prior art.
  • Each set of alignment pads includes a color film substrate common voltage pad CF-com for inputting the common voltage of the color film substrate, an array substrate common voltage pad A-com for inputting the common voltage of the array substrate, and a clock signal.
  • a common voltage pad Vss for inputting a common terminal voltage
  • a data signal voltage pad R, G, B for inputting a pixel electrode data signal voltage.
  • the alignment wiring area is provided with a first metal layer M1, an insulation layer AS, and a second metal layer M2.
  • Each group of alignment wiring consists of a main wiring (1101, 1201, etc.) and a connecting wire (1202, etc.).
  • the main wiring ( 1101, 1201, etc.) are provided on the first metal layer M1
  • connection lines (1202, etc.) are provided on the second metal layer M2
  • the first metal layer M1 and the second metal layer M2 are separated by the insulating layer AS, and the first metal layer M1
  • the traces with the second metal layer M2 are electrically connected through the through holes of the insulation layer AS.
  • FIG. 2 to FIG. 4 are schematic diagrams of effects of static short circuit in the prior art.
  • the pad CF-com is used to access the high-potential signal (H), and the pad A-com, the clock pads CK1, CK2, CK3, CK4, CK5, CK6 ...
  • CKn and low-frequency clock soldering Disks LC1, LC2, start signal pad ST, common voltage pad Vss, and data signal voltage pads R, G, and B are used to access the low-potential signal (L), and the main line is crossed on the connection line (1202, etc.)
  • the electrostatic signal (ESD) is prone to be generated due to the large difference in the potential signal at the cross-line area A.
  • the generation of static electricity can cause the pad CF-com to short-circuit with other pad signals.
  • the generation and easy to cause the potential of the high signal loaded with CF-com is pulled down, which in turn causes the liquid crystal to fail to feel the voltage difference required for alignment, which in turn causes the liquid crystal alignment to be abnormal.
  • liquid crystal display Liquid Crystal Display (LCD) field
  • GOA Gate Driver On Array
  • the inventor of the present application found that the liquid crystal display (Liquid Crystal Display (LCD) field, using Gate Driver On Array (GOA) technology array substrates have significantly more peripheral signal traces than non-GOA products, and the number of cross-line areas is correspondingly increased.
  • the cross-line area is prone to generate static electricity, and the risk of static electricity will increase. Therefore, it is necessary to improve the product ESD protection.
  • the technical problem mainly solved by this application is to provide an array substrate, a display panel, and a display device, which can reduce the risk of static electricity generated between the alignment wires and improve the electrostatic protection ability of the product.
  • a technical solution adopted in the present application is to provide an array substrate, wherein the array substrate includes a display area and a non-display area, and a plurality of groups of alignment pads are arranged in the non-display area, and each group of alignment The pads are electrically connected to the corresponding alignment traces.
  • the alignment pads are divided into high-potential pads and low-potential pads.
  • the alignment wires corresponding to the high-potential pads are set in the high-potential routing area, and the low-potential pads correspond to
  • the alignment traces are set in the low-potential trace area, and the high-potential trace area and the low-potential trace area are located on both sides of multiple sets of alignment pads; among them, the alignment traces in the high-potential trace area are in multiple sets of alignment pads.
  • the orthographic projections on the disk and the orthographic projections of the alignment traces in the low-potential routing area on multiple sets of alignment pads do not overlap each other; where the number of alignment traces in the high-potential routing area is less than the low-potential routing area
  • the number of internal alignment routing, the high-potential routing area is set on the side away from the display area, and the low-potential routing area is set on the side close to the display area; if the number of alignment lines in the high-potential routing area is greater than low Directional routing in the potential routing area
  • a technical solution adopted in the present application is to provide an array substrate including a display area and a non-display area, and a plurality of groups of alignment pads are arranged in the non-display area, and each group of alignment pads is provided. Corresponding alignment wires are electrically connected respectively.
  • the alignment pads are divided into high-potential pads and low-potential pads.
  • the alignment wires corresponding to the high-potential pads are arranged in the high-potential wiring areas, and the low-potential pads correspond to the
  • the alignment traces are set in the low-potential trace area, and the high-potential trace area and the low-potential trace area are located on both sides of multiple sets of alignment pads, respectively.
  • a display panel including an array substrate, the array substrate including a display area and a non-display area, and a plurality of groups are arranged in the non-display area.
  • Alignment pads, each group of alignment pads are electrically connected to corresponding alignment traces respectively, wherein the alignment pads are divided into high-potential pads and low-potential pads, and the alignment wires corresponding to the high-potential pads are set at high-potential pads
  • the alignment traces corresponding to the low potential pads are disposed in the low potential trace area, and the high potential trace area and the low potential trace area are located on both sides of multiple sets of alignment pads, respectively.
  • a display device where the display device includes a display panel, the display panel includes an array substrate, and the array substrate includes a display area and a non-display area, There are multiple sets of alignment pads in the non-display area. Each group of alignment pads is electrically connected to the corresponding alignment traces. Among them, the alignment pads are divided into high-potential pads and low-potential pads. The alignment traces are set in the high-potential trace area, and the alignment traces corresponding to the low-potential pads are arranged in the low-potential trace area. The high-potential trace area and the low-potential trace area are located on both sides of multiple sets of alignment pads.
  • the beneficial effect of this application is that, unlike the case of the prior art, the array substrate provided by this application partitions the alignment traces according to the potential level, so that the traces with similar potentials are arranged in the same area, which can avoid potential differences.
  • the large cross-line area can prevent the occurrence of static short circuit and improve the electrostatic protection of the product.
  • FIG. 1 is a schematic diagram of an alignment alignment around an array substrate in the prior art
  • FIG. 2 is a schematic view showing the effect of an electrostatic short circuit in the prior art
  • FIG. 3 is a schematic diagram of an effect of an electrostatic short circuit in the prior art
  • FIG. 5 is a schematic structural diagram of a first embodiment of an array substrate of the present application.
  • FIG. 6 is a schematic diagram of alignment routing in a non-display area in FIG. 5;
  • FIG. 7 is a schematic diagram of peripheral alignment routing of the first embodiment of the array substrate of the present application.
  • FIG. 8 is a schematic diagram of peripheral alignment routing of the second embodiment of the array substrate of the present application.
  • FIG. 9 is a schematic structural diagram of a first embodiment of a display panel of the present application.
  • FIG. 10 is a schematic structural diagram of a first embodiment of a display device of the present application.
  • FIG. 5 is a schematic structural diagram of the first embodiment of the array substrate of the present application.
  • FIG. 6 is a schematic diagram of the alignment routing of the non-display area in FIG. 5.
  • the array substrate 50 includes a display area 501 and a non-display area 502.
  • the non-display area 502 is provided with a plurality of sets of alignment pads 503, and the plurality of sets of alignment pads 503 are electrically connected to corresponding positions of the alignment traces.
  • the alignment pad 503 is divided into a high-potential pad 5031 and a low-potential pad 5032.
  • the alignment routing area 504 includes a high-potential routing area 5041 and a low-potential routing area 5042.
  • the high-potential routing area 5041 and the low-potential routing area 5042 are located on both sides of multiple sets of alignment pads 503, respectively.
  • the alignment traces corresponding to the disc 5031 are disposed in the high-potential trace region 5041, and the alignment traces corresponding to the low-potential pad 5032 are disposed in the low-potential trace region 5042.
  • the orthographic projection of the alignment wiring on the alignment pad in the high-potential routing area and the alignment wiring in the low-potential routing area are on the alignment pad.
  • the orthographic projections on each other do not overlap each other. In this way, the crossover zone can be minimized.
  • FIG. 7 is a schematic diagram of peripheral alignment routing of the first embodiment of the array substrate of the present application.
  • the alignment traces include main traces (7101, 7201, etc.) and connection lines (7102, 7202, etc.).
  • the main traces (7101, 7201, etc.) are arranged in the first direction and extend in the second direction.
  • the connection lines (7102, 7202, etc.) are arranged along the second direction and extend to the first direction, the first direction is perpendicular to the second direction; the arrangement direction and extension direction of the main traces in the high-potential routing area and the main traces in the low-potential routing area
  • the alignment direction and extension direction of the traces are opposite.
  • the main traces (7101, 7201, etc.) are arranged in the vertical direction and extend in the horizontal direction, and the connecting lines (7102, 7202, etc.) are arranged in the horizontal direction and extend in the vertical direction.
  • the pad CF-com is used to access the high-potential signal
  • the corresponding alignment routing area is the high-potential routing area
  • the pad A-com the clock pad CK1, CK2, CK3, CK4, CK5, CK6 ... CKn
  • the line area is a low-potential routing area.
  • the main traces (7201, etc.) in the low-potential routing area are arranged upward in a vertical direction and extend to the left in the horizontal direction; while the main traces (7101) in the high-potential routing area are arranged in a vertical direction.
  • the stages are arranged downward and extend to the right in the horizontal direction, the two directions are just opposite.
  • the arrangement direction of the main traces in the high-potential trace area may be opposite to that of the main traces in the low-potential trace area, but the main traces in the high-potential trace area
  • the extension direction of is the same as that of the main trace in the low-potential trace area. That is, the main trace 7101 in FIG. 7 may also extend to the left in the horizontal direction.
  • a partition with a smaller number of alignment lines in the routing area is set on a side far from the display area.
  • the edge film formation guarantee area can be prevented from being affected.
  • the high-potential routing area is set on a side away from the display area, and the low-potential routing area is set on The side near the display area; if the number of alignment lines in the high-potential routing area is greater than the number of alignment lines in the low-potential routing area, set the high-potential routing area to the side near the display area and The line area is disposed on a side remote from the display area.
  • FIG. 8 is a schematic diagram of peripheral alignment routing of the second embodiment of the array substrate of the present application.
  • the pad CF-com, the clock pads CK1, CK2, CK3, CK4, CK5, CK6 ... CKn, the low-frequency clock pads LC1, LC2, the start signal pad ST, and the common voltage pad Vss It is used to access high-potential signals.
  • the corresponding alignment routing area is the high-potential routing area.
  • Pads A-com and data signal voltage pads R, G, and B are used to access low-potential signals.
  • the connected alignment routing area is a low-potential routing area.
  • the number of traces in the high-potential routing area is greater than the number of traces in the low-potential routing area. Therefore, the high-potential routing area is disposed on a side close to the display area. Compared to the situation shown in FIG. 7.
  • the present application further provides a display panel.
  • FIG. 9, is a schematic structural diagram of a first embodiment of a display panel of the present application.
  • the display panel 90 includes an array substrate 901.
  • the array substrate 901 includes a display area and a non-display area.
  • the non-display area is provided with multiple sets of alignment pads, and the multiple sets of alignment pads are respectively corresponding to the alignment traces.
  • the alignment pad is divided into a high potential pad and a low potential pad.
  • the alignment routing area includes a high-potential routing area and a low-potential routing area.
  • the high-potential routing area and the low-potential routing area are respectively located on two sides of multiple sets of alignment pads, and the alignment routing corresponding to the high-potential pads. It is set in the high-potential trace area, and the alignment trace corresponding to the low-potential pad is set in the low-potential trace area.
  • the specific structural features and beneficial effects of the array substrate 901 are the same as those in the foregoing embodiment. For details, refer to the description of the foregoing embodiment, and details are not described herein again.
  • the present application further provides a display device.
  • FIG. 10 is a schematic structural diagram of a first embodiment of a display device of the present application.
  • the display device 100 includes a display panel 1001.
  • the display panel 1001 includes an array substrate.
  • the array substrate includes a display area and a non-display area.
  • the non-display area is provided with a plurality of sets of alignment pads.
  • the corresponding positions of the alignment wires are electrically connected, and the alignment pads are divided into high-potential pads and low-potential pads.
  • the alignment routing area includes a high-potential routing area and a low-potential routing area.
  • the high-potential routing area and the low-potential routing area are respectively located on two sides of multiple sets of alignment pads, and the alignment routing corresponding to the high-potential pads. It is set in the high-potential trace area, and the alignment trace corresponding to the low-potential pad is set in the low-potential trace area.
  • the specific structural features and beneficial effects of the array substrate are the same as those in the foregoing embodiments. For details, refer to the description of the foregoing embodiments, and details are not described herein again.
  • the array substrate provided by the present application partitions the alignment traces according to the potential level, so that the traces with similar potentials are arranged in the same area, which can avoid the occurrence of crossover regions with large potential differences and the occurrence of electrostatic short circuits. To improve the electrostatic protection of the product.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种阵列基板（50）、显示面板及显示设备，阵列基板（50）包括显示区（501）和非显示区（502），非显示区（502）内设置有多组配向焊盘（503），每组配向焊盘（503）分别电连接相对应的配向走线，其中，配向焊盘分为高电位焊盘（5031）和低电位焊盘（5032），高电位焊盘（5031）对应的配向走线设置在高电位走线区（5041），低电位焊盘（5032）对应的配向走线设置在低电位走线区（5042），高电位走线区（5041）和低电位走线区（5042）分别位于多组配向焊盘（503）的两侧。能够降低配向走线间产生静电的风险，提高产品的静电防护能力。

Description

一种阵列基板、显示面板及显示设备
【技术领域】
本申请涉及显示技术领域，特别是涉及一种阵列基板、显示面板及显示设备。
【背景技术】
随着电子技术的发展，电子产品逐渐的轻、薄、短、小化，其内部的电子元器件不断小型化，集成电路的集成度不断提高，这使得单元线路越来越窄，相应的静电耐受能力越来越差，静电敏感度越来越高。而静电已成为电子工业中造成器件失效、产成品合格率低及其早期失效的主要原因，严重影响产品直通率及质量稳定性与可靠性，给制造商的生产成本、声誉造成不良影响。
目前市场上的TFT-LCD显示面板中，垂直配向(Vertically aligned，VA)型液晶显示面板因其具有极高的对比度，在大尺寸显示，如电视等方面具有非常广的应用。而高垂直排列(High Vertically aligned，HVA)模式是VA模式中一个重要的分支。HVA型液晶显示面板工作时是由阵列基板侧的像素电极和彩膜基板侧的公共电极形成的垂直电场来控制液晶层的液晶分子的旋转。
在VA模式的液晶显示面板通过聚合物稳定配向的方式进行配向时，需要对液晶层施于固化预定电压，并在该电压下通过光线照射，使液晶层中的反应性单体聚合并固化，从而在液晶层两侧的基板上同时形成聚合物层，使液晶单元产生一定的偏转角度，从而完成液晶光配向过程。
在液晶光配向中，需要在液晶显示面板的周围预先形成光配向走线，以实现固化预定电压等的施加操作。当配向走线较多时，容易出现跨线，而在跨线处易产生静电释放，使走线损坏，进而影响液晶显示面板的配向。
请参阅图1，图1是现有技术中阵列基板外围配向走线示意图。每组配向焊盘中包括用于输入彩膜基板公共电压的彩膜基板公共电压焊盘CF-com，用于输入阵列基板公共电压的阵列基板公共电压焊盘A-com，用于输入时钟信号的n个时钟焊盘CK1、CK2、CK3、CK4、CK5、CK6……CKn，用于输入低频时钟信号的低频时钟焊盘LC1、LC2，用于输入起始信号的起始信号焊盘ST，用于输入公共端电压的公共电压焊盘Vss，用于输入像素电极数据信号电压的数据信号电压焊盘R、G、B。配向走线区设置有第一金属层M1、绝缘层AS、第二金属层M2，每组配向走线由主走线（1101、1201等）和连接线（1202等）组成，主走线（1101、1201等）设置在第一金属层M1，连接线（1202等）设置在第二金属层M2，第一金属层M1和第二金属层M2由绝缘层AS隔开，第一金属层M1和第二金属层M2的走线通过绝缘层AS的通孔电连接。
请参阅图2-图4，图2-图4是现有技术中发生静电短路的效果示意图。在进行液晶配向时，焊盘CF-com用于接入高电位信号（H），而焊盘A-com、时钟焊盘CK1、CK2、CK3、CK4、CK5、CK6……CKn、低频时钟焊盘LC1、LC2、起始信号焊盘ST、公共电压焊盘Vss、数据信号电压焊盘R、G、B则用于接入低电位信号（L），在连接线（1202等）跨越主走线1101时，由于跨线区域A处的电位信号差异较大，容易产生静电（ESD），如图2所示，静电的产生会导致焊盘CF-com与其他焊盘信号发生短路，短路的产生又容易导致加载CF-com高信号的电位被拉低，进而导致液晶无法感受到配向所需的电压差，既而导致液晶配向异常。如图3所示，易发生静电短路的跨线区域一般有两种，一种是具有高电位的焊盘CF-com的连接线3102与具有低电位的其他焊盘的主走线3201、3301、3401、3501等的跨线区域（图3a所示），另一种是具有高电位的焊盘CF-com的主走线3101与具有低电位的其他焊盘的连接线3202、3302等的跨线区域（图3b所示）。
本申请的发明人在长期的研发过程中，发现在液晶显示（Liquid Crystal Display，LCD）领域，采用阵列基板行驱动(Gate Driver On Array，GOA)技术的阵列基板，其外围信号走线明显多于非GOA产品，跨线区域也相应增多，而跨线区容易产生静电，产生静电的风险也将增大，因此需要提高产品的静电防护能力。
【发明内容】
本申请主要解决的技术问题是提供一种阵列基板、显示面板及显示设备，能够降低配向走线间产生静电的风险，提高产品的静电防护能力。
为解决上述技术问题，本申请采用的一个技术方案是：提供一种阵列基板，其中，所述阵列基板包括显示区和非显示区，非显示区内设置有多组配向焊盘，每组配向焊盘分别电连接相对应的配向走线，配向焊盘分为高电位焊盘和低电位焊盘，高电位焊盘对应的配向走线设置在高电位走线区，低电位焊盘对应的配向走线设置在低电位走线区，高电位走线区和低电位走线区分别位于多组配向焊盘的两侧；其中，高电位走线区内的配向走线在多组配向焊盘上的正投影与低电位走线区内的配向走线在多组配向焊盘上的正投影互不重叠；其中，若高电位走线区内配向走线的数量小于低电位走线区内配向走线的数量，则高电位走线区设置在远离显示区的一侧，低电位走线区设置在靠近显示区的一侧；若高电位走线区内配向走线的数量大于低电位走线区内配向走线的数量，则高电位走线区设置在靠近显示区的一侧，低电位走线区设置在远离显示区的一侧。
为解决上述技术问题，本申请采用的一个技术方案是：提供一种阵列基板，所述阵列基板包括显示区和非显示区，非显示区内设置有多组配向焊盘，每组配向焊盘分别电连接相对应的配向走线，其中，配向焊盘分为高电位焊盘和低电位焊盘，高电位焊盘对应的配向走线设置在高电位走线区，低电位焊盘对应的配向走线设置在低电位走线区，高电位走线区和低电位走线区分别位于多组配向焊盘的两侧。
为解决上述技术问题，本申请采用的另一个技术方案是：提供一种显示面板，所述显示面板包括阵列基板，所述阵列基板包括显示区和非显示区，非显示区内设置有多组配向焊盘，每组配向焊盘分别电连接相对应的配向走线，其中，配向焊盘分为高电位焊盘和低电位焊盘，高电位焊盘对应的配向走线设置在高电位走线区，低电位焊盘对应的配向走线设置在低电位走线区，高电位走线区和低电位走线区分别位于多组配向焊盘的两侧。
为解决上述技术问题，本申请采用的另一个技术方案是：提供一种显示设备，所述显示设备包括显示面板，所述显示面板包括阵列基板，所述阵列基板包括显示区和非显示区，非显示区内设置有多组配向焊盘，每组配向焊盘分别电连接相对应的配向走线，其中，配向焊盘分为高电位焊盘和低电位焊盘，高电位焊盘对应的配向走线设置在高电位走线区，低电位焊盘对应的配向走线设置在低电位走线区，高电位走线区和低电位走线区分别位于多组配向焊盘的两侧。
本申请的有益效果是：区别于现有技术的情况，本申请所提供的阵列基板，通过将配向走线按照电位高低进行分区，使电位相近的走线设置在同一区域，能够避免出现电位差异较大的跨线区，防止产生静电短路现象，提高产品的静电防护能力。
【附图说明】
图1是现有技术中阵列基板外围配向走线示意图；
图2是现有技术中发生静电短路的效果示意图；
图3是现有技术中发生静电短路的效果示意图；
图4是现有技术中发生静电短路的效果示意图；
图5是本申请阵列基板第一实施方式的结构示意图；
图6是是图5中非显示区的配向走线示意图；
图7是本申请阵列基板第一实施方式的外围配向走线示意图；
图8是本申请阵列基板第二实施方式的外围配向走线示意图；
图9是本申请显示面板第一实施方式的结构示意图；
图10是本申请显示设备第一实施方式的结构示意图。
【具体实施方式】
为使本申请的目的、技术方案及效果更加清楚、明确，以下参照附图并举实施例对本申请进一步详细说明。
本申请提供一种阵列基板，请参阅图5-图6，图5是本申请阵列基板第一实施方式的结构示意图，图6是图5中非显示区的配向走线示意图。在该实施方式中，阵列基板50包括显示区501和非显示区502，非显示区502内设置有多组配向焊盘503，多组配向焊盘503分别与配向走线的相应位置电连接，配向焊盘503分为高电位焊盘5031和低电位焊盘5032。其中，配向走线区504包括高电位走线区5041和低电位走线区5042，高电位走线区5041和低电位走线区5042分别位于多组配向焊盘503的两侧，高电位焊盘5031对应的配向走线设置在高电位走线区5041，低电位焊盘5032对应的配向走线设置在低电位走线区5042。通过将配向走线按照电位高低进行分区，使电位相近的走线设置在同一区域，能够避免出现电位差异较大的跨线区，防止产生静电短路，提高产品的静电防护能力。
可选地，在一实施方式中，在进行配向走线时，高电位走线区内的配向走线在配向焊盘上的正投影与低电位走线区内的配向走线在配向焊盘上的正投影互不重叠。通过这种方式，能够尽量减少跨线区。
具体地，请参阅图7，图7是本申请阵列基板第一实施方式的外围配向走线示意图。配向走线包括主走线（7101、7201等）和连接线（7102、7202等），主走线（7101、7201等）沿第一方向排列，且向第二方向延伸，连接线（7102、7202等）沿第二方向排列，且向第一方向延伸，第一方向与第二方向垂直；高电位走线区内的主走线的排列方向和延伸方向与低电位走线区内的主走线的排列方向和延伸方向相反。
图7所示情况，主走线（7101、7201等）沿竖直方向排列，并沿水平方向延伸，连接线（7102、7202等）沿水平方向排列，并沿竖直方向延伸。其中，焊盘CF-com用于接入高电位信号，其对应连接的配向走线区域为高电位走线区；焊盘A-com、时钟焊盘CK1、CK2、CK3、CK4、CK5、CK6……CKn、低频时钟焊盘LC1、LC2、起始信号焊盘ST、公共电压焊盘Vss、数据信号电压焊盘R、G、B则用于接入低电位信号，其对应连接的配向走线区域为低电位走线区。低电位走线区内的主走线（7201等）沿竖直方向逐级向上排列，并沿水平方向向左延伸；而高电位走线区内的主走线（7101）沿竖直方向逐级向下排列，并沿水平方向向右延伸，两者方向正好相反。
在另一实施方式中，也可以是高电位走线区内的主走线的排列方向与低电位走线区内的主走线的排列方向相反，但高电位走线区内的主走线的延伸方向与低电位走线区内的主走线的延伸方向相同。即图7中主走线7101也可以沿水平方向向左延伸。
可选地，在一实施方式中，将走线区内配向走线数量较少的分区设置在远离显示区的一侧，通过这种方式，能够以防边缘成膜保证区受影响。其中，若高电位走线区的配向走线的数量小于低电位走线区配向走线的数量，则将高电位走线区设置在远离显示区的一侧，而低电位走线区设置在靠近显示区的一侧；若高电位走线区配向走线的数量大于低电位走线区配向走线的数量，则将高电位走线区设置在靠近显示区的一侧，而低电位走线区设置在远离显示区的一侧。
具体地，请参阅图8，图8是本申请阵列基板第二实施方式的外围配向走线示意图。图8所示情况，焊盘CF-com、时钟焊盘CK1、CK2、CK3、CK4、CK5、CK6……CKn、低频时钟焊盘LC1、LC2、起始信号焊盘ST、公共电压焊盘Vss用于接入高电位信号，其对应连接的配向走线区域为高电位走线区；焊盘A-com、数据信号电压焊盘R、G、B则用于接入低电位信号，其对应连接的配向走线区域为低电位走线区。其中，高电位走线区的走线数量大于低电位走线区的走线数量，因此将高电位走线区设置在靠近显示区的一侧。相比图7所示的情况则相反。
本申请还提供一种显示面板，请参阅图9，图9是本申请显示面板第一实施方式的结构示意图。在该实施方式中，显示面板90包括阵列基板901，阵列基板901包括显示区和非显示区，非显示区内设置有多组配向焊盘，多组配向焊盘分别与配向走线的相应位置电连接，配向焊盘分为高电位焊盘和低电位焊盘。其中，配向走线区包括高电位走线区和低电位走线区，高电位走线区和低电位走线区分别位于多组配向焊盘的两侧，高电位焊盘对应的配向走线设置在高电位走线区，低电位焊盘对应的配向走线设置在低电位走线区。阵列基板901的具体结构特征及有益效果与上述实施方式中的相同，具体请参阅上述实施方式的描述，在此不再赘述。
本申请还提供一种显示设备，请参阅图10，图10是本申请显示设备第一实施方式的结构示意图。在该实施方式中，显示设备100包括显示面板1001，显示面板1001包括阵列基板，阵列基板包括显示区和非显示区，非显示区内设置有多组配向焊盘，多组配向焊盘分别与配向走线的相应位置电连接，配向焊盘分为高电位焊盘和低电位焊盘。其中，配向走线区包括高电位走线区和低电位走线区，高电位走线区和低电位走线区分别位于多组配向焊盘的两侧，高电位焊盘对应的配向走线设置在高电位走线区，低电位焊盘对应的配向走线设置在低电位走线区。阵列基板的具体结构特征及有益效果与上述实施方式中的相同，具体请参阅上述实施方式的描述，在此不再赘述。
以上方案，本申请所提供的阵列基板，通过将配向走线按照电位高低进行分区，使电位相近的走线设置在同一区域，能够避免出现电位差异较大的跨线区，防止产生静电短路现象，提高产品的静电防护能力。
以上所述仅为本申请的实施方式，并非因此限制本申请的专利范围，凡是利用本申请说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本申请的专利保护范围内。

Claims (19)

  1. 一种阵列基板，其中，所述阵列基板包括显示区和非显示区，所述非显示区内设置有多组配向焊盘，每组所述配向焊盘分别电连接相对应的配向走线，所述配向焊盘分为高电位焊盘和低电位焊盘，所述高电位焊盘对应的所述配向走线设置在高电位走线区，所述低电位焊盘对应的所述配向走线设置在低电位走线区，所述高电位走线区和所述低电位走线区分别位于所述多组配向焊盘的两侧；
    其中，所述高电位走线区内的所述配向走线在所述多组配向焊盘上的正投影与所述低电位走线区内的所述配向走线在所述多组配向焊盘上的正投影互不重叠；
    其中，若所述高电位走线区内所述配向走线的数量小于所述低电位走线区内所述配向走线的数量，则所述高电位走线区设置在远离所述显示区的一侧，所述低电位走线区设置在靠近所述显示区的一侧；
    若所述高电位走线区内所述配向走线的数量大于所述低电位走线区内所述配向走线的数量，则所述高电位走线区设置在靠近所述显示区的一侧，所述低电位走线区设置在远离所述显示区的一侧。
  2. 根据权利要求1所述的阵列基板，其中，所述配向走线包括主走线和连接线，所述主走线沿第一方向排列，且向第二方向延伸，所述连接线沿所述第二方向排列，且向所述第一方向延伸，所述第一方向与所述第二方向垂直；所述高电位走线区内的所述主走线的排列方向和延伸方向与所述低电位走线区内的所述主走线的排列方向和延伸方向相反。
  3. 根据权利要求1所述的阵列基板，其中，所述配向走线包括主走线和连接线，所述主走线沿第一方向排列，且向第二方向延伸，所述连接线沿所述第二方向排列，且向所述第一方向延伸，所述第一方向与所述第二方向垂直；所述高电位走线区内的所述主走线的排列方向与所述低电位走线区内的所述主走线的排列方向相反，所述高电位走线区内的所述主走线的延伸方向与所述低电位走线区内的所述主走线的延伸方向相同。
  4. 根据权利要求1所述的阵列基板，其中，所述配向走线区设置有第一金属层、绝缘层和第二金属层，所述第一金属层和所述第二金属层的走线通过所述绝缘层的通孔电连接，所述配向走线包括主走线和连接线，所述主走线设置在所述第一金属层，所述连接线设置在所述第二金属层。
  5. 根据权利要求1所述的阵列基板，其中，每组所述配向焊盘包括：用于输入彩膜基板公共电压的彩膜基板公共电压焊盘，用于输入阵列基板公共电压的阵列基板公共电压焊盘，用于输入时钟信号的n个时钟焊盘，用于输入低频时钟信号的低频时钟焊盘，用于输入起始信号的起始信号焊盘，用于输入公共端电压的公共电压焊盘，用于输入像素电极数据信号电压的数据信号电压焊盘。
  6. 一种阵列基板，其中，所述阵列基板包括显示区和非显示区，所述非显示区内设置有多组配向焊盘，每组所述配向焊盘分别电连接相对应的配向走线，其中，所述配向焊盘分为高电位焊盘和低电位焊盘，所述高电位焊盘对应的所述配向走线设置在高电位走线区，所述低电位焊盘对应的所述配向走线设置在低电位走线区，所述高电位走线区和所述低电位走线区分别位于所述多组配向焊盘的两侧。
  7. 根据权利要求6所述的阵列基板，其中，所述高电位走线区内的所述配向走线在所述多组配向焊盘上的正投影与所述低电位走线区内的所述配向走线在所述多组配向焊盘上的正投影互不重叠。
  8. 根据权利要求7所述的阵列基板，其中，所述配向走线包括主走线和连接线，所述主走线沿第一方向排列，且向第二方向延伸，所述连接线沿所述第二方向排列，且向所述第一方向延伸，所述第一方向与所述第二方向垂直；所述高电位走线区内的所述主走线的排列方向和延伸方向与所述低电位走线区内的所述主走线的排列方向和延伸方向相反。
  9. 根据权利要求7所述的阵列基板，其中，所述配向走线包括主走线和连接线，所述主走线沿第一方向排列，且向第二方向延伸，所述连接线沿所述第二方向排列，且向所述第一方向延伸，所述第一方向与所述第二方向垂直；所述高电位走线区内的所述主走线的排列方向与所述低电位走线区内的所述主走线的排列方向相反，所述高电位走线区内的所述主走线的延伸方向与所述低电位走线区内的所述主走线的延伸方向相同。
  10. 根据权利要求6所述的阵列基板，其中，所述高电位走线区内所述配向走线的数量小于所述低电位走线区内所述配向走线的数量，所述高电位走线区设置在远离所述显示区的一侧，所述低电位走线区设置在靠近所述显示区的一侧。
  11. 根据权利要求6所述的阵列基板，其中，所述高电位走线区内所述配向走线的数量大于所述低电位走线区内所述配向走线的数量，所述高电位走线区设置在靠近所述显示区的一侧，所述低电位走线区设置在远离所述显示区的一侧。
  12. 根据权利要求6所述的阵列基板，其中，所述配向走线区设置有第一金属层、绝缘层和第二金属层，所述第一金属层和所述第二金属层的走线通过所述绝缘层的通孔电连接，所述配向走线包括主走线和连接线，所述主走线设置在所述第一金属层，所述连接线设置在所述第二金属层。
  13. 根据权利要求6所述的阵列基板，其中，每组所述配向焊盘包括：用于输入彩膜基板公共电压的彩膜基板公共电压焊盘，用于输入阵列基板公共电压的阵列基板公共电压焊盘，用于输入时钟信号的n个时钟焊盘，用于输入低频时钟信号的低频时钟焊盘，用于输入起始信号的起始信号焊盘，用于输入公共端电压的公共电压焊盘，用于输入像素电极数据信号电压的数据信号电压焊盘。
  14. 一种显示面板，其中，所述显示面板包括阵列基板，所述阵列基板包括显示区和非显示区，所述非显示区内设置有多组配向焊盘，每组所述配向焊盘分别电连接相对应的配向走线，其中，所述配向焊盘分为高电位焊盘和低电位焊盘，所述高电位焊盘对应的所述配向走线设置在高电位走线区，所述低电位焊盘对应的所述配向走线设置在低电位走线区，所述高电位走线区和所述低电位走线区分别位于所述多组配向焊盘的两侧。
  15. 根据权利要求14所述的显示面板，其中，所述高电位走线区内的所述配向走线在所述多组配向焊盘上的正投影与所述低电位走线区内的所述配向走线在所述多组配向焊盘上的正投影互不重叠。
  16. 根据权利要求15所述的显示面板，其中，所述配向走线包括主走线和连接线，所述主走线沿第一方向排列，且向第二方向延伸，所述连接线沿所述第二方向排列，且向所述第一方向延伸，所述第一方向与所述第二方向垂直；所述高电位走线区内的所述主走线的排列方向和延伸方向与所述低电位走线区内的所述主走线的排列方向和延伸方向相反。
  17. 根据权利要求15所述的显示面板，其中，所述配向走线包括主走线和连接线，所述主走线沿第一方向排列，且向第二方向延伸，所述连接线沿所述第二方向排列，且向所述第一方向延伸，所述第一方向与所述第二方向垂直；所述高电位走线区内的所述主走线的排列方向与所述低电位走线区内的所述主走线的排列方向相反，所述高电位走线区内的所述主走线的延伸方向与所述低电位走线区内的所述主走线的延伸方向相同。
  18. 根据权利要求14所述的显示面板，其中，所述高电位走线区内所述配向走线的数量小于所述低电位走线区内所述配向走线的数量，所述高电位走线区设置在远离所述显示区的一侧，所述低电位走线区设置在靠近所述显示区的一侧。
  19. 根据权利要求14所述的显示面板，其中，所述高电位走线区内所述配向走线的数量大于所述低电位走线区内所述配向走线的数量，所述高电位走线区设置在靠近所述显示区的一侧，所述低电位走线区设置在远离所述显示区的一侧。
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