WO2020000377A1 - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

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Publication number
WO2020000377A1
WO2020000377A1 PCT/CN2018/093691 CN2018093691W WO2020000377A1 WO 2020000377 A1 WO2020000377 A1 WO 2020000377A1 CN 2018093691 W CN2018093691 W CN 2018093691W WO 2020000377 A1 WO2020000377 A1 WO 2020000377A1
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WIPO (PCT)
Prior art keywords
bonding layer
bonding
layer
semiconductor structure
substrate
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PCT/CN2018/093691
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English (en)
French (fr)
Inventor
陈俊
华子群
胡思平
王家文
王涛
朱继锋
丁滔滔
王新胜
朱宏斌
程卫华
杨士宁
Original Assignee
长江存储科技有限责任公司
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Application filed by 长江存储科技有限责任公司 filed Critical 长江存储科技有限责任公司
Priority to PCT/CN2018/093691 priority Critical patent/WO2020000377A1/zh
Priority to CN202311005995.6A priority patent/CN116995059A/zh
Priority to CN201880096611.7A priority patent/CN112567521B/zh
Priority to TW107128251A priority patent/TWI667764B/zh
Priority to US16/378,518 priority patent/US20200006275A1/en
Publication of WO2020000377A1 publication Critical patent/WO2020000377A1/zh
Priority to US17/465,866 priority patent/US20210398932A1/en
Priority to US17/945,103 priority patent/US20230005873A1/en

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Definitions

  • the present invention relates to the field of semiconductor technology, and in particular, to a semiconductor structure and a method for forming the same.
  • the bonding films used on the wafer bonding surface are mostly silicon oxide or silicon nitride films.
  • silicon oxide and silicon nitride films are used as the bonding films, and the bonding strength is insufficient, which causes defects to easily occur during the process, and the product yield is affected.
  • a metal connection structure is also formed in the bonding film.
  • the metal connection structure is prone to diffusion at the bonding interface, which affects product performance.
  • the technical problem to be solved by the present invention is to provide a semiconductor structure and a method for forming the same.
  • the invention provides a semiconductor structure, the semiconductor structure includes: a first substrate; a first bonding layer on a surface of the first substrate, and a material of the first bonding layer is a medium including Si, N, and C material.
  • the atomic concentration of C is greater than 0 and less than 50%.
  • the atomic concentration of C is uniformly distributed.
  • the atomic concentration of C gradually changes as the thickness of the first bonding layer increases.
  • the density of the first bonding layer gradually changes with increasing thickness.
  • the thickness of the first bonding layer is greater than
  • it further includes: a second substrate, a second bonding layer is formed on a surface of the second substrate, and the second bonding layer is relatively bonded and fixed to the surface of the first bonding layer.
  • the material of the second bonding layer is the same as that of the first bonding layer.
  • it further includes: a first bonding pad penetrating through the first bonding layer; a second bonding pad penetrating through the second bonding layer; the first bonding pad and the second bonding pad Relative bonding.
  • the technical solution of the present invention further provides a method for forming a semiconductor structure, including: providing a first substrate; forming a first bonding layer on a surface of the first substrate, and a material of the first bonding layer including Si, N And C dielectric materials.
  • the first bonding layer is formed by a chemical vapor deposition process.
  • the atomic concentration of C is greater than 0 and less than 50%.
  • the atomic concentration of C is uniformly distributed.
  • the atomic concentration of C gradually changes as the thickness of the first bonding layer increases.
  • the density of the first bonding layer gradually changes with increasing thickness.
  • the thickness of the first bonding layer is greater than
  • the method further includes: providing a second substrate; forming a second bonding layer on a surface of the second substrate; and relatively fixing and fixing the surface of the second bonding layer and the surface of the first bonding layer.
  • the material of the second bonding layer is the same as that of the first bonding layer.
  • the method further includes: forming a first bonding pad penetrating through the first bonding layer; forming a second bonding pad penetrating through the second bonding layer; and connecting the surface of the second bonding layer with While the surface of the first bonding layer is relatively bonded and fixed, the first bonding pad and the second bonding pad are relatively bonded and connected.
  • the material of the first bonding layer of the semiconductor structure of the present invention is a dielectric material containing Si, N, and C, which can have a high bonding force during bonding, and can block the diffusion of the metal material at the bonding interface, thereby improving The performance of the formed semiconductor structure.
  • 1 to 4 are schematic structural diagrams of a process of forming a semiconductor structure according to an embodiment of the present invention.
  • FIG. 5 is a schematic diagram of a semiconductor structure according to a specific embodiment of the present invention.
  • FIG. 6 is a schematic diagram of a semiconductor structure according to an embodiment of the present invention.
  • FIGS. 1 to 4 are schematic structural diagrams of a process of forming a semiconductor structure according to an embodiment of the present invention.
  • a first substrate 100 is provided.
  • the first substrate 100 includes a first semiconductor substrate 101 and a first device layer 102 formed on a surface of the first semiconductor substrate 101.
  • the first semiconductor substrate 101 may be a single crystal silicon substrate, a Ge substrate, a SiGe substrate, an SOI or a GOI, etc .; according to the actual needs of the device, a suitable first semiconductor substrate 101 may be selected, which is not limited herein .
  • the first semiconductor substrate 101 is a single crystal silicon wafer.
  • the first device layer 102 includes a semiconductor device formed on the semiconductor substrate 101, a metal interconnection structure connected to the semiconductor device, a dielectric layer covering the semiconductor device and the metal interconnection structure, and the like.
  • the first device layer 102 may have a multi-layer or single-layer structure.
  • the first device layer 102 includes a dielectric layer and a 3D NAND structure formed in the dielectric layer.
  • a first bonding layer 200 is formed on a surface of the first substrate 100, and a material of the first bonding layer is a dielectric material including Si, N, and C.
  • the first bonding layer 200 may be formed by a chemical vapor deposition process.
  • the first bonding layer 200 is formed by a plasma chemical vapor deposition process.
  • the material of the first bonding layer 200 is a dielectric material containing Si, N, and C. Based on the reaction gas used in the chemical vapor deposition process and the needs of specific products, the first bonding layer 200 may also be doped with It is doped with at least one of O, H, P, F and other elements.
  • the material of the first bonding layer 200 may be silicon doped silicon nitride, carbon doped silicon oxynitride, nitrogen doped silicon oxycarbide, or the like.
  • the first bonding layer 200 is formed by a plasma chemical vapor deposition process, and a reaction gas used includes one of trimethylsilane or tetramethylsilane and NH 3 , trimethylsilane Or the flow ratio of tetramethylsilane to NH 3 is greater than 0.5, and the radio frequency power is greater than 300W.
  • the first bonding layer 200 may also be formed by processing a dielectric material.
  • a silicon nitride film is formed on the surface of the first substrate 100, and the silicon nitride film is carbon-doped to form the first bonding layer 200.
  • a suitable dielectric film material and a thin film processing method can be selected according to the material of the first bonding layer 200 to be formed.
  • the concentration of each component in the first bonding layer 200 can be adjusted, and the concentration between the first bonding layer 200 and the first device layer 102 can be adjusted.
  • the adhesive force, the dielectric constant of the first bonding layer 200, and the bonding force after bonding with other bonding layers are adjusted.
  • C in the first bonding layer 200 can effectively improve the bonding force between the first bonding layer 201 and other bonding layers during the bonding process.
  • the atomic concentration of C in the first bonding layer 200 is greater than 0 and less than 50%.
  • the process parameters can be gradually adjusted so that the first The component concentration in a bonding layer 200 gradually changes, so that the material components on both sides of the interface between the first bonding layer 200 and the first device layer 102 are close.
  • the parameters of the deposition process are adjusted so that the atomic concentration of C follows the first bonding
  • the thickness of the layer 200 increases and gradually increases, so that the atomic concentration of C on the surface of the first bonding layer 200 is maximized.
  • the atomic concentration of C may be gradually decreased as the thickness of the first bonding layer 200 is increased, or gradually increased and then gradually decreased.
  • the deposition process parameters are kept unchanged, so that each element in the first bonding layer 200 remains stable at different thickness positions.
  • the process parameters of the stroke may also be adjusted so that the density of the first bonding layer 200 formed gradually changes with increasing thickness. For example, from the surface of the first device layer 102 upwards, the density of the first bonding layer 200 gradually increases, decreases gradually, or increases first and then decreases. The density of the interface between the first bonding layer 200 and the first device layer 102 is close.
  • the thickness of the first bonding layer 200 cannot be too small, so as to ensure that the first bonding layer 200 has a sufficient bonding thickness when bonding the first bonding layer 200 with other bonding layers. . In a specific embodiment, the thickness of the first bonding layer 200 is greater than
  • the method further includes: providing a second substrate 300; and forming a second bonding layer 400 on a surface of the second substrate 300.
  • the second substrate 300 includes a second semiconductor substrate 301 and a second device layer 302 on a surface of the second semiconductor substrate 201.
  • a chemical vapor deposition process is used to form a second bonding layer 400 on the surface of the second device layer 302.
  • the material of the second bonding layer 400 may be silicon oxide or silicon nitride.
  • the material of the second bonding layer 400 may also be a dielectric material containing Si, N, and C. Please refer to the description of the first bonding layer 200 in the foregoing specific implementation manner. More details. In a specific embodiment, a material of the second bonding layer 400 is the same as that of the first bonding layer 200.
  • the surfaces of the first bonding layer 200 of the second bonding layer 400 are relatively bonded and fixed.
  • the second bonding layer 400 and the first bonding layer 200 each containing C, part C is present in the form of -CH 3, -CH 3 more susceptible to oxidation is -OH, and is formed in the Si-O bonding process Bonding, so that more silicon-oxygen bonds can be formed at the bonding interface, thereby forming a stronger bonding force.
  • the bonding force between the second bonding layer 400 and the first bonding layer 200 is greater than 1.7 J / M 2 , and in the prior art, a bonding layer containing no C is used for bonding. , Usually the bonding force is less than 1.5J / M 2 .
  • the first substrate 100 is a substrate on which a 3D NAND memory structure is formed
  • the second substrate 200 is a substrate on which a peripheral circuit is formed.
  • the above-mentioned bonding layers may also be formed on both side surfaces of the substrate to achieve multilayer bonding.
  • the method further includes: forming a first bonding pad 501 penetrating through the first bonding layer 200; and forming a second bonding pad penetrating through the second bonding layer 400 502; while the surface of the second bonding layer 400 and the surface of the first bonding layer 200 are relatively bonded and fixed, the first bonding pad 501 and the second bonding pad 502 are relatively bonded and connected .
  • the first bonding pad 501 and the second bonding pad 502 may be connected to a semiconductor device and a metal interconnection layer in the first device layer 102 and the second device layer 302, respectively.
  • the forming method of the first bonding pad 501 includes: patterning the first bonding layer 200 to form an opening penetrating the first bonding layer 200; filling a metal material into the opening, and performing Flatten to form a first bonding pad 501 that fills the opening. The same method is used to form the second bonding pad 502 in the second bonding layer 400. Bonding the first bonding pad 501 and the second bonding pad 502 to each other can realize the electrical connection between the semiconductor devices in the first device layer 102 and the second device layer 302.
  • the materials of the first bonding pad 501 and the second bonding pad 502 may be metal materials such as Cu and W.
  • the first bonding layer 200 and the second bonding layer 400 contain C, which can effectively block the material of the first bonding pad 501 and the second bonding pad 502 from diffusing at the bonding interface, thereby improving the Performance of semiconductor structures.
  • the above method is also used for multi-piece substrate bonding.
  • a third substrate 600 is further provided, and a third bonding layer 700 and a fourth bonding layer 800 are formed on opposite sides of the third substrate 600 respectively.
  • the third bonding layer 700 and the surface of the first bonding layer 200 are relatively bonded and fixed, and the fourth bonding layer 800 and the surface of the second bonding layer 400 are fixed and bonded to form a three-layer bonding structure.
  • the materials and forming methods of the third bonding layer 700 and the fourth bonding layer 800 please refer to the materials and forming methods of the first bonding layer 200 in the foregoing specific implementation manner, and details are not described herein again.
  • a third bonding pad 701 is formed in the third bonding layer 700
  • a fourth bonding pad 801 is formed in the fourth bonding layer 800
  • the third bonding pad 701 and The first bonding pad 501 is key-connected
  • the fourth bonding pad 801 and the second bonding pad 502 are key-connected.
  • the above method can also be used to form a bonding structure with more than four layers.
  • a bonding layer is formed on the surface of the substrate.
  • the material of the bonding layer is a dielectric material containing Si, N, and C. After bonding, the bonding layer can also have a strong bonding force on the bonding surface, and can Block the diffusion of metallic materials at the bonding interface, thereby improving the performance of the formed semiconductor structure.
  • the type of semiconductor device in each substrate in the semiconductor structure is not limited to the given embodiment. Except for 3D NAND, it may be a CMOS circuit, a CIS circuit, or a TFT circuit. and many more.
  • a specific embodiment of the present invention also provides a semiconductor structure.
  • FIG. 2 is a schematic structural diagram of a semiconductor structure according to an embodiment of the present invention.
  • the semiconductor structure includes: a first substrate 100; a first bonding layer 200 on a surface of the first substrate 100, and a material of the first bonding layer 200 is a dielectric material including Si, N, and C.
  • the first substrate 100 includes a first semiconductor substrate 101 and a first device layer 102 formed on a surface of the first semiconductor substrate 101.
  • the first semiconductor substrate 101 may be a single crystal silicon substrate, a Ge substrate, a SiGe substrate, an SOI or a GOI, etc .; according to the actual needs of the device, a suitable first semiconductor substrate 101 may be selected, which is not limited herein. .
  • the first semiconductor substrate 101 is a single crystal silicon wafer.
  • the first device layer 102 includes a semiconductor device formed on the semiconductor substrate 101, a metal interconnection structure connected to the semiconductor device, a dielectric layer covering the semiconductor device and the metal interconnection structure, and the like.
  • the first device layer 102 may have a multi-layer or single-layer structure.
  • the first device layer 102 includes a dielectric layer and a 3D NAND structure formed in the dielectric layer.
  • the material of the first bonding layer 200 is a dielectric material including Si, N, and C. Based on the formation process of the first bonding layer 200 and the requirements of specific products, the first bonding layer 200 may further include Doped with at least one of elements such as O, H, P, and F.
  • the material of the first bonding layer 200 may be silicon doped silicon nitride, carbon doped silicon oxynitride, nitrogen doped silicon oxycarbide, or the like.
  • the concentration of each component in the first bonding layer 200 can be adjusted, and the concentration between the first bonding layer 200 and the first device layer 102 can be adjusted.
  • the adhesion force, the dielectric constant of the first bonding layer 200 and the bonding force after bonding with other bonding layers are adjusted.
  • C in the first bonding layer 200 can effectively improve the bonding force between the first bonding layer 200 and other bonding layers during the bonding process.
  • the atomic concentration of C in the first bonding layer 200 is greater than 0 and less than 50%.
  • the component concentration in the first bonding layer 200 may also gradually change with the thickness, so that the first The material composition on both sides of the interface between the bonding layer 200 and the first device layer 102 is close.
  • the C atom concentration in the first bonding layer 200 gradually increases as the thickness of the first bonding layer 200 increases, so that the first bond The atomic concentration of C on the surface of the bonding layer 200 is the largest.
  • the atomic concentration of C in the first bonding layer 200 gradually decreases as the thickness of the first bonding layer 200 increases, or gradually increases first and then gradually decreases. In other specific embodiments, each element in the first bonding layer 200 remains stable at different thickness positions and has a uniformly distributed atomic concentration.
  • the density of the first bonding layer 200 gradually changes as the thickness increases. For example, from the surface of the first device layer 102 upward, the density of the first bonding layer 200 gradually increases. Increase, decrease gradually, or increase first and then decrease. The density of the interface between the first bonding layer 200 and the first device layer 102 is close.
  • the thickness of the first bonding layer 200 cannot be too small, so as to ensure that when the first bonding layer 200 is bonded with other bonding layers, the first bonding layer 200 has a sufficient bonding thickness. In a specific embodiment, the thickness of the first bonding layer 200 is greater than
  • FIG. 4 is a schematic diagram of a semiconductor structure according to another embodiment of the present invention.
  • the semiconductor structure further includes: a second substrate 300, a second bonding layer 400 is formed on a surface of the second substrate 300, and the second bonding layer 400 and the first bonding layer The 200 surface is relatively bonded and fixed.
  • the second substrate 300 includes a second semiconductor substrate 301 and a second device layer 302 on a surface of the second semiconductor substrate 201.
  • the material of the second bonding layer 400 may be silicon oxide or silicon nitride.
  • the material of the second bonding layer 400 may also be a dielectric material including Si, N, and C.
  • a material of the second bonding layer 400 is the same as that of the first bonding layer 200.
  • the second bonding layer 400 and the surface of the first bonding layer 200 are relatively bonded and fixed. Because both the second bonding layer 400 and the first bonding layer 200 contain C, part of the C is -CH. The form of 3 exists, -CH 3 is more easily oxidized to -OH, and forms Si-O bonds during the bonding process, so that more silicon-oxygen bonds are formed at the bonding interface, thereby forming a stronger bonding force.
  • the semiconductor structure may include more than three substrates, and adjacent substrates are bonded through a bonding layer in a specific embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of a semiconductor structure according to another embodiment of the present invention.
  • the semiconductor structure further includes: a first bonding pad 501 penetrating through the first bonding layer 200; a second bonding pad 502 penetrating through the second bonding layer 400; The surface of the two bonding layers 400 and the surface of the first bonding layer 200 are relatively bonded and fixed, and the first bonding pad 501 and the second bonding pad 502 are relatively bonded and connected.
  • the first bonding pad 501 and the second bonding pad 502 may be connected to a semiconductor device and a metal interconnection layer in the first device layer 102 and the second device layer 302, respectively.
  • the materials of the first bonding pad 501 and the second bonding pad 502 may be metal materials such as Cu and W.
  • the first bonding layer 200 and the second bonding layer 400 contain C, which can effectively block the material of the first bonding pad 501 and the second bonding pad 502 from diffusing at the bonding interface, thereby improving the Performance of semiconductor structures.
  • the first substrate 100 is a substrate on which a 3D NAND memory structure is formed
  • the second substrate 200 is a substrate on which a peripheral circuit is formed.
  • FIG. 6 is a schematic diagram of a semiconductor structure according to another embodiment of the present invention.
  • the semiconductor structure further includes: a third substrate 600, and a third bonding layer 700 and a fourth bonding layer 800 are formed on opposite sides of the third substrate 600;
  • the bonding layer 700 is relatively bonded and fixed to the surface of the first bonding layer 200
  • the fourth bonding layer 800 is fixed to the surface of the second bonding layer 400 to form a three-layer bonding structure.
  • a third bonding pad 701 is further formed in the third bonding layer 700, and a fourth bonding pad 801 is formed in the fourth bonding layer 800.
  • the third bonding pad 701 and The first bonding pad 501 is keyed, and the fourth bonding pad 801 is keyed to the second bonding pad 502.
  • the semiconductor structure may also be a bonding structure with more than four layers.

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Abstract

一种半导体结构及其形成方法，半导体结构包括：第一基底（100）；位于第一基底表面的第一键合层（200），第一键合层的材料为包含Si、N和C的介质材料。半导体结构的第一键合层在键合时能够具有较高的键合力。

Description

半导体结构及其形成方法 技术领域
本发明涉及半导体技术领域，尤其涉及一种半导体结构及其形成方法。
背景技术
在3D的芯片技术平台中，通常会将两片及以上形成有半导体器件的结构通过晶圆键合技术进行键合，以提高芯片的集成度。现有的晶圆键合技术，在晶圆键合面上采用的键合薄膜多为氧化硅或氮化硅薄膜。
现有技术中，采用氧化硅和氮化硅薄膜作为键合薄膜，键合强度不够，导致工艺过程中容易出现缺陷，产品良率受到影响。
并且，键合薄膜内还形成有金属连接结构，在混合键合的过程中，所述金属连接结构容易在键合界面出现扩散现象，导致产品性能受到影响。
因此，如何提高晶圆键合的质量，是目前亟待解决的问题。
发明内容
本发明所要解决的技术问题是，提供一种半导体结构及其形成方法。
本发明提供一种半导体结构，所述半导体结构包括：第一基底；位于所述第一基底表面的第一键合层，所述第一键合层的材料为包含Si、N和C的介质材料。
可选的，所述第一键合层中，C的原子浓度大于0且小于50％。
可选的，所述第一键合层中，C的原子浓度均匀分布。
可选的，所述第一键合层中，C的原子浓度随第一键合层厚度增加而逐渐改变。
可选的，所述第一键合层的致密度随厚度增加而逐渐改变。
可选的，所述第一键合层的厚度大于
Figure PCTCN2018093691-appb-000001
可选的，还包括：第二基底，所述第二基底表面形成有第二键合层，所述第二键合层与所述第一键合层表面相对键合固定。
可选的，所述第二键合层的材料与所述第一键合层的材料相同。
可选的，还包括：贯穿所述第一键合层的第一键合垫；贯穿所述第二键合层的第二键合垫；所述第一键合垫与第二键合垫相对键合连接。
本发明的技术方案还提供一种半导体结构的形成方法，包括：提供第一基底；在所述第一基底表面形成第一键合层，所述第一键合层的材料为包含Si、N和C的介质材料。
可选的，采用化学气相沉积工艺形成所述第一键合层。
可选的，所述第一键合层中，C的原子浓度大于0且小于50％。
可选的，所述第一键合层中，C的原子浓度均匀分布。
可选的，所述第一键合层中，C的原子浓度随第一键合层厚度增加而逐渐改变。
可选的，所述第一键合层的致密度随厚度增加而逐渐改变。
可选的，所述第一键合层的厚度大于
Figure PCTCN2018093691-appb-000002
可选的，还包括：提供第二基底；在所述第二基底表面形成第二键合层；将所述第二键合层表面与所述第一键合层表面相对键合固定。
可选的，所述第二键合层与所述第一键合层的材料相同。
可选的，还包括：形成贯穿所述第一键合层的第一键合垫；形成贯穿所述第二键合层的第二键合垫；在将所述第二键合层表面与所述第一键合层表面相对键合固定的同时，将所述第一键合垫与第二键合垫相对键合连接。
本发明的半导体结构的第一键合层的材料为包含Si、N和C的介质材料，在键合时能够具有较高的键合力，并且能够阻挡金属材料在键合界面的扩散，从而提高形成的半导体结构的性能。
附图说明
图1至图4为本发明一具体实施方式的半导体结构的形成过程的结构示意图；
图5为本发明一具体实施方式的半导体结构的示意图；
图6为本发明一具体实施方式的半导体结构的示意图。
具体实施方式
下面结合附图对本发明提供的半导体结构及其形成方法的具体实施方式做详细说明。
请参考图1至图4，为本发明一具体实施方式的半导体结构的形成过程的结构示意图。
请参考图1，提供第一基底100。
所述第一基底100包括第一半导体衬底101、形成于所述第一半导体衬底101表面的第一器件层102。
所述第一半导体衬底101可以为单晶硅衬底、Ge衬底、SiGe衬底、SOI或GOI等；根据器件的实际需求，可以选择合适的第一半导体衬底101，在此不作限定。该具体实施方式中，所述第一半导体衬底101为单晶硅晶圆。
所述第一器件层102包括形成于所述半导体衬底101上的半导体器件、连接所述半导体器件的金属互连结构、覆盖所述半导体器件以及金属互连结构的介质层等。所述第一器件层102可以为多层或单层结构。在一个具体实施方式中，所述第一器件层102包括介质层以及形成于介质层内的3D NAND结构。
请参考图2，在所述第一基底100表面形成第一键合层200，所述第一键合层的材料为包含Si、N和C的介质材料。
可以采用化学气相沉积工艺，形成所述第一键合层200。该具体实施方式中，采用等离子体化学气相沉积工艺形成所述第一键合层200。
所述第一键合层200的材料为包含Si、N和C的介质材料，基于化学气相沉积工艺中采用的反应气体，以及具体产品的需求，所述第一键合层200内还可以掺杂有O、H、P、F等元素中的至少一种。所述第一键合层200的材料可以为掺碳氮化硅、掺碳氮氧化硅、掺氮碳氧化硅等。
在一个具体实施方式中，采用等离子化学气相沉积工艺形成所述第一键合层200，采用的反应气体包括：三甲基硅烷或四甲基硅烷中的一种以及NH 3，三甲基硅烷或四甲基硅烷与NH 3的流量比大于0.5，射频功率大于300W。
在其他具体实施方式中，还可以通过对介质材料进行处理形成所述第一键合层200。例如，在所述第一基底100表面形成氮化硅薄膜，并对所述氮化硅 薄膜进行碳掺杂，形成所述第一键合层200。可以根据待形成的第一键合层200的材料选择合适的介质薄膜材料以及薄膜处理方式。
通过控制所述第一键合层200的形成工艺参数，可以调整所述第一键合层200内各组分的浓度，对所述第一键合层200与第一器件层102之间的粘附力、第一键合层200的介电系数以及与其他键合层进行键合后的键合力进行调整。
所述第一键合层200中的C能够有效提高所述第一键合层201在键合过程中，与其他键合层之间的键合力。C浓度越高，与其他键合层之间进行键合时产生的键合力越大。在一个具体实施方式中，所述第一键合层200中，C的原子浓度大于0且小于50％。
由于不同材料层之间的粘附力与界面两侧的材料组分相关，材料组分越接近，粘附力越强。为了进一步增强所述第一键合层200与所述第一器件层102之间的粘附力，可以在形成所述第一键合层200的过程中，逐渐调整工艺参数，使得所述第一键合层200内的组分浓度逐渐发生变化，使得所述第一键合层200与所述第一器件层102界面两侧的材料组分接近。在一个具体实施方式中，在形成所述第一键合层200的过程中，随着第一键合层200厚度的增加，通过调整沉积工艺的参数，使得C的原子浓度随第一键合层200厚度增加而逐渐增大，使得所述第一键合层200表面的C的原子浓度最大。在其他具体实施方式中，也可以使得C的原子浓度随第一键合层200厚度增加而逐渐减小或者先逐渐增大再逐渐减小。在其他具体实施方式中，在形成所述第一键合层200的过程中，保持沉积工艺参数不变，使得第一键合层200中各元素在不同厚度位置处保持稳定不变。
在另一具体实施方式中，也可以通过调整行程工艺参数，使得形成的所述第一键合层200的致密度随厚度增加而逐渐改变。例如自所述第一器件层102表面向上，所述第一键合层200的致密度逐渐增大、逐渐减小或者先增大后减小。所述第一键合层200与第一器件层102界面处密度接近。
所述第一键合层200的厚度不能过小，以确保在将所述第一键合层200与其他键合层进行键合时，所述第一键合层200具有足够的键合厚度。在一个具体实施方式中，所述第一键合层200的厚度大于
Figure PCTCN2018093691-appb-000003
请参考图3，在另一具体实施方式中，还包括：提供第二基底300；在所述第二基底300表面形成第二键合层400。
所述第二基底300包括第二半导体衬底301以及位于所述第二半导体衬底201表面的第二器件层302。
采用化学气相沉积工艺在所述第二器件层302表面形成第二键合层400，所述第二键合层400的材料可以为氧化硅或氮化硅。
在该具体实施方式中，所述第二键合层400的材料也可以为包含Si、N和C的介质材料，请参考上述具体实施方式中的第一键合层200的描述，在此不再赘述。在一个具体实施方式中，所述第二键合层400的材料与上述第一键合层200的材料相同。
请参考图4，将所述第二键合层400所述第一键合层200表面相对键合固定。
所述第二键合层400与第一键合层200内均含有C，部分C以-CH 3的形式存在，-CH 3更易被氧化为-OH，并在键合过程中形成Si-O键，使得在键合界面上能够形成更多的硅氧键，从而形成较强的键合力。在一个具体实施方式中，所述第二键合层400与第一键合层200之间的键合力大于1.7J/M 2，而现有技术中采用不含C的键合层进行键合，通常键合力小于1.5J/M 2。
在一个具体实施方式中，所述第一基底100为形成有3D NAND存储结构的基底，而所述第二基底200为形成有外围电路的基底。
在其他具体实施方式中，还可以在基底的两侧表面均形成上述键合层，以实现多层键合。
请参考图5，在另一具体实施方式中，还包括：形成贯穿所述第一键合层200的第一键合垫501；形成贯穿所述第二键合层400的第二键合垫502；在将所述第二键合层400表面与所述第一键合层200表面相对键合固定的同时，将所述第一键合垫501与第二键合垫502相对键合连接。
所述第一键合垫501和第二键合垫502可以分别连接至所述第一器件层102和第二器件层302内的半导体器件以及金属互连层。
所述第一键合垫501的形成方法包括：对所述第一键合层200进行图形化， 形成贯穿所述第一键合层200的开口；在所述开口内填充金属材料，并进行平坦化，形成填充满所述开口的第一键合垫501。采用相同的方法在所述第二键合层400内形成所述第二键合垫502。将所述第一键合垫501与第二键合垫502键合连接，可以实现所述第一器件层102和第二器件层302内的半导体器件之间的电连接。
所述第一键合垫501和第二键合垫502的材料可以是Cu、W等金属材料。所述第一键合层200和第二键合层400内含有C，能够有效阻挡所述第一键合垫501和第二键合垫502的材料在键合界面发生扩散，从而提高所述半导体结构的性能。
上述方法还用于多片基底键合。
请参考图6，在本发明一具体实施方式中，还包括提供第三基底600，在所述第三基底600的相对两侧表面分别形成第三键合层700和第四键合层800；将所述第三键合层700与第一键合层200表面相对键合固定，将所述第四键合层800与第二键合层400表面键合固定，形成三层键合结构。
所述第三键合层700和第四键合层800的材料与形成方法请参照上述具体实施方式中第一键合层200的材料与形成方法，在此不再赘述。
该具体实施方式中，还包括在第三键合层700内形成第三键合垫701，在第四键合层800内形成第四键合垫801，将所述第三键合垫701与第一键合垫501键合连接，将所述第四键合垫801与第二键合垫502键合连接。
在其他具体实施方式中，还可以采用上述方法形成四层以上的键合结构。
上述具体实施方式，在基底表面形成键合层，所述键合层的材料为包含Si、N和C的介质材料，在键合后也能在键合表面具有较强的键合力，并且能够阻挡金属材料在键合界面的扩散，从而提高形成的半导体结构的性能。
需说明的是，在本发明的技术方案中，半导体结构中各个基底内的半导体器件类型并不应局限于所给实施例，除了3D NAND之外，其可以为CMOS电路、CIS电路、TFT电路等等。
本发明的具体实施方式还提供一种半导体结构。
请参考图2，为本发明一具体实施方式的半导体结构的结构示意图。
所述半导体结构，包括：第一基底100；位于所述第一基底100表面的第一键合层200，所述第一键合层200材料为包含Si、N和C的介质材料。
所述第一基底100包括第一半导体衬底101、形成于所述第一半导体衬底101表面的第一器件层102。
所述第一半导体衬底101可以为单晶硅衬底、Ge衬底、SiGe衬底、SOI或GOI等；根据器件的实际需求，可以选择合适的第一半导体衬底101，在此不作限定。该具体实施方式中，所述第一半导体衬底101为单晶硅晶圆。
所述第一器件层102包括形成于所述半导体衬底101上的半导体器件、连接所述半导体器件的金属互连结构、覆盖所述半导体器件以及金属互连结构的介质层等。所述第一器件层102可以为多层或单层结构。在一个具体实施方式中，所述第一器件层102包括介质层以及形成于介质层内的3D NAND结构。
所述第一键合层200的材料为包含Si、N和C的介质材料，基于所述第一键合层200的形成工艺以及具体产品的需求，所述第一键合层200内还可以掺杂有O、H、P、F等元素中的至少一种。所述第一键合层200的材料可以为掺碳氮化硅、掺碳氮氧化硅、掺氮碳氧化硅等。
通过控制所述第一键合层200的形成工艺参数，可以调整所述第一键合层200内各组分的浓度，对所述第一键合层200与第一器件层102之间的粘附力、所述第一键合层200的介电系数以及与其他键合层进行键合后的键合力进行调整。
所述第一键合层200中的C能够有效提高所述第一键合层200在键合过程中，与其他键合层之间的键合力。C浓度越高，与其他键合层之间进行键合时产生的键合力越大。在一个具体实施方式中，所述第一键合层200中，C的原子浓度大于0且小于50％。
由于不同材料层之间的粘附力与界面两侧的材料组分相关，材料组分越接近，粘附力越强。为了进一步增强所述第一键合层200与所述第一器件层102之间的粘附力，所述第一键合层200内的组分浓度也可以随厚度逐渐变化，使得所述第一键合层200与所述第一器件层102界面两侧的材料组分接近。在一个具体实施方式中，随着第一键合层200厚度的增加，第一键合层200内的C 原子浓度随第一键合层200厚度增加而逐渐增大，使得所述第一键合层200表面的C的原子浓度最大。在其他具体实施方式中，第一键合层200内的C的原子浓度随第一键合层200厚度增加而逐渐减小或者先逐渐增大再逐渐减小。在其他具体实施方式中，所述第一键合层200中各元素在不同厚度位置处保持稳定不变，具有均匀分布的原子浓度。
在另一具体实施方式中，所述第一键合层200的致密度随厚度增加而逐渐改变，例如自所述第一器件层102表面向上，所述第一键合层200的致密度逐渐增大、逐渐减小或者先增大后减小。所述第一键合层200与第一器件层102界面处密度接近。
所述第一键合层200的厚度不能过小，以确保所述第一键合层200与其他键合层进行键合时，所述第一键合层200具有足够的键合厚度。在一个具体实施方式中，所述第一键合层200的厚度大于
Figure PCTCN2018093691-appb-000004
请参考图4，为本发明另一具体实施方式的半导体结构的示意图。
该具体实施方式中，所述半导体结构还包括：第二基底300，所述第二基底300表面形成有第二键合层400，所述第二键合层400与所述第一键合层200表面相对键合固定。
所述第二基底300包括第二半导体衬底301以及位于所述第二半导体衬底201表面的第二器件层302。所述第二键合层400的材料可以为氧化硅或氮化硅。所述第二键合层400的材料也可以为包含Si、N和C的介质材料，具体请参考上述具体实施方式中的第一键合层200的描述，在此不再赘述。在一个具体实施方式中，所述第二键合层400的材料与上述第一键合层200的材料相同。
所述第二键合层400与所述第一键合层200的表面相对键合固定，由于所述第二键合层400与第一键合层200内均含有C，部分C以-CH 3的形式存在，-CH 3更易被氧化为-OH，并在键合过程中形成Si-O键，使得在键合界面上形成较多的硅氧键，从而形成较强的键合力。
在其他具体实施方式中，所述半导体结构可以包括三个以上的基底，相邻基底之间均通过本发明具体实施方式中的键合层进行键合。
请参考图5，为发明另一具体实施方式的半导体结构的结构示意图。
该具体实施方式中，所述半导体结构还包括：贯穿所述第一键合层200的第一键合垫501；贯穿所述第二键合层400的第二键合垫502；所述第二键合层400表面与所述第一键合层200表面相对键合固定且所述第一键合垫501与第二键合垫502相对键合连接。
所述第一键合垫501和第二键合垫502可以分别连接至所述第一器件层102和第二器件层302内的半导体器件以及金属互连层。
所述第一键合垫501和第二键合垫502的材料可以是Cu、W等金属材料。所述第一键合层200和第二键合层400内含有C，能够有效阻挡所述第一键合垫501和第二键合垫502的材料在键合界面发生扩散，从而提高所述半导体结构的性能。
在一个具体实施方式中，所述第一基底100为形成有3D NAND存储结构的基底，而所述第二基底200为形成有外围电路的基底。
请参考图6，为本发明另一具体实施方式的半导体结构示意图。
该具体实施方式中，所述半导体结构还包括：第三基底600，在所述第三基底600的相对两侧表面形成有第三键合层700和第四键合层800；所述第三键合层700与第一键合层200表面相对键合固定，所述第四键合层800与第二键合层400表面键合固定，形成三层键合结构。
所述第三键合层700和第四键合层800的材料与结构请参照上述具体实施方式中第一键合层200的材料与结构，在此不再赘述。
该具体实施方式中，所述第三键合层700还形成有第三键合垫701，在第四键合层800内形成有第四键合垫801，所述第三键合垫701与第一键合垫501键合连接，所述第四键合垫801与第二键合垫502键合连接。
在其他具体实施方式中，所述半导体结构还可以为四层以上的键合结构。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (19)

  1. 一种半导体结构，其特征在于，包括：
    第一基底；
    位于所述第一基底表面的第一键合层，所述第一键合层的材料为包含Si、N和C的介质材料。
  2. 根据权利要求1所述的半导体结构，其特征在于，所述第一键合层中，C的原子浓度大于0且小于50％。
  3. 根据权利要求1所述的半导体结构，其特征在于，所述第一键合层中，C的原子浓度均匀分布。
  4. 根据权利要求1所述的半导体结构，其特征在于，所述第一键合层中，C的原子浓度随第一键合层厚度增加而逐渐改变。
  5. 根据权利要求1所述的半导体结构，其特征在于，所述第一键合层的致密度随厚度增加而逐渐改变。
  6. 根据权利要求1所述的半导体结构，其特征在于，所述第一键合层的厚度大于
    Figure PCTCN2018093691-appb-100001
  7. 根据权利要求1所述的半导体结构，其特征在于，还包括：第二基底，所述第二基底表面形成有第二键合层，所述第二键合层与所述第一键合层表面相对键合固定。
  8. 根据权利要求7所述的半导体结构，其特征在于，所述第二键合层的材料与所述第一键合层的材料相同。
  9. 根据权利要求7所述的半导体结构，其特征在于，还包括：贯穿所述第一键合层的第一键合垫；贯穿所述第二键合层的第二键合垫；所述第一键合垫与第二键合垫相对键合连接。
  10. 一种半导体结构的形成方法，其特征在于，包括：
    提供第一基底；
    在所述第一基底表面形成第一键合层，所述第一键合层的材料为包含Si、N和C的介质材料。
  11. 根据权利要求10所述的半导体结构的形成方法，其特征在于，采用化学气 相沉积工艺形成所述第一键合层。
  12. 根据权利要求10所述的半导体结构的形成方法，其特征在于，所述第一键合层中，C的原子浓度大于0且小于50％。
  13. 根据权利要求10所述的半导体结构的形成方法，其特征在于，所述第一键合层中，C的原子浓度均匀分布。
  14. 根据权利要求10所述的半导体结构的形成方法，其特征在于，所述第一键合层中，C的原子浓度随第一键合层厚度增加而逐渐改变。
  15. 根据权利要求10所述的半导体结构的形成方法，其特征在于，所述第一键合层的致密度随厚度增加而逐渐改变。
  16. 根据权利要求10所述的半导体结构的形成方法，其特征在于，所述第一键合层的厚度大于
    Figure PCTCN2018093691-appb-100002
  17. 根据权利要求10所述的半导体结构的形成方法，其特征在于，还包括：
    提供第二基底；
    在所述第二基底表面形成第二键合层；
    将所述第二键合层表面与所述第一键合层表面相对键合固定。
  18. 根据权利要求17所述的半导体结构的形成方法，其特征在于，所述第二键合层与所述第一键合层的材料相同。
  19. 根据权利要求17所述的半导体结构的形成方法，其特征在于，还包括：形成贯穿所述第一键合层的第一键合垫；形成贯穿所述第二键合层的第二键合垫；在将所述第二键合层表面与所述第一键合层表面相对键合固定的同时，将所述第一键合垫与第二键合垫相对键合连接。
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