WO2020000231A1 - 记忆体驱动装置 - Google Patents

记忆体驱动装置 Download PDF

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Publication number
WO2020000231A1
WO2020000231A1 PCT/CN2018/092995 CN2018092995W WO2020000231A1 WO 2020000231 A1 WO2020000231 A1 WO 2020000231A1 CN 2018092995 W CN2018092995 W CN 2018092995W WO 2020000231 A1 WO2020000231 A1 WO 2020000231A1
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Prior art keywords
switch
terminal
signal
coupled
memory
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PCT/CN2018/092995
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English (en)
French (fr)
Inventor
吴瑞仁
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江苏时代全芯存储科技股份有限公司
江苏时代芯存半导体有限公司
铨芯科技股份有限公司
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Application filed by 江苏时代全芯存储科技股份有限公司, 江苏时代芯存半导体有限公司, 铨芯科技股份有限公司 filed Critical 江苏时代全芯存储科技股份有限公司
Priority to PCT/CN2018/092995 priority Critical patent/WO2020000231A1/zh
Priority to US17/255,434 priority patent/US11315632B2/en
Priority to CN201880083372.1A priority patent/CN112292727A/zh
Publication of WO2020000231A1 publication Critical patent/WO2020000231A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/003—Cell access
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0038—Power supply circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G11C2013/0076—Write operation performed depending on read result
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G11C2013/0092—Write characterized by the shape, e.g. form, length, amplitude of the write pulse
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/79—Array wherein the access device being a transistor

Definitions

  • the present disclosure relates to a memory driving device, and more particularly to a driving device for writing a phase change memory.
  • DRAM dynamic random access memory
  • SRAM static random access memory
  • memristive memory includes phase change memory (Phase change memory, PCM), which can change the resistance value of the element through the crystal phase change of its own material, and store the information with the change in resistance value.
  • PCM phase change memory
  • the memristive memory must perform the SET or RESET operation through the corresponding driving voltage / current.
  • the existing memory driving circuit cannot adaptively adjust the voltage of the driving operation in response to the resistance change of the memory, which will cause the crystal phase to change incompletely during the writing operation. Therefore, how to design a driving circuit suitable for memristive memory to adjust the driving operation voltage in response to the resistance change of the memory is one of the important research and development topics at present, and it has become a great need in the related field. Improvement goals.
  • the memory driving device includes a control circuit, a reference voltage generating circuit, and a first switch.
  • the control circuit is configured to generate a first signal according to the input signal.
  • the reference voltage generating circuit includes a reference resistor and is used to generate a reference signal according to the first signal.
  • the first switch is coupled to the memory resistance, and is used for generating a driving signal according to the reference signal to read and write the memory resistance.
  • the control circuit includes an inverter, a second switch, a current source, a capacitor, and an amplifier.
  • the first end of the inverter is used to receive an input signal.
  • the control terminal of the second switch is coupled to the second terminal of the inverter, and the first terminal of the second switch is coupled to the operating voltage.
  • the first terminal of the amplifier, the first terminal of the capacitor, the first terminal of the current source, and the second terminal of the second switch are coupled to the first node.
  • the reference voltage generating circuit further includes a third switch.
  • the control terminal of the third switch is coupled to the output terminal of the amplifier, and the first terminal of the third switch is coupled to the operating voltage.
  • the first terminal of the reference resistor, the second terminal of the amplifier, and the second terminal of the third switch are coupled to the second node.
  • control terminal of the first switch is coupled to the output terminal of the amplifier, the first terminal of the first switch is coupled to the operating voltage, and the second terminal of the first switch is coupled to the first terminal of the memory resistor. At the third node.
  • the inverter when the input signal is the first voltage level, the inverter generates a second voltage level according to the first voltage level to turn on the second switch, and the working voltage is transmitted to the first via the second switch. Node, when the first node is at the first voltage level, the output terminal of the amplifier outputs the second voltage level to turn on the first switch and the third switch.
  • the inverter when the input signal is at the second voltage level, the inverter generates the first voltage level according to the second voltage level, so that the second switch is not turned on, and the charge stored on the capacitor is passed through the current source. Discharge to reduce the voltage value of the first node.
  • the voltage value of the first node decreases, the voltage value of the output terminal of the amplifier increases, and the resistance value of the first switch and the resistance value of the third switch become larger, so that the second The voltage value of the node becomes smaller than that of the third node.
  • a feedback circuit is further included to generate a comparison signal according to the reference signal and the driving signal.
  • the control circuit controls the voltage value of the first signal according to the comparison signal.
  • a first terminal of the feedback circuit receives a reference signal
  • a second terminal of the feedback circuit receives a driving signal
  • an output terminal of the feedback circuit is coupled to the control circuit.
  • control circuit includes a fourth switch for adjusting a discharge current flowing through the fourth switch in response to the comparison signal.
  • the control circuit includes an inverter, a second switch, a third switch, a capacitor, a current source, and an amplifier.
  • the first end of the inverter is used to receive an input signal.
  • the control terminal of the second switch is coupled to the second terminal of the inverter, and the first terminal of the second switch is coupled to the operating voltage.
  • the first terminal of the current source is coupled to the first terminal of the fourth switch.
  • the first terminal of the amplifier, the first terminal of the capacitor, the second terminal of the second switch, and the second terminal of the fourth switch are coupled to the first node.
  • the present disclosure discloses a memory driving device, and more particularly, it relates to a driving device for writing a phase change memory, so as to adjust the driving of the write operation according to the resistance value of the phase change memory.
  • the voltage decrease time and the voltage value in the decrease time interval can self-correct the decrease time of the drive voltage of the write operation and the voltage value of the time interval to optimize the drive waveform of the write operation and further improve the reliability and success rate of the write operation. .
  • FIG. 1 is a schematic diagram of a memory device according to some embodiments of the disclosure.
  • FIG. 2 is a schematic diagram of an operating state of a memory unit according to some embodiments of the disclosure.
  • FIG. 3 is a schematic diagram of a write driving circuit according to some embodiments of the present disclosure.
  • FIG. 4 is an operation schematic diagram of a write driving circuit according to some embodiments of the present disclosure.
  • FIG. 5 is an operation schematic diagram of a write driving circuit according to some embodiments of the present disclosure.
  • FIG. 6 is an operation schematic diagram of a write driving circuit according to some embodiments of the present disclosure.
  • FIG. 7 is an experimental data diagram of driving signals according to some embodiments of the present disclosure.
  • FIG. 8 is an experimental data diagram of a first signal and a driving signal according to some embodiments of the present disclosure.
  • FIG. 1 is a schematic diagram of a memory device 100 according to some embodiments of the disclosure.
  • the memory device 100 includes a memory composed of a plurality of word lines WL1 to WLN and a plurality of bit lines BL1 to BLN.
  • the bit line driving circuit 130 includes a plurality of decoding circuits 140A to 140N and a plurality of write driving circuits 150A to 150N.
  • the controller 160 is coupled to the character line driving circuit 120 and the bit line driving circuit 130.
  • the character line driving circuit 120 is coupled to a plurality of character lines WL1 to WLN.
  • the bit line driving circuit 130 is coupled to a plurality of bit lines BL1 to BLN.
  • a plurality of write driving circuits 150A to 150N are coupled to the controller 160
  • a plurality of decoding circuits 140A to 140N are respectively coupled to one of the plurality of write driving circuits 150A to 150N
  • a plurality of The decoding circuits 140A to 140N are coupled to portions of the plurality of bit lines BL1 to BLN, respectively.
  • the memory array 100 includes a plurality of memory cells M11 to MNN. Each of the plurality of memory cells M11 to MNN is coupled between a corresponding bit line among the plurality of bit lines BL1 to BLN and a corresponding character line among the plurality of character lines WL1 to WLN.
  • Each of the plurality of memory units M11 to MNN includes a memory layer (not shown).
  • the memory layer is made of a specific material, wherein the specific material can have different electrical properties based on changes in its internal component states (eg, crystalline / amorphous, magnetic fields, etc.) based on external operating conditions.
  • the memory units M11 to MNN can equivalently store different data.
  • the memory units M11 to MNN may be phase change random access memory units, where the memory layer may be implemented by materials such as chalcogenides, but is not limited thereto. At different operating temperatures, the memory layer has different crystal states to equivalently store different data.
  • the above-mentioned types of the memory cells M11 to MNN and their implementation materials are merely examples.
  • Other forms of memory that can be used to implement the memory units M11 to MNN such as variable resistance random access memory (ReRAM), magnetoresistive random access memory (MRAM), etc. Covered.
  • ReRAM variable resistance random access memory
  • MRAM magnetoresistive random access memory
  • the decoding circuits 140A to 140N are operable as switches for controlling a memory layer.
  • one of the decoding circuits 140A to 140N is turned on, one of the memory cells M11 to MNN is equivalently selected. Under this condition, a bias voltage / current is applied to the memory layer of one of the selected memory cells M11 to MNN from the corresponding bit line to change the element state of the memory layer.
  • the numbers of the bit lines BL1 to BLN, the character lines WL1 to WLN, and the memory cells M11 to MNN in FIG. 1 described above are merely examples, and the present invention is not limited thereto.
  • the following paragraphs take the memory cells M11 to MNN implemented as phase change memory cells as an example, but as mentioned previously, the memory cells M11 to MNN in this case are not limited to phase change memory cells. .
  • FIG. 2 is a schematic diagram illustrating operation states of the memory units M11 to MNN according to some embodiments of the present invention.
  • a read pulse wave READ can be applied to the memory units M11 to MNN, and the current of the memory units M11 to MNN can be judged to identify the stored memory.
  • the data is data "1" or data "0".
  • a reset write pulse RESET is applied to the memory units M11 to MNN, the operating voltages of the memory units M11 to MNN will increase at a high speed, and the temperature of the phase change material of the memory units M11 to MNN will rise to melt. State, followed by rapid cooling of the operating voltage, so that the phase change material R1 is in an amorphous state. Under these conditions, the memory cells M11 to MNN have high resistance values.
  • the write pulse wave SET is applied to the memory cells M11 to MNN, as the voltage of the write pulse wave SET increases, the operating temperature of the memory layer of the memory cells M11 to MNN exceeds a specific temperature within a certain period of time.
  • the device state of the memory layer is crystalline. Under these conditions, the memory cells M11 to MNN have low resistance values.
  • the write pulse wave SET includes a rise time interval, a sustain time interval, and a decrease time interval.
  • the voltage value of the write pulse SET rapidly rises to the set value Vset during the time interval t0 to t1.
  • the voltage value of the write pulse wave SET is maintained at the set value Vset.
  • the voltage value of the write pulse wave SET drops to zero at a relatively slow speed. It can be known from physics theory that when the current flows, it has a heating effect on the phase change material.
  • the temperature it presents makes the phase change material crystallize slowly.
  • the temperature decrease helps the material to be in a stable crystalline state, so that the phase change material maintains a low resistance value.
  • the decrease time interval of the write pulse wave SET is longer, the memory cells M11 to MNN can be better crystallized, and then reach a lower resistance value.
  • FIG. 3 is a schematic diagram of a write driving circuit 300 according to some embodiments of the present disclosure.
  • the write driving circuit 300 is coupled to the decoding circuit 140, and the decoding circuit 140 is coupled to the memory unit M.
  • the write driving circuit 300 shown in FIG. 3 may be the write driving circuits 150A to 150N in FIG. 1
  • the decoding circuit 140 may be one of the decoding circuits 140A to 140N in FIG. 1
  • the memory unit M It may be one of the memory cells M11 to MNN in FIG. 1.
  • the memory unit M includes a switch Q4 and a memory resistance Rpcm.
  • the memory resistance Rpcm may be a resistance formed by the elements of the memory layer in the memory unit M after a write operation or a rewrite operation.
  • the write driving circuit 300 includes a control circuit 310, a reference voltage generating circuit 330, and a switch Q1.
  • the reference voltage generating circuit 330 includes a reference resistor Rref.
  • the control circuit 310 is coupled to the reference voltage generating circuit 330
  • the reference voltage generating circuit 330 is coupled to the switch Q1
  • the switch Q1 is coupled to the memory unit M.
  • control circuit 310 is configured to generate a first signal S2 according to the input signal S1.
  • the reference voltage generating circuit 330 is configured to generate a reference signal S3 according to the first signal S2.
  • the switch Q1 is used to generate a driving signal S4 according to the reference signal S3 to read and write the memory resistance Rpcm.
  • the fall time interval of the driving signal S4 will be greater than the fall time interval of the reference signal S3.
  • the control circuit 310 includes an inverter INV, a switch Q2, a current source CS, a capacitor C, and an amplifier A1.
  • the first terminal of the inverter INV is used to receive the input signal S1.
  • the control terminal of the switch Q2 is coupled to the second terminal of the inverter INV, and the first terminal of the switch Q2 is coupled to the operating voltage VDD.
  • the first terminal of the amplifier A1, the first terminal of the capacitor C, the first terminal of the current source CS, and the second terminal of the switch Q2 are coupled to the node N1.
  • the second terminal of the capacitor C and the second terminal of the current source CS are coupled to the ground.
  • the reference voltage generating circuit 330 further includes a switch Q3.
  • the control terminal of the switch Q3 is coupled to the output terminal of the amplifier A1, the first terminal of the switch Q3 is coupled to the operating voltage VDD, the second terminal of the switch Q3, the first terminal of the reference resistor Rref, and the amplifier A1 The second terminal is coupled to the node N2, and the second terminal of the reference resistor Rref is coupled to the ground.
  • the output of amplifier A1 is coupled to the second end of amplifier A1 via the switch Q3 feedback. In this way, amplifier A1 forms a negative feedback configuration, so the voltage behavior at node N2 will be equal to the voltage behavior at node N1. .
  • control terminal of the switch Q1 is coupled to the output terminal of the amplifier A1
  • first terminal of the switch Q1 is coupled to the operating voltage VDD
  • second terminal of the switch Q1 is coupled to the first terminal of the memory resistor Rpcm. ⁇ Node N3.
  • FIG. 4 is a schematic diagram illustrating an operation of the write driving circuit 300 according to some embodiments of the present disclosure.
  • FIG. 5 is a schematic diagram illustrating an operation of the write driving circuit 300 according to some embodiments of the present disclosure. It should be noted that, for the convenience of illustration, the following description will be made by using the switches Q1 to Q3 as P-type transistors, but the embodiments of the present invention are not limited thereto.
  • the input signal S1 is a sustaining time interval of the write pulse wave SET
  • the input signal S1 is a high voltage level.
  • the inverter INV generates a low voltage level according to the high voltage level. Since the control terminal of the switch Q2 is at a low voltage level, the switch Q2 is turned on. After the switch Q2 is turned on, the operating voltage VDD is transmitted to the node N1 via the switch Q2 to charge the capacitor C. Therefore, the node N1 is at a high voltage level.
  • the output terminal of the amplifier A1 outputs a low voltage level.
  • the switches Q1 and Q3 Since the control terminals of the switches Q1 and Q3 are both at a low voltage level, the switches Q1 and Q3 are turned on. After the switches Q1 and Q3 are turned on, the operating voltage VDD is transmitted to the node N2 and the node N3 through the switches Q1 and Q3.
  • the input signal S1 is a decrease time interval of the write pulse wave SET, the voltage level of the input signal S1 gradually decreases.
  • the inverter INV generates a high voltage level according to the low voltage level. Since the control terminal of the switch Q2 is at a high voltage level, the switch Q2 is not turned on. At this time, the charge stored in the capacitor C is discharged through the current source CS, and thus the voltage value of the node N1 gradually decreases.
  • the voltage value at the node N1 gradually decreases, the voltage value at the output of the amplifier A1 gradually increases.
  • the equivalent resistance values of the switches Q1 and Q3 gradually increase, and the voltage values of the nodes N2 and N3 gradually decrease.
  • the amplifier A1 can be regarded as a voltage follower in the write driving circuit 300, the voltage value of the node N2 is the same as the voltage value of the node N1. That is, the node N2 reflects the voltage value of the node N1, so that the voltage value of the reference signal S3 of the node N2 is the same as the voltage value of the first signal S2 of the node N1.
  • the switch Q1 is the same as the switch Q3. Since the switch Q1 and the switch Q3 receive the same output voltage from the output terminal of the amplifier A1, the switch Q1 and the switch Q3 can be regarded as including the same equivalent resistance value.
  • the input signal S1 is in the falling time interval of the write pulse SET, if the resistance value of the memory resistance Rpcm is the same or slightly smaller than the resistance value of the reference resistance Rref, the voltage value of the driving signal S4 of the node N3 and the reference signal of the node N2 The voltage value of S3 is the same.
  • the voltage value of the driving signal S4 at the node N3 is greater than the voltage value of the reference signal S3 at the node N2.
  • FIG. 7 is an experimental data diagram of the driving signal S4 according to some embodiments of the present disclosure. As shown in FIG. 7, it is assumed that the pulse wave of the first signal S2 is as shown by the pulse wave SET1.
  • the pulse wave of the driving signal S4 is shown as the pulse wave SET2, and the pulse wave of the reference signal S3 is the same as the first signal S2. That is, the lowering time interval of the driving signal S4 is longer than the lowering time interval of the reference signal S3, and during the lowering time interval, the voltage value of the driving signal S4 is higher than the voltage value of the reference signal S3.
  • the drive signal S4 can set the memory resistance Rpcm with a higher voltage value and extend the decrease time of the write pulse SET so that the memory resistance Rpcm can reach a better crystalline state.
  • the resistance value of the memory resistance Rpcm gradually decreases, and the voltage value of the node N3 also decreases.
  • FIG. 6 is a schematic operation diagram of a write driving circuit 600 according to some embodiments of the present disclosure.
  • the write driving circuit 600 is coupled to the decoding circuit 140, and the decoding circuit 140 is coupled to the memory unit M.
  • the write driving circuit 600 shown in FIG. 6 may be the write driving circuits 150A to 150N in FIG. 1
  • the decoding circuit 140 may be one of the decoding circuits 140A to 140N in FIG. 1
  • the memory unit M It may be one of the memory cells M11 to MNN in FIG. 1.
  • the write driving circuit 600 includes a control circuit 610, a reference voltage generating circuit 630, a feedback circuit 650, and a switch Q1.
  • the control circuit 610 is coupled to the reference voltage generating circuit 630
  • the reference voltage generating circuit 630 is coupled to the switch Q1
  • the switch Q1 is coupled to the memory unit M
  • the feedback circuit 650 is coupled to the control circuit 610, The reference voltage generating circuit 630 and the switch Q1.
  • the control circuit 610 is used for generating the first signal S2 according to the input signal S1.
  • the reference voltage generating circuit 630 is configured to generate a reference signal S3 according to the first signal S2.
  • the switch Q1 is used to generate a driving signal S4 according to the reference signal S3 to read and write the memory resistance Rpcm.
  • the feedback circuit 650 is configured to generate a comparison signal S5 according to the reference signal S3 and the driving signal S4, and output the comparison signal S5 to the control circuit 610.
  • the control circuit 610 further controls the voltage value of the first signal S2 according to the comparison signal S5.
  • the control circuit 610 includes an inverter INV, a switch Q2, a current source CS, a capacitor C, an amplifier A1, and a switch Q5.
  • the first terminal of the inverter INV is used to receive the input signal S1
  • the output terminal of the amplifier A1 is coupled to the reference voltage generating circuit 630.
  • the control terminal of the switch Q2 is coupled to the second terminal of the inverter INV, and the first terminal of the switch Q2 is coupled to the operating voltage VDD.
  • the first terminal of the amplifier A1, the first terminal of the capacitor C, the first terminal of the switch Q5, and the second terminal of the switch Q2 are coupled to the node N1.
  • the second terminal of the switch Q5 is coupled to the first terminal of the current source CS.
  • the second terminal of the capacitor C and the second terminal of the current source CS are coupled to the ground.
  • the switches Q1 to Q3 are P-type transistors and the switch Q5 is an N-type transistor.
  • the embodiment of the present invention is not limited thereto.
  • connection mode and detailed structure of the switch Q1 and the reference voltage generating circuit 630 are substantially the same as those of the switch Q1 and the reference voltage generating circuit 330 in FIG. 3, and are not repeated here.
  • the feedback circuit 350 includes a comparator A2.
  • the first terminal of the comparator A2 is coupled to the node N2
  • the second terminal of the comparator A2 is coupled to the node N3
  • the output terminal of the comparator A2 is coupled to the control terminal of the switch Q5.
  • the first end of the comparator A2 receives the reference signal S3, and the second end of the comparator A2 receives the driving signal S4. After comparing the reference signal S3 and the driving signal S4, the comparator A2 generates a comparison signal S5, and then The output terminal of the comparator A2 outputs a comparison signal S5 to the control circuit 610.
  • the switch Q5 adjusts the discharge current flowing through the switch Q5 corresponding to the comparison signal S5.
  • the input signal S1 is a sustain time interval of the write pulse wave SET
  • the input signal S1 is at a high voltage level.
  • the inverter INV generates a low voltage level according to the high voltage level. Since the control terminal of the switch Q2 is at a low voltage level, the switch Q2 is turned on. After the switch Q2 is turned on, the operating voltage VDD is transmitted to the node N1 via the switch Q2 and charges the capacitor C. At this time, the node N1 is at a high voltage level. When the node N1 is at a high voltage level, the output terminal of the amplifier INV outputs a low voltage level.
  • the switches Q1 and Q3 Since the control terminals of the switches Q1 and Q3 are both at a low voltage level, the switches Q1 and Q3 are turned on. After the switches Q1 and Q3 are turned on, the operating voltage VDD is transmitted to the node N2 and the node N3 through the switches Q1 and Q3.
  • the voltage level of the input signal S1 gradually decreases.
  • the inverter INV When the input signal S1 is at a low voltage level, the inverter INV generates a high voltage level according to the low voltage level. Since the control terminal of the switch Q2 is at a high voltage level, the switch Q2 is not turned on. At this time, the charge stored on the capacitor C is discharged through the switch Q5 through the current source CS, and the voltage value of the node N1 is gradually reduced accordingly. As the voltage value at the node N1 gradually decreases, the voltage value at the output of the amplifier INV gradually increases. As the voltage values of the control terminals of the switches Q1 and Q3 gradually increase, the equivalent resistance values of the switches Q1 and Q3 gradually increase, and then the voltage values of the nodes N2 and N3 gradually decrease.
  • the reference signal S3 is smaller than the driving signal S4, and the voltage value of the comparison signal S5 is therefore smaller.
  • the voltage value at the control terminal of the switch Q5 is low, so the conduction degree of the switch Q5 is low, and the current flowing through the voltage source CS is small.
  • the voltage value of the first signal S2 of the node N1 decreases more slowly, and the voltage value of the driving signal S4 of the node N3 decreases more slowly, thereby further reducing the time interval of the driving signal S4.
  • the voltage value of the memory resistance Rpcm decreases.
  • the voltage value of the driving signal S4 of the node N3 decreases, and the voltage value of the comparison signal S5 is high.
  • the voltage value at the control terminal of the switch Q5 is higher, and therefore the conduction degree of the switch Q5 is higher, which further causes the current flowing through the voltage source CS to be larger, until the voltage value of the node N1 drops to zero.
  • the pulse wave of the first signal S2 is as shown by the pulse wave SET1.
  • the pulse wave of the driving signal S4 is shown as the pulse wave SET3, and the pulse wave of the reference signal S3 is the same as the first signal S2. That is, the lowering time interval of the driving signal S4 is longer than the lowering time interval of the reference signal S3, and during the lowering time interval, the voltage value of the driving signal S4 is higher than the voltage value of the reference signal S3.
  • the decrease time interval of the write drive circuit 600 is longer, and the voltage drop speed of the drive signal S4 is slower.
  • FIG. 8 is a graph 800 of experimental data of the first signal S2 and the driving signal S4 according to some embodiments of the present disclosure.
  • the driving signal S4A is the voltage value of the driving signal S4 measured when the resistance of the memory resistor Rpcm is the same as the resistance of the reference resistor Rref.
  • the driving signal S4B is a voltage value of the driving signal S4 measured when the resistance of the memory resistor Rpcm is slightly greater than the resistance of the reference resistor Rref.
  • the driving signal S4C is a voltage value of the driving signal S4 measured when the resistance of the memory resistor Rpcm is greater than the resistance of the reference resistor Rref. It can be known from FIG.
  • the voltage value of the driving signal S4 is the same as the voltage value of the first signal S2.
  • the decrease time interval of the driving signal S4 is longer than the decrease time interval of the first signal S2, and the voltage value of the drive signal S4 is also greater than the decrease time interval. The voltage value of the first signal S2.
  • the embodiments of the present invention disclose a memory driving device, and more particularly, a driving device for writing a phase change memory, so as to adjust the drive of the write operation according to the resistance value of the phase change memory.
  • the voltage decrease time and the voltage value in the decrease time interval are provided.
  • the memory driving device of the present disclosure can self-correct the decrease time of the drive voltage of the write operation and the voltage value of the time interval to optimize the drive waveform of the write operation and further improve the write operation. Reliability and success rate.

Abstract

一种记忆体驱动装置于此揭露。此记忆体驱动装置包含控制电路、参考电压产生电路以及第一开关。控制电路用以依据输入信号产生第一信号。参考电压产生电路包含参考电阻，并用以依据第一信号产生参考信号。第一开关与记忆体电阻相耦接，用以依据第一信号产生驱动信号以读写记忆体电阻。当输入信号降低，且记忆体电阻的电阻值大于参考电阻的电阻值时，驱动信号的降低时间大于参考信号的降低时间。

Description

记忆体驱动装置 技术领域
本揭示内容是关于一种记忆体驱动装置，特别是关于一种用以写入一种相变记忆体的驱动装置。
背景技术
现有的记忆体技术，如动态随机存取记忆体(DRAM)以及静态随机存取记忆体(SRAM)等等的发展渐趋成熟，从而面临到尺度上的物理极限。因此，发展新的记忆体技术以符合未来记忆体应用为目前相关领域重要的研发课题。
于记忆体技术中，忆阻性记忆体包含相变化记忆体(Phase change memory，PCM)，其可通过本身材料的晶相变化改变元件电阻值，以电阻值的变化储存信息，当记忆元件中的材料为结晶态时，其呈现低电阻值，反之，当为非结晶态时，其呈现高电阻值，借以储存如“1”或“0”的数据。
举例而言，忆阻性记忆体须透过相应的驱动电压/电流以执行设置写入(SET)或重置写入(RESET)的操作。然而，现有的记忆体驱动电路无法因应相变化记忆体的电阻值而适应性地调整驱动操作的电压，这将于写入操作时造成晶相变化不完全。因此，如何能在设计出适用于忆阻性记忆体的驱动电路，以因应相变化记忆体的电阻值而调整驱动操作的电压，实属当前重要研发课题之一，亦成为当前相关领域极需改进的目标。
发明内容
本揭示内容的一态样为一记忆体驱动装置。此记忆体驱动装置包含控制电路、参考电压产生电路以及第一开关。控制电路用以依据输入信号产生第一信号。参考电压产生电路包含参考电阻，并用以依据第一信号产生参考信号。第一开关与记忆体电阻相耦接，用以依据参考信号产生驱动信号以读写记忆体电阻。当输入信号降低，且记忆体电阻的电阻值大于参考电阻的电阻值时，驱动信号的降低时间大于参考信号的降低时间。
在一些实施例中，控制电路包含反向器、第二开关、电流源、电容以及放大器。反向器的第一端用以接收输入信号。第二开关的控制端耦接于反向器的 第二端，第二开关的第一端耦接于工作电压。放大器的第一端、电容的第一端、电流源的第一端以及第二开关的第二端耦接于第一节点。
在一些实施例中，参考电压产生电路还包含第三开关。第三开关的控制端耦接于放大器的输出端，第三开关的第一端耦接于工作电压。参考电阻的第一端、放大器的第二端以及第三开关的第二端耦接于第二节点。
在一些实施例中，第一开关的控制端耦接于放大器的输出端，第一开关的第一端耦接于工作电压，第一开关的第二端与记忆体电阻的第一端耦接于第三节点。
在一些实施例中，当输入信号为第一电压准位时，反向器依据第一电压准位产生第二电压准位，以导通第二开关，工作电压经由第二开关传送至第一节点，当第一节点为第一电压准位时，放大器的输出端输出第二电压准位，以导通第一开关与第三开关。
在一些实施例中，当输入信号为第二电压准位时，反向器依据第二电压准位产生第一电压准位，以使第二开关不导通，电容上储存的电荷经由电流源放电，以降低第一节点的电压值，当第一节点的电压值降低时，放大器的输出端的电压值升高，第一开关的电阻值与第三开关的电阻值变大，以使第二节点的电压值与第三节点的电压值变小。
在一些实施例中，还包含回授电路，用以依据参考信号以及驱动信号产生比较信号。控制电路依据比较信号控制第一信号的电压值。
在一些实施例中，回授电路的第一端接收参考信号，回授电路的第二端接收驱动信号，且回授电路的输出端耦接于控制电路。
在一些实施例中，控制电路包含第四开关，用以相应于比较信号调整流经第四开关的放电电流。
在一些实施例中，其中控制电路包含反向器、第二开关、第三开关、电容、电流源以及放大器。反向器的第一端用以接收输入信号。第二开关的控制端耦接于反向器的第二端，第二开关的第一端耦接于工作电压。电流源的第一端耦接于第四开关的第一端。放大器的第一端、电容的第一端、第二开关的第二端以及第四开关的第二端耦接于第一节点。
综上所述，本揭示内容揭示一种记忆体驱动装置，特别是关于一种用以写入一种相变记忆体的驱动装置，借以因应相变记忆体的电阻值调整写入操作的 驱动电压的降低时间以及降低时间区间的电压值。此外，本揭示的记忆体驱动装置可自我校正写入操作的驱动电压的降低时间以及降低时间区间的电压值，以优化写入操作的驱动波形，并进而提高写入操作的可靠性与成功率。
附图说明
图1为根据本案的一些实施例所绘示的一种记忆体装置的示意图；
图2为根据本案的一些实施例所绘示的记忆体单元的操作状态的示意图；
图3为根据本揭示内容一些实施例所绘示的写入驱动电路的示意图；
图4为根据本揭示内容一些实施例所绘示的写入驱动电路的操作示意图；
图5为根据本揭示内容一些实施例所绘示的写入驱动电路的操作示意图；
图6为根据本揭示内容一些实施例所绘示的写入驱动电路的操作示意图；
图7为根据本揭示内容一些实施例所绘示的驱动信号的实验数据图；
图8为根据本揭示内容一些实施例所绘示的第一信号与驱动信号的实验数据图。
具体实施方式
下文是举实施例配合所附附图作详细说明，以更好地理解本案的态样，但所提供的实施例并非用以限制本揭示内容所涵盖的范围，而结构操作的描述非用以限制其执行的顺序，任何由元件重新组合的结构，所产生具有均等功效的装置，皆为本揭示内容所涵盖的范围。此外，根据业界的标准及惯常做法，附图仅以辅助说明为目的，并未依照原尺寸作图，实际上各种特征的尺寸可任意地增加或减少以便于说明。下述说明中相同元件将以相同的符号标示来进行说明以便于理解。
在全篇说明书与权利要求书所使用的用词(terms)，除有特别注明外，通常具有每个用词使用在此领域中、在此揭露的内容中与特殊内容中的平常意义。某些用以描述本揭示内容的用词将于下或在此说明书的别处讨论，以提供本领域技术人员在有关本揭示内容的描述上额外的引导。
此外，在本文中所使用的用词“包含”、“包括”、“具有”、“含有”等等，均为开放性的用语，即意指“包含但不限于”。此外，本文中所使用的“及/或”，包含相关列举项目中一或多个项目的任意一个以及其所有组合。
于本文中，当一元件被称为“连接”或“耦接”时，可指“电性连接”或“电性耦接”。“连接”或“耦接”亦可用以表示二或多个元件间相互搭配操作或互动。此外，虽然本文中使用“第一”、“第二”、…等用语描述不同元件，该用语仅是用以区别以相同技术用语描述的元件或操作。除非上下文清楚指明，否则该用语并非特别指称或暗示次序或顺位，亦非用以限定本发明。
请参考图1。图1为根据本案的一些实施例所绘示的一种记忆体装置100的示意图。以相变化记忆体(PCM)为例，如图1所示，记忆体装置100包含由多条字符线(word line)WL1至WLN与多条位线(bit line)BL1至BLN所组成的记忆体阵列110、字符线驱动电路120、位线驱动电路130、控制器160。位线驱动电路130包含多个解码电路140A至140N以及多个写入驱动电路150A至150N。
于连接关系上，控制器160与字符线驱动电路120以及位线驱动电路130相耦接。字符线驱动电路120与多条字符线WL1至WLN相耦接。位线驱动电路130与多条位线BL1至BLN相耦接。详细而言，多个写入驱动电路150A至150N与控制器160相耦接，多个解码电路140A至140N分别与多个写入驱动电路150A至150N中的一者相耦接，而多个解码电路140A至140N分别与多条位线BL1至BLN中的部分相耦接。此外，记忆体阵列100包含多个记忆体单元M11至MNN。多个记忆体单元M11至MNN中的每一者耦接于多条位线BL1至BLN中的一对应位线以及多条字符线WL1至WLN中的一对应字符线之间。
多个记忆体单元M11至MNN中的每一者皆包含记忆层(未绘示)。记忆层由特定材料制成，其中此特定材料可基于外部操作条件改变其内部元件状态(例如：晶态/非晶态、磁场等等)而具有不同的电性。如此，依据记忆层所呈现的不同电性(例如：电阻、磁阻等等)，记忆体单元M11至MNN可等效储存不同的数据。举例而言，在一些实施例中，记忆体单元M11至MNN可为相变化(phase change)随机存取式记忆体单元，其中记忆层可由硫族化物等材料实现，但不限于此。在不同的操作温度下，记忆层具有不同的结晶状态，以等效储存不同的数据。
上述关于记忆体单元M11至MNN的类型以及其实施材料仅为示例。可用于实现记忆体单元M11至MNN的其他形式的记忆体，例如包含可变式电 阻随机存取式记忆体(ReRAM)、磁阻式随机存取式记忆体(MRAM)等等，皆为本案所涵盖的范围。
请再参阅图1。解码电路140A至140N可操作为用于控制记忆层的开关。解码电路140A至140N中的一者导通时，记忆体单元M11至MNN中的一者等效被选取。于此条件下，偏压电压/电流自对应的位线施加至被选取的记忆体单元M11至MNN中的一者的记忆层，以改变此记忆层的元件状态。
上述图1中的位线BL1至BLN、字符线WL1至WLN以及记忆体单元M11至MNN的数量仅为示例，本案并不以此为限。
为易于说明，以下段落以记忆体单元M11至MNN由相变式记忆体单元实施为例说明，但如先前所述，本案的记忆体单元M11至MNN并不仅以相变式记忆体单元为限。
请参阅图2。图2为根据本案的一些实施例所绘示的记忆体单元M11至MNN的操作状态的示意图。
如图2所示，当欲读取记忆体单元M11至MNN时，可在记忆体单元M11至MNN上施加一读取脉波READ，并判别记忆体单元M11至MNN的电流大小以辨别所储存的数据是数据“1”或数据“0”。
此外，若在记忆体单元M11至MNN施加一重置写入脉波RESET，记忆体单元M11至MNN的操作电压将高速上升，记忆体单元M11至MNN的相变化材料的温度随之上升到熔融状态，接着操作电压快速冷却，而使相变化材料R1呈非结晶态(amorphous)。于此条件下，记忆体单元M11至MNN具有高阻值。
另一方面，若在记忆体单元M11至MNN施加写入脉波SET，随着写入脉波SET的电压上升，记忆体单元M11至MNN的记忆层的操作温度在一定期间内超过特定温度后，记忆层的元件状态为晶态(crystalline)。于此条件下，记忆体单元M11至MNN具有低阻值。
详细而言，如图2所示，写入脉波SET包含上升时间区间、维持时间区间以及降低时间区间。于上升时间区间t0至t1，写入脉波SET的电压值于时间区间t0至t1快速上升至设置值Vset。于时间区间t1至t2，写入脉波SET的电压值维持在设置值Vset。于时间区间t2至t3，写入脉波SET的电压值以较为缓慢的速度下降至零。由物理学理上可知，当电流流动时，对相变化材料 有加温的作用，在写入脉波SET的电压值为设置值Vset时，其所呈现的温度使相变化材料结晶化，而缓慢的降温有助于材料处于稳定的结晶态，以使相变化材料维持低的电阻值。也就是说，当写入脉波SET的降低时间区间较长时，记忆体单元M11至MNN可较佳的结晶化，并进而达到较低的电阻值。
请参阅图3。图3为根据本揭示内容一些实施例所绘示的写入驱动电路300的示意图。如图3所绘示，写入驱动电路300耦接于解码电路140，而解码电路140又耦接于记忆体单元M。如图3所绘示的写入驱动电路300可为图1中的写入驱动电路150A至150N，解码电路140可为图1中的解码电路140A至140N中的一者，而记忆体单元M可为图1中的记忆体单元M11至MNN中的一者。
记忆体单元M包含开关Q4以及记忆体电阻Rpcm。记忆体电阻Rpcm可为记忆体单元M中的记忆层的元件经由写入操作或重新写入操作后所形成的电阻。
写入驱动电路300包含控制电路310、参考电压产生电路330以及开关Q1。参考电压产生电路330包含参考电阻Rref。于连接关系上，控制电路310耦接于参考电压产生电路330，参考电压产生电路330耦接于开关Q1，而开关Q1耦接于记忆体单元M。
于操作关系上，控制电路310用以依据输入信号S1产生第一信号S2。参考电压产生电路330用以依据第一信号S2产生参考信号S3。开关Q1用以依据参考信号S3产生驱动信号S4以读写记忆体电阻Rpcm。当记忆体电阻Rpcm的电阻值大于参考电阻Rref的电阻值时，驱动信号S4的降低时间区间会大于参考信号S3的降低时间区间。
在一些实施例中，如图3所绘示，控制电路310包含反向器INV、开关Q2、电流源CS、电容C以及放大器A1。于连接关系上，反向器INV的第一端用以接收输入信号S1。开关Q2的控制端耦接于反向器INV的第二端，开关Q2的第一端耦接于工作电压VDD。放大器A1的第一端、电容C的第一端、电流源CS的第一端以及开关Q2的第二端耦接于节点N1。电容C的第二端以及电流源CS的第二端耦接于地。
在一些实施例中，参考电压产生电路330还包含开关Q3。于连接关系上，开关Q3的控制端耦接于放大器A1的输出端，开关Q3的第一端耦接于工作 电压VDD，开关Q3的第二端、参考电阻Rref的第一端以及放大器A1的第二端耦接于节点N2，而参考电阻Rref的第二端耦接于地。简单言之，放大器A1的输出端经由开关Q3回授耦接于放大器A1的第二端，如此放大器A1形成负回授组态，因此节点N2上的电压行为会等同于节点N1上的电压行为。
在一些实施例中，开关Q1的控制端耦接于放大器A1的输出端，开关Q1的第一端耦接于工作电压VDD，开关Q1的第二端与记忆体电阻Rpcm的第一端耦接于节点N3。
关于写入驱动电路300的详细操作方式将于以下配合图4与图5进行说明。图4为根据本揭示内容一些实施例所绘示的写入驱动电路300的操作示意图。图5为根据本揭示内容一些实施例所绘示的写入驱动电路300的操作示意图。需注意的是，为了便于例示说明，以下将以开关Q1至Q3为P型晶体管进行说明，然而本案的实施方式并不以此为限。
请参阅图4。当输入信号S1为写入脉波SET的维持时间区间时，输入信号S1为高电压准位。此时，反向器INV依据高电压准位产生低电压准位。由于开关Q2的控制端为低电压准位，开关Q2导通。开关Q2导通后，工作电压VDD经由开关Q2传送至节点N1而对电容C充电，因此，节点N1为高电压准位。当节点N1为高电压准位时，放大器A1的输出端输出低电压准位。由于开关Q1与开关Q3的控制端均为低电压准位，开关Q1与开关Q3导通。于开关Q1与开关Q3导通后，工作电压VDD经由开关Q1与开关Q3传送至节点N2与节点N3。
请参阅图5。当输入信号S1为写入脉波SET的降低时间区间时，输入信号S1的电压准位逐渐降低。当输入信号S1为低电压准位时，反向器INV依据低电压准位产生高电压准位。由于开关Q2的控制端为高电压准位，开关Q2不导通。此时电容C里储存的电荷经由电流源CS放电，节点N1的电压值因此逐渐降低。随着节点N1的电压值逐渐降低，放大器A1的输出端的电压值逐渐升高。由于开关Q1与开关Q3的控制端的电压值逐渐升高，开关Q1与开关Q3的等效电阻值逐渐变大，并进而使节点N2与节点N3的电压值逐渐变小。
详细而言，由于放大器A1于写入驱动电路300中可视为电压随耦器(voltage follower)，节点N2的电压值与节点N1的电压值相同。即节点N2会 反映(mirror)节点N1的电压值，以使节点N2的参考信号S3的电压值与节点N1的第一信号S2的电压值相同。
接着，假设开关Q1与开关Q3相同，由于开关Q1与开关Q3由放大器A1的输出端接收相同的输出电压，开关Q1与开关Q3可视为包含相同的等效电阻值。当输入信号S1位于写入脉波SET的降低时间区间时，若是记忆体电阻Rpcm的电阻值相同或略小于参考电阻Rref的电阻值，节点N3的驱动信号S4的电压值与节点N2的参考信号S3的电压值相同。另一方面，若是记忆体电阻Rpcm的电阻值大于参考电阻Rref的电阻值，节点N3的驱动信号S4的电压值大于节点N2的参考信号S3的电压值。
请一并参阅图7。图7为根据本揭示内容一些实施例所绘示的驱动信号S4的实验数据图。如图7所绘示，假设第一信号S2的脉波如脉波SET1所示，于写入驱动电路300的实施例中，当记忆体电阻Rpcm的电阻值大于参考电阻Rref的电阻值时，驱动信号S4的脉波如脉波SET2所示，而参考信号S3的脉波与第一信号S2相同。也就是说，驱动信号S4的降低时间区间较参考信号S3的降低时间区间长，且于降低时间区间，驱动信号S4的电压值较参考信号S3的电压值高。
如此一来，驱动信号S4即可用较高的电压值设定记忆体电阻Rpcm，并延长写入脉波SET的降低时间，以使记忆体电阻Rpcm可达到较佳的结晶状态。而随着记忆体电阻Rpcm逐渐达到较佳的结晶状态，记忆体电阻Rpcm的电阻值逐渐降低，节点N3的电压值亦随之降低。
请回头参阅图6。图6为根据本揭示内容一些实施例所绘示的写入驱动电路600的操作示意图。如图3所绘示，写入驱动电路600耦接于解码电路140，而解码电路140又耦接于记忆体单元M。如图6所绘示的写入驱动电路600可为图1中的写入驱动电路150A至150N，解码电路140可为图1中的解码电路140A至140N中的一者，而记忆体单元M可为图1中的记忆体单元M11至MNN中的一者。
写入驱动电路600包含控制电路610、参考电压产生电路630、回授电路650以及开关Q1。于连接关系上，控制电路610耦接于参考电压产生电路630，参考电压产生电路630耦接于开关Q1，开关Q1耦接于记忆体单元M，而回授电路650耦接于控制电路610、参考电压产生电路630以及开关Q1。
于操作关系上，控制电路610用以依据输入信号S1产生第一信号S2。参考电压产生电路630用以依据第一信号S2产生参考信号S3。开关Q1用以依据参考信号S3产生驱动信号S4以读写记忆体电阻Rpcm。回授电路650用以依据参考信号S3以及驱动信号S4产生比较信号S5，并输出比较信号S5至控制电路610。控制电路610更依据比较信号S5以控制第一信号S2的电压值。当输入信号S1降低，且记忆体电阻Rpcm的电阻值大于参考电阻Rref的电阻值时，驱动信号S4的降低时间大于参考信号S3的降低时间。
在一些实施例中，如图6所绘示，控制电路610包含反向器INV、开关Q2、电流源CS、电容C、放大器A1以及开关Q5。于连接关系上，反向器INV的第一端用以接收输入信号S1，放大器A1的输出端耦接于参考电压产生电路630。开关Q2的控制端耦接于反向器INV的第二端，开关Q2的第一端耦接于工作电压VDD。放大器A1的第一端、电容C的第一端、开关Q5的第一端以及开关Q2的第二端耦接于节点N1。开关Q5的第二端耦接于电流源CS的第一端。电容C的第二端以及电流源CS的第二端耦接于地。
需注意的是，为了便于例示说明，于图6中，开关Q1至Q3为P型晶体管，而开关Q5为N型晶体管，然而本案的实施方式并不以此为限。
开关Q1以及参考电压产生电路630的连接方式与详细结构大致上与图3中的开关Q1以及参考电压产生电路330相同，在此不重复叙述。
在一些实施例中，回授电路350包含比较器A2。于连接关系上，比较器A2的第一端耦接于节点N2，比较器A2的第二端耦接于节点N3，而比较器A2的输出端耦接于开关Q5的控制端。
于操作关系上，比较器A2的第一端接收参考信号S3，比较器A2的的第二端接收驱动信号S4，于比较参考信号S3与驱动信号S4之后，比较器A2产生比较信号S5，接着，比较器A2的输出端输出比较信号S5至控制电路610。开关Q5相应于比较信号S5调整流经该开关Q5的放电电流。
详细而言，当输入信号S1为写入脉波SET的维持时间区间时，输入信号S1为高电压准位。此时，反向器INV依据高电压准位产生低电压准位。由于开关Q2的控制端为低电压准位，开关Q2导通。开关Q2导通后，工作电压VDD经由开关Q2传送至节点N1并对电容C充电。此时，节点N1为高电压准位。当节点N1为高电压准位时，放大器INV的输出端输出低电压准位。由 于开关Q1与开关Q3的控制端均为低电压准位，开关Q1与开关Q3导通。于开关Q1与开关Q3导通后，工作电压VDD经由开关Q1与开关Q3传送至节点N2与节点N3。
另一方面，当输入信号S1为写入脉波SET的降低时间区间时，输入信号S1的电压准位逐渐降低。当输入信号S1为低电压准位时，反向器INV依据低电压准位产生高电压准位。由于开关Q2的控制端为高电压准位，开关Q2不导通。此时电容C上储存的电荷通过电流源CS经开关Q5放电，节点N1的电压值因此而逐渐降低。随着节点N1的电压值逐渐降低，放大器INV的输出端的电压值逐渐升高。由于开关Q1与开关Q3的控制端的电压值逐渐升高，开关Q1与开关Q3的等效电阻值逐渐变大，并进而使节点N2与节点N3的电压值逐渐变小。
当记忆体电阻Rpcm的电阻值大于参考电阻Rref的电阻值时，参考信号S3小于驱动信号S4，比较信号S5的电压值因而较小。此时，开关Q5的控制端的电压值较低，因而开关Q5的导通程度较低，进而使流经电压源CS的电流较小。如此一来，节点N1的第一信号S2的电压值的下降速度较慢，而节点N3的驱动信号S4的电压值的下降速度亦较慢，并进而使驱动信号S4的降低时间区间较长。
于记忆体电阻Rpcm较佳的结晶化之后，记忆体电阻Rpcm的电压值降低。此时，节点N3的驱动信号S4的电压值降低，比较信号S5的电压值较高。此时，开关Q5的控制端的电压值较高，因而开关Q5的导通程度较高，进而使流经电压源CS的电流较大，直到节点N1的电压值降至零。
请参阅图7。如图7所绘示，假设第一信号S2的脉波如脉波SET1所示，于写入驱动电路600的实施例中，当记忆体电阻Rpcm的电阻值大于参考电阻Rref的电阻值时，驱动信号S4的脉波如脉波SET3所示，而参考信号S3的脉波与第一信号S2相同。也就是说，驱动信号S4的降低时间区间较参考信号S3的降低时间区间长，且于降低时间区间，驱动信号S4的电压值较参考信号S3的电压值高。此外，相较于写入驱动电路300的实施例，写入驱动电路600的降低时间区间更长，且驱动信号S4的电压下降速度较缓。
请参阅图8。图8为根据本揭示内容一些实施例所绘示的第一信号S2与驱动信号S4的实验数据图800。驱动信号S4A为记忆体电阻Rpcm的电阻值 与参考电阻Rref的电阻值相同的情况下所测得驱动信号S4的电压值。驱动信号S4B为记忆体电阻Rpcm的电阻值略大于参考电阻Rref的电阻值的情况下所测得驱动信号S4的电压值。驱动信号S4C为记忆体电阻Rpcm的电阻值更大于参考电阻Rref的电阻值的情况下所测得驱动信号S4的电压值。由图8可得知，当记忆体电阻Rpcm的电阻值与参考电阻Rref的电阻值相同时，驱动信号S4的电压值与第一信号S2的电压值相同。而当记忆体电阻Rpcm的电阻值大于参考电阻Rref的电阻值时，驱动信号S4的降低时间区间较第一信号S2的降低时间区间长，且于降低时间区间，驱动信号S4的电压值亦大于第一信号S2的电压值。
由上述可知，本案的实施方式揭示一种记忆体驱动装置，特别是关于一种用以写入一种相变记忆体的驱动装置，借以因应相变记忆体的电阻值调整写入操作的驱动电压的降低时间以及降低时间区间的电压值。此外，透过回授电路，本揭示的记忆体驱动装置可自我校正写入操作的驱动电压的降低时间以及降低时间区间的电压值，以优化写入操作的驱动波形，并进而提高写入操作的可靠性与成功率。
虽然本揭示内容已以实施方式揭露如上，然其并非用以限定本揭示内容，任何熟悉此技艺者，在不脱离本揭示内容的精神和范围内，当可作各种更动与润饰，因此本揭示内容的保护范围当视所附的权利要求书所界定的范围为准。

Claims (10)

  1. 一种记忆体驱动装置，包含：
    一控制电路，用以依据一输入信号产生一第一信号；
    一参考电压产生电路，包含一参考电阻，并用以依据该第一信号产生一参考信号；以及
    一第一开关，与一记忆体电阻相耦接，用以依据该参考信号产生一驱动信号以读写该记忆体电阻；
    其中当该输入信号降低，且该记忆体电阻的电阻值大于该参考电阻的电阻值时，该驱动信号的降低时间大于该参考信号的降低时间。
  2. 根据权利要求1所述的记忆体驱动装置，其中该控制电路包含：
    一反向器，该反向器的一第一端用以接收该输入信号；
    一第二开关，该第二开关的一控制端耦接于该反向器的一第二端，该第二开关的一第一端耦接于一工作电压；
    一电流源；
    一电容；以及
    一放大器；
    其中该放大器的一第一端、该电容的一第一端、该电流源的一第一端以及该第二开关的一第二端耦接于一第一节点。
  3. 根据权利要求2所述的记忆体驱动装置，其中该参考电压产生电路还包含：
    一第三开关，其中该第三开关的一控制端耦接于该放大器的一输出端，该第三开关的一第一端耦接于该工作电压；
    其中该参考电阻的一第一端、该放大器的一第二端以及该第三开关的一第二端耦接于一第二节点。
  4. 根据权利要求2所述的记忆体驱动装置，其中该第一开关的一控制端耦接于该放大器的该输出端，该第一开关的一第一端耦接于该工作电压，该第一开关的一第二端与该记忆体电阻的一第一端耦接于一第三节点。
  5. 根据权利要求3所述的记忆体驱动装置，其中当该输入信号为一第一电压准位时，该反向器依据该第一电压准位产生一第二电压准位，以导通该第二开关，该工作电压经由该第二开关传送至该第一节点，当该第一节点为该第一电压准位时，该放大器的该输出端输出该第二电压准位，以导通该第一开关与该第三开关。
  6. 根据权利要求5所述的记忆体驱动装置，其中当该输入信号为该第二电压准位时，该反向器依据该第二电压准位产生该第一电压准位，以使该第二开关不导通，该电容上所储存的电荷经由该电流源元件放电，以降低该第一节点的电压值，当该第一节点的电压值降低时，该放大器的该输出端的电压值升高，该第一开关的电阻值与该第三开关的电阻值变大，以使该第二节点的电压值与该第三节点的电压值变小。
  7. 根据权利要求1所述的记忆体驱动装置，还包含：
    一回授电路，用以依据该参考信号以及该驱动信号产生一比较信号；
    其中该控制电路依据该比较信号控制该第一信号的电压值。
  8. 根据权利要求7所述的记忆体驱动装置，其中该回授电路的一第一端接收该参考信号，该回授电路的一第二端接收该驱动信号，且该回授电路的一输出端耦接于该控制电路。
  9. 根据权利要求8所述的记忆体驱动装置，其中该控制电路包含：
    一第四开关，用以相应于该比较信号调整流经该第四开关的一放电电流。
  10. 根据权利要求1所述的记忆体驱动装置，其中该控制电路包含：
    一反向器，该反向器的一第一端用以接收该输入信号；
    一第二开关，该第二开关的一控制端耦接于该反向器的一第二端，该第二开关的一第一端耦接于一工作电压；
    一第四开关；
    一电容；
    一电流源，该电流源的一第一端耦接于该第三开关的一第一端；以及
    一放大器，
    其中该放大器的一第一端、该电容的一第一端、该第二开关的一第二端以及该第四开关的一第二端耦接于一第一节点。
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