WO2019242255A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2019242255A1
WO2019242255A1 PCT/CN2018/121215 CN2018121215W WO2019242255A1 WO 2019242255 A1 WO2019242255 A1 WO 2019242255A1 CN 2018121215 W CN2018121215 W CN 2018121215W WO 2019242255 A1 WO2019242255 A1 WO 2019242255A1
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Prior art keywords
switch
pixel
coupled
sub
display panel
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PCT/CN2018/121215
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English (en)
French (fr)
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单剑锋
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惠科股份有限公司
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Publication of WO2019242255A1 publication Critical patent/WO2019242255A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • the present application relates to the field of display, and in particular, to a display panel and a display device.
  • Liquid crystal display devices have the advantages of low cost, low power consumption, and high performance, and have been widely used in electronics and digital products.
  • the driving of the pixel circuit in the display device needs to be implemented by driving the corresponding scanning lines and data lines through the gate driving circuit and the source driving circuit.
  • GOA Gate Driver Onon Array
  • HSD Half Source Driver
  • HSD technology halves the number of data lines and doubles the number of scan lines, so that each data line corresponds to two columns of adjacent pixel circuits. This technology can save half of the source driver chip. However, this technology also has certain shortcomings. Because the same data line connects two columns of pixel circuits, and the number of scanning lines doubles, the scanning time of the pixel circuit is shortened, which is prone to insufficient driving capacity, inconsistent charging efficiency, and parasitic capacitance between pixel circuits Problems such as imbalance and delay and distortion of signal waveforms cause the display device to have large viewing angles, vertical bright and dark lines, and other phenomena. If multi-domain or multi-region display with main pixels and sub-pixels is considered, the HSD technology is more difficult to implement.
  • An object of the present application is to provide a display panel and a display device, including but not limited to overcoming the problems and defects of the above-mentioned HSD technology.
  • a display panel including:
  • a pixel region which is divided into a main pixel region and a sub-pixel region; a plurality of data lines;
  • a plurality of pixel groups are disposed in the pixel area, and each of the pixel groups includes:
  • the first pixel circuit includes:
  • a first switch a control end of the first switch is coupled to a first scan line, a first end is coupled to a first data line, and a second end is coupled to a first sub-pixel;
  • a second switch the control end of the second switch is coupled to the first scan line, the first end is coupled to the first data line, and the second end is coupled to the first main pixel;
  • the second pixel circuit includes:
  • a third switch the control end of the third switch is coupled to the second scan line, the first end is coupled to the first data line, and the second end is coupled to the second sub-pixel;
  • a fourth switch the control end of the fourth switch is coupled to the second scan line, the first end is coupled to the first data line, and the second end is coupled to the second main pixel;
  • the first switch and the second switch are located in the same column, and the third switch and the fourth switch are located in the same column;
  • the first switch and the third switch are located in a sub-pixel area
  • the second switch and the fourth switch are located in a main pixel area
  • an area of the sub-pixel area is greater than or equal to an area of the main pixel area.
  • the first sub-pixel is located in the same row as the second main pixel, and the second sub-pixel is located in the same row as the first main pixel.
  • the first sub-pixel and the second sub-pixel are located in the same row, and the second main pixel and the first main pixel are located in the same row.
  • the ratio of the area of the main pixel area to the area of the sub-pixel area is 1: 1, 1: 2, 2: 3, or 4: 6.
  • the sub-pixel region and the main pixel region are in a checkerboard configuration, a cross configuration, or a grid configuration.
  • the scan line is a periodic multi-segment polyline design.
  • the sub-pixel region and the main pixel region are arranged in a cross configuration, and the boundary of the display panel is a non-linear pixel arrangement.
  • the display panel is applied to a non-rectangular display device.
  • the non-rectangular display device includes a vehicle-mounted display device.
  • the sub-pixel area and the main pixel area are in a checkerboard configuration or a grid configuration, and a boundary of the display panel is a linear design.
  • the display panel is applied to a rectangular display device.
  • the first scanning line is turned on, and the first switch and the second switch are charged and discharged; during the second scanning period, the second scanning line is turned on , The third switch and the fourth switch perform charging and discharging.
  • the first scanning period and the second scanning period are adjacent scanning periods.
  • the polarities of adjacent main pixel regions and the sub-pixel regions located in the same row and coupled to the same data line are different.
  • each of the pixel groups further includes a plurality of capacitors, and the second ends of the first switch, the second switch, the third switch, and the fourth switch are each connected to one of the capacitors.
  • the positive electrode of the capacitor is coupled, and the negative electrode of the capacitor is grounded.
  • the 2n-1 scanning lines and the 2n scanning lines are arranged adjacent to each other, and the 2n scanning lines and the 2n + 1 scanning lines are spaced apart; wherein, n ⁇ 1 and n is an integer.
  • Another object of the present application is to provide a display panel, including:
  • a pixel region which is divided into a main pixel region and a sub-pixel region
  • a plurality of pixel groups are disposed in the pixel area, and each of the pixel groups includes:
  • the first pixel circuit includes:
  • a first switch a control end of the first switch is coupled to a first scan line, a first end is coupled to a first data line, and a second end is coupled to a first sub-pixel;
  • a second switch the control end of the second switch is coupled to the first scan line, the first end is coupled to the first data line, and the second end is coupled to the first main pixel;
  • the second pixel circuit includes:
  • a third switch the control end of the third switch is coupled to the second scan line, the first end is coupled to the first data line, and the second end is coupled to the second sub-pixel;
  • a fourth switch the control end of the fourth switch is coupled to the second scan line, the first end is coupled to the first data line, and the second end is coupled to the second main pixel;
  • the first switch and the second switch are located in the same column, the third switch and the fourth switch are located in the same column, and the first scan line and the second scan line are adjacently configured or Interval configuration
  • the first switch and the third switch are located in a sub-pixel area
  • the second switch and the fourth switch are located in a main pixel area, and an area of the sub-pixel area is greater than or equal to an area of the main pixel area;
  • the sub-pixel area and the main pixel area are in a checkerboard configuration or a grid configuration, and a boundary of the display panel is a linear design, and the display panel is applied to a rectangular display device.
  • Another object of the present application is to provide a display device, including:
  • Display panel including:
  • a pixel region which is divided into a main pixel region and a sub-pixel region
  • a plurality of pixel groups are disposed in the pixel area, and each of the pixel groups includes:
  • the first pixel circuit includes:
  • a first switch a control end of the first switch is coupled to a first scan line, a first end is coupled to a first data line, and a second end is coupled to a first sub-pixel;
  • a second switch the control end of the second switch is coupled to the first scan line, the first end is coupled to the first data line, and the second end is coupled to the first main pixel;
  • the second pixel circuit includes:
  • a third switch the control end of the third switch is coupled to the second scan line, the first end is coupled to the first data line, and the second end is coupled to the second sub-pixel;
  • a fourth switch the control end of the fourth switch is coupled to the second scan line, the first end is coupled to the first data line, and the second end is coupled to the second main pixel;
  • the first switch and the second switch are located in the same column, and the third switch and the fourth switch are located in the same column;
  • the first switch and the third switch are located in a sub-pixel area
  • the second switch and the fourth switch are located in a main pixel area, and an area of the sub-pixel area is greater than or equal to an area of the main pixel area;
  • the display panel is coupled to the gate driving circuit through the plurality of scan lines, and the display panel is coupled to the source driving circuit through the plurality of data lines.
  • the design of the pixel circuit and the structure can enhance the charging efficiency of the HSD display panel, solve the problem of large viewing role deviation, and improve the stability and quality of the display panel.
  • FIG. 1 is a schematic diagram of an exemplary pixel circuit
  • FIG. 2 is a schematic diagram of a pixel circuit according to an embodiment of the present application.
  • FIG. 3 is a schematic diagram of a pixel structure according to an embodiment of the present application.
  • FIG. 4 is a schematic diagram of pixel polarity arrangement according to an embodiment of the present application.
  • FIG. 5 is a schematic diagram of a pixel structure according to another embodiment of the present application.
  • FIG. 6 is a schematic diagram of pixel polarity arrangement according to another embodiment of the present application.
  • FIG. 7 is a schematic diagram of a pixel circuit according to still another embodiment of the present application.
  • FIG. 8 is a schematic diagram of a pixel structure according to another embodiment of the present application.
  • FIG. 9 is a schematic diagram of pixel polarity arrangement according to another embodiment of the present application.
  • FIG. 10 is a block diagram of a display device according to an embodiment of the present application.
  • FIG. 1 is a schematic diagram of an exemplary pixel circuit. Please refer to FIG. 1.
  • An exemplary pixel circuit 10 includes: a plurality of scanning lines (Gn, Gn + 1, Gn + 2, Gn + 3); a plurality of data lines (Dm, Dm + 1), and The scanning lines Gn are arranged crosswise, where n and m are positive integers greater than 1.
  • Multiple active switches 110 are respectively coupled to the corresponding scanning lines and data lines. Among them, the left and right adjacent active switches are coupled to the same data line. And different scanning lines are coupled, so that the number of data lines is halved and the number of scanning lines is doubled; and a plurality of capacitors 130 are respectively coupled to active switches and pixels.
  • This circuit is designed as HSD (Half Source Driver) technology, which can reduce the number of Source Driver ICs and save costs. Because the same data line connects two columns of pixel circuits, and the number of scanning lines doubles, the scanning time of the pixel circuits is shortened, which is prone to insufficient driving capacity, inconsistent charging efficiency, imbalance of parasitic capacitance between pixel circuits, and delay distortion of signal waveforms. Problems, and cause the display device to appear large role deviation, vertical bright and dark lines and other phenomena. For example, the pixel circuits of the odd-numbered columns driven first have insufficient charging and lower brightness, and the pixel circuits of the even-numbered columns driven later have better charging and higher brightness, causing bright and dark lines.
  • HSD Half Source Driver
  • FIG. 2 is a schematic diagram of a pixel circuit according to an embodiment of the application
  • FIG. 3 is a schematic diagram of a pixel polarity arrangement according to an embodiment of the application
  • FIG. 4 is a schematic diagram of a pixel polarity arrangement according to an embodiment of the application. Please refer to FIG. 2 to FIG. 4 at the same time.
  • a display panel 20 is provided, including:
  • a pixel region including a main pixel region and a sub-pixel region
  • a plurality of pixel groups 100 are disposed in the pixel area, and each of the pixel groups 100 includes:
  • the first pixel circuit includes:
  • a first switch 111 a control terminal of the first switch 111 is coupled to the first scan line Gn, a first terminal is coupled to the first data line Dm, and a second terminal is coupled to the first sub-pixel 121;
  • a second switch 112 a control terminal of the second switch 112 is coupled to the first scan line Gn, a first terminal is coupled to the first data line Dm, and a second terminal is coupled to the first main pixel 122;
  • the second pixel circuit includes:
  • a third switch 113 a control terminal of the third switch 113 is coupled to the second scan line Gn + 1, a first terminal is coupled to the first data line Dm, and a second terminal is coupled to the second sub-pixel 123;
  • a fourth switch 114 a control end of the fourth switch 114 is coupled to the second scan line Gn + 1, a first end is coupled to the first data line Dm, and a second end is coupled to the second main pixel 124;
  • the first switch 111 and the second switch 112 are located in the same column, and the third switch 113 and the fourth switch 114 are located in the same column;
  • the first switch 111 and the third switch 113 are located in a sub-pixel area
  • the second switch 112 and the fourth switch 114 are located in a main pixel area
  • an area of the sub-pixel area is greater than or equal to the main pixel The area of the area.
  • the first sub-pixel 121 and the second main pixel 124 are located in the same row, and the second sub-pixel 123 and the first main pixel 122 are located in the same row.
  • a ratio of an area of the main pixel region to an area of the sub-pixel region is 1: 1, 1: 2, 2: 3, or 4: 6.
  • each of the pixel groups further includes four capacitors 130, the first switch 111, the second switch 112, the third switch 113, and all capacitors.
  • the second ends of the fourth switches 114 are each coupled to at least one positive electrode of the capacitor 130, and the negative electrode of the capacitor 130 is grounded.
  • the 2n-1th scanning line and the 2nth scanning line are arranged adjacently, and the 2nth scanning line and the 2n + 1th scanning line are arranged at intervals; where n ⁇ 1 and n is Integer.
  • the first scanning line Gn is turned on, and the first switch 111 and the second switch 112 are charged and discharged; during the second scanning period, all The second scan line Gn + 1 is turned on, and the third switch 113 and the fourth switch 114 are charged and discharged; wherein the first scan period and the second scan period are adjacent scan periods.
  • the polarities of adjacent main pixel regions and the sub-pixel regions located in the same row and coupled to the same data line Dm are different. As shown in FIG. 4, in each pixel group 100, two pixel regions in the same row have different polarities, and two pixel regions in the same column have the same polarity.
  • the sub-pixel area and the main pixel area are in a checkerboard configuration, a cross configuration, or a grid configuration.
  • the arrangement manner of the sub-pixel area and the main pixel area is a cross arrangement, and a pixel arrangement with a non-linear design is arranged at the boundary. This design can be applied to non-rectangular display devices. Such as vehicle display devices.
  • FIG. 5 is a schematic diagram of a pixel structure according to another embodiment of the present application
  • FIG. 6 is a schematic diagram of a pixel polarity arrangement according to another embodiment of the present application.
  • a display panel 30 having a pixel area, the pixel area is divided into a main pixel area and a sub-pixel area, and includes: a plurality of pixel groups 100 disposed in the pixel area,
  • Each of the pixel groups 100 includes a first pixel circuit including a first switch 111, a control terminal of the first switch 111 is coupled to a first scan line Gn, a first terminal is coupled to a first data line Dm, The two terminals are coupled to the first sub-pixel 121; the second switch 112, the control terminal of the second switch 112 is coupled to the first scan line Gn, the first terminal is coupled to the first data line Dm, and the second terminal is coupled to the first
  • the second pixel circuit includes:
  • the first switch 111 and the second switch 112 are located in the same column, and the third switch 113 and the fourth switch 114 are located in the same column.
  • the first switch 111 and the third switch 113 are located in a sub-pixel area
  • the second switch 112 and the fourth switch 114 are located in a main pixel area
  • an area of the sub-pixel area is greater than or equal to the main pixel The area of the area.
  • the boundary of the display panel 30 is a linear design, which can be applied to a rectangular display device.
  • the corresponding scanning line Gn is a multi-segment polyline design.
  • the scan line may be, for example, a periodic multi-segment polyline design. In this embodiment, each period is a four-segment polyline.
  • FIG. 7 is a schematic diagram of a pixel circuit according to another embodiment of the application
  • FIG. 8 is a schematic diagram of a pixel structure according to another embodiment of the application
  • FIG. 9 is a schematic diagram of pixel polarity arrangement according to another embodiment of the application. Please refer to FIG. 7 to FIG. 9 at the same time.
  • a display panel 40 has a pixel area, and the pixel area is divided into a main pixel area and a sub-pixel area, including: a plurality of data lines Dm; Scan lines Gn; a plurality of pixel groups 100 are disposed in the pixel area, and each of the pixel groups 100 includes a first pixel circuit including a first switch 111, and a control terminal of the first switch 111 is coupled A first scan line Gn, a first terminal coupled to the first data line Dm, a second terminal coupled to the first sub-pixel 121, and a second switch 112, a control terminal of the second switch 112 is coupled to the first scan line Gn, The first terminal is coupled to the first data line Dm, and the second terminal is coupled to the first main pixel 122.
  • the second pixel circuit includes a third switch 113, and a control terminal of the third switch 113 is coupled to the second scan line Gn. +1, the first terminal is coupled to the first data line Dm, the second terminal is coupled to the second sub-pixel 123; the fourth switch 114, the control terminal of the fourth switch 114 is coupled to the second scan line Gn + 1, the first One end is coupled to the first data line Dm, and the second end is coupled to the second main pixel 124.
  • the nth scan line and the n + 1th scan line are arranged at intervals, as shown in FIG. 7. Since one pixel area is spaced between two scanning lines arranged at intervals, the possibility of short circuit of the pixel circuit can be reduced, and the stability and quality of the product can be improved.
  • the first main pixel 122 and the second main pixel 124 are located in the same row, and the first sub-pixel 121 and the second sub-pixel 123 are located in the same row.
  • the pixel circuit in each embodiment and the combination of the main pixel and the sub-pixel can solve the problem of large viewing role deviation of the HSD display panel and improve the display effect.
  • the display panel of the present application may be, for example, a liquid crystal display panel, but it is not limited thereto, and may also be an OLED display panel, a W-OLED display panel, a QLED display panel, a plasma display panel, or a curved display panel. Or other types of display panels.
  • FIG. 10 is a schematic structural diagram of a display device according to an embodiment of the present application. Please refer to FIG. 2 to FIG. 10 at the same time.
  • a display device 1 includes a display panel 2, a Timing Controller (TCON) 3, a gate driving circuit 4 and a source driving circuit 5;
  • the display panel 2 is coupled to the gate driving circuit 4 through the plurality of scanning lines, and the display panel 2 is coupled to the source driving circuit 5 through the plurality of data lines.
  • the display panel 2 may be, for example, the display panel (20, 30, 40) described in the above embodiments.
  • the source driving circuit may be any device or circuit having a function of driving data of pixels of a display panel, for example, a source driver chip (IC) or a thin film source driver chip (S-COF, Source-Chip (on Film).
  • the gate driving circuit may be any device or circuit having a function of progressively scanning and charging the pixels of the display panel, for example, a gate driver IC (Gate Driver IC) or a thin film gate driver chip (G-COF, Gate- Chip, Film, etc.
  • the design of the pixel circuit and the structure in this application can enhance the charging efficiency of the HSD display panel, solve the problem of large viewing roles, and improve the stability and quality of the display panel.

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Abstract

一种显示面板(2,20,30,40)及显示装置(1)，显示面板(2,20,30,40)包括：像素区域，像素区域被划分为主像素区域和子像素区域；多条数据线(Dm)；多条扫描线(Gn)；多个像素组(100)，设置于像素区域，每一像素组(100)包括：第一像素电路，第二像素电路；子像素区域的面积大于或等于主像素区域的面积。

Description

显示面板及显示装置
本申请要求于2018年06月22日提交中国专利局，申请号为201810652505.4，申请名称为“显示面板及显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示领域，特别涉及一种显示面板及显示装置。
背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然构成现有技术。液晶显示装置，具有低成本、低功耗和高性能的优点，在电子、数码产品等领域有着广泛的运用。而显示装置中像素电路的驱动，则需通过栅极驱动电路和源极驱动电路驱动相应的扫描线和数据线加以实现。随着面板尺寸，解析度，及大视角影像品质的需求提高，并进一步提高用户体验及节约成本，各产商开发了很多有关显示领域的制造技术，如GOA(Gate Driver on Array)电路设计，HSD(Half Source Driver，半源极驱动)技术。
HSD技术，其将数据线的数量减半，扫描线的数量加倍，以此使得每一数据线对应连接两列相邻的像素电路，通过此技术，可以节约一半的源极驱动芯片。但此技术亦存在一定的缺陷，由于同一数据线连接两列像素电路，且数量加倍的扫描线使得像素电路的扫描时间缩短，容易出现驱动能力不足，充电效率不一致，像素电路之间的寄生电容不平衡及信号波形的延迟失真等问题，并导致显示装置出现大视角色偏，垂直亮暗线等现象。如若考虑主像素和子像素搭配的多畴或多区域显示，则HSD技术更不容易实现。
申请内容
本申请的一个目的在于提供一种一种显示面板及显示装置，包括但不限于 克服上述HSD技术存在的问题和缺陷。
本申请实施例采用的技术方案是：
提供一种显示面板，包括：
像素区域，所述像素区域被划分为主像素区域和子像素区域；多条数据线；
多条扫描线；
多个像素组，设置于所述像素区域，每一所述像素组包括：
第一像素电路，包括：
第一开关，所述第一开关的控制端耦接第一扫描线，第一端耦接第一数据线，第二端耦接第一子像素；
第二开关，所述第二开关的控制端耦接第一扫描线，第一端耦接第一数据线，第二端耦接第一主像素；
第二像素电路，包括：
第三开关，所述第三开关的控制端耦接第二扫描线，第一端耦接第一数据线，第二端耦接第二子像素；
第四开关，所述第四开关的控制端耦接第二扫描线，第一端耦接第一数据线，第二端耦接第二主像素；
其中，所述第一开关和所述第二开关位于同一列，所述第三开关和所述第四开关位于同一列；
所述第一开关和所述第三开关位于子像素区域，所述第二开关和所述第四开关位于主像素区域，所述子像素区域的面积大于或等于所述主像素区域的面积。
在一个实施例中，所述第一子像素与所述第二主像素位于同一行，所述第二子像素与所述第一主像素位于同一行。
在一个实施例中，所述第一子像素与所述第二子像素位于同一行，所述第二主像素与所述第一主像素位于同一行。
在一个实施例中，所述主像素区域的面积与所述子像素区域的面积比例为 1:1，1:2，2:3或4:6。
在一个实施例中，所述子像素区域和所述主像素区域为棋盘配置，交叉配置或网格配置。
在一个实施例中，依据所述主像素区域和所述子像素区域的面积关系及配置，所述扫描线为周期性的多段折线设计。
在一个实施例中，所述子像素区域与所述主像素区域的排布方式为交叉配置，所述显示面板的边界为非直线型设计的像素排列。
在一个实施例中，所述显示面板应用于非矩形显示装置。
在一个实施例中，所述非矩形显示装置包括车载显示装置。
在一个实施例中，所述子像素区域和所述主像素区域为棋盘配置或网格配置，所述显示面板的边界为为直线型设计。
在一个实施例中，所述显示面板应用于矩形显示装置。
在一个实施例中，在第一扫描周期内，所述第一扫描线打开，所述第一开关和所述第二开关进行充放电；在第二扫描周期内，所述第二扫描线打开，所述第三开关和所述第四开关进行充放电。
在一个实施例中，所述第一扫描周期和所述第二扫描周期为相邻的扫描周期。
在一个实施例中，位于同一行且耦接相同数据线的相邻所述主像素区域和所述子像素区域的极性为相异。
在一个实施例中，每一所述像素组还包括多个电容，所述第一开关、所述第二开关、所述第三开关和所述第四开关的第二端各与一个所述电容的正极耦接，所述电容的负极接地。
在一个实施例中，所述多条扫描线中，第2n-1条扫描线和第2n条扫描线相邻设置，第2n条扫描线和第2n+1条扫描线间隔设置；其中，n≥1且n为整数。
本申请的另一目的在于提供一种显示面板，包括：
像素区域，所述像素区域被划分为主像素区域和子像素区域；
多条数据线；
多条扫描线；
多个像素组，设置于所述像素区域，每一所述像素组包括：
第一像素电路，包括：
第一开关，所述第一开关的控制端耦接第一扫描线，第一端耦接第一数据线，第二端耦接第一子像素；
第二开关，所述第二开关的控制端耦接第一扫描线，第一端耦接第一数据线，第二端耦接第一主像素；
第二像素电路，包括：
第三开关，所述第三开关的控制端耦接第二扫描线，第一端耦接第一数据线，第二端耦接第二子像素；
第四开关，所述第四开关的控制端耦接第二扫描线，第一端耦接第一数据线，第二端耦接第二主像素；
其中，所述第一开关和所述第二开关位于同一列，所述第三开关和所述第四开关位于同一列，所述第一扫描线和所述第二扫描线为相邻配置或间隔配置；
所述第一开关和所述第三开关位于子像素区域，所述第二开关和所述第四开关位于主像素区域，所述子像素区域的面积大于或等于所述主像素区域的面积；
位于同一行且耦接相同数据线的相邻所述主像素区域和所述子像素区域的极性为相异；
所述子像素区域和所述主像素区域为棋盘配置或网格配置，所述显示面板的边界为为直线型设计，所述显示面板应用于矩形显示装置。
本申请的再一目的在于提供一种显示装置，包括：
栅极驱动电路；
源极驱动电路；以及
显示面板，包括：
像素区域，所述像素区域被划分为主像素区域和子像素区域；
多条数据线；
多条扫描线；
多个像素组，设置于所述像素区域，每一所述像素组包括：
第一像素电路，包括：
第一开关，所述第一开关的控制端耦接第一扫描线，第一端耦接第一数据线，第二端耦接第一子像素；
第二开关，所述第二开关的控制端耦接第一扫描线，第一端耦接第一数据线，第二端耦接第一主像素；
第二像素电路，包括：
第三开关，所述第三开关的控制端耦接第二扫描线，第一端耦接第一数据线，第二端耦接第二子像素；
第四开关，所述第四开关的控制端耦接第二扫描线，第一端耦接第一数据线，第二端耦接第二主像素；
其中，所述第一开关和所述第二开关位于同一列，所述第三开关和所述第四开关位于同一列；
所述第一开关和所述第三开关位于子像素区域，所述第二开关和所述第四开关位于主像素区域，所述子像素区域的面积大于或等于所述主像素区域的面积；
所述显示面板通过所述多条扫描线与所述栅极驱动电路耦接，所述显示面板通过所述多条数据线与所述源极驱动电路耦接。
本申请实施例通过像素电路及结构的设计，可以增强HSD显示面板的充电效率，解决大视角色偏问题，提高显示面板的稳定性及品质。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例或示范性技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图。
图1为范例性的像素电路示意图；
图2为本申请一实施例的像素电路示意图；
图3为本申请一实施例的像素结构示意图；
图4为本申请一实施例的像素极性排列示意图；
图5为本申请又一实施例的像素结构示意图；
图6为本申请又一实施例的像素极性排列示意图；
图7为本申请再一实施例的像素电路示意图；
图8为本申请再一实施例的像素结构示意图；
图9为本申请再一实施例的像素极性排列示意图；
图10为本申请一实施例的显示装置模块图。
具体实施方式
为了使本申请的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本申请进行进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
需说明的是，当部件被称为“固定于”或“设置于”另一个部件，它可以直接在另一个部件上或者间接在该另一个部件上。当一个部件被称为是“连接于”另一个部件，它可以是直接或者间接连接至该另一个部件上。术语“上”、“下”、“左”、“右”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制，对于本领域的普通技术人员而言，可以根据具体情况理解上述术语的具体含义。术语“第一”、“第二”仅用于便于描述目的，而不能理解为指示或暗示相对重要性或者 隐含指明技术特征的数量。“多个”的含义是两个或两个以上，除非另有明确具体的限定。
为了说明本申请所述的技术方案，以下结合具体附图及实施例进行详细说明。
图1为范例性的像素电路示意图。请参考图1，一种范例性的像素电路10，包括：多条扫描线(Gn，Gn+1，Gn+2，Gn+3)；多条数据线(Dm，Dm+1)，与所述扫描线Gn交叉配置，其中，n，m为大于1的正整数；多个主动开关110，分别耦接对应的扫描线和数据线；其中，左右相邻的主动开关耦接同一数据线，并耦接不同扫描线，以此使得数据线的数量减半，扫描线的数量加倍；以及多个电容130，分别耦接主动开关和像素。此电路设计为HSD(Half Source Driver，半源极驱动)技术，可以减少源极驱动芯片(Source Driver IC)的数量，并节约成本。由于同一数据线连接两列像素电路，且数量加倍的扫描线使得像素电路的扫描时间缩短，容易出现驱动能力不足，充电效率不一致，像素电路之间的寄生电容不平衡及信号波形的延迟失真等问题，并导致显示装置出现大视角色偏，垂直亮暗线等现象。如：先驱动的奇数列的像素电路由于充电较为不足，亮度较低，而后驱动的偶数列像素电路充电较好，亮度较高，造成亮暗线问题。
图2为本申请一实施例的像素电路示意图，图3为本申请一实施例的像素极性排列示意图及图4为本申请一实施例的像素极性排列示意图。请同时参考图2至图4，在本申请的一实施例中，提供一种显示面板20，包括：
像素区域，所述像素区域区包括主像素区域和子像素区域；
多条数据线Dm；
多条扫描线Gn；
多个像素组100，设置于所述像素区域，每一所述像素组100包括：
第一像素电路，包括：
第一开关111，所述第一开关111的控制端耦接第一扫描线Gn，第一端 耦接第一数据线Dm，第二端耦接第一子像素121；
第二开关112，所述第二开关112的控制端耦接第一扫描线Gn，第一端耦接第一数据线Dm，第二端耦接第一主像素122；
第二像素电路，包括：
第三开关113，所述第三开关113的控制端耦接第二扫描线Gn+1，第一端耦接第一数据线Dm，第二端耦接第二子像素123；
第四开关114，所述第四开关114的控制端耦接第二扫描线Gn+1，第一端耦接第一数据线Dm，第二端耦接第二主像素124；
其中，所述第一开关111和所述第二开关112位于同一列，所述第三开关113和所述第四开关114位于同一列；
所述第一开关111和所述第三开关113位于子像素区域，所述第二开关112和所述第四开关114位于主像素区域，所述子像素区域的面积大于或等于所述主像素区域的面积。
在本申请的一实施例中，所述第一子像素121与所述第二主像素124位于同一行，所述第二子像素123与所述第一主像素122位于同一行。
在本申请的一实施例中，所述主像素区域的面积与所述子像素区域的面积比例为1:1，1:2，2:3或4:6。
如图2所示，在本申请的一实施例中，每一所述像素组还包括四个电容130，所述第一开关111、所述第二开关112、所述第三开关113和所述第四开关114的第二端各与至少一个所述电容130的正极耦接，所述电容130的负极接地。
在本申请的一实施例中，第2n-1条扫描线和第2n条扫描线相邻设置，第2n条扫描线和第2n+1条扫描线间隔设置；其中，n≥1且n为整数。
在本申请的一实施例中，在第一扫描周期内，所述第一扫描线Gn打开，所述第一开关111和所述第二开关112进行充放电；在第二扫描周期内，所述第二扫描线Gn+1打开，所述第三开关113和所述第四开关114进行充放电； 其中，所述第一扫描周期和所述第二扫描周期为相邻的扫描周期。
在一些实施例中，位于同一行且耦接相同数据线Dm的相邻所述主像素区域和所述子像素区域的极性为相异。如图4所示，在每一像素组100中，位于同一行的两像素区域极性相异，位于同一列的两像素区域极性相同。
在一些实施例中，所述子像素区域和所述主像素区域为棋盘配置，交叉配置或网格配置。请参考图2至图4，所述子像素区域与所述主像素区域的排布方式为交叉配置，在其边界为非直线型设计的像素排列，此设计可适用于非矩形显示装置上，如车载显示装置等。
图5为本申请又一实施例的像素结构示意图及图6为本申请又一实施例的像素极性排列示意图。请同时参考图2，图5和图6，一种显示面板30，具有像素区域，所述像素区域区分为主像素区域和子像素区域，包括：多个像素组100，设置于所述像素区域，每一所述像素组100包括：第一像素电路，包括：第一开关111，所述第一开关111的控制端耦接第一扫描线Gn，第一端耦接第一数据线Dm，第二端耦接第一子像素121；第二开关112，所述第二开关112的控制端耦接第一扫描线Gn，第一端耦接第一数据线Dm，第二端耦接第一主像素122；第二像素电路，包括：第三开关113，所述第三开关113的控制端耦接第二扫描线Gn+1，第一端耦接第一数据线Dm，第二端耦接第二子像素123；第四开关114，所述第四开关114的控制端耦接第二扫描线Gn+1，第一端耦接第一数据线Dm，第二端耦接第二主像素124。其中，所述第一开关111和所述第二开关112位于同一列，所述第三开关113和所述第四开关114位于同一列。所述第一开关111和所述第三开关113位于子像素区域，所述第二开关112和所述第四开关114位于主像素区域，所述子像素区域的面积大于或等于所述主像素区域的面积。其中，所述显示面板30的边界为直线型设计，可适用于矩形显示装置。
在本申请的一实施例中，为符合所述显示面板30直线型设计的边界，对应扫描线Gn为多段折线设计。其中，所述扫描线可例如为周期性的多段折线 设计，于此实施例中，每一周期为四段折线。
图7为本申请再一实施例的像素电路示意图，图8为本申请再一实施例的像素结构示意图及图9为本申请再一实施例的像素极性排列示意图。请同时参考图7至图9，在本申请的一实施例中，一种显示面板40，具有像素区域，所述像素区域区分为主像素区域和子像素区域，包括：多条数据线Dm；多条扫描线Gn；多个像素组100，设置于所述像素区域，每一所述像素组100包括：第一像素电路，包括：第一开关111，所述第一开关111的控制端耦接第一扫描线Gn，第一端耦接第一数据线Dm，第二端耦接第一子像素121；第二开关112，所述第二开关112的控制端耦接第一扫描线Gn，第一端耦接第一数据线Dm，第二端耦接第一主像素122；第二像素电路，包括：第三开关113，所述第三开关113的控制端耦接第二扫描线Gn+1，第一端耦接第一数据线Dm，第二端耦接第二子像素123；第四开关114，所述第四开关114的控制端耦接第二扫描线Gn+1，第一端耦接第一数据线Dm，第二端耦接第二主像素124。其中，第n条扫描线和第n+1条扫描线间隔设置，其如图7所示。由于间隔设置的两个扫描线之间间隔一个像素区域，可减小像素电路短路的可能，提高产品的稳定性及品质。
在本申请的一实施例中，所述第一主像素122与所述第二主像素124位于同一行，所述第一子像素121与所述第二子像素123位于同一行。
在一些实施例中，通过各实施例中的像素电路，及其所述主像素和所述子像素的搭配，可以解决HSD显示面板的大视角色偏问题，提高显示效果。
在一些实施例中，本申请的显示面板可例如为液晶显示面板，然不限于此，其亦可为OLED显示面板，W-OLED显示面板，QLED显示面板，等离子体显示面板，曲面型显示面板或其他类型显示面板。
图10为本申请一实施例的显示装置的结构示意图。请同时参考图2至图10，一种显示装置1，包括一显示面板2、一屏驱动板(Timing Controller，TCON)3、一栅极驱动电路4和一源极驱动电路5；其中，所述显示面板2通过所述 多条扫描线与所述栅极驱动电路4耦接，所述显示面板2通过所述多条数据线与所述源极驱动电路5耦接。显示面板2可例如为上述各实施例中所述的显示面板(20，30，40)。
在应用中，源极驱动电路可以是任意的具有对显示面板的像素进行数据驱动功能的任意器件或电路，例如，源极驱动芯片(Source Driver IC)或薄膜源极驱动芯片(S-COF，Source-Chip on Film)等。栅极驱动电路可以是任意的具有对显示面板的像素进行逐行扫描充电功能的任意器件或电路，例如，栅极驱动芯片(Gate Driver IC)或薄膜栅极驱动芯片(G-COF，Gate-Chip on Film)等。本申请通过像素电路及结构的设计，可以增强HSD显示面板的充电效率，解决大视角色偏问题，提高显示面板的稳定性及品质。
以上仅为本申请的可选实施例而已，并不用于限制本申请。对于本领域的技术人员来说，本申请可以有各种更改和变化。凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的权利要求范围之内。

Claims (18)

  1. 一种显示面板，包括：
    像素区域，所述像素区域被划分为主像素区域和子像素区域；多条数据线；
    多条扫描线；
    多个像素组，设置于所述像素区域，每一所述像素组包括：
    第一像素电路，包括：
    第一开关，所述第一开关的控制端耦接第一扫描线，第一端耦接第一数据线，第二端耦接第一子像素；
    第二开关，所述第二开关的控制端耦接第一扫描线，第一端耦接第一数据线，第二端耦接第一主像素；
    第二像素电路，包括：
    第三开关，所述第三开关的控制端耦接第二扫描线，第一端耦接第一数据线，第二端耦接第二子像素；
    第四开关，所述第四开关的控制端耦接第二扫描线，第一端耦接第一数据线，第二端耦接第二主像素；
    其中，所述第一开关和所述第二开关位于同一列，所述第三开关和所述第四开关位于同一列；
    所述第一开关和所述第三开关位于子像素区域，所述第二开关和所述第四开关位于主像素区域，所述子像素区域的面积大于或等于所述主像素区域的面积。
  2. 如权利要求1所述的显示面板，其中，所述第一子像素与所述第二主像素位于同一行，所述第二子像素与所述第一主像素位于同一行。
  3. 如权利要求1所述的显示面板，其中，所述第一子像素与所述第二子像素位于同一行，所述第二主像素与所述第一主像素位于同一行。
  4. 如权利要求1所述的显示面板，其中，所述主像素区域的面积与所述子像素区域的面积比例为1:1，1:2，2:3或4:6。
  5. 如权利要求1所述的显示面板，其中，所述子像素区域和所述主像素区域为棋盘配置，交叉配置或网格配置。
  6. 如权利要求5所述的显示面板，其中，依据所述主像素区域和所述子像素区域的面积关系及配置，所述扫描线为周期性的多段折线设计。
  7. 如权利要求5所述的显示面板，其中，所述子像素区域与所述主像素区域的排布方式为交叉配置，所述显示面板的边界为非直线型设计的像素排列。
  8. 如权利要求7所述的显示面板，其中，所述显示面板应用于非矩形显示装置。
  9. 如权利要求8所述的显示面板，其中，所述非矩形显示装置包括车载显示装置。
  10. 如权利要求5所述的显示面板，其中，所述子像素区域和所述主像素区域为棋盘配置或网格配置，所述显示面板的边界为为直线型设计。
  11. 如权利要求10所述的显示面板，其中，所述显示面板应用于矩形显示装置。
  12. 如权利要求1所述的显示面板，其中，在第一扫描周期内，所述第一扫描线打开，所述第一开关和所述第二开关进行充放电；在第二扫描周期内，所述第二扫描线打开，所述第三开关和所述第四开关进行充放电。
  13. 如权利要求12所述的显示面板，其中，所述第一扫描周期和所述第二扫描周期为相邻的扫描周期。
  14. 如权利要求12所述的显示面板，其中，位于同一行且耦接相同数据线的相邻所述主像素区域和所述子像素区域的极性为相异。
  15. 如权利要求1所述的显示面板，其中，每一所述像素组还包括多个电容，所述第一开关、所述第二开关、所述第三开关和所述第四开关的第二端各与一个所述电容的正极耦接，所述电容的负极接地。
  16. 如权利要求1所述的显示面板，其中，所述多条扫描线中，第2n-1 条扫描线和第2n条扫描线相邻设置，第2n条扫描线和第2n+1条扫描线间隔设置；其中，n≥1且n为整数。
  17. 一种显示面板，包括：
    像素区域，所述像素区域被划分为主像素区域和子像素区域；
    多条数据线；
    多条扫描线；
    多个像素组，设置于所述像素区域，每一所述像素组包括：
    第一像素电路，包括：
    第一开关，所述第一开关的控制端耦接第一扫描线，第一端耦接第一数据线，第二端耦接第一子像素；
    第二开关，所述第二开关的控制端耦接第一扫描线，第一端耦接第一数据线，第二端耦接第一主像素；
    第二像素电路，包括：
    第三开关，所述第三开关的控制端耦接第二扫描线，第一端耦接第一数据线，第二端耦接第二子像素；
    第四开关，所述第四开关的控制端耦接第二扫描线，第一端耦接第一数据线，第二端耦接第二主像素；
    其中，所述第一开关和所述第二开关位于同一列，所述第三开关和所述第四开关位于同一列，所述第一扫描线和所述第二扫描线为相邻配置或间隔配置；
    所述第一开关和所述第三开关位于子像素区域，所述第二开关和所述第四开关位于主像素区域，所述子像素区域的面积大于或等于所述主像素区域的面积；
    位于同一行且耦接相同数据线的相邻所述主像素区域和所述子像素区域的极性为相异；
    所述子像素区域和所述主像素区域为棋盘配置或网格配置，所述显示面板 的边界为为直线型设计，所述显示面板应用于矩形显示装置。
  18. 一种显示装置，包括：
    栅极驱动电路；
    源极驱动电路；以及
    显示面板，包括：
    像素区域，所述像素区域被划分为主像素区域和子像素区域；
    多条数据线；
    多条扫描线；
    多个像素组，设置于所述像素区域，每一所述像素组包括：
    第一像素电路，包括：
    第一开关，所述第一开关的控制端耦接第一扫描线，第一端耦接第一数据线，第二端耦接第一子像素；
    第二开关，所述第二开关的控制端耦接第一扫描线，第一端耦接第一数据线，第二端耦接第一主像素；
    第二像素电路，包括：
    第三开关，所述第三开关的控制端耦接第二扫描线，第一端耦接第一数据线，第二端耦接第二子像素；
    第四开关，所述第四开关的控制端耦接第二扫描线，第一端耦接第一数据线，第二端耦接第二主像素；
    其中，所述第一开关和所述第二开关位于同一列，所述第三开关和所述第四开关位于同一列；
    所述第一开关和所述第三开关位于子像素区域，所述第二开关和所述第四开关位于主像素区域，所述子像素区域的面积大于或等于所述主像素区域的面积；
    所述显示面板通过所述多条扫描线与所述栅极驱动电路耦接，所述显示面板通过所述多条数据线与所述源极驱动电路耦接。
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CN113219743B (zh) * 2021-04-20 2022-07-01 北海惠科光电技术有限公司 显示面板、显示设备以及显示面板的驱动方法
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