WO2019232722A1 - 感光像素电路及制程方法 - Google Patents

感光像素电路及制程方法 Download PDF

Info

Publication number
WO2019232722A1
WO2019232722A1 PCT/CN2018/090143 CN2018090143W WO2019232722A1 WO 2019232722 A1 WO2019232722 A1 WO 2019232722A1 CN 2018090143 W CN2018090143 W CN 2018090143W WO 2019232722 A1 WO2019232722 A1 WO 2019232722A1
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor substrate
floating diffusion
optical isolation
region
photosensitive
Prior art date
Application number
PCT/CN2018/090143
Other languages
English (en)
French (fr)
Inventor
刘毅成
杨孟达
Original Assignee
深圳市汇顶科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市汇顶科技股份有限公司 filed Critical 深圳市汇顶科技股份有限公司
Priority to CN201880000878.1A priority Critical patent/CN111066147A/zh
Priority to PCT/CN2018/090143 priority patent/WO2019232722A1/zh
Publication of WO2019232722A1 publication Critical patent/WO2019232722A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures

Definitions

  • the present application relates to a back-illuminated photosensitive pixel circuit and a manufacturing method thereof, and more particularly to a back-illuminated photosensitive pixel circuit and a manufacturing method capable of isolating light crosstalk or light interference.
  • CMOS image sensors (CMOS, Image Sensor, CIS) are now widely used in many consumer and professional applications.
  • the traditional image sensor uses a front-side illumination (FSI) structure.
  • FSI front-side illumination
  • the disadvantage of the front-side structure is that the larger the area of the circuit in the circuit layer, the smaller the actual photosensitive area, that is, the front-side image sensor. Actually received less light, which results in a poor sensitivity and signal-to-noise of the front-illuminated image sensor.
  • the back-illuminated image sensor uses the back of a photodiode to receive light, and its photosensitive area is not affected by the circuit area in the circuit layer.
  • the back-illuminated image sensor has better light sensitivity and signal-to-noise ratio.
  • the floating diffusion (Floating Diffusion) node of the light-sensing pixel circuit in the back-illuminated CMOS image sensor will receive light from the back and generate unnecessary photoelectrons (hereinafter referred to as light interference) or light crosstalk (Crosstalk), which will distort the image.
  • the traditional CMOS image sensor uses a rolling shutter (Rolling Shutter, RS).
  • Rolling Shutter RS
  • the disadvantage of the rolling shutter is that when the exposure is started and stopped, there will be a slight time difference between the pixel column and the pixel column, resulting in a fast response time.
  • the image of a moving object is distorted, or the so-called "Jello" effect occurs when the camera shakes.
  • the prior art has developed a Global Shutter (GS) image sensor.
  • GS Global Shutter
  • the pixel circuit of the global shutter image sensor is reset infrequently, resulting in more severe light crosstalk or light interference.
  • the purpose of some embodiments of the present application is to provide a back-illuminated photosensitive pixel circuit and a manufacturing method that can isolate light crosstalk or light interference, so as to improve the shortcomings of the prior art.
  • an embodiment of the present application provides a photosensitive pixel circuit, which is applied to an image sensor including a semiconductor substrate; a photosensitive element is disposed on a front surface of the semiconductor substrate; and a reading circuit is disposed on the substrate.
  • the reading circuit includes a transmission gate and a floating diffusion node, the transmission gate is coupled between the photosensitive element and the floating diffusion node, and the floating diffusion node occupies the semiconductor substrate A floating diffusion region; and a light isolation member disposed on a back surface of the semiconductor substrate, the light isolation member occupying a light isolation region on the semiconductor substrate, a projection result of the light isolation region and the The floating diffusion regions are coincident; wherein the light isolating member is used to isolate light from the back surface.
  • the optical isolation component is formed of at least one optical isolation material, and the optical transmittance of the optical isolation material is less than 5%.
  • the optical isolation component includes a reflective layer and an isolation layer, and the reflective layer is formed between the isolation layer and the semiconductor substrate.
  • the reflective layer is made of a metal, a heavy metal, or a compound thereof.
  • the isolation layer is made of a material of a metal interlayer dielectric layer, or the isolation layer is made of silicon dioxide or a passive metal.
  • the metal interlayer dielectric layer is made of undoped silica glass or fluorosilica glass.
  • the photosensitive element occupies a photosensitive region on the semiconductor substrate, and the projection result of the optical isolation region and the photosensitive region do not coincide with each other.
  • the read circuit occupies a first area on the semiconductor substrate, and the projection result of the optical isolation area coincides with the first area.
  • An embodiment of the present application provides a manufacturing method for manufacturing a photosensitive pixel circuit.
  • the photosensitive pixel circuit includes a semiconductor substrate, a photosensitive element, and a reading circuit.
  • the reading circuit includes a transmission gate and a floating diffusion node.
  • the floating diffusion node occupies a floating diffusion region on the semiconductor substrate.
  • the manufacturing method includes A back surface of the semiconductor substrate and a groove is formed below the floating diffusion region; and an optical isolation member is formed to fill the groove; wherein the optical isolation member occupies a portion of the semiconductor substrate An optical isolation region, where a projection result of the optical isolation region coincides with the floating diffusion region; wherein the optical isolation component is used to isolate the light from the back surface for the floating diffusion node.
  • the step of forming the groove includes forming the groove by using dry etching or wet etching.
  • the step of forming the photo-isolation component includes forming a reflective layer on the surface of the groove by means of chemical vapor deposition, physical vapor deposition, or electroplating; and forming an isolation layer to fill the groove. .
  • the step of forming the isolation layer includes using a metal interlayer dielectric layer process to form the isolation layer.
  • a light isolating component is used to isolate / block light from the backside to generate light crosstalk or light interference to the floating diffusion node, so that the pixel output signal can more simply represent a signal generated by the photosensitive element receiving light.
  • FIG. 1 is a schematic cross-sectional view of a back-illuminated photosensitive pixel circuit according to a first embodiment of the present application
  • FIG. 2 is a circuit diagram of the back-illuminated photosensitive pixel circuit of FIG. 1;
  • FIG. 3 is a schematic top view and a bottom view of the back-illuminated photosensitive pixel circuit of FIG. 1;
  • FIG. 4 is a schematic diagram of a manufacturing method according to Embodiment 1 of the present application.
  • FIG. 5 is a schematic bottom view of a photosensitive pixel array according to a first embodiment of the present application.
  • FIG. 1 is a schematic cross-sectional view of a back-side illumination (BSI) photosensitive pixel circuit 10 formed as an integrated circuit in an embodiment of the present application.
  • FIG. 2 is a back-illuminated photosensitive circuit.
  • the back-illuminated photosensitive pixel circuit 10 includes a semiconductor substrate 12, a photosensitive element PD, a reading circuit 14, and an optical isolator 16.
  • the reading circuit 14 includes a transmission gate TG, a floating diffusion node FD, and a reset.
  • the photosensitive element PD may be a photosensitive diode (PD).
  • the transmission gate TG is coupled between the photosensitive element PD and the floating diffusion node FD.
  • the transmission gate TG can be turned on and the photoelectron generated by the photosensitive element PD due to receiving light. Drain to floating diffusion node FD.
  • the read transistor RD is turned on, and the back-illuminated photosensitive pixel circuit 10 outputs a pixel output signal Pout through the source follower transistor SF and the read transistor RD.
  • FIG. 1 only shows a schematic cross-sectional view of the photosensitive element PD, the transfer gate TG, the floating diffusion node FD, and the reset transistor RD.
  • the source follower transistor SF and the read transistor RD are still shown with a circuit symbol )To represent.
  • the photosensitive element PD and the reading circuit 14 are disposed on a front surface TS of the semiconductor substrate 12, and the optical isolation member 16 is disposed on a back surface BS of the semiconductor substrate 12.
  • the optical isolation component 16 is used to isolate the light received by the back BS (ie, isolate the light from the back BS) for the floating diffusion node FD.
  • the floating diffusion node FD (which may be an n + region) occupies a floating diffusion region R FD on the semiconductor substrate 12, and the optical isolation member 16 occupies an optical isolation region on the semiconductor substrate 12.
  • R ISO the projection result of the optical isolation member 16 / the optical isolation region R ISO coincides with the floating diffusion region R FD .
  • the projection result of the optical isolation member 16 / the optical isolation region R ISO covers at least the floating diffusion node FD / the floating diffusion region R FD .
  • the optical isolation component 16 can isolate / block light interference or crosstalk generated by the light from the back BS to the floating diffusion node FD.
  • the light d1 irradiated to the floating diffusion node FD in the vertical direction in FIG. 1 will cause optical interference to the floating diffusion node FD in the absence of the optical isolation member 16.
  • the light ct of the diffusion node FD may cause optical crosstalk to the floating diffusion node FD.
  • the back-illuminated photosensitive pixel circuit 10 includes a light-isolation component 16
  • the light-isolation component 16 can isolate / block light interference or light cross-talk from the light diffusion d1 or light ct to the floating diffusion node FD, so that the back-illuminated photosensitive pixel
  • the pixel output signal Pout of the circuit 10 can more simply represent a signal generated by the light receiving element PD when receiving light.
  • Sub-picture 3a in FIG. 3 shows a schematic top view of the back-illuminated photosensitive pixel circuit 10 formed as an integrated circuit.
  • Sub-picture 3b shows a bottom-view schematic diagram of the back-illuminated photosensitive pixel circuit 10 formed as an integrated circuit. Both sub-pictures 3a and 3b are marked with a first side L1 and a second side L2. As shown in FIG. 3a, the photosensitive element PD occupies a photosensitive region R PD on the front surface TS of the semiconductor substrate 12.
  • the photosensitive region R PD is a white rectangle with a truncated corner in the lower right in FIG. 3 a.
  • the floating diffusion region R FD is a sub-region.
  • the read circuit 14 occupies a region R 14 ′ on the front surface TS of the semiconductor substrate 12 except for the transmission gate TG and the floating diffusion node FD.
  • the dashed lines in sub-FIG. 3b represent the boundaries of the photosensitive region R PD , the floating diffusion region R FD, and the region R 14.
  • the optical isolation member 16 occupies the optical isolation region R on the back surface BS of the semiconductor substrate 12.
  • the optical isolating component 16 / the optical isolating area R ISO 's projection result coincides with the area (ie, the floating diffusion area R FD plus the area R 14 ' ) in which the entire reading circuit 14 stands in the semiconductor substrate 12, and the light
  • the projection result of the isolating member 16 / light isolating region R ISO and the photosensitive region R PD do not coincide with each other.
  • the optical isolation member 16 is formed of at least one optical isolation material. Generally, the optical transmittance of the optical isolation material 16 is less than 5%. Preferably, the optical isolation member 16 has a light transmittance of 0 (and completely Opaque).
  • the optical isolation component 16 may include a reflective layer 160 and an isolation layer 162.
  • the reflective layer 160 is formed between the isolation layer 162 and the semiconductor substrate 12.
  • the reflective layer 160 may be made of metal, heavy metal, or a compound thereof (light transmittance approaching 0 or light reflectance approaching 1), but is not limited thereto.
  • the isolation layer 162 may be made of a material that is insensitive to photoelectricity. It is made to avoid electrons generated by light crosstalk or light interference from floating to the floating diffusion node FD.
  • the isolation layer 162 may be made of silicon dioxide (SiO 2 ) or passive metal (Passive Metal), or made of a material of an inter-metal dielectric layer (Inter-Metal Dielectric (IMD)).
  • the intermediate metal interlayer dielectric layer may be made of undoped silicate glass (USG) or fluorosilicate glass (FSG), but is not limited thereto.
  • the optical isolation component 16 can use the isolation layer 162 to shield the light d1 from the back surface BS, so that the floating diffusion node FD is not directly irradiated by the light.
  • the light isolation member 16 can reflect the light ct back (reflect the light ct back to the photosensitive element PD) by using the reflective layer 160, that is, limit the light to the photosensitive region R PD .
  • the back-illuminated photosensitive pixel circuit 10 can be applied to a photosensitive pixel array.
  • FIG. 5 is a schematic bottom view of a photosensitive pixel array 50 according to an embodiment of the present application.
  • the photosensitive pixel array 50 includes a plurality of back-illuminated photosensitive pixel circuits 10 arranged in a 3 ⁇ 3 array.
  • FIG. 5 omits the symbol “10” of the back-illuminated photosensitive pixel circuit. It can be seen from FIG.
  • the optical isolation member 16 substantially covers the bottom of the photosensitive pixel array 50 and does not cover the photosensitive region R PD of the photosensitive component PD to allow light to pass through without causing light crosstalk or light interference to the floating diffusion node, thereby improving light sensitivity.
  • Pixel array performance
  • the manufacturing method of the optical isolation component 16 is not limited.
  • the optical isolation component 16 can be formed using a technology similar to Deep Trench Isolation (DTI) in a semiconductor process.
  • DTI Deep Trench Isolation
  • FIG. 4 is a schematic diagram of a manufacturing method of manufacturing a back-illuminated photosensitive pixel circuit 10.
  • a notch NCH may be formed on the back surface BS of the semiconductor substrate 12 and below the floating diffusion region R FD (from the center of the semiconductor substrate 12 toward the back surface BS), where The method of the groove NCH is not limited.
  • the method of dry etching (Dry Etching) or wet etching (Wet Etching) can be used to form the groove NCH.
  • a reflective layer 160 can be formed on the surface of the groove NCH. The method for forming the reflective layer 160 is not limited.
  • the isolation layer 162 can be filled in the groove NCH, and the method of forming the reflection layer 160 is not limited.
  • the IMD process can be used to use USG or FSU as the material To fill the groove NCH, an isolation layer 162 is formed.
  • the IMD process is known to those skilled in the art, so it will not be repeated here.
  • the manufacturing method in FIG. 4 is to first form the photosensitive element PD and the reading circuit 14 and then the optical isolation member 16, but is not limited thereto.
  • the optical isolation member 16 may be formed first and then the photosensitive element PD and the reading circuit 14 are formed. It also belongs to the scope of the present invention.
  • a front-illuminated photosensitive pixel circuit may be above the floating diffusion node (from the center of the semiconductor substrate to the front side). (Direction) is provided with a light shielding layer (Light shielding layer) to shield light crosstalk or light interference from the front surface of the semiconductor substrate.
  • a light shielding layer Light shielding layer
  • the prior art is not designed for back-illuminated photosensitive pixel circuits, which may be subject to light crosstalk or light interference from the backside.
  • the present application utilizes the optical isolation member 16 to isolate / block light from the back BS to generate optical crosstalk or optical interference to the floating diffusion node FD, so that the pixel output signal Pout can more simply represent the light receiving element PD receiving the light Generated signal.
  • this application can be applied to an image sensor of a global shutter (Global Shutter, GS).
  • the present application utilizes a light isolating component to isolate / block light from the backside to produce light crosstalk or light interference to the floating diffusion node, so that the pixel output signal can more simply represent the signal generated by the light receiving element when receiving light.

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Electromagnetism (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)

Abstract

一种感光像素电路（10），包括半导体基材（12）；感光元件（PD），设置于所述半导体基材（12）的一正面（TS）；读取电路（14），设置于所述正面（TS），所述读取电路（14）包括一传输闸（TG）以及一浮动扩散节点（FD），所述浮动扩散节点（FD）于所述半导体基材（12）占有一浮动扩散区域（R FD）；以及光隔离部件（16），设置于所述半导体基材（12）的一背面（BS），所述光隔离部件（16）于所述半导体基材（12）占有一光隔离区域（R ISO），所述光隔离区域（R ISO）的一投影结果与所述浮动扩散区域（R FD）重合；其中，所述光隔离部件（16）用来隔离来自所述背面（BS）的光线（d1）。

Description

感光像素电路及制程方法 技术领域
本申请涉及一种背照式感光像素电路及制程方法，尤其涉及一种可隔离光串扰或光干扰的背照式感光像素电路及制程方法。
背景技术
CMOS影像传感器(CMOS Image Sensor，CIS)现今广泛见于许多消费性及专业应用中。传统影像传感器采用前照式(Front-Side Illumination，FSI)的结构，前照式结构的缺点在于，当电路层中的电路面积越大时，实际感光的面积越小，即前照式影像传感器实际收到的光线较少，而导致前照式影像传感器的感光灵敏度及信噪比较差。
习知技术已发展出背照式(Back-Side Illumination，BSI)结构的影像传感器，背照式影像传感器利用感光二极管的背部接收光照，而其感光面积不受电路层中电路面积的影响，使得背照式影像传感器具有较佳的感光灵敏度及信噪比。然而，背照式CMOS影像传感器中感光像素电路的浮动扩散(Floating Diffusion)节点会受到来自背部的光照而产生不必要的光电子(以下简称光干扰)或光串扰(Crosstalk)，而使影像失真。
另一方面，传统CMOS影像传感器采用滚动式快门(Rolling Shutter，RS)，滚动式快门的缺点在于，在曝光开始和停止时，像素列与像素列之间会有些微时间差，而造成对应于快速移动对象的影像产生变形，或是当照相机震动时会发生所谓的「果冻(Jello)」效应。为避免此缺陷，现有技术已发展出全局式快门(Global Shutter，GS)影像传感器。然而，全局式快门影像传感器的像素电路进行重置(Reset)的频率较不频繁，导致光串扰或光干扰的影响更加严重。
因此，现有技术实有改进的必要。
发明内容
因此，本申请部分实施例的目的即在于提供一种可隔离光串扰或光干扰的背照式感光像素电路及制程方法，以改善现有技术的缺点。
为了解决上述技术问题，本申请实施例提供了一种感光像素电路，应用于一影像传感器，包括半导体基材；感光元件，设置于所述半导体基材的一正面；读取电路，设置于所述正面，所述读取电路包括一传输闸以及一浮动扩散节点，所述传输闸耦接于所述感光元件与所述浮动扩散节点之间，所述浮动扩散节点于所述半导体基材占有一浮动扩散区域；以及光隔离部件，设置于所述半导体基材的一背面，所述光隔离部件于所述半导体基材占有一光隔离区域，所述光隔离区域的一投影结果与所述浮动扩散区域重合；其中，所述光隔离部件用来隔离来自所述背面的光线。
例如，所述光隔离部件由至少一光隔离材料所形成，所述光隔离材料的光穿透率小于5％。
例如，所述光隔离部件包括一反射层以及一隔离层，所述反射层形成于所述隔离层与所述半导体基材之间。
例如，所述反射层由金属、重金属或其化合物所制成。
例如，所述隔离层由一金属层间介电质层的材质所制成，或所述隔离层由二氧化硅或钝态金属所制成。
例如，所述金属层间介电质层由未掺杂硅玻璃或氟硅玻璃所制成。
例如，所述感光元件于所述半导体基材占有一感光区域，所述光隔离区域的所述投影结果与所述感光区域不相互重合。
例如，所述读取电路于所述半导体基材占有一第一区域，所述光隔离区域的所述投影结果与所述第一区域重合。
本申请实施例提供了一种制程方法，所述制程方法用来制造一感光像素电路，所述感光像素电路包括半导体基材、感光元件以及读取电路，所述感光元件及所述读取电路设置于所述半导体基材的一正面，所述读取电路包括一传输 闸以及一浮动扩散节点，所述浮动扩散节点于所述半导体基材占有一浮动扩散区域，所述制程方法包括于所述半导体基材的一背面且于所述浮动扩散区域的下方形成一凹槽；以及形成一光隔离部件，以填满所述凹槽；其中所述光隔离部件于所述半导体基材占有一光隔离区域，所述光隔离区域的一投影结果与所述浮动扩散区域重合；其中，所述光隔离部件用来替所述浮动扩散节点隔离来自所述背面的光线。
例如，形成所述凹槽的步骤包括利用干式蚀刻或湿式蚀刻的方式，形成所述凹槽。
例如，形成所述光隔离部件的步骤包括利用化学气相沉积、物理气相沉积或电镀的方式，于所述凹槽的表面，形成一反射层；以及形成一隔离层，以填满所述凹槽。
例如，形成所述隔离层的步骤包括利用一金属层间介电质层制程，形成所述隔离层。
本申请实施例利用光隔离部件来隔离/阻隔来自背面的光线对浮动扩散节点产生光串扰或光干扰，而使得像素输出信号更能单纯地代表感光元件接收光照所产生的信号。
附图说明
图1为本申请实施例一背照式感光像素电路的剖面示意图；
图2为图1背照式感光像素电路的电路图；
图3绘示图1背照式感光像素电路的俯视示意图及仰视示意图；
图4为本申请实施例一制程方法的示意图；
图5为本申请实施例一感光像素阵列的仰视示意图。
具体实施方式
为了使本申请的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本申请进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本申请，并不用于限定本申请。
请参考图1及图2，图1为本申请实施例一背照式(Back-Side Illumination，BSI)感光像素电路10形成为集成电路(Integrated Circuit)的剖面示意图，图2为背照式感光像素电路10的电路示意图。背照式感光像素电路10包括半导体基材12、感光元件PD、读取电路14以及光隔离部件16，读取电路14包括一传输闸TG、一浮动扩散(Floating Diffusion)节点FD、一重置晶体管RG、一源跟随(Source Follower)晶体管SF以及一读取晶体管RD。感光元件PD可为一感光二极管(Photo Diode，PD)，传输闸TG耦接于感光元件PD与浮动扩散节点FD之间，传输闸TG可导通并将感光元件PD因接受光照而产生的光电子汲取至浮动扩散节点FD。当欲读取浮动扩散节点FD中的电荷量时，读取晶体管RD导通，而背照式感光像素电路10通过源跟随晶体管SF及读取晶体管RD输出一像素输出信号Pout。为了方面说明，图1仅绘示感光元件PD、 传输闸TG、浮动扩散节点FD以及重置晶体管RD的剖面示意图，源跟随晶体管SF及读取晶体管RD于图1中仍以电路符号(Circuit Symbol)来表示。
如图1所示，感光元件PD及读取电路14设置于半导体基材12的一正面TS，光隔离部件16设置于半导体基材12的一背面BS。光隔离部件16用来替浮动扩散节点FD隔离背面BS所接收到的光线(即隔离来自背面BS的光线)。换句话说，浮动扩散节点FD(其可为一n+型区(n+region))于半导体基材12占有一浮动扩散区域R FD，而光隔离部件16于半导体基材12占有一光隔离区域R ISO，光隔离部件16/光隔离区域R ISO的投影结果与浮动扩散区域R FD重合。换句话说，光隔离部件16/光隔离区域R ISO的投影结果至少涵盖浮动扩散节点FD/浮动扩散区域R FD。
如此一来，光隔离部件16可隔离/阻隔来自背面BS的光线对浮动扩散节点FD所产生的光干扰或光串扰(Crosstalk)。详细来说，图1中于垂直方向上照射到浮动扩散节点FD的光线d1在没有光隔离部件16的情况下会对浮动扩散节点FD产生光干扰，图1中于非垂直方向上照射到浮动扩散节点FD的光线ct在没有光隔离部件16的情况下会对浮动扩散节点FD产生光串扰。然而，在背照式感光像素电路10包括光隔离部件16的情况下，光隔离部件16可隔离/阻隔光线d1或光线ct对浮动扩散节点FD的光干扰或光串扰，使得背照式感光像素电路10的像素输出信号Pout更能单纯地代表感光元件PD接收光照所产生的信号。
更进一步地，光隔离部件16/光隔离区域R ISO的投影结果可涵盖整个读取电路14于半导体基材12中所站有的区域。请参考图3，图3中的子图3a绘示背照式感光像素电路10形成为集成电路的俯视示意图，子图3b绘示背照式感光像素电路10形成为集成电路的仰视示意图，其中子图3a及子图3b均标示有第一边L1以及第二边L2。如子图3a所示，感光元件PD于半导体基材12的正面TS占有一感光区域R PD，感光区域R PD为子图3a中具有右下方截角的白色矩形，浮动扩散区域R FD为子图3a中位于感光区域R PD右下方的三角形，读取电路14除了传输闸TG及浮动扩散节点FD以外其他电路元件于半导体基材12的正面TS占有一区域R 14’。另外，子图3b中的虚线代表感光区域R PD、浮动扩散区域R FD及区域R 14的边界，如子图3b所示，光隔离部件16于半导体基材12的背面BS占有光隔离区域R ISO，光隔离部件16/光隔离区域R ISO的投影结果与整个读取电路14于半导体基材12中所站有的区域(即浮动扩散区域R FD加上区域R 14’)重合，而光隔离部件16/光隔离区域R ISO的投影结果与感光区域R PD不相互重合。
另外，光隔离部件16由至少一光隔离材料所形成，一般来说，光隔离材料16的光穿透率小于5％，较佳地，光隔离部件16由光穿透率为0(及完全不透光)的光隔离材料所形成。
于一实施例中，光隔离部件16可包括一反射层160以及一隔离层162，反射层160形成于隔离层162与半导体基材12之间。反射层160可由(光穿透率趋近于0或光反射率趋近于1的)金属、重金属或其化合物所制成，而不在此 限，另外，隔离层162可由对光电不灵敏的材质所制成，以避免光串扰或光干扰所产生的电子游离至浮动扩散节点FD。举例来说，隔离层162可由二氧化硅(SiO 2)或钝态金属(Passive Metal)所制成，或是由一金属层间介电质层(Inter-Metal Dielectric，IMD)的材质所制成，其该中金属层间介电质层可由未掺杂硅玻璃(Undoped silicate glass，USG)或氟硅玻璃(Fluorosilicate glass，FSG)所制成，而不在此限。
如此一来，光隔离部件16可利用隔离层162来屏蔽来自背面BS的光线d1，使得浮动扩散节点FD不至于被光线直接照射到。另外，光隔离部件16可利用反射层160将光线ct反射回去(将光线ct反射回感光元件PD)，即将光线限制在感光区域R PD。
另外，背照式感光像素电路10可应用于感光像素阵列中。请参考图5，图5为本申请实施例一感光像素阵列50的仰视示意图。感光像素阵列50包括排列成3×3阵列的多个背照式感光像素电路10，为求简洁，图5省略背照式感光像素电路的符号“10”。由图5可知，光隔离部件16大致覆盖感光像素阵列50的底部，而不覆盖感光组件PD的感光区域R PD使光线得以通过，而不会对浮动扩散节点产生光串扰或光干扰，增进感光像素阵列的效能。
另外，关于光隔离部件16的制程方式并未有所限，举例来说，光隔离部件16可利用半导体制程中类似于深槽隔离(Deep Trench Isolation，DTI)技术来形成。
请参考图4，图4为制造背照式感光像素电路10的制程方法的示意图。如子图4a所示，可于半导体基材12的背面BS且于浮动扩散区域R FD的下方(由半导体基材12的中心朝向背面BS的方向)形成一凹槽(Notch)NCH，其中形成凹槽NCH的方式并未有所限，例如，可利用干式蚀刻(Dry Etching)或湿式蚀刻(Wet Etching)的方式，形成凹槽NCH。形成凹槽NCH之后，如子图4b所示，可于凹槽NCH的表面，形成反射层160，其中形成反射层160的方式并未有所限，例如，可利用化学气相沉积(Chemical Vapor Deposition，CVD)、物理气相沉积(Physical Vapor Deposition，PVD)、电镀(Electroplating)或涂布(Coating)的方式，于凹槽NCH的表面形成反射层160。形成凹槽NCH之后，如子图4c所示，可将隔离层162填满凹槽NCH，其中形成反射层160的方式并未有所限，例如，可利用IMD制程，以USG或FSU为材质来填满凹槽NCH，即形成隔离层162，其中IMD制程为本领域技术人员所知，故于此不再赘述。
另外，于图4的制程方法是先形成感光组件PD及读取电路14再形成光隔离部件16，而不限于此，亦可先形成光隔离部件16再形成感光组件PD及读取电路14，亦属于本发明的范畴。
现有技术中，为了避免前照式(FrontSide Illumination，FSI)感光像素电路中浮动扩散节点受到的光照，前照式感光像素电路可于浮动扩散节点的上方(由半导体基材的中心朝向正面的方向)设置光屏蔽层(Light Shielding Layer)， 以屏蔽来自半导体基材正面的光串扰或光干扰。然而，现有技术并未针对背照式感光像素电路(其可能受到来自背面)的光串扰或光干扰进行设计。相较之下，本申请利用光隔离部件16来隔离/阻隔来自背面BS的光线对浮动扩散节点FD产生光串扰或光干扰，而使得像素输出信号Pout更能单纯地代表感光元件PD接收光照所产生的信号。另外，本申请可应用于全局式快门(Global Shutter，GS)的影像传感器中。
综上所述，本申请利用光隔离部件来隔离/阻隔来自背面的光线对浮动扩散节点产生光串扰或光干扰，而使得像素输出信号更能单纯地代表感光元件接收光照所产生的信号。
以上所述仅为本申请的部分实施例而已，并不用以限制本申请，凡在本申请的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本申请的保护范围之内。

Claims (12)

  1. 一种感光像素电路，应用于一影像传感器，其特征在于，包括：
    半导体基材；
    感光元件，设置于所述半导体基材的一正面；
    读取电路，设置于所述正面，所述读取电路包括一传输闸以及一浮动扩散节点，所述传输闸耦接于所述感光元件与所述浮动扩散节点之间，所述浮动扩散节点于所述半导体基材占有一浮动扩散区域；以及
    光隔离部件，设置于所述半导体基材的一背面，所述光隔离部件于所述半导体基材占有一光隔离区域，所述光隔离区域的一投影结果与所述浮动扩散区域重合；
    其中，所述光隔离部件用来隔离来自所述背面的光线。
  2. 如权利要求1所述的感光像素电路，其特征在于，所述光隔离部件由至少一光隔离材料所形成，所述光隔离材料的光穿透率小于5％。
  3. 如权利要求1所述的感光像素电路，其特征在于，所述光隔离部件包括一反射层以及一隔离层，所述反射层形成于所述隔离层与所述半导体基材之间。
  4. 如权利要求3所述的感光像素电路，其特征在于，所述反射层由金属、重金属或其化合物所制成。
  5. 如权利要求3所述的感光像素电路，其特征在于，所述隔离层由一金属层间介电质层的材质所制成，或所述隔离层由二氧化硅或钝态金属所制成。
  6. 如权利要求3所述的感光像素电路，其特征在于，所述金属层间介电质层由未掺杂硅玻璃或氟硅玻璃所制成。
  7. 如权利要求1所述的感光像素电路，其特征在于，所述感光元件于所述半导体基材占有一感光区域，所述光隔离区域的所述投影结果与所述感光区域不相互重合。
  8. 如权利要求1所述的感光像素电路，其特征在于，所述读取电路于所述半导体基材占有一第一区域，所述光隔离区域的所述投影结果与所述第一区域重合。
  9. 一种制程方法，其特征在于，所述制程方法用来制造一感光像素电路，所述感光像素电路包括半导体基材、感光元件以及读取电路，所述感光元件及所述读取电路设置于所述半导体基材的一正面，所述读取电路包括一传输闸以及一浮动扩散节点，所述浮动扩散节点于所述半导体基材占有一浮动扩散区域，所述制程方法包括：
    于所述半导体基材的一背面且于所述浮动扩散区域的下方形成一凹槽；
    以及
    形成一光隔离部件，以填满所述凹槽；
    其中所述光隔离部件于所述半导体基材占有一光隔离区域，所述光隔离区域的一投影结果与所述浮动扩散区域重合；
    其中，所述光隔离部件用来替所述浮动扩散节点隔离来自所述背面的光线。
  10. 如权利要求9所述的制程方法，其特征在于，形成所述凹槽的步骤包括：
    利用干式蚀刻或湿式蚀刻的方式，形成所述凹槽。
  11. 如权利要求9所述的制程方法，其特征在于，形成所述光隔离部件的步骤包括：
    利用化学气相沉积、物理气相沉积或电镀的方式，于所述凹槽的表面，形成一反射层；以及
    形成一隔离层，以填满所述凹槽。
  12. 如权利要求11所述的制程方法，其特征在于，形成所述隔离层的步骤包括：
    利用一金属层间介电质层制程，形成所述隔离层。
PCT/CN2018/090143 2018-06-06 2018-06-06 感光像素电路及制程方法 WO2019232722A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201880000878.1A CN111066147A (zh) 2018-06-06 2018-06-06 感光像素电路及制程方法
PCT/CN2018/090143 WO2019232722A1 (zh) 2018-06-06 2018-06-06 感光像素电路及制程方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2018/090143 WO2019232722A1 (zh) 2018-06-06 2018-06-06 感光像素电路及制程方法

Publications (1)

Publication Number Publication Date
WO2019232722A1 true WO2019232722A1 (zh) 2019-12-12

Family

ID=68769157

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2018/090143 WO2019232722A1 (zh) 2018-06-06 2018-06-06 感光像素电路及制程方法

Country Status (2)

Country Link
CN (1) CN111066147A (zh)
WO (1) WO2019232722A1 (zh)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101546776A (zh) * 2009-05-08 2009-09-30 北京思比科微电子技术有限公司 Cmos图像传感器电路结构及其制作方法
CN103779369A (zh) * 2012-10-22 2014-05-07 佳能株式会社 摄像装置、其制造方法和照相机
CN105304655A (zh) * 2014-06-26 2016-02-03 原相科技股份有限公司 具连接到浮动扩散区的半导体电容的背感光式半导体结构
CN107958912A (zh) * 2016-10-17 2018-04-24 中芯国际集成电路制造(上海)有限公司 半导体装置及其制造方法
CN108122938A (zh) * 2016-11-28 2018-06-05 豪威科技股份有限公司 背侧照明图像传感器及其制造方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013098446A (ja) * 2011-11-04 2013-05-20 Sony Corp 固体撮像素子、固体撮像素子の製造方法、及び、電子機器

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101546776A (zh) * 2009-05-08 2009-09-30 北京思比科微电子技术有限公司 Cmos图像传感器电路结构及其制作方法
CN103779369A (zh) * 2012-10-22 2014-05-07 佳能株式会社 摄像装置、其制造方法和照相机
CN105304655A (zh) * 2014-06-26 2016-02-03 原相科技股份有限公司 具连接到浮动扩散区的半导体电容的背感光式半导体结构
CN107958912A (zh) * 2016-10-17 2018-04-24 中芯国际集成电路制造(上海)有限公司 半导体装置及其制造方法
CN108122938A (zh) * 2016-11-28 2018-06-05 豪威科技股份有限公司 背侧照明图像传感器及其制造方法

Also Published As

Publication number Publication date
CN111066147A (zh) 2020-04-24

Similar Documents

Publication Publication Date Title
US9443897B2 (en) X-Y address type solid state image pickup device and method of producing the same
JP6105538B2 (ja) ソリッドステート撮像装置とその製造方法
KR100703376B1 (ko) 매설된 렌즈를 갖는 이미지 센서 및 그 제조 방법
US20200161357A1 (en) Image pickup device and method for manufacturing image pickup device
JP2012169530A (ja) 固体撮像装置、および、その製造方法、電子機器
WO2014141991A1 (ja) 固体撮像装置およびその製造方法、並びに電子機器
JP2009016826A (ja) 裏面照射イメージセンサ
JP2009021415A (ja) 固体撮像装置およびその製造方法
CN105580138B (zh) 固态成像装置和电子设备
JP2006080457A (ja) 固体撮像素子及びその製造方法
JP2000164839A (ja) 固体撮像装置
WO2019232722A1 (zh) 感光像素电路及制程方法
JP5223883B2 (ja) 固体撮像素子
JPH03276677A (ja) 固体撮像素子
JP2001352051A (ja) 固体撮像素子及びその製造方法
US20150214262A1 (en) Image sensor and method for fabricating the same
USRE50032E1 (en) Solid-state imaging device, method of manufacturing a solid-state imaging device, and electronic apparatus
KR20050106930A (ko) 시모스 이미지센서 및 그 제조방법
JP2007194359A (ja) 固体撮像素子及び固体撮像素子の製造方法
KR100658931B1 (ko) 시모스 이미지센서 및 그의 제조방법
JP2002184966A (ja) 固体撮像素子
JPH05190819A (ja) 固体撮像装置
KR20100079255A (ko) 이미지센서의 제조방법

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18921580

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 18921580

Country of ref document: EP

Kind code of ref document: A1