WO2019227741A1 - 一种tft阵列基板、显示面板 - Google Patents

一种tft阵列基板、显示面板 Download PDF

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Publication number
WO2019227741A1
WO2019227741A1 PCT/CN2018/103476 CN2018103476W WO2019227741A1 WO 2019227741 A1 WO2019227741 A1 WO 2019227741A1 CN 2018103476 W CN2018103476 W CN 2018103476W WO 2019227741 A1 WO2019227741 A1 WO 2019227741A1
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metal layer
substrate
flat portion
tft array
layer
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French (fr)
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赵阳
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US16/096,812 priority Critical patent/US11127761B2/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H10D86/443—Interconnections, e.g. scanning lines adapted for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/471—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having different architectures, e.g. having both top-gate and bottom-gate TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate

Definitions

  • the invention belongs to the field of display technology, and particularly relates to a TFT array substrate and a display panel.
  • the opposite sides of the first metal layer and the second metal layer are usually aligned to make the second metal layer and the flat layer in the gate insulation layer have approximately the same width.
  • the thickness is only The protective layer needs to climb the first metal layer, and the gate insulation layer and the second metal layer are close to each other. the height of.
  • the protection layer has to be continuously climbed because the cut-in processing has been performed, so that the protection layer cannot be buffered. Therefore, the protective layer is prone to film breakage at the connection between the gate insulating layer and the second metal layer, and then problems such as oxidation occur. But at present, there are no good solutions to avoid this problem.
  • the present invention provides a TFT array substrate and a display panel.
  • the second metal layer is set back a distance, and the distance between the second metal layer and the gate insulating layer is increased to make the protective layer It is buffered to avoid film breakage and oxidation.
  • a first aspect of the present invention provides a TFT array substrate, including:
  • a first metal layer disposed on the substrate
  • a gate insulating layer provided on the first metal layer and extending to a surface of the substrate, the gate insulating layer including a flat portion provided on the first metal layer and A pair of stepped portions connected on opposite sides of the flat portion;
  • a second metal layer provided on the flat portion, and an area of the second metal layer orthographically projected on the surface of the substrate is smaller than an area of the surface of the flat portion;
  • a protective layer is disposed on the second metal layer and the gate insulating layer.
  • an area of an orthographic projection of the second metal layer on a surface of the substrate that is, a lower surface of the second metal layer adjacent to the surface of the flat portion of the second metal layer.
  • the area of the orthographic projection on the flat surface because the area of the orthographic projection of the second metal layer on the surface of the substrate is smaller than the area of the flat portion surface, it means that one side or opposite sides of the second metal layer are retracted to the center of the flat portion surface by a section The distance makes the second metal layer "backward" for a distance, so that the flat portions of the second metal layer and the gate insulating layer form a stepped structure.
  • the protective layer does not need continuous climbing, but the climbing is divided into two sections, and the protective layer can be buffered at the step structure.
  • the protection layer is less prone to problems such as film breakage and oxidation, which greatly improves the stability of the TFT array substrate.
  • two opposite sides of the second metal layer are retracted to a center of the flat portion by a preset width.
  • the preset width is 0.5-1 ⁇ m.
  • the opposite sides of the first metal layer are first inclined surfaces
  • the stepped portion includes a second inclined surface connected to the flat portion
  • the opposite sides of the second metal layer are third inclined surfaces.
  • the included angle between the first inclined surface, the second inclined surface, and the third inclined surface and the surface of the substrate is 40-60 °.
  • the gate insulating layer is provided with a first trench so that the second metal layer is partially disposed on the first metal layer.
  • the second metal layer is provided with a second groove, and the orthographic projection of the second groove is located within the orthographic projection of the first groove.
  • the area of the orthographic projection of the second metal layer on the surface of the substrate is smaller than the area of the surface of the flat portion by a coating process, a mask process, or an etching process.
  • the materials of the first metal layer and the second metal layer are respectively selected from one or more of copper, tungsten, chromium and aluminum.
  • the material of the gate insulating layer includes silicon oxide, silicon nitride, silicon oxynitride, or aluminum oxide, and the material of the protective layer includes silicon oxide or silicon nitride.
  • a second aspect of the present invention provides a display panel including the TFT array substrate according to the first aspect of the present invention.
  • the protective layer of the TFT array substrate is not prone to problems such as film breakage and oxidation, the stability of the display panel is greatly improved.
  • FIG. 1 is a schematic structural diagram of a TFT array substrate according to an embodiment of the present invention.
  • FIG. 2 is a schematic structural diagram of a TFT array substrate in another embodiment of the present invention.
  • a TFT array substrate 100 provided by an embodiment of the present invention includes:
  • a gate insulating layer 3 provided on the first metal layer 2 and extending to the surface of the substrate 1; the gate insulating layer 3 includes a gate insulating layer 3 provided on the first metal layer 2 An upper flat portion 31 and a pair of stepped portions 32 connected to opposite sides of the flat portion 31;
  • the second metal layer 4 is disposed on the flat portion 31, and the area of the orthographic projection of the second metal layer 4 on the surface of the substrate 1 is smaller than the area of the surface of the flat portion 31. ;
  • a protective layer 5 is provided on the second metal layer 4 and the gate insulating layer 3.
  • An embodiment of the present invention provides a TFT array substrate 100.
  • the center is retracted for a distance, so that the second metal layer 4 "backs up" for a distance, so that the second metal layer 4 and the flat portion 31 of the gate insulating layer 3 form a stepped structure.
  • the protective layer 5 does not need to continuously climb, but the climbing is divided into two sections, and the protective layer 5 can be buffered at the step structure.
  • the protection layer 5 is less prone to problems such as film breakage and oxidation, which greatly improves the stability of the TFT array substrate 100.
  • both opposite sides of the second metal layer 4 are retracted to a center of the flat portion 31 by a preset width.
  • the opposite sides of the second metal layer 4 are indented by a predetermined width, so that both sides of the second metal layer 4 form a stepped structure with the flat portion 31, and finally the stability of the TFT array substrate 100 is further improved.
  • the preset width is 0.5-1 ⁇ m. If the preset width is less than 0.5 ⁇ m, the protection layer 5 cannot function as a buffer, and problems of film breakage and oxidation still occur. However, if the preset width is greater than 1 ⁇ m, the second metal layer 4 may be disconnected, which may damage the performance of the TFT array substrate 100.
  • the preset width is 0.6-0.9 ⁇ m, and more preferably, the preset width is 0.7-0.8 ⁇ m.
  • opposite sides of the first metal layer 2 are first inclined surfaces
  • the stepped portion 32 includes a second inclined surface connected to the flat portion 31, and opposite two sides of the second metal layer 4
  • the side is a third slope; the included angle between the first slope, the second slope, and the third slope and the surface of the substrate 1 is 40-60 °.
  • the stepped portion 32 of the gate insulating layer 3 prepared based on the first metal layer 2 is also an inclined structure.
  • the opposite sides of the second metal layer 4 are also inclined structures.
  • the included angle between the first, second, and third slopes and the surface of the substrate 1 is 40-60 °.
  • the decrease of the angle can reduce the "slope" of the climbing layer of the protective layer 5 during the preparation process, and is also beneficial to prevent the protective layer 5 Problems such as cracking and subsequent "oxidation" occur.
  • the included angle between the first inclined surface, the second inclined surface, and the third inclined surface and the surface of the substrate 1 is 45-55 °.
  • the gate insulating layer 3 is provided with a first trench 33 so that the second metal layer 4 is partially disposed on the first metal layer 2.
  • the trenches opened by the gate insulating layer 3 overlap the first metal layer 2 and the second metal layer 4 to facilitate subsequent wiring operations.
  • the first trench 33 is located in the middle of the gate insulating layer 3.
  • the second metal layer 4 is provided with a second groove 41.
  • the orthographic projection of the second groove 41 on the surface of the substrate 1 is located on the first groove 33 on the substrate 1. Within the orthographic projection of the surface.
  • the second groove 41 is located directly above the first groove 33.
  • the area of the orthographic projection of the second metal layer 4 on the surface of the substrate 1 is smaller than the area of the surface of the flat portion 31 by a coating process, a mask process, or an etching process.
  • the materials of the first metal layer 2 and the second metal layer 4 are respectively selected from one or more of copper, tungsten, chromium, and aluminum.
  • the first metal layer 2 and the second metal layer 4 are made of the same material or different materials.
  • the material of the gate insulating layer 3 includes silicon oxide, silicon nitride, silicon nitride oxide, or aluminum oxide.
  • a material of the protective layer 5 includes silicon oxide or silicon nitride.
  • the material of the active layer is indium gallium zinc oxide (IGZO).
  • a display panel provided by an embodiment of the present invention includes the TFT array substrate 100 according to the embodiment of the present invention.
  • the protective layer 5 of the TFT array substrate 100 is not prone to problems such as film breakage and oxidation, the stability of the display panel is greatly improved.

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  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种TFT阵列基板（100），包括：基板（1）；第一金属层（2），第一金属层（2）设于基板（1）之上；栅极绝缘层（3），栅极绝缘层（3）设于第一金属层（2）之上并延伸至基板（1）表面，栅极绝缘层（3）包括设于第一金属层（2）上的平坦部（31）和与平坦部（31）相对两侧相连接的一对阶梯部（32）；第二金属层（4），第二金属层（4）设于平坦部（31）之上，第二金属层（4）在基板（1）表面的正投影的面积小于平坦部（31）表面的面积；保护层（5），保护层（5）设于第二金属层（4）和栅极绝缘层（3）之上。由于第二金属层（4）正投影的面积小于平坦部（31）表面的面积，即第二金属层（4）的一侧或相对的两侧向内缩进了一段距离，使第二金属层（4）"后退"了一段距离。因此，保护层（5）不需要连续爬坡。最终使得保护层（5）不易出现破膜、氧化等问题，大大提高了TFT阵列基板（100）的稳定性。

Description

一种TFT阵列基板、显示面板
本申请要求2018年5月29日提交中国专利局的，申请号为2018105284737，发明名称为“一种TFT阵列基板、显示面板”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明属于显示技术领域，具体涉及一种TFT阵列基板、显示面板。
背景技术
在TFT阵列基板的制备过程中，通常会将第一金属层与第二金属层的相对两侧进行切齐处理，使得第二金属层与栅极绝缘层中的平坦层的宽度大致相等。但在制备保护层时，厚度仅为
Figure PCTCN2018103476-appb-000001
的保护层需要爬坡第一金属层，栅极绝缘层和第二金属层近
Figure PCTCN2018103476-appb-000002
的高度。而此时由于已经进行了切齐处理，导致保护层需要连续爬坡，使保护层无法得到缓冲。因此，保护层在栅极绝缘层和第二金属层的连接处极易发生破膜，进而出现氧化等问题。但目前，尚没有一些良好的解决办法来避免此问题。
发明内容
鉴于此，为了解决上述问题，本发明提供了一种TFT阵列基板、显示面板，将第二金属层后退一段距离，进而增大第二金属层与栅极绝缘层之间的距离来使保护层得到缓冲，避免破膜，氧化现象的发生。
本发明第一方面提供了一种TFT阵列基板，包括：
基板；
第一金属层，所述第一金属层设于所述基板之上；
栅极绝缘层，所述栅极绝缘层设于所述第一金属层之上并延伸至所述基板 表面，所述栅极绝缘层包括设于所述第一金属层上的平坦部和与所述平坦部相对两侧相连接的一对阶梯部；
第二金属层，所述第二金属层设于所述平坦部之上，所述第二金属层在所述基板表面的正投影的面积小于所述平坦部表面的面积；
保护层，所述保护层设于所述第二金属层和所述栅极绝缘层之上。
本发明第一方面提供的一种TFT阵列基板，所述第二金属层在所述基板表面的正投影的面积，即第二金属层与平坦部表面相邻接的第二金属层的下表面在所述平坦部表面的正投影的面积。由于所述第二金属层在所述基板表面的正投影的面积小于所述平坦部表面的面积，意味着第二金属层的一侧或相对的两侧向平坦部表面的中心缩进了一段距离，使得第二金属层“后退”了一段距离，让第二金属层和栅极绝缘层的平坦部形成了一台阶结构。因此，在保护层的制备过程中，保护层不需要连续爬坡，而是使爬坡分成了两段，保护层可以在台阶结构处得到缓冲。最终导致保护层不易出现破膜、氧化等问题，大大提高了TFT阵列基板的稳定性。
其中，所述第二金属层的相对两侧均向所述平坦部的中心缩进预设宽度。
其中，所述预设宽度为0.5-1μm。
其中，所述第一金属层的相对两侧为第一斜面，所述阶梯部包括与所述平坦部相连的第二斜面，所述第二金属层的相对两侧为第三斜面，所述第一斜面、所述第二斜面和所述第三斜面与所述基板表面的夹角为40-60°。
其中，所述栅极绝缘层设有第一沟槽以使所述第二金属层部分设于所述第一金属层之上。
其中，所述第二金属层设有第二沟槽，所述第二沟槽的正投影位于所述第一沟槽的正投影之内。
其中，通过涂布工艺、光罩工艺或刻蚀工艺使所述第二金属层在所述基板表面的正投影的面积小于所述平坦部表面的面积。
其中，所述第一金属层与所述第二金属层的材质分别选自铜、钨、铬和铝中的一种或多种。
其中，所述栅极绝缘层的材质包括氧化硅、氮化硅、氮氧化硅或氧化铝，所述保护层的材质包括氧化硅或氮化硅。
本发明第二方面提供了一种显示面板，包括本发明第一方面所述的TFT阵列基板。
本发明第二方面提供的一种显示面板，由于TFT阵列基板的保护层不易出现破膜、氧化等问题，使得显示面板的稳定性得到了大大的提升。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对本发明实施例中所需要使用的附图进行说明。
图1为本发明一实施例中TFT阵列基板的结构示意图；
图2为本发明另一实施例中TFT阵列基板的结构示意图。
具体实施方式
以下是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也视为本发明的保护范围。
本发明实施例提供的一种TFT阵列基板100，包括：
基板1；
第一金属层2，所述第一金属层2设于所述基板1之上；
栅极绝缘层3，所述栅极绝缘层3设于所述第一金属层2之上并延伸至所述 基板1表面，所述栅极绝缘层3包括设于所述第一金属层2上的平坦部31和与所述平坦部31相对两侧相连接的一对阶梯部32；
第二金属层4，所述第二金属层4设于所述平坦部31之上，所述第二金属层4在所述基板1表面的正投影的面积小于所述平坦部31表面的面积；
保护层5，所述保护层5设于所述第二金属层4和所述栅极绝缘层3之上。
本发明实施例提供的一种TFT阵列基板100，所述第二金属层4在所述基板1表面的正投影的面积，即第二金属层4与平坦部31表面相邻接的第二金属层4的下表面在所述平坦部31表面的正投影的面积。由于所述第二金属层4在所述基板1表面的正投影的面积小于所述平坦部31表面的面积，意味着第二金属层4的一侧或相对的两侧向平坦部31表面的中心缩进了一段距离，使得第二金属层4“后退”了一段距离，让第二金属层4和栅极绝缘层3的平坦部31形成了一台阶结构。因此，在保护层5的制备过程中，保护层5不需要连续爬坡，而是使爬坡分成了两段，保护层5可以在台阶结构处得到缓冲。最终导致保护层5不易出现破膜、氧化等问题，大大提高了TFT阵列基板100的稳定性。
本发明实施方式中，所述第二金属层4的相对两侧均向所述平坦部31的中心缩进预设宽度。第二金属层4的相对两侧均缩进预设宽度，使得第二金属层4的两侧均与平坦部31形成台阶结构，最终导致TFT阵列基板100的稳定性得到进一步的提升。
本发明实施方式中，所述预设宽度为0.5-1μm。预设宽度若小于0.5μm，则无法起到使保护层5缓冲的作用，仍然会出现破膜和氧化的问题。但预设宽度若大于1μm，则会导致第二金属层4断线，破坏了TFT阵列基板100的性能。优选地，预设宽度为0.6-0.9μm，更优选地，预设宽度为0.7-0.8μm。
本发明实施方式中，所述第一金属层2的相对两侧为第一斜面，所述阶梯 部32包括与所述平坦部31相连的第二斜面，所述第二金属层4的相对两侧为第三斜面；所述第一斜面、所述第二斜面和所述第三斜面与所述基板1表面的夹角为40-60°。由于第一金属层2的相对两侧即第一斜面为倾斜结构，因此，基于第一金属层2制备出的栅极绝缘层3的阶梯部32也为倾斜结构。而因为第一金属层2和第二金属层4进行了切齐处理，因此第二金属层4的相对两侧也为斜面结构。第一斜面、第二斜面和第三斜面与基板1表面的夹角为40-60°，角度的降低可使保护层5在制备过程中爬坡的“坡度”降低，也有利于防止保护层5发生破裂、进而出现的“氧化”等问题。优选地，第一斜面、第二斜面和第三斜面与基板1表面的夹角为45-55°。
本发明实施方式中，所述栅极绝缘层3设有第一沟槽33以使所述第二金属层4部分设于所述第一金属层2之上。栅极绝缘层3开设的沟槽会使第一金属层2与第二金属层4搭接在一起，方便后续的布线操作。优选地，第一沟槽33位于所述栅极绝缘层3的中间。
本发明实施方式中，所述第二金属层4设有第二沟槽41，所述第二沟槽41在所述基板1表面的正投影位于所述第一沟槽33在所述基板1表面的正投影之内。优选地，所述第二沟槽41位于所述第一沟槽33的正上方。本发明实施方式中，通过涂布工艺、光罩工艺或刻蚀工艺使所述第二金属层4在所述基板1表面的正投影的面积小于所述平坦部31表面的面积。
本发明实施方式中，第一金属层2与第二金属层4的材质分别选自铜、钨、铬和铝中的一种或多种。
本发明实施方式中，所述第一金属层2与所述第二金属层4为相同材质或不同材质。
本发明实施方式中，所述栅极绝缘层3的材质包括氧化硅、氮化硅、氮氧 化硅或氧化铝。
本发明实施方式中，所述保护层5的材质包括氧化硅或氮化硅。
本发明实施方式中，有源层的材质为铟镓锌氧化物(IGZO)。
本发明实施例提供的一种显示面板，包括本发明实施例所述的TFT阵列基板100。
本发明实施例提供的一种显示面板，由于TFT阵列基板100的保护层5不易出现破膜、氧化等问题，使得显示面板的稳定性得到了大大的提升。
以上对本发明实施方式所提供的内容进行了详细介绍，本文对本发明的原理及实施方式进行了阐述与说明，以上说明只是用于帮助理解本发明的方法及其核心思想；同时，对于本领域的一般技术人员，依据本发明的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本发明的限制。

Claims (20)

  1. 一种TFT阵列基板，其中，包括：
    基板；
    第一金属层，所述第一金属层设于所述基板之上；
    栅极绝缘层，所述栅极绝缘层设于所述第一金属层之上并延伸至所述基板表面，所述栅极绝缘层包括设于所述第一金属层上的平坦部和与所述平坦部相对两侧相连接的一对阶梯部；
    第二金属层，所述第二金属层设于所述平坦部之上，所述第二金属层在所述基板表面的正投影的面积小于所述平坦部表面的面积；
    保护层，所述保护层设于所述第二金属层和所述栅极绝缘层之上。
  2. 如权利要求1所述的TFT阵列基板，其中，所述第二金属层的相对两侧均向所述平坦部的中心缩进预设宽度。
  3. 如权利要求2所述的TFT阵列基板，其中，所述预设宽度为0.5-1μm。
  4. 如权利要求3所述的TFT阵列基板，其中，所述预设宽度为0.6-0.9μm。
  5. 如权利要求1所述的TFT阵列基板，其中，所述第一金属层的相对两侧为第一斜面，所述阶梯部包括与所述平坦部相连的第二斜面，所述第二金属层的相对两侧为第三斜面，所述第一斜面、所述第二斜面和所述第三斜面与所述基板表面的夹角为40-60°。
  6. 如权利要求1所述的TFT阵列基板，其中，所述栅极绝缘层设有第一沟槽以使所述第二金属层部分设于所述第一金属层之上。
  7. 如权利要求6所述的TFT阵列基板，其中，所述第二金属层设有第二沟槽，所述第二沟槽在所述基板表面的正投影位于所述第一沟槽在所述基板表面 的正投影之内。
  8. 如权利要求1所述的TFT阵列基板，其中，通过涂布工艺、光罩工艺或刻蚀工艺使所述第二金属层在所述基板表面的正投影的面积小于所述平坦部表面的面积。
  9. 如权利要求1所述的TFT阵列基板，其中，所述第一金属层与所述第二金属层的材质分别选自铜、钨、铬和铝中的一种或多种。
  10. 如权利要求1所述的TFT阵列基板，其中，所述栅极绝缘层的材质包括氧化硅、氮化硅、氮氧化硅或氧化铝，所述保护层的材质包括氧化硅或氮化硅。
  11. 一种显示面板，其中，包括TFT阵列基板，所述TFT阵列基板包括：
    基板；
    第一金属层，所述第一金属层设于所述基板之上；
    栅极绝缘层，所述栅极绝缘层设于所述第一金属层之上并延伸至所述基板表面，所述栅极绝缘层包括设于所述第一金属层上的平坦部和与所述平坦部相对两侧相连接的一对阶梯部；
    第二金属层，所述第二金属层设于所述平坦部之上，所述第二金属层在所述基板表面的正投影的面积小于所述平坦部表面的面积；
    保护层，所述保护层设于所述第二金属层和所述栅极绝缘层之上。
  12. 如权利要求11所述的显示面板，其中，所述第二金属层的相对两侧均向所述平坦部的中心缩进预设宽度。
  13. 如权利要求12所述的显示面板，其中，所述预设宽度为0.5-1μm。
  14. 如权利要求11所述的显示面板，其中，所述第一金属层的相对两侧为第一斜面，所述阶梯部包括与所述平坦部相连的第二斜面，所述第二金属层的 相对两侧为第三斜面，所述第一斜面、所述第二斜面和所述第三斜面与所述基板表面的夹角为40-60°。
  15. 如权利要求11所述的显示面板，其中，所述栅极绝缘层设有第一沟槽以使所述第二金属层部分设于所述第一金属层之上。
  16. 如权利要求15所述的显示面板，其中，所述第二金属层设有第二沟槽，所述第二沟槽在所述基板表面的正投影位于所述第一沟槽在所述基板表面的正投影之内。
  17. 如权利要求11所述的显示面板，其中，通过涂布工艺、光罩工艺或刻蚀工艺使所述第二金属层在所述基板表面的正投影的面积小于所述平坦部表面的面积。
  18. 如权利要求11所述的显示面板，其中，所述第一金属层与所述第二金属层的材质分别选自铜、钨、铬和铝中的一种或多种。
  19. 如权利要求11所述的显示面板，其中，所述栅极绝缘层的材质包括氧化硅、氮化硅、氮氧化硅或氧化铝。
  20. 如权利要求11所述的显示面板，其中，所述保护层的材质包括氧化硅或氮化硅。
PCT/CN2018/103476 2018-05-29 2018-08-31 一种tft阵列基板、显示面板 Ceased WO2019227741A1 (zh)

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