WO2019227422A1 - 上电复位电路及隔离式半桥驱动器 - Google Patents

上电复位电路及隔离式半桥驱动器 Download PDF

Info

Publication number
WO2019227422A1
WO2019227422A1 PCT/CN2018/089333 CN2018089333W WO2019227422A1 WO 2019227422 A1 WO2019227422 A1 WO 2019227422A1 CN 2018089333 W CN2018089333 W CN 2018089333W WO 2019227422 A1 WO2019227422 A1 WO 2019227422A1
Authority
WO
WIPO (PCT)
Prior art keywords
signal
voltage
circuit
coupled
power
Prior art date
Application number
PCT/CN2018/089333
Other languages
English (en)
French (fr)
Inventor
朱煜
力争
王国瑞
王明贵
侯惠淇
张振明
蔡中华
庞志远
王晨
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to PCT/CN2018/089333 priority Critical patent/WO2019227422A1/zh
Priority to CN201880094042.2A priority patent/CN112204884B/zh
Publication of WO2019227422A1 publication Critical patent/WO2019227422A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied

Definitions

  • the embodiments of the present application relate to the field of circuit technology, and in particular, to a power on reset (POR) circuit and an isolated half-bridge driver.
  • POR power on reset
  • high-speed isolated communication interfaces are widely used, such as switched envelope trackers, isolated DC-DC (DC-DC) power modules with high power density and efficiency, inverters that require high isolation voltage and high reliability, And highly automated test equipment.
  • An important module in the high-speed isolated communication interface is a high-speed high-voltage isolated module, that is, an isolated half-bridge driver.
  • Common isolated half-bridge drivers are implemented based on electromagnetic coupling. They use a transformer to perform signal shaping transmission, and a hysteresis comparator at the output of the transformer to implement signal recovery.
  • the hysteresis comparator is usually biased at a threshold.
  • the logic level at the output of the hysteresis comparator is in an unknown state. If you start running from this uncertain initial state, it is likely to cause incorrect execution of the system and even destroy the normal working ability of the entire system. Therefore, the POR circuit is required to set the hysteresis comparator to the initial state during the power-on process.
  • FIG. 1 illustrates a schematic diagram of an existing POR circuit by way of example.
  • a bandgap reference (BGR) circuit 11 generates a reference voltage, and then the comparator 12 compares the divided voltage of the power supply with the reference voltage, and outputs a reset signal at the output terminal 13 according to the comparison result.
  • the power is divided by a resistor R1 and a resistor R2 connected in series.
  • the embodiments of the present application provide a power-on reset circuit applied to an isolated half-bridge driver, which can be used to solve the situation that a POR circuit based on a bandgap reference is applied in a fast power-up process because the reference voltage settling time is relatively short. Long, if the reference voltage is not established during the fast power-on process, the problem of a power-on reset signal cannot be generated during the fast power-on process, thereby improving the reliability of the POR circuit.
  • an embodiment of the present application provides a power-on reset circuit.
  • the power-on reset circuit includes a delay circuit, an inverter circuit, and a switch circuit. One end of the delay circuit is coupled to the power supply, and the other end of the delay circuit is coupled to the ground.
  • the delay circuit is used to output a voltage signal when the power supply voltage rises from zero voltage to a steady-state voltage.
  • the inverting circuit is configured to perform inverting processing on the voltage signal to obtain a control signal.
  • the switch circuit is used to be turned on under the control of the control signal to output the power or ground as a reset signal.
  • the switching circuit is turned on by means of the power supply voltage, so that the power supply or ground is output as a reset signal, thereby realizing stability throughout the power-on process.
  • the output reset signal improves the reliability of the POR circuit.
  • the switching circuit includes: a first NMOS transistor.
  • the gate of the first NMOS tube is used to receive a control signal, and the first NMOS tube is turned on under the control of the control signal.
  • the source of the first NMOS tube is coupled to the ground, and the drain of the first NMOS tube is used for Ground is output as a reset signal.
  • the switching circuit includes the first NMOS tube
  • the inverting circuit includes 2n cascaded inverters, and the inverting circuit is used for the voltage signal Perform 2n inversion processing to obtain a control signal.
  • the control signal is a high-level signal and n is a positive integer.
  • the inverting circuit includes an inverter or 2m + 1 cascaded inverters.
  • the inversion circuit is used to perform 1 or 2m + 1 inversion processing on the voltage signal to obtain a control signal.
  • the control signal is a high-level signal and m is a positive integer.
  • the switching circuit includes: a first PMOS tube.
  • the gate of the first PMOS tube is used to receive a control signal, and the first PMOS tube is turned on under the control of the control signal.
  • the source of the first PMOS tube is coupled to a power source, and the drain of the first PMOS tube is used for The power supply is output as a reset signal.
  • the inverting circuit when the switching circuit includes the first PMOS tube, if the voltage signal output by the delay circuit is a low-level signal, the inverting circuit includes 2n cascaded inverters, and the inverting circuit is used for the voltage signal Perform 2n inversion processing to obtain a control signal.
  • the control signal is a low-level signal and n is a positive integer.
  • the inverting circuit includes an inverter or 2m + 1 cascaded inverters.
  • the inversion circuit is used to perform 1 or 2m + 1 inversion processing on the voltage signal to obtain a control signal.
  • the control signal is a low-level signal and m is a positive integer.
  • the NMOS tube is turned on under the driving of a high-level signal
  • the PMOS tube is turned on under the driving of a low-level signal. Therefore, the voltage signal can be processed through an inverter, which can Generate a control signal for triggering the MOS tube to turn on.
  • the delay circuit includes a first resistor and a first capacitor.
  • the first terminal of the first resistor is coupled to the power source, the second terminal of the first resistor and the first terminal of the first capacitor are coupled to the first node, and the second terminal of the first capacitor is coupled to the ground; the power supply voltage rises from zero voltage In the process of reaching the steady-state voltage, the first node is used to output a voltage signal, and the voltage signal is a low-level signal.
  • the delay circuit includes a second resistor and a second capacitor.
  • the first terminal of the second capacitor is coupled to the power source, the second terminal of the second capacitor and the first terminal of the second resistor are coupled to the second node, and the second terminal of the second resistor is coupled to the ground; the power supply voltage rises from zero voltage In the process of reaching the steady-state voltage, the second node is used to output a voltage signal, and the voltage signal is a high-level signal.
  • the delay circuit includes: a second PMOS tube, a second NMOS tube, and a third resistor.
  • the gate of the second PMOS tube is coupled to the first end of the third resistor
  • the source of the second PMOS tube is coupled to the power source
  • the drain of the second PMOS tube and the gate of the second NMOS tube are coupled to the third node
  • the second end of the three resistors, the source of the second NMOS tube, and the drain of the second NMOS tube are all coupled to the ground; in the process of the power supply voltage rising from zero voltage to the steady-state voltage, the third node is used to output a voltage signal
  • the voltage signal is a low-level signal.
  • an embodiment of the present application provides an isolated half-bridge driver.
  • the isolated half-bridge driver includes a transformer, a hysteresis comparator, and a power-on reset circuit according to the above aspect.
  • the output of the transformer is coupled to the input of the hysteresis comparator.
  • the power-on reset circuit is used to output a reset signal to reset the hysteresis comparator to its initial state.
  • the power-on reset circuit is specifically configured to output a reset signal to an input terminal of the hysteresis comparator; or, output a reset signal to an output terminal of the hysteresis comparator.
  • the hysteresis comparator By coupling the output of the POR circuit to the input or output of the hysteresis comparator, the hysteresis comparator is set to the initial state during the power-on process.
  • the switching circuit is turned on by means of the power supply voltage, thereby outputting the power supply or ground as a reset signal, thereby achieving power-on of the power supply
  • the reset signal can be stably output during the whole process, which improves the reliability of the POR circuit.
  • FIG. 1 is a schematic diagram of a conventional POR circuit
  • FIG. 2 is a structural block diagram of a POR circuit provided by an embodiment of the present application.
  • 3 to 5 are circuit structure diagrams of several kinds of delay circuits provided by the embodiments of the present application.
  • FIG. 12 and FIG. 13 are circuit structure diagrams of an isolated half-bridge driver according to an embodiment of the present application.
  • FIG. 2 shows a structural block diagram of a POR circuit provided by an embodiment of the present application.
  • the POR circuit 20 includes a delay circuit 30, an inverter circuit 40, and a switch circuit 50.
  • One end of the delay circuit 30 is coupled to a power source, and the other end of the delay circuit 30 is coupled to ground.
  • the delay circuit 30 is configured to output a voltage signal during a process in which the power supply voltage rises from a zero voltage to a steady-state voltage. Specifically, the output terminal of the delay circuit 30 is coupled to the input terminal of the inverter circuit 40, and the output terminal of the delay circuit 30 outputs the voltage signal to the input terminal of the inverter circuit 40.
  • the power supply is used to provide power to the POR circuit 20 so that the POR circuit 20 can work normally.
  • the power supply voltage will rise from zero voltage to the steady-state voltage.
  • the steady-state voltage can also be called the normal working voltage.
  • the value of the steady-state voltage can be determined by the actual circuit structure and application scenario, which is not limited in the embodiments of the present application.
  • the delay circuit 30 is an RC delay circuit.
  • the delay circuit 30 includes a first resistor R1 and a first capacitor C1.
  • the first resistor R1 and the first capacitor C1 are coupled in series.
  • the first terminal of the first resistor R1 is coupled to the power source
  • the second terminal of the first resistor R1 and the first terminal of the first capacitor C1 are coupled to the first node 31, and the second terminal of the first capacitor C1 is coupled to the ground.
  • the first node 31 is the output terminal of the delay circuit 30.
  • the first node 31 is used to output a voltage signal.
  • the voltage at the first node 31 is low level compared to the power supply voltage, so the voltage signal output by the delay circuit 30 shown in FIG. 3 is low level. signal.
  • the delay circuit 30 includes a second resistor R2 and a second capacitor C2.
  • the second capacitor C2 and the second resistor R2 are coupled in series.
  • the first terminal of the second capacitor C2 is coupled to the power source
  • the second terminal of the second capacitor C2 and the first terminal of the second resistor R2 are coupled to the second node 32
  • the second terminal of the second resistor R2 is coupled to the ground.
  • the second node 32 is the output terminal of the delay circuit 30. In the process of the power supply voltage rising from zero voltage to the steady-state voltage, the second node 32 is used to output a voltage signal.
  • the voltage signal output from the delay circuit 30 shown in 4 is a high-level signal.
  • the delay circuit 30 includes a second PMOS transistor P2, a second NMOS transistor N2, and a third resistor R3.
  • the gate of the second PMOS transistor P2 is coupled to the first end of the third resistor R3, the source of the second PMOS transistor P2 is coupled to the power source, and the drain of the second PMOS transistor P2 and the gate of the second NMOS transistor N2 are coupled to Third node 33.
  • the second terminal of the third resistor R3, the source of the second NMOS transistor N2, and the drain of the second NMOS transistor N2 are all coupled to the ground.
  • the third node 33 is the output terminal of the delay circuit 30.
  • the third node 33 is used to output a voltage signal.
  • the voltage at the third node 33 is low compared to the power supply voltage, so the voltage signal output by the delay circuit 30 shown in FIG. 5 is low. signal.
  • the types of the resistors are not limited, for example, they may be MOS resistors, polycrystalline resistors (that is, Poly Resistance), etc., as long as it can realize the resistance function.
  • the types of the capacitors are not limited, for example, they may be MOS capacitors, MIM capacitors, MOM capacitors, etc., as long as they can be implemented The capacitor function is sufficient.
  • the inverting circuit 40 is configured to perform an inverting process on a voltage signal to obtain a control signal.
  • the inverter circuit 40 includes one or more inverters, and the voltage signal is converted into a control signal by the inverter.
  • the output terminal of the inverting circuit 40 is coupled to the input terminal of the switching circuit 50, and the output terminal of the inverting circuit 40 outputs the above control signal to the input terminal of the switching circuit 50.
  • the switch circuit 50 is configured to be turned on under the control of a control signal to output a power source or a ground as a reset signal.
  • the switching circuit 50 is turned on by means of the power supply voltage, thereby outputting the power supply or ground as a reset signal.
  • the switch circuit 50 includes a controllable switch, and the controllable switch refers to a switching device that can be controlled to be turned on or off by a signal.
  • the controllable switch is a voltage-type switch control device.
  • the voltage-type switch control device can switch between on and off states according to different voltages.
  • the voltage-type switching control device includes any one of the following: MOSFET (metallic oxide semiconductor effector, metal oxide semiconductor field effect transistor), IGBT (insulated gate bipolar transistor), MCT (insulated gate bipolar transistor), MCT ( MOS controlled thyristor (MOS controlled thyristor), SIT (static induction transistor).
  • MOSFET metal oxide semiconductor effector, metal oxide semiconductor field effect transistor
  • IGBT insulated gate bipolar transistor
  • MCT insulated gate bipolar transistor
  • MCT MOS controlled thyristor
  • SIT static induction transistor
  • the switching circuit 50 includes a first NMOS transistor, that is, the controllable switch is a first NMOS transistor.
  • the gate of the first NMOS tube is used to receive the control signal and to turn on the first NMOS tube under the control of the control signal.
  • the source of the first NMOS tube is coupled to the ground, and the drain of the first NMOS tube is used to use the ground as Reset signal output.
  • the switching circuit 50 includes a first PMOS transistor, that is, the controllable switch is a first PMOS transistor.
  • the gate of the first PMOS tube is used to receive the control signal and to turn on the first PMOS tube under the control of the control signal.
  • the source of the first PMOS tube is coupled to the power source, and the drain of the first PMOS tube is used as the power source. Reset signal output.
  • the inverter circuit 40 Since the gate of the NMOS transistor is turned on under a high-level signal, when the controllable switch is the first NMOS transistor, the inverter circuit 40 needs to output a high-level signal as a control signal.
  • the inverting circuit 40 includes 2n cascaded inverters.
  • the phase circuit 40 is configured to perform a 2n inversion process on the voltage signal to obtain a control signal.
  • the control signal is a high-level signal and n is a positive integer.
  • the voltage signal output by the delay circuit 30 is a low-level signal (for example, when the delay circuit 30 adopts the structure shown in FIG.
  • the inverter circuit 40 includes an inverter or 2m + 1 stages The inverter is connected to the inverter.
  • the inverter circuit 40 is configured to perform an inversion process on the voltage signal once or 2m + 1 times to obtain a control signal.
  • the control signal is a high-level signal and m is a positive integer.
  • the inverting circuit 40 includes one inverter, the inverting circuit 40 is configured to perform one inversion process on the voltage signal to obtain a control signal; when the inverting circuit 40 includes 2m + 1 cascaded inverters, The inversion circuit 40 is configured to perform a 2m + 1 inversion process on the voltage signal to obtain a control signal.
  • the inverter circuit 40 Since the gate of the PMOS tube is turned on under a low-level signal, when the controllable switch is the first PMOS tube, the inverter circuit 40 needs to output a low-level signal as a control signal.
  • the inverter circuit 40 includes 2n cascaded inverters The inverter and the inverting circuit 40 are used to perform a 2n inversion process on the voltage signal to obtain a control signal.
  • the control signal is a low-level signal and n is a positive integer.
  • the inverter circuit 40 When the voltage signal output by the delay circuit 30 is a high-level signal (for example, when the delay circuit 30 adopts the structure shown in FIG. 4), the inverter circuit 40 includes an inverter or 2m + 1 cascaded inverters. The phaser and the inverting circuit 40 are used to perform one or 2m + 1 inversion processing on the voltage signal to obtain a control signal.
  • the control signal is a low-level signal and m is a positive integer.
  • the inverting circuit 40 When the inverting circuit 40 includes one inverter, the inverting circuit 40 is configured to perform one inversion process on the voltage signal to obtain a control signal; when the inverting circuit 40 includes 2m + 1 cascaded inverters, The inversion circuit 40 is configured to perform a 2m + 1 inversion process on the voltage signal to obtain a control signal.
  • the inverting circuit 40 includes 2n (ie, even) cascaded inverters.
  • the output terminal of the i-th inverter is coupled to the input terminal of the i + 1th inverter, and i is a positive integer less than 2n.
  • the input terminal of the first inverter is coupled to the output terminal of the delay circuit 30, and the output terminal of the 2n inverter is coupled to the input terminal of the switching circuit 50.
  • the inverter circuit 40 includes an inverter or 2m + 1 (ie odd number) cascaded inverters.
  • the inverter circuit 40 includes one inverter, the input terminal of the inverter is coupled to the output terminal of the delay circuit 30, and the output terminal of the inverter is coupled to the input terminal of the switching circuit 50.
  • the inverting circuit 40 includes 2m + 1 cascaded inverters, the output terminal of the jth inverter is coupled to the input terminal of the j + 1th inverter, and j is a positive integer less than 2m + 1 .
  • the input terminal of the first inverter is coupled to the output terminal of the delay circuit 30, and the output terminal of the 2m + 1 inverter is coupled to the input terminal of the switching circuit 50.
  • FIG. 6 to FIG. 8 are schematic diagrams of three different POR circuits 20 when the switching circuit 50 includes the first NMOS transistor N1.
  • the delay circuit 30 adopts the structure shown in FIG.
  • the gate of the first NMOS transistor N1 is coupled to the output terminal of the inverter circuit 40, the source of the first NMOS transistor N1 is coupled to the ground, and the drain of the first NMOS transistor N1 is the output terminal 21 of the POR circuit 20.
  • the inverter circuit 40 includes an inverter 40 a, the input terminal of the inverter 40 a is coupled to the first node 31, and the output terminal of the inverter 40 a is coupled to the gate of the first NMOS transistor N1. .
  • the voltage V1 at the first node 31 is low compared to the power supply voltage.
  • V2 keeps outputting a high level, and the first NMOS tube N1 is turned on, generating a Low-impedance path to ground to output ground as a reset signal.
  • the delay circuit 30 adopts the structure shown in FIG.
  • the gate of the first NMOS transistor N1 is coupled to the output terminal of the inverter circuit 40, the source of the first NMOS transistor N1 is coupled to the ground, and the drain of the first NMOS transistor N1 is the output terminal 21 of the POR circuit 20.
  • the inverter circuit 40 includes two cascaded inverters 40b and 40c. The input terminal of the inverter 40b is coupled to the second node 32. The output terminal of the inverter 40b and the input of the inverter 40c. The terminal of the inverter 40c is coupled to the gate of the first NMOS transistor N1.
  • V1 increases with the power supply voltage and passes through the inverter 40b and the inverter. After the conversion of 40c, V2 keeps outputting high level, and the first NMOS tube N1 is turned on to generate a low-impedance path to the ground, thereby outputting the ground as a reset signal.
  • the delay circuit 30 adopts the structure shown in FIG.
  • the gate of the first NMOS transistor N1 is coupled to the output terminal of the inverter circuit 40, the source of the first NMOS transistor N1 is coupled to the ground, and the drain of the first NMOS transistor N1 is the output terminal 21 of the POR circuit 20.
  • the inverting circuit 40 includes an inverter 40d, an input terminal of the inverter 40d is coupled to the third node 33, and an output terminal of the inverter 40d is coupled to the gate of the first NMOS transistor N1. .
  • the voltage V1 at the third node 33 is low compared to the power supply voltage.
  • V2 keeps outputting a high level.
  • the first NMOS tube N1 is turned on, resulting in a Low-impedance path to ground to output ground as a reset signal.
  • FIG. 9 to FIG. 11 are schematic diagrams of three different POR circuits 20 when the switch circuit 50 includes the first PMOS transistor P1.
  • the delay circuit 30 adopts the structure shown in FIG.
  • the gate of the first PMOS transistor P1 is coupled to the output terminal of the inverter circuit 40
  • the source of the first PMOS transistor P1 is coupled to the power source
  • the drain of the first PMOS transistor P1 is the output terminal 21 of the POR circuit 20.
  • the inverter circuit 40 includes two cascaded inverters 40e and 40f.
  • the input terminal of the inverter 40e is coupled to the first node 31.
  • the terminal of the inverter 40f is coupled to the gate of the first PMOS transistor P1.
  • the voltage V1 at the first node 31 is at a low level compared to the power supply voltage.
  • V2 keeps outputting a low level.
  • the first PMOS transistor P1 turns on, creating a low-impedance path to the power supply, so that the power supply is output as a reset signal.
  • the delay circuit 30 adopts the structure shown in FIG.
  • the gate of the first PMOS transistor P1 is coupled to the output terminal of the inverter circuit 40
  • the source of the first PMOS transistor P1 is coupled to the power source
  • the drain of the first PMOS transistor P1 is the output terminal 21 of the POR circuit 20.
  • the inverter circuit 40 includes an inverter 40g, an input terminal of the inverter 40g is coupled to the second node 32, and an output terminal of the inverter 40g is coupled to the gate of the first PMOS transistor P1.
  • V1 the voltage of the second resistor R2 (that is, the voltage at the second node 32) V1 increases with the power supply voltage and is converted by the inverter 40g. V2 keeps the output low level, the first PMOS tube P1 is turned on, and a low-impedance path to the power source is generated, so that the power source is output as a reset signal.
  • the delay circuit 30 adopts the structure shown in FIG.
  • the gate of the first PMOS transistor P1 is coupled to the output terminal of the inverter circuit 40
  • the source of the first PMOS transistor P1 is coupled to the power source
  • the drain of the first PMOS transistor P1 is the output terminal 21 of the POR circuit 20.
  • the inverter circuit 40 includes two cascaded inverters 40h and 40i.
  • the input terminal of the inverter 40h is coupled to the third node 33.
  • the terminal of the inverter 40i is coupled to the gate of the first PMOS transistor P1.
  • the voltage V1 at the third node 33 is at a low level compared to the power supply voltage.
  • V2 maintains an output low level.
  • the first PMOS transistor P1 turns on, creating a low-impedance path to the power supply, so that the power supply is output as a reset signal.
  • the output terminal of the delay circuit 30 continues to output a voltage signal.
  • the voltage signal is converted by the inverter circuit 40 to generate a control signal.
  • the switch circuit 50 is turned off under the control of the control signal, thereby stopping the output Reset signal.
  • the switching circuit is turned on by means of the power supply voltage, so that the power supply or ground is output as a reset signal, and the power-on The reset signal can be output stably during the whole process, which improves the reliability of the POR circuit.
  • the BGR circuit and the comparator in the POR circuit implemented based on the bandgap reference need to consume a certain static power consumption during normal operation, and the POR circuit provided in the embodiment of the present application has no static current in the MOS tube during normal operation, so No static power consumption.
  • FIG. 12 and FIG. 13 are schematic circuit diagrams of an isolated half-bridge driver according to an embodiment of the present application.
  • the isolated half-bridge driver includes a transformer T, a hysteresis comparator 50, and the POR circuit 20 described above.
  • the output terminal of the transformer T is coupled to the input terminal of the hysteresis comparator 50.
  • the isolated half-bridge driver shown in FIG. 12 and FIG. 13 is implemented based on electromagnetic coupling. It uses a transformer T to implement signal shaping transmission, and a hysteresis comparator 50 is used at the output end of the transformer T to implement signal recovery.
  • the input terminal of the transformer T is used to receive an input signal.
  • the input terminal of the transformer T is used to receive a signal output by the driving circuit.
  • the transformer T is used to perform shaping processing on the input signal, and outputs the shaped signal at the output end of the transformer T.
  • the secondary side of the transformer T includes two coils as an example. In practical applications, the secondary side of the transformer T may include one coil or multiple coils. Not limited.
  • the hysteresis comparator 50 is configured to receive the above-mentioned shaped signal and convert the shaped signal into a square wave signal.
  • the output terminal of the hysteresis comparator 50 is used to output the above-mentioned square wave signal.
  • the output of the hysteresis comparator 50 may be coupled to the input of the driver, and the output of the driver (OUT1 and OUT2 shown in the figure) may be coupled to the driving tube respectively.
  • the signal realizes controlling the driving tube.
  • the POR circuit 20 and the isolated half-bridge driver share the same power source, and the power source can provide power to each component in the POR circuit 20 to make it work normally.
  • the POR circuit 20 is used to output a reset signal during the power-on process to set the hysteresis comparator 50 to an initial state.
  • the reset signal output by the POR circuit 20 is a pull-down level signal (that is, as shown in FIGS. 6-8, the ground is output as a reset signal)
  • the hysteresis comparator 50 is pulled down to the initial state;
  • the reset signal is a pull-up level signal (that is, as shown in FIG. 9 to FIG. 11, the power supply is output as a reset signal)
  • the hysteresis comparator 50 is pulled up to the initial state.
  • the output of the POR circuit 20 is coupled to the input of the hysteresis comparator 50.
  • the POR circuit 20 is specifically configured to output a reset signal to the input of the hysteresis comparator 50, as shown in node A in the figure. And B. That is, the signal at the input terminal of the hysteresis comparator 50 is controlled by the POR circuit 20 to ensure that the hysteresis comparator 50 outputs a desired signal at the output terminal.
  • the output of the POR circuit 20 is coupled to the output of the hysteresis comparator 50.
  • the POR circuit 20 is specifically configured to output a reset signal to the output of the hysteresis comparator 50, as shown in the figure. C and D are shown. That is, the signal at the output of the hysteresis comparator 50 is directly controlled by the POR circuit 20 so that the hysteresis comparator 50 outputs a desired signal at the output.
  • the output terminal of the POR circuit is coupled to the input terminal or output terminal of the hysteresis comparator, so that the hysteresis comparator is set to the initial state during the power-on process.
  • Coupled may be directly connected or indirectly connected, which is not limited in the embodiments of the present application.

Landscapes

  • Electronic Switches (AREA)

Abstract

本申请公开了一种上电复位电路及隔离式半桥驱动器，该上电复位电路包括：延时电路、反相电路和开关电路。其中，延时电路的一端耦合至电源，延时电路的另一端耦合至地。延时电路用于在电源电压从零电压上升至稳态电压的过程中，输出电压信号。反相电路用于对电压信号执行反相处理，得到控制信号。开关电路用于在控制信号的控制下导通，以将电源或者地作为复位信号输出。本申请实施例提供的方案，在电源上电的过程中，借助于电源电压将开关电路导通，从而将电源或者地作为复位信号输出，实现了在电源上电的整个过程中都能稳定输出复位信号，提高了POR电路的可靠性。

Description

上电复位电路及隔离式半桥驱动器 技术领域
本申请实施例涉及电路技术领域，特别涉及一种上电复位(Power On Reset，POR)电路及隔离式半桥驱动器。
背景技术
目前，高速隔离通信接口应用十分广泛，比如开关式包络跟踪器、高功率密度和效率的隔离式DC-DC(直流-直流)电源模块、需要高隔离电压和高可靠性的逆变器、以及高度自动测试设备等。高速隔离通信接口中的一个重要模块为高速高压隔离模块，也即隔离式半桥驱动器。
常见的隔离式半桥驱动器基于电磁耦合实现，其采用变压器实现信号整形传输，在变压器的输出端采用迟滞比较器实现信号的恢复。迟滞比较器通常偏置在阈值处，在电源上电过程中，迟滞比较器的输出端的逻辑电平处于未知状态。如果从这种不确定的初始状态开始运行，很可能会造成系统的错误执行，甚至会破坏整个系统的正常工作能力。因此，需要POR电路在电源上电的过程中，将迟滞比较器置初态。
请参考图1，其示例性示出了一种现有的POR电路的示意图。由带隙基准(bandgap reference，BGR)电路11产生一基准电压，而后通过比较器12将电源的分压与上述基准电压作比较，并根据比较结果在输出端13输出复位信号。其中，通过串联的电阻R1和电阻R2对电源进行分压。
然而，当上述基于带隙基准实现的POR电路应用在快速上电的过程中，由于基准电压建立时间较长，如果在快速上电过程中基准电压还未建立，则无法在快速上电过程中产生所需的上电复位信号。
发明内容
本申请实施例提供了一种应用于隔离式半桥驱动器中的上电复位电路，可用于解决基于带隙基准实现的POR电路应用在快速上电过程中的情况下，由于基准电压建立时间较长，如果在快速上电过程中基准电压还未建立，则无法在快速上电过程中产生上电复位信号的问题，从而提高POR电路的可靠性。
一方面，本申请实施例提供一种上电复位电路，该上电复位电路包括：延时电路、反相电路和开关电路。其中，延时电路的一端耦合至电源，延时电路的另一端耦合至地。延时电路用于在电源电压从零电压上升至稳态电压的过程中，输出电压信号。反相电路用于对电压信号执行反相处理，得到控制信号。开关电路用于在控制信号的控制下导通，以将电源或者地作为复位信号输出。
本申请实施例提供的方案中，在电源上电的过程中，借助于电源电压将开关电路导通，从而将电源或者地作为复位信号输出，实现了在电源上电的整个过程中都能稳定输出复位信号，提高了POR电路的可靠性。
在一个可能的设计中，开关电路包括：第一NMOS管。第一NMOS管的栅极用于接收 控制信号，并在所述控制信号的控制下导通该第一NMOS管，第一NMOS管的源极耦合至地，第一NMOS管的漏极用于将地作为复位信号输出。
可选地，当开关电路包括第一NMOS管时，如果延时电路输出的电压信号为高电平信号，则反相电路包括2n个级联的反相器，反相电路用于对电压信号执行2n次反相处理，得到控制信号，该控制信号为高电平信号，n为正整数；如果延时电路输出的电压信号为低电平信号，则反相电路包括1个反相器或2m+1个级联的反相器，反相电路用于对电压信号执行1次或2m+1次反相处理，得到控制信号，该控制信号为高电平信号，m为正整数。
在另一个可能的设计中，开关电路包括：第一PMOS管。第一PMOS管的栅极用于接收控制信号，并在所述控制信号的控制下导通该第一PMOS管，第一PMOS管的源极耦合至电源，第一PMOS管的漏极用于将电源作为复位信号输出。
可选地，当开关电路包括第一PMOS管时，如果延时电路输出的电压信号为低电平信号，则反相电路包括2n个级联的反相器，反相电路用于对电压信号执行2n次反相处理，得到控制信号，该控制信号为低电平信号，n为正整数；如果延时电路输出的电压信号为高电平信号，则反相电路包括1个反相器或2m+1个级联的反相器，反相电路用于对电压信号执行1次或2m+1次反相处理，得到控制信号，该控制信号为低电平信号，m为正整数。
针对NMOS管和PMOS管不同的导通特性，NMOS管在高电平信号的驱动下导通，PMOS管在低电平信号的驱动下导通，因此通过反相器对电压信号进行处理，能够生成用于触发MOS管导通的控制信号。
本申请实施例还提供了几种针对延时电路的设计方案：
在一个可能的设计中，延时电路包括：第一电阻和第一电容。第一电阻的第一端耦合至电源，第一电阻的第二端和第一电容的第一端耦合于第一节点，第一电容的第二端耦合至地；在电源电压从零电压上升至稳态电压的过程中，第一节点用于输出电压信号，该电压信号为低电平信号。
在另一个可能的设计中，延时电路包括：第二电阻和第二电容。第二电容的第一端耦合至电源，第二电容的第二端和第二电阻的第一端耦合于第二节点，第二电阻的第二端耦合至地；在电源电压从零电压上升至稳态电压的过程中，第二节点用于输出电压信号，该电压信号为高电平信号。
在另一个可能的设计中，延时电路包括：第二PMOS管、第二NMOS管和第三电阻。第二PMOS管的栅极和第三电阻的第一端耦合，第二PMOS管的源极耦合至电源，第二PMOS管的漏极和第二NMOS管的栅极耦合于第三节点；第三电阻的第二端、第二NMOS管的源极和第二NMOS管的漏极均耦合至地；在电源电压从零电压上升至稳态电压的过程中，第三节点用于输出电压信号，该电压信号为低电平信号。
另一方面，本申请实施例提供一种隔离式半桥驱动器，该隔离式半桥驱动器包括：变压器、迟滞比较器、以及如上述方面所述的上电复位电路。变压器的输出端和迟滞比较器的输入端耦合。上电复位电路用于输出复位信号，以将迟滞比较器置初态。
可选地，上电复位电路具体用于输出复位信号至迟滞比较器的输入端；或者，输出复位信号至迟滞比较器的输出端。
通过将POR电路的输出端耦合至迟滞比较器的输入端或者输出端，实现在电源上电的过程中，将迟滞比较器置初态。
相较于现有技术，本申请实施例提供的方案中，在电源上电的过程中，借助于电源电压将开关电路导通，从而将电源或者地作为复位信号输出，实现了在电源上电的整个过程中都能稳定输出复位信号，提高了POR电路的可靠性。
附图说明
图1是一种现有的POR电路的示意图；
图2是本申请一个实施例提供的POR电路的结构框图；
图3至图5是本申请实施例提供的几种延时电路的电路结构图；
图6至图11是本申请实施例提供的几种POR电路的电路结构图；
图12和图13是本申请实施例提供的隔离式半桥驱动器的电路结构图。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请实施方式作进一步地详细描述。
请参考图2，其示出了本申请一个实施例提供的POR电路的结构框图。该POR电路20包括：延时电路30、反相电路40和开关电路50。其中，延时电路30的一端耦合至电源，延时电路30的另一端耦合至地。
延时电路30，用于在电源电压从零电压上升至稳态电压的过程中，输出电压信号。具体地，延时电路30的输出端和反相电路40的输入端耦合，延时电路30的输出端输出上述电压信号至反相电路40的输入端。
电源用于为POR电路20提供电能，以使得POR电路20能够正常工作。在电源上电的过程中，电源电压将会从零电压上升至稳态电压，稳态电压也可称为正常工作电压。稳态电压的取值可以由实际电路结构和应用场景决定，本申请实施例对此不作限定。
可选地，延时电路30为RC延时电路。
在一个示例中，如图3所示，延时电路30包括：第一电阻R1和第一电容C1。第一电阻R1和第一电容C1串联耦合。第一电阻R1的第一端耦合至电源，第一电阻R1的第二端和第一电容C1的第一端耦合于第一节点31，第一电容C1的第二端耦合至地。第一节点31即为延时电路30的输出端，在电源电压从零电压上升至稳态电压的过程中，第一节点31用于输出电压信号。在电源电压从零电压上升至稳态电压的过程中，第一节点31处的电压相较于电源电压为低电平，因此图3所示的延时电路30输出的电压信号为低电平信号。
在另一个示例中，如图4所示，延时电路30包括：第二电阻R2和第二电容C2。第二电容C2和第二电阻R2串联耦合。第二电容C2的第一端耦合至电源，第二电容C2的第二端和第二电阻R2的第一端耦合于第二节点32，第二电阻R2的第二端耦合至地。第二节点32即为延时电路30的输出端，在电源电压从零电压上升至稳态电压的过程中，第二节点32用于输出电压信号。在电源电压从零电压上升至稳态电压的过程中，因第二电容C2上的电压不能突变，第二电阻R2的电压(也即第二节点32处的电压)随电源电压增加，因此图4所示的延时电路30输出的电压信号为高电平信号。
在又一个示例中，如图5所示，延时电路30包括：第二PMOS管P2、第二NMOS管 N2和第三电阻R3。第二PMOS管P2的栅极和第三电阻R3的第一端耦合，第二PMOS管P2的源极耦合至电源，第二PMOS管P2的漏极和第二NMOS管N2的栅极耦合于第三节点33。第三电阻R3的第二端、第二NMOS管N2的源极和第二NMOS管N2的漏极均耦合至地。第三节点33即为延时电路30的输出端，在电源电压从零电压上升至稳态电压的过程中，第三节点33用于输出电压信号。在电源电压从零电压上升至稳态电压的过程中，第三节点33处的电压相较于电源电压为低电平，因此图5所示的延时电路30输出的电压信号为低电平信号。
在本申请实施例中，对上文所述的电阻(包括第一电阻R1、第二电阻R2、第三电阻R3)的类型不作限定，例如其可以是MOS电阻、多晶电阻(也即Poly电阻)等，其只要能够实现电阻功能即可。在本申请实施例中，对上文所述的电容(包括第一电容C1、第二电容C2)的类型也不作限定，例如其可以是MOS电容、MIM电容、MOM电容等，其只要能够实现电容功能即可。
反相电路40，用于对电压信号执行反相处理，得到控制信号。
可选地，反相电路40包括一个或者多个反相器，通过反相器将电压信号转换为控制信号。反相电路40的输出端和开关电路50的输入端耦合，反相电路40的输出端输出上述控制信号至开关电路50的输入端。
开关电路50，用于在控制信号的控制下导通，以将电源或者地作为复位信号输出。
在本申请实施例中，在电源上电的过程中，借助于电源电压将开关电路50导通，从而将电源或者地作为复位信号输出。
可选地，开关电路50中包括可控开关，可控开关是指能够通过信号控制其导通或断开的开关器件。可选地，可控开关为电压型开关控制器件。电压型开关控制器件能够根据不同的电压，在导通和断开两种不同状态间切换。示例性地，电压型开关控制器件包括以下任意一种：MOSFET(metallic oxide semiconductor field effect transistor，金属氧化物半导体场效应晶体管)、IGBT(insulated gate bipolar transistor，绝缘栅双极型晶体管)、MCT(MOS controlled thyristor，MOS控制晶闸管)、SIT(static induction transistor，静电感应晶体管)。可控开关用于在控制信号的控制下导通，以将电源或者地作为复位信号输出。
在一种可能的实施方式中，开关电路50包括第一NMOS管，也即上述可控开关为第一NMOS管。第一NMOS管的栅极用于接收控制信号，并在控制信号的控制下导通第一NMOS管，第一NMOS管的源极耦合至地，第一NMOS管的漏极用于将地作为复位信号输出。
在另一种可能的实施方式中，开关电路50包括第一PMOS管，也即上述可控开关为第一PMOS管。第一PMOS管的栅极用于接收控制信号，并在控制信号的控制下导通第一PMOS管，第一PMOS管的源极耦合至电源，第一PMOS管的漏极用于将电源作为复位信号输出。
由于NMOS管的栅极在高电平信号下导通，因此当可控开关为第一NMOS管时，反相电路40需要输出高电平信号作为控制信号。可选地，当延时电路30输出的电压信号为高电平信号时(例如当延时电路30采用图4所示结构时)，反相电路40包括2n个级联的反相器，反相电路40用于对电压信号执行2n次反相处理，得到控制信号，该控制信号为高电平信号，n为正整数。当延时电路30输出的电压信号为低电平信号时(例如当延时电路30采用图3或图5所示结构时)，反相电路40包括1个反相器或2m+1个级联的反相器， 反相电路40用于对电压信号执行1次或2m+1次反相处理，得到控制信号，该控制信号为高电平信号，m为正整数。当反相电路40包括1个反相器时，反相电路40用于对电压信号执行1次反相处理得到控制信号；当反相电路40包括2m+1个级联的反相器时，反相电路40用于对电压信号执行2m+1次反相处理得到控制信号。
由于PMOS管的栅极在低电平信号下导通，因此当可控开关为第一PMOS管时，反相电路40需要输出低电平信号作为控制信号。可选地，当延时电路30输出的电压信号为低电平信号时(例如当延时电路30采用图3或图5所示结构时)，反相电路40包括2n个级联的反相器，反相电路40用于对电压信号执行2n次反相处理，得到控制信号，该控制信号为低电平信号，n为正整数。当延时电路30输出的电压信号为高电平信号时(例如当延时电路30采用图4所示结构时)，反相电路40包括1个反相器或2m+1个级联的反相器，反相电路40用于对电压信号执行1次或2m+1次反相处理，得到控制信号，该控制信号为低电平信号，m为正整数。当反相电路40包括1个反相器时，反相电路40用于对电压信号执行1次反相处理得到控制信号；当反相电路40包括2m+1个级联的反相器时，反相电路40用于对电压信号执行2m+1次反相处理得到控制信号。
当电压信号和控制信号均为高电平信号时，或者当电压信号和控制信号均为低电平信号时，反相电路40包括2n个(也即偶数个)级联的反相器。上述2n个反相器中，第i个反相器的输出端和第i+1个反相器的输入端耦合，i为小于2n的正整数。其中，第1个反相器的输入端和延时电路30的输出端耦合，第2n个反相器的输出端和开关电路50的输入端耦合。
当电压信号为高电平信号且控制信号为低电平信号时，或者当电压信号为低电平信号且控制信号为高电平信号时，反相电路40包括1个反相器或2m+1个(也即奇数个)级联的反相器。当反相电路40包括1个反相器时，这一个反相器的输入端和延时电路30的输出端耦合，这一个反相器的输出端和开关电路50的输入端耦合。当反相电路40包括2m+1个级联的反相器时，第j个反相器的输出端和第j+1个反相器的输入端耦合，j为小于2m+1的正整数。其中，第1个反相器的输入端和延时电路30的输出端耦合，第2m+1个反相器的输出端和开关电路50的输入端耦合。
请参考图6-图8，其示出了当开关电路50包括第一NMOS管N1时，3种不同的POR电路20的示意图。
在图6中，延时电路30采用图3所示结构。第一NMOS管N1的栅极和反相电路40的输出端耦合，第一NMOS管N1的源极耦合至地，第一NMOS管N1的漏极为POR电路20的输出端21。在图6中，反相电路40包括1个反相器40a，该反相器40a的输入端和第一节点31耦合，该反相器40a的输出端和第一NMOS管N1的栅极耦合。在电源上电过程中，第一节点31处的电压V1相较于电源电压为低电平，经过反相器40a的转换，V2保持输出高电平，第一NMOS管N1导通，产生一个到地的低阻抗通路，从而将地作为复位信号输出。
在图7中，延时电路30采用图4所示结构。第一NMOS管N1的栅极和反相电路40的输出端耦合，第一NMOS管N1的源极耦合至地，第一NMOS管N1的漏极为POR电路20的输出端21。在图7中，反相电路40包括2个级联的反相器40b和40c，反相器40b的输入端和第二节点32耦合，反相器40b的输出端和反相器40c的输入端耦合，反相器40c 的输出端和第一NMOS管N1的栅极耦合。在电源上电过程中，因第二电容C2上的电压不能突变，第二电阻R2的电压(也即第二节点32处的电压)V1随电源电压增加，经反相器40b和反相器40c的转换后，V2保持输出高电平，第一NMOS管N1导通，产生一个到地的低阻抗通路，从而将地作为复位信号输出。
在图8中，延时电路30采用图5所示结构。第一NMOS管N1的栅极和反相电路40的输出端耦合，第一NMOS管N1的源极耦合至地，第一NMOS管N1的漏极为POR电路20的输出端21。在图8中，反相电路40包括1个反相器40d，该反相器40d的输入端和第三节点33耦合，该反相器40d的输出端和第一NMOS管N1的栅极耦合。在电源上电过程中，第三节点33处的电压V1相较于电源电压为低电平，经过反相器40d的转换，V2保持输出高电平，第一NMOS管N1导通，产生一个到地的低阻抗通路，从而将地作为复位信号输出。
请参考图9-图11，其示出了当开关电路50包括第一PMOS管P1时，3种不同的POR电路20的示意图。
在图9中，延时电路30采用图3所示结构。第一PMOS管P1的栅极和反相电路40的输出端耦合，第一PMOS管P1的源极耦合至电源，第一PMOS管P1的漏极为POR电路20的输出端21。在图9中，反相电路40包括2个级联的反相器40e和40f，反相器40e的输入端和第一节点31耦合，反相器40e的输出端和反相器40f的输入端耦合，反相器40f的输出端和第一PMOS管P1的栅极耦合。在电源上电过程中，第一节点31处的电压V1相较于电源电压为低电平，经反相器40e和反相器40f的转换后，V2保持输出低电平，第一PMOS管P1导通，产生一个到电源的低阻抗通路，从而将电源作为复位信号输出。
在图10中，延时电路30采用图4所示结构。第一PMOS管P1的栅极和反相电路40的输出端耦合，第一PMOS管P1的源极耦合至电源，第一PMOS管P1的漏极为POR电路20的输出端21。在图10中，反相电路40包括1个反相器40g，反相器40g的输入端和第二节点32耦合，反相器40g的输出端和第一PMOS管P1的栅极耦合。在电源上电过程中，因第二电容C2上的电压不能突变，第二电阻R2的电压(也即第二节点32处的电压)V1随电源电压增加，经反相器40g的转换后，V2保持输出低电平，第一PMOS管P1导通，产生一个到电源的低阻抗通路，从而将电源作为复位信号输出。
在图11中，延时电路30采用图5所示结构。第一PMOS管P1的栅极和反相电路40的输出端耦合，第一PMOS管P1的源极耦合至电源，第一PMOS管P1的漏极为POR电路20的输出端21。在图11中，反相电路40包括2个级联的反相器40h和40i，反相器40h的输入端和第三节点33耦合，反相器40h的输出端和反相器40i的输入端耦合，反相器40i的输出端和第一PMOS管P1的栅极耦合。在电源上电过程中，第三节点33处的电压V1相较于电源电压为低电平，经反相器40h和反相器40i的转换后，V2保持输出低电平，第一PMOS管P1导通，产生一个到电源的低阻抗通路，从而将电源作为复位信号输出。
另外，在电源电压达到稳态电压之后，延时电路30的输出端继续输出电压信号，电压信号经反相电路40转换生成控制信号，开关电路50在控制信号的控制下断开，从而停止输出复位信号。
综上所述，本申请实施例提供的技术方案中，在电源上电的过程中，借助于电源电压将开关电路导通，从而将电源或者地作为复位信号输出，实现了在电源上电的整个过程中 都能稳定输出复位信号，提高了POR电路的可靠性。
另外，基于带隙基准实现的POR电路中的BGR电路和比较器在正常工作时需要消耗一定的静态功耗，而本申请实施例提供的POR电路，在正常工作时MOS管无静态电流，因此无静态功耗。
请参考图12和图13，其示出了本申请一个实施例提供的隔离式半桥驱动器的电路示意图。该隔离式半桥驱动器包括：变压器T、迟滞比较器50、以及上文介绍的POR电路20。其中，变压器T的输出端和迟滞比较器50的输入端耦合。
图12和图13所示的隔离式半桥驱动器基于电磁耦合实现，其采用变压器T实现信号整形传输，在变压器T的输出端采用迟滞比较器50实现信号的恢复。
具体来讲，变压器T的输入端用于接收输入信号，例如当变压器T的输入端和驱动电路的输出端耦合时，变压器T的输入端用于接收驱动电路输出的信号。变压器T用于对上述输入信号进行整形处理，并在变压器T的输出端输出整形处理后的信号。在图12和图13中，仅以变压器T的副边包含两个线圈为例，在实际应用中，变压器T的副边可以包含一个线圈，也可以包含多个线圈，本申请实施例对此不作限定。
迟滞比较器50用于接收上述整形处理后的信号，并将该整形处理后的信号转换为方波信号。迟滞比较器50的输出端用于输出上述方波信号。例如，如图12和图13所示，迟滞比较器50的输出端可以和驱动器的输入端耦合，驱动器的输出端(图中所示的OUT1和OUT2)可以分别耦合驱动管，通过上述方波信号实现对驱动管进行控制。
POR电路20和隔离式半桥驱动器共用同一电源，该电源能够为POR电路20中的各个元器件提供电能，使得其正常工作。POR电路20用于在电源上电的过程中，输出复位信号，以将迟滞比较器50置初态。当POR电路20输出的复位信号为下拉电平信号(也即如图6-图8所示，将地作为复位信号输出)时，将迟滞比较器50下拉置初态；当POR电路20输出的复位信号为上拉电平信号(也即如图9-图11所示，将电源作为复位信号输出)时，将迟滞比较器50上拉置初态。
在一个示例中，如图12所示，POR电路20的输出端与迟滞比较器50的输入端耦合，POR电路20具体用于输出复位信号至迟滞比较器50的输入端，如图中节点A和B所示。也即，通过POR电路20对迟滞比较器50的输入端的信号进行控制，从而确保迟滞比较器50在输出端输出期望的信号。
在另一个示例中，如图13所示，POR电路20的输出端与迟滞比较器50的输出端耦合，POR电路20具体用于输出复位信号至迟滞比较器50的输出端，如图中节点C和D所示。也即，通过POR电路20直接对迟滞比较器50的输出端的信号进行控制，以使得迟滞比较器50在输出端输出期望的信号。
综上所述，本申请实施例提供的方案中，通过将POR电路的输出端耦合至迟滞比较器的输入端或者输出端，实现在电源上电的过程中，将迟滞比较器置初态。
在本文中所述的“耦合”可以是直接相连，也可以间接相连，本申请实施例对此不作限定。
以上所述的具体实施方式，对本申请实施例的目的、技术方案和有益效果进行了进一步详细说明，所应理解的是，以上所述仅为本申请实施例的具体实施方式而已，并不用于 限定本申请实施例的保护范围，凡在本申请实施例的技术方案的基础之上，所做的任何修改、等同替换、改进等，均应包括在本申请实施例的保护范围之内。

Claims (10)

  1. 一种上电复位电路，其特征在于，所述上电复位电路包括：延时电路、反相电路和开关电路；其中，所述延时电路的一端耦合至电源，所述延时电路的另一端耦合至地；
    所述延时电路，用于在所述电源电压从零电压上升至稳态电压的过程中，输出电压信号；
    所述反相电路，用于对所述电压信号执行反相处理，得到控制信号；
    所述开关电路，用于在所述控制信号的控制下导通，以将所述电源或者所述地作为复位信号输出。
  2. 根据权利要求1所述的上电复位电路，其特征在于，所述开关电路包括：第一NMOS管；
    所述第一NMOS管的栅极用于接收所述控制信号，并在所述控制信号的控制下导通所述第一NMOS管；
    所述第一NMOS管的源极耦合至所述地；
    所述第一NMOS管的漏极用于将所述地作为所述复位信号输出。
  3. 根据权利要求2所述的上电复位电路，其特征在于，
    当所述电压信号为高电平信号时，所述反相电路包括2n个级联的反相器，所述反相电路用于对所述电压信号执行2n次反相处理，得到所述控制信号，所述控制信号为高电平信号，所述n为正整数；
    或者，
    当所述电压信号为低电平信号时，所述反相电路包括1个反相器或2m+1个级联的反相器，所述反相电路用于对所述电压信号执行1次或2m+1次反相处理，得到所述控制信号，所述控制信号为高电平信号，所述m为正整数。
  4. 根据权利要求1所述的上电复位电路，其特征在于，所述开关电路包括：第一PMOS管；
    所述第一PMOS管的栅极用于接收所述控制信号，并在所述控制信号的控制下导通所述第一PMOS管；
    所述第一PMOS管的源极耦合至所述电源；
    所述第一PMOS管的漏极用于将所述电源作为所述复位信号输出。
  5. 根据权利要求4所述的上电复位电路，其特征在于，
    当所述电压信号为低电平信号时，所述反相电路包括2n个级联的反相器，所述反相电路用于对所述电压信号执行2n次反相处理，得到所述控制信号，所述控制信号为低电平信号，所述n为正整数；
    或者，
    当所述电压信号为高电平信号时，所述反相电路包括1个反相器或2m+1个级联的反相 器，所述反相电路用于对所述电压信号执行1次或2m+1次反相处理，得到所述控制信号，所述控制信号为低电平信号，所述m为正整数。
  6. 根据权利要求1至5任一项所述的上电复位电路，其特征在于，所述延时电路包括：第一电阻和第一电容；
    所述第一电阻的第一端耦合至所述电源；
    所述第一电阻的第二端和所述第一电容的第一端耦合于第一节点；
    所述第一电容的第二端耦合至所述地；
    在所述电源电压从零电压上升至稳态电压的过程中，所述第一节点用于输出所述电压信号，所述电压信号为低电平信号。
  7. 根据权利要求1至5任一项所述的上电复位电路，其特征在于，所述延时电路包括：第二电阻和第二电容；
    所述第二电容的第一端耦合至所述电源；
    所述第二电容的第二端和所述第二电阻的第一端耦合于第二节点；
    所述第二电阻的第二端耦合至所述地；
    在所述电源电压从零电压上升至稳态电压的过程中，所述第二节点用于输出所述电压信号，所述电压信号为高电平信号。
  8. 根据权利要求1至5任一项所述的上电复位电路，其特征在于，所述延时电路包括：第二PMOS管、第二NMOS管和第三电阻；
    所述第二PMOS管的栅极和所述第三电阻的第一端耦合，所述第二PMOS管的源极耦合至所述电源，所述第二PMOS管的漏极和所述第二NMOS管的栅极耦合于第三节点；
    所述第三电阻的第二端、所述第二NMOS管的源极和所述第二NMOS管的漏极均耦合至所述地；
    在所述电源电压从零电压上升至稳态电压的过程中，所述第三节点用于输出所述电压信号，所述电压信号为低电平信号。
  9. 一种隔离式半桥驱动器，其特征在于，所述隔离式半桥驱动器包括：变压器、迟滞比较器、以及如权利要求1至8任一项所述的上电复位电路；
    所述变压器的输出端和所述迟滞比较器的输入端耦合；
    所述上电复位电路用于输出所述复位信号，以将所述迟滞比较器置初态。
  10. 根据权利要求9所述的隔离式半桥驱动器，其特征在于，
    所述上电复位电路具体用于输出所述复位信号至所述迟滞比较器的输入端；或者，输出所述复位信号至所述迟滞比较器的输出端。
PCT/CN2018/089333 2018-05-31 2018-05-31 上电复位电路及隔离式半桥驱动器 WO2019227422A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/CN2018/089333 WO2019227422A1 (zh) 2018-05-31 2018-05-31 上电复位电路及隔离式半桥驱动器
CN201880094042.2A CN112204884B (zh) 2018-05-31 2018-05-31 上电复位电路及隔离式半桥驱动器

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2018/089333 WO2019227422A1 (zh) 2018-05-31 2018-05-31 上电复位电路及隔离式半桥驱动器

Publications (1)

Publication Number Publication Date
WO2019227422A1 true WO2019227422A1 (zh) 2019-12-05

Family

ID=68697712

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2018/089333 WO2019227422A1 (zh) 2018-05-31 2018-05-31 上电复位电路及隔离式半桥驱动器

Country Status (2)

Country Link
CN (1) CN112204884B (zh)
WO (1) WO2019227422A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114421940B (zh) * 2022-03-31 2022-07-26 深圳通锐微电子技术有限公司 一种上电复位电路

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103066972A (zh) * 2013-01-25 2013-04-24 湘潭芯力特电子科技有限公司 一种带有全局使能脉冲控制自动复位功能的上电复位电路
CN106921371A (zh) * 2015-12-28 2017-07-04 上海新微技术研发中心有限公司 低功耗上电复位电路
CN106972846A (zh) * 2017-03-21 2017-07-21 上海华力微电子有限公司 一种上电复位电路

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050001660A1 (en) * 2003-06-26 2005-01-06 Amit Roy Power-on reset circuit
JP5217763B2 (ja) * 2008-07-03 2013-06-19 株式会社リコー 初期化信号出力回路
JP5400567B2 (ja) * 2009-10-23 2014-01-29 株式会社東芝 半導体スイッチ
CN101795132B (zh) * 2010-04-02 2012-11-28 日银Imp微电子有限公司 一种集成电路的i/o口的电位上拉电路和下拉电路
CN102695341B (zh) * 2012-05-28 2014-07-16 矽力杰半导体技术(杭州)有限公司 一种适应于电子变压器的led驱动电源
CN102710242B (zh) * 2012-06-17 2015-04-08 湖南华宽通电子科技有限公司 一种应用于高频pll的片内上电复位检测电路
US8680901B2 (en) * 2012-08-06 2014-03-25 Texas Instruments Incorporated Power on reset generation circuits in integrated circuits
CN103532531A (zh) * 2013-10-12 2014-01-22 中山大学 一种上电复位电路及方法
CN104579263B (zh) * 2013-10-14 2018-04-10 北京同方微电子有限公司 一种高响应速度、低温度系数的复位电路
CN105553460B (zh) * 2015-12-11 2018-09-21 中国航空工业集团公司西安航空计算技术研究所 一种用于1394bphy发送器的驱动器电路
CN107231145B (zh) * 2016-03-23 2020-10-27 中国科学院微电子研究所 复位单元和芯片

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103066972A (zh) * 2013-01-25 2013-04-24 湘潭芯力特电子科技有限公司 一种带有全局使能脉冲控制自动复位功能的上电复位电路
CN106921371A (zh) * 2015-12-28 2017-07-04 上海新微技术研发中心有限公司 低功耗上电复位电路
CN106972846A (zh) * 2017-03-21 2017-07-21 上海华力微电子有限公司 一种上电复位电路

Also Published As

Publication number Publication date
CN112204884B (zh) 2024-04-26
CN112204884A (zh) 2021-01-08

Similar Documents

Publication Publication Date Title
TWI778574B (zh) 電子電路及操作一電子電路之方法
TWI681630B (zh) 半橋式GaN電路及電子組件
US9887697B2 (en) Gate drive circuit to reduce parasitic coupling
US10461737B2 (en) Configurable clamp circuit
US9374090B2 (en) Circuit arrangement and method of operating the same
Liu et al. A 100V gate driver with sub-nanosecond-delay capacitive-coupled level shifting and dynamic timing control for ZVS-based synchronous power converters
WO2020164434A1 (zh) 一种双向电平转换电路和双向电平转换芯片
US20180013423A1 (en) Single-ended-to-differential converter
US7626441B2 (en) Drive circuit with BOT level shifter for transmitting an input signal and assigned method
TW201931771A (zh) 脈衝驅動之功率場效電晶體
WO2019227422A1 (zh) 上电复位电路及隔离式半桥驱动器
KR20200134700A (ko) 전력 스위치용 변조 및 복조 회로
EP3477861B1 (en) Switching device and power conversion device
TW201806319A (zh) 使用升壓電路的位準位移器
US10536147B1 (en) Level shifter
WO2019173272A1 (en) Level shifter circuit
JP2020096444A (ja) スイッチング回路
WO2018152719A1 (zh) 方波产生方法及方波产生电路
TWI804248B (zh) 具有低傳輸延遲的位準轉換器
US12009814B2 (en) Level shifter with low propagation delay
US20230308101A1 (en) Level shifter with low propagation delay
US9537489B1 (en) Level shifter with dynamic bias technique under overstress voltage
CN107547074B (zh) 一种上电复位电路
US20230268918A1 (en) Switching device
CN108205286A (zh) 可编程逻辑控制器及其输出电路和方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18921086

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 18921086

Country of ref document: EP

Kind code of ref document: A1