WO2019223243A1 - 共振隧穿二极管晶圆结构的制备方法 - Google Patents

共振隧穿二极管晶圆结构的制备方法 Download PDF

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WO2019223243A1
WO2019223243A1 PCT/CN2018/113062 CN2018113062W WO2019223243A1 WO 2019223243 A1 WO2019223243 A1 WO 2019223243A1 CN 2018113062 W CN2018113062 W CN 2018113062W WO 2019223243 A1 WO2019223243 A1 WO 2019223243A1
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layer
ingaas
inp
etch
etching
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PCT/CN2018/113062
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French (fr)
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张翠
丁庆
杨旻蔚
孙竹
许奔
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雄安华讯方舟科技有限公司
深圳市太赫兹科技创新研究院
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Publication of WO2019223243A1 publication Critical patent/WO2019223243A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/66196—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices with an active layer made of a group 13/15 material
    • H01L29/66204—Diodes
    • H01L29/66219—Diodes with a heterojunction, e.g. resonant tunneling diodes [RTD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching

Definitions

  • the invention belongs to the field of micro-nano processing technology, and particularly relates to a method for preparing a resonant tunneling diode wafer structure.
  • terahertz waves Due to its unique properties, terahertz waves have a narrow pulse width, high bandwidth, low photon energy, and can penetrate most dry, non-metallic, non-polar substances and dielectric materials. They can be used for detection, imaging, and integration of high-bandwidth wireless communication systems. , Has been widely used in various major fields (aerospace, marine equipment, security, medical, cultural heritage, etc.). However, due to the lack of effective terahertz radiation sources and detection methods, electromagnetic waves in the terahertz frequency band have not been fully studied and applied. In many terahertz practical applications, high-power radiation sources are required to irradiate the target object in order to carry out applications such as detection and imaging.
  • resonant tunneling diode Tunneling diode (RTD) -based monolithic terahertz integrated circuit (TMIC) high-power radiation source has the advantages of room temperature operation, high integration, small size, small power consumption, high frequency, and low cost, and has become the most potential integration Terahertz radiation source.
  • FIG. 1 The wafer structure of a commonly used InP-based InGaAs / Al x In 1-x As material system for preparing resonant tunneling diodes is shown in FIG. 1.
  • the first step in the micro-nano processing preparation process is to top-doped InGaAs (n ++- InGaAs, which is layer 1 in Figure 1) on a clean wafer.
  • the second step is to use wet etching to etch the material to the second layer of heavy doping.
  • InGaAs (n ++- InGaAs, that is, layer 10 in FIG. 1), so that Ti / Pd / Au is deposited thereon to form an ohmic contact at the receiving end (or transmitting end) to facilitate the access of a bias voltage later.
  • the speed of wet etching of InGaAs is approximately 100nm / min. However, if there are factors such as thickness control errors or changes in manufacturing environment factors during the wafer preparation process, the etching speed will be different.
  • the etching speed of 100nm / min is not easy to achieve precise control. Therefore, the prior art needs to be improved.
  • the purpose of the present invention is to overcome the above-mentioned shortcomings of the prior art, and to provide a method for preparing a resonant tunneling diode wafer structure, which aims to solve the problem that the etching precision of the existing resonant tunneling diode wafer structure is not high. technical problem.
  • One aspect of the present invention provides a method for preparing a resonant tunneling diode wafer structure, including the following steps:
  • a first etching solution that can etch InGaAs and AlAs materials but does not etch InP materials is first etched from the second heavily doped InGaAs layer to the InP layer, and then used.
  • a second ohmic contact is formed by depositing a metal on the first heavily doped InGaAs layer after the etching process.
  • an InP layer is deposited on the first heavily doped InGaAs layer, and then two special etching solutions are used.
  • Etching the deposited functional layer that is, the first etching solution that can etch InGaAs and AlAs materials, but not the InP material, is etched to the InP layer, and then the InP material is etched, but InGaAs is not etched Materials and AlAs materials are etched to the first heavily doped InGaAs layer.
  • the two etch solutions can accurately complete each etching reaction to the end.
  • Such an etching method can remove the preparation from the wafer
  • the influence of factors such as thickness control errors or changes in manufacturing environment factors during the process increases the tolerance for experimental errors, and can better achieve accurate control of the wet etching process of resonant tunneling diodes.
  • FIG. 1 is a schematic structural diagram of a resonant tunneling diode wafer obtained by a conventional wet etching process
  • FIG. 2 is a schematic structural diagram of a resonant tunneling diode wafer obtained by wet etching according to the present invention.
  • An embodiment of the present invention provides a method for preparing a resonant tunneling diode wafer structure, including the following steps:
  • a first heavily doped InGaAs layer, an InP layer, a first AlAs barrier layer, an InGaAs potential well layer, a second AlAs barrier layer, and a second heavily doped InGaAs layer are sequentially stacked and deposited on the substrate;
  • S05 depositing a metal on the first heavily doped InGaAs layer after the etching process to form a first ohmic contact.
  • an InP layer is deposited on the first heavily doped InGaAs layer, and then two unique engravings are used.
  • the etchant etches the deposited functional layer, that is, the first etching solution that can etch InGaAs and AlAs materials, but does not etch InP materials, is etched to the InP layer, and then the InP material is etched but not etched
  • the second etching solution that etches InGaAs and AlAs materials is etched to the first heavily doped InGaAs layer.
  • the two etching solutions can accurately complete each etching reaction to the end.
  • Such an etching method can remove the The influence of factors such as thickness control errors or changes in manufacturing environment factors during the circle preparation process increases the tolerance for experimental errors, which can better achieve the precise control of the wet etching process of resonant tunneling diodes.
  • the first heavily doped InGaAs layer may be a collection layer.
  • a metal is deposited on the first ohmic contact to form a receiving layer.
  • the corresponding second heavily doped InGaAs layer is an emission layer, and a second ohmic contact is deposited on the metal to form an emission end structure; or the first heavily doped InGaAs layer may be an emission layer and etched
  • the first ohmic contact is deposited on the metal to form the emitter structure.
  • the second heavily doped InGaAs layer corresponding to this is the collection layer.
  • the second ohmic contact is deposited on the metal to form the receiving end.
  • the InP layer mainly separates the two etching solutions.
  • the wafer first undergoes the etching process of the InGaAs material and the AlAs material until there is no reaction.
  • the InP layer etching ends, and then Go through the etching process of InP material until there is no reaction.
  • the first AlAs barrier layer, the InGaAs potential well layer, and the second AlAs barrier layer are all double barrier structures composed of an undoped functional layer.
  • the InP layer and the A first lightly doped InGaAs layer and a first undoped InGaAs layer are further stacked and deposited between the first AlAs barrier layers, and the first undoped InGaAs layer is in phase with the first AlAs barrier layer. adjacent.
  • a second undoped InGaAs layer and a second lightly doped InGaAs layer are further deposited between the second AlAs barrier layer and the second heavily doped InGaAs layer, and the second undoped InGaAs layer It is adjacent to the second AlAs barrier layer.
  • the first heavily doped InGaAs layer and the first lightly doped InGaAs layer may collectively constitute an emission layer or a collection layer, and accordingly the second heavily doped InGaAs layer and the second lightly doped InGaAs layer may jointly constitute an emission layer or A collection layer, and the first undoped InGaAs layer and the second undoped InGaAs layer can be used as symmetrical spacers at both ends, respectively, for isolating the transmitting / receiving layer from the undoped barrier region.
  • a first low-doped InGaAs layer is also deposited between the first undoped InGaAs layer and the first lightly-doped InGaAs layer.
  • a second low-doped InGaAs layer is also deposited between the second undoped InGaAs layer and the second lightly-doped InGaAs layer.
  • the heavily doped InGaAs layer refers to a doped InGaAs layer having a Si doping concentration of 2 to 3E19 (ie, 2 to 3 ⁇ 10 19 ) cm -1
  • the lightly doped InGaAs layer refers to Si doping.
  • a low-doped InGaAs layer refers to a Si doped concentration of 2 ⁇ 5E16 (ie, 2 ⁇ 5 ⁇ 10 16 ) cm -1 Doped InGaAs layer.
  • the preferred two types of etching solutions have better precision in the etching effect. More preferably, the etching rate using the first etching solution is 100-400 nm / min; the etching rate using the second etching solution is 500-2500 nm / min.
  • the etching temperature of the first etching solution shown is 20 ° C
  • the etching temperature of the second etching solution shown is 20 ° C
  • the metal includes at least one of Ti, Pd, and Au. These metals are deposited on the first heavily doped InGaAs layer and the second heavily doped InGaAs layer, respectively, to better form an ohmic contact.
  • the InP layer is a doped InP layer having a Si doping concentration of 3E18 to 1E19 (ie, 3 ⁇ 10 18 to 1 ⁇ 10 19 ) cm ⁇ 1 .
  • the doped InP layer can make the electrons pass through and pass through smoothly, and the current is more conductive.
  • the substrate is an InP substrate. Because the InGaAs material matches the InP lattice, the lightly doped InP layer allows electrons to pass through and pass through smoothly; therefore, the doped InP in the embodiment of the present invention
  • the introduction of layers will not have a negative impact on device performance, but will be conducive to optimizing the wet etching process for device fabrication.
  • an InAlAs layer is further deposited between the InP layer and the first lightly doped InGaAs layer, and the first etching solution can also etch the InAlAs material, that is, the first etchable material is used.
  • the first etching solution that etches the InGaAs material, the AlAs material, and the InAlAs material, but does not etch the InP material, is etched to the InP layer, and then the etchable InP material, but not the InGaAs material, AlAs material, and the first The two etching solutions etch to the first heavily doped InGaAs layer.
  • a method for manufacturing a resonant tunneling diode wafer structure includes the following steps:
  • a first heavily doped InGaAs layer (layer 11), an InP layer (layer 10), an InAlAs layer (layer 9), and a first lightly doped InGaAs layer (layer 8) are sequentially stacked and deposited on the InP substrate.
  • a first etching solution H 3 PO 4 : H 2 O 2 : H 2 O
  • a first etching solution H 3 PO 4 : H 2 O 2 : H 2 O
  • S15 depositing a metal (Ti / Pd / Au) on the first heavily doped InGaAs layer (layer 11) after the etching process to form a first ohmic contact.
  • a metal Ti / Pd / Au
  • a method for manufacturing a resonant tunneling diode wafer structure includes the following steps:
  • a first heavily doped InGaAs layer (layer 11), an InP layer (layer 10), an InAlAs layer (layer 9), and a first lightly doped InGaAs layer (layer 8) are sequentially stacked and deposited on the InP substrate.
  • a first etching solution H 3 PO 4 : H 2 O 2 : H 2 O
  • a first etching solution H 3 PO 4 : H 2 O 2 : H 2 O
  • S15 depositing a metal (Ti / Pd / Au) on the first heavily doped InGaAs layer (layer 11) after the etching process to form a first ohmic contact.
  • a metal Ti / Pd / Au

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Abstract

本方案涉及一种共振隧穿二极管晶圆结构的制备方法，包括如下步骤：提供衬底；在衬底上依次层叠沉积的第一重掺杂InGaAs层、InP层、第一AlAs势垒层、InGaAs势阱层、第二AlAs势垒层和第二重掺杂InGaAs层；在所述第二重掺杂InGaAs层上沉积金属图形，形成第二欧姆接触；在金属图形以外的区域，先用可刻蚀InGaAs材料和AlAs材料、但不刻蚀InP材料的第一刻蚀液从第二重掺杂InGaAs层刻蚀至InP层，再用可刻蚀InP材料、但不刻蚀InGaAs材料和AlAs材料的第二刻蚀液刻蚀至第一重掺杂InGaAs层；在经刻蚀处理后的第一重掺杂InGaAs层上沉积金属形成第一欧姆接触。

Description

共振隧穿二极管晶圆结构的制备方法 技术领域
本发明属于微纳米加工技术领域，具体涉及一种共振隧穿二极管晶圆结构的制备方法。
 背景技术
太赫兹波因其独特性能，脉宽窄、高带宽、低光子能量、能穿透大部分干燥、非金属、非极性物质和电介质材料，可以用于检测、成像以及集成高宽带无线通讯系统，在各大领域（航空航天、海工装备、安防、医疗、文化遗产等）都有广泛的应用。然而由于缺乏有效的太赫兹辐射源和检测方法，太赫兹频段的电磁波一直未能得到充分研究与应用。在许多太赫兹实际应用中，都需要使用高功率辐射源照射在目标物体上，以此开展检测、成像等应用。因此，有效的高功率太赫兹辐射源成为技术攻关的重中之重。以共振隧穿二极管（resonant tunneling diode，RTD）为基础的单片太赫兹集成电路（TMIC）的高功率辐射源具有室温工作、高度集成化、体积小、功耗小、频率高、成本低等优势成为最有潜力的集成太赫兹辐射源。
用于制备共振隧穿二极管的常用的InP基的InGaAs/Al xIn 1-xAs材料体系的晶圆层结构如图1所示。在基底上沉积各功能层后，用微纳加工技术加工；微纳加工制备过程的第一步是在干净的晶圆上顶层重掺杂的InGaAs（n ++-InGaAs，即图1中层1）上沉积Ti/Pd/Au形成发射端（或接收端）欧姆接触，方便之后偏置电压的接入，第二步便是利用湿法刻蚀的方法将材料腐蚀到第二层重掺杂的InGaAs（n ++-InGaAs，即图1中层10）上，以便在其上沉积Ti/Pd/Au形成接收端（或发射端）欧姆接触，方便之后偏置电压的接入。湿法刻蚀InGaAs的速度大致为100nm/min，然而如果晶圆制备过程出现厚度控制的误差或制备环境因素的改变等因素，刻蚀速度会有所差别，单纯地以需刻蚀的厚度/刻蚀速率，得到刻蚀需用的时间来控制腐蚀过程，很可能会出现误差，而晶圆层结构每层的厚度也是nm级，最薄的只有一点几纳米，最厚的也才百纳米级，100nm/min的刻蚀速度并不容易实现精确的控制。因此，现有技术有待改进。
技术问题
本发明的目的在于克服现有技术的上述不足，提供一种共振隧穿二极管晶圆结构的制备方法，旨在解决现有共振隧穿二极管晶圆结构的制备过程中，刻蚀精度不高的技术问题。
 技术解决方案
为实现上述发明目的，本发明采用的技术方案如下：
本发明一方面提供一种共振隧穿二极管晶圆结构的制备方法，包括如下步骤：
提供衬底；
在所述衬底上依次层叠沉积的第一重掺杂InGaAs层、InP层、第一AlAs势垒层、InGaAs势阱层、第二AlAs势垒层和第二重掺杂InGaAs层；
在所述第二重掺杂InGaAs层上沉积金属图形，形成第一欧姆接触；
在所述金属图形以外的区域，先用可刻蚀InGaAs材料和AlAs材料、但不刻蚀InP材料的第一刻蚀液从所述第二重掺杂InGaAs层刻蚀至InP层，再用可刻蚀InP材料、但不刻蚀InGaAs材料和AlAs材料的第二刻蚀液刻蚀至所述第一重掺杂InGaAs层；
在经刻蚀处理后的所述第一重掺杂InGaAs层上沉积金属形成第二欧姆接触。
 有益效果
本发明提供的共振隧穿二极管晶圆结构的制备方法，在沉积各种功能层的过程中，在第一重掺杂InGaAs层上沉积有一层InP层，然后使用了两种特有的刻蚀液刻蚀沉积的功能层，即先用可刻蚀InGaAs材料和AlAs材料、但不刻蚀InP材料的第一刻蚀液刻蚀至InP层，再用可刻蚀InP材料、但不刻蚀InGaAs材料和AlAs材料的第二刻蚀液刻蚀至第一重掺杂InGaAs层，如此，两种刻蚀液可将每次刻蚀反应精确至结束，这样的刻蚀方法可以去除由晶圆制备过程出现厚度控制的误差或制备环境因素的改变等因素的影响，从而增大对实验误差的容忍度，可以更好地实现共振遂穿二极管的湿法刻蚀过程的精确控制。
 附图说明
图1为现有湿法刻蚀得到的共振隧穿二极管晶圆结构示意图；
图2为本发明湿法刻蚀得到的共振隧穿二极管晶圆结构示意图。
 本发明的实施方式
为了使本发明要解决的技术问题、技术方案及有益效果更加清楚明白，以下结合实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
本发明实施例提供了一种共振隧穿二极管晶圆结构的制备方法，包括如下步骤：
S01：提供衬底；
S02：在所述衬底上依次层叠沉积的第一重掺杂InGaAs层、InP层、第一AlAs势垒层、InGaAs势阱层、第二AlAs势垒层和第二重掺杂InGaAs层；
S03：在所述第二重掺杂InGaAs层上沉积金属图形，形成第二欧姆接触；
S04：在所述金属图形以外的区域，先用可刻蚀InGaAs材料和AlAs材料、但不刻蚀InP材料的第一刻蚀液从所述第二重掺杂InGaAs层刻蚀至InP层，再用可刻蚀InP材料、但不刻蚀InGaAs材料和AlAs材料的第二刻蚀液刻蚀至所述第一重掺杂InGaAs层；
S05：在经刻蚀处理后的所述第一重掺杂InGaAs层上沉积金属形成第一欧姆接触。
本发明实施例提供的共振隧穿二极管晶圆结构的制备方法，在沉积各种功能层的过程中，在第一重掺杂InGaAs层上沉积有一层InP层，然后使用了两种特有的刻蚀液刻蚀沉积的功能层，即先用可刻蚀InGaAs材料和AlAs材料、但不刻蚀InP材料的第一刻蚀液刻蚀至InP层，再用可刻蚀InP材料、但不刻蚀InGaAs材料和AlAs材料的第二刻蚀液刻蚀至第一重掺杂InGaAs层，如此，两种刻蚀液可将每次刻蚀反应精确至结束，这样的刻蚀方法可以去除由晶圆制备过程出现厚度控制的误差或制备环境因素的改变等因素的影响，从而增大对实验误差的容忍度，可以更好地实现共振遂穿二极管的湿法刻蚀过程的精确控制。
在本发明实施例提供的共振隧穿二极管晶圆结构的制备方法中，第一重掺杂InGaAs层可以为收集层，刻蚀结束后，在上沉积金属制成第一欧姆接触，从而形成接收端结构，与此对应的第二重掺杂InGaAs层为发射层，在上沉积金属制成第二欧姆接触，从而形成发射端结构；或者第一重掺杂InGaAs层可以为发射层，刻蚀结束后，在上沉积金属制成第一欧姆接触，从而形成发射端结构，与此对应的第二重掺杂InGaAs层为收集层，在上沉积金属制成第二欧姆接触，从而形成接受端结构；InP层主要对两种刻蚀液起分隔结束作用，在实际操作过程中，晶圆先经历InGaAs材料和AlAs材料的刻蚀过程，直至没有反应，此时到InP层刻蚀结束，再经历InP材料的刻蚀过程，直至没有反应。
进一步地，在上述步骤S02中，第一AlAs势垒层、InGaAs势阱层和第二AlAs势垒层均为未掺杂的功能层组成的双势垒结构，优选地，所述InP层和所述第一AlAs势垒层之间还层叠沉积有第一轻掺杂InGaAs层和第一无掺杂InGaAs层，且所述第一无掺杂InGaAs层与所述第一AlAs势垒层相邻。所述第二AlAs势垒层和所述第二重掺杂InGaAs层之间还层叠沉积有第二无掺杂InGaAs层和第二轻掺杂InGaAs层，且所述第二无掺杂InGaAs层与所述第二AlAs势垒层相邻。此时，第一重掺杂InGaAs层和第一轻掺杂InGaAs层可以共同组成发射层或收集层，对应地第二重掺杂InGaAs层和第二轻掺杂InGaAs层可以共同组成发射层或收集层，而第一无掺杂InGaAs层和第二无掺杂InGaAs层可分别作为两端对称的间隔层，用于隔离发射层/接收层与未掺杂的势垒区。为了使发射层/收集层与未掺杂的双势垒区隔离效果更好，所述第一无掺杂InGaAs层和第一轻掺杂InGaAs层之间还沉积有第一低掺杂InGaAs层，所述第二无掺杂InGaAs层和第二轻掺杂InGaAs层之间还沉积有第二低掺杂InGaAs层。在上述掺杂的InGaAs层中，重掺杂InGaAs层指Si掺杂浓度为2~3E19（即2~3×10 19）cm -1的掺杂InGaAs层，轻掺杂InGaAs层指Si掺杂浓度为2~3E18（即2~3×10 18）cm -1的掺杂InGaAs层，低掺杂InGaAs层指Si掺杂浓度为2~5E16（即2~5×10 16）cm -1的掺杂InGaAs层。
进一步地，在上述步骤S04中，所示第一刻蚀液为H 3PO 4：H 2O 2：H 2O=1：1：8-38的酸溶液。所示第二刻蚀液为HCl：H 3PO 4＝1：1-4的酸溶液。该优选的两种刻蚀液，共同刻蚀的精度效果更优。更优选地，用上述第一刻蚀液的刻蚀速度为100-400nm/min；用上述第二刻蚀液的刻蚀速度为500-2500nm/min。刻蚀液中，水分越多，酸浓度越低，刻蚀速率越低，但根据样品的不同大小使用不同量的刻蚀液进行刻蚀时，使用量对刻蚀速率无明显影响。一般情况下，所示第一刻蚀液的刻蚀温度为20℃，所示第二刻蚀液的刻蚀温度为20℃，该温度条件下可很好地完成刻蚀。
进一步地，在上述步骤S03和S05中，所述金属包括Ti、Pd、Au中的至少一种。用这些金属分别沉积在第一重掺杂InGaAs层和第二重掺杂InGaAs层上，可更好地形成欧姆接触。
进一步地，上述制备方法中，所述InP层为Si掺杂浓度为3E18~1E19（即3×10 18 ~1×10 19）cm -1的掺杂InP层。该掺杂的InP层，可使电子顺利通过及遂穿，电流更加导通。更优选地，所述衬底为InP衬底，因InGaAs材料与InP晶格匹配，而轻度掺杂的InP层，可使电子顺利通过及遂穿；所以本发明实施例的掺杂的InP层的引入不会对器件性能产生负面影响，反而会有利于优化器件制备的湿法刻蚀过程。
进一步地，上述制备方法中，所述InP层和所述第一轻掺杂InGaAs层之间还沉积有InAlAs层，且所述第一刻蚀液还可刻蚀InAlAs材料，即先用可刻蚀InGaAs材料、AlAs材料和InAlAs材料、但不刻蚀InP材料的第一刻蚀液刻蚀至InP层，再用可刻蚀InP材料、但不刻蚀InGaAs材料、AlAs材料和InAlAs材料的第二刻蚀液刻蚀至第一重掺杂InGaAs层。
本发明先后进行过多次试验，现举一部分试验结果作为参考对发明进行进一步详细描述，下面结合具体实施例进行详细说明。
实施例1
一种共振隧穿二极管晶圆结构（见图2）的制备方法，包括如下步骤：
S11：提供InP衬底；
S12：在所述InP衬底上依次层叠沉积的第一重掺杂InGaAs层（层11）、InP层（层10）、InAlAs层（层9）、第一轻掺杂InGaAs层（层8）、第一无掺杂InGaAs层（层7）、第一AlAs势垒层（层6）、InGaAs势阱层（层5）、第二AlAs势垒层（层4）、第二无掺杂InGaAs（层3）、第二轻掺杂InGaAs层（层2）和第二重掺杂InGaAs层（层1）；
S13：在所述第二重掺杂InGaAs层（层1）上沉积金属（Ti/Pd/Au）形成第二欧姆接触；
S14：在所述金属以外的区域，先用可刻蚀InGaAs材料、InAlAs材料和AlAs材料、但不刻蚀InP材料的第一刻蚀液（H 3PO 4：H 2O 2：H 2O=1：1：8的酸溶液）从所述第二重掺杂InGaAs层（层1）刻蚀至InP层（层10），刻蚀温度为20℃，刻蚀速率大约为400nm/min；再用可刻蚀InP材料、但不刻蚀InGaAs材料、InAlAs材料和AlAs材料的第二刻蚀液（HCl：H 3PO 4＝1：1的酸溶液）刻蚀至所述第一重掺杂InGaAs层（层11）；刻蚀温度为20℃，刻蚀速率大约为2500nm/min；
S15：在经刻蚀处理后的所述第一重掺杂InGaAs层（层11）上沉积金属（Ti/Pd/Au）形成第一欧姆接触。
实施例2
一种共振隧穿二极管晶圆结构（见图2）的制备方法，包括如下步骤：
S11：提供InP衬底；
S12：在所述InP衬底上依次层叠沉积的第一重掺杂InGaAs层（层11）、InP层（层10）、InAlAs层（层9）、第一轻掺杂InGaAs层（层8）、第一无掺杂InGaAs层（层7）、第一AlAs势垒层（层6）、InGaAs势阱层（层5）、第二AlAs势垒层（层4）、第二无掺杂InGaAs（层3）、第二轻掺杂InGaAs层（层2）和第二重掺杂InGaAs层（层1）；
S13：在所述第二重掺杂InGaAs层（层1）上沉积金属（Ti/Pd/Au）形成第二欧姆接触；
S14：在所述金属以外的区域，先用可刻蚀InGaAs材料、InAlAs材料和AlAs材料、但不刻蚀InP材料的第一刻蚀液（H 3PO 4：H 2O 2：H 2O=1：1：38的酸溶液）从所述第二重掺杂InGaAs层（层1）刻蚀至InP层（层10），刻蚀温度为20℃，刻蚀速率大约为100nm/min；再用可刻蚀InP材料、但不刻蚀InGaAs材料、InAlAs材料和AlAs材料的第二刻蚀液（HCl：H 3PO 4＝1：4的酸溶液）刻蚀至所述第一重掺杂InGaAs层（层11）；刻蚀温度为20℃，刻蚀速率大约为500nm/min；
S15：在经刻蚀处理后的所述第一重掺杂InGaAs层（层11）上沉积金属（Ti/Pd/Au）形成第一欧姆接触。
以上所述仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。

Claims (10)

  1. 一种共振隧穿二极管晶圆结构的制备方法，其特征在于，包括如下步骤：
    提供衬底；
    在所述衬底上依次层叠沉积的第一重掺杂InGaAs层、InP层、第一AlAs势垒层、InGaAs势阱层、第二AlAs势垒层和第二重掺杂InGaAs层；
    在所述第二重掺杂InGaAs层上沉积金属图形，形成第二欧姆接触；
    在所述金属图形以外的区域，先用可刻蚀InGaAs材料和AlAs材料、但不刻蚀InP材料的第一刻蚀液从所述第二重掺杂InGaAs层刻蚀至InP层，再用可刻蚀InP材料、但不刻蚀InGaAs材料和AlAs材料的第二刻蚀液刻蚀至所述第一重掺杂InGaAs层；
    在经刻蚀处理后的所述第一重掺杂InGaAs层上沉积金属形成第一欧姆接触。
  2. 如权利要求1所述的制备方法，其特征在于，所示第一刻蚀液为H 3PO 4：H 2O 2：H 2O=1：1：8-38的酸溶液。
  3. 如权利要求1所述的制备方法，其特征在于，所示第二刻蚀液为HCl：H 3PO 4＝1：1-4的酸溶液。
  4. 如权利要求1所述的制备方法，其特征在于，所示第一刻蚀液的刻蚀速度为100-400nm/min；和/或
    所示第二刻蚀液的刻蚀速度为500-2500nm/min。
  5. 如权利要求1所述的制备方法，其特征在于，所示第一刻蚀液的刻蚀温度为20℃；和/或
    所示第二刻蚀液的刻蚀温度为20℃。
  6. 如权利要求1所述的制备方法，其特征在于，所述InP层为Si掺杂浓度为3×10 18 cm -1~1×10 19 cm -1的掺杂InP层。
  7. 如权利要求1-6任一项所述的制备方法，其特征在于，所述InP层和所述第一AlAs势垒层之间还层叠沉积有第一轻掺杂InGaAs层和第一无掺杂InGaAs层，且所述第一无掺杂InGaAs层与所述第一AlAs势垒层相邻。
  8. 如权利要求1-6任一项所述的制备方法，其特征在于，所述第二AlAs势垒层和所述第二重掺杂InGaAs层之间还层叠沉积有第二无掺杂InGaAs层和第二轻掺杂InGaAs层，且所述第二无掺杂InGaAs层与所述第二AlAs势垒层相邻。
  9. 如权利要求7任一项所述的制备方法，其特征在于，所述InP层和所述第一轻掺杂InGaAs层之间还沉积有InAlAs层，且所述第一刻蚀液还可刻蚀InAlAs材料。
  10. 如权利要求1-6任一项所述的制备方法，其特征在于，所述衬底为InP衬底；和/或
    所述金属包括Ti、Pd、Au中的至少一种。
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1800890A (zh) * 2006-01-19 2006-07-12 清华大学 一种光源集成的光子晶体带隙限制光波导
CN101064275A (zh) * 2006-04-28 2007-10-31 中国科学院半导体研究所 采用干法刻蚀技术实现rtd与hemt单片集成的方法
CN103022218A (zh) * 2012-12-26 2013-04-03 华中科技大学 一种InAs雪崩光电二极管及其制造方法
CN105720130A (zh) * 2015-07-10 2016-06-29 中国科学院物理研究所 基于量子阱带间跃迁的光电探测器
CN106784123A (zh) * 2016-11-23 2017-05-31 苏州苏纳光电有限公司 单行载流子光电探测器及其制作方法
CN108648997A (zh) * 2018-05-21 2018-10-12 雄安华讯方舟科技有限公司 共振隧穿二极管晶圆结构的制备方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1800890A (zh) * 2006-01-19 2006-07-12 清华大学 一种光源集成的光子晶体带隙限制光波导
CN101064275A (zh) * 2006-04-28 2007-10-31 中国科学院半导体研究所 采用干法刻蚀技术实现rtd与hemt单片集成的方法
CN103022218A (zh) * 2012-12-26 2013-04-03 华中科技大学 一种InAs雪崩光电二极管及其制造方法
CN105720130A (zh) * 2015-07-10 2016-06-29 中国科学院物理研究所 基于量子阱带间跃迁的光电探测器
CN106784123A (zh) * 2016-11-23 2017-05-31 苏州苏纳光电有限公司 单行载流子光电探测器及其制作方法
CN108648997A (zh) * 2018-05-21 2018-10-12 雄安华讯方舟科技有限公司 共振隧穿二极管晶圆结构的制备方法

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