WO2019223175A1 - 一种基于非挥发性存储器的数据自毁方法及系统 - Google Patents

一种基于非挥发性存储器的数据自毁方法及系统 Download PDF

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WO2019223175A1
WO2019223175A1 PCT/CN2018/104545 CN2018104545W WO2019223175A1 WO 2019223175 A1 WO2019223175 A1 WO 2019223175A1 CN 2018104545 W CN2018104545 W CN 2018104545W WO 2019223175 A1 WO2019223175 A1 WO 2019223175A1
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data
storage
self
volatile memory
different
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French (fr)
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陈杰智
曹芮
宫玉昕
杨文静
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山东大学
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Priority to US16/341,877 priority Critical patent/US20210373793A1/en
Priority to JP2019545750A priority patent/JP6835370B2/ja
Publication of WO2019223175A1 publication Critical patent/WO2019223175A1/zh

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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0602Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/062Securing storage systems
    • G06F3/0622Securing storage systems in relation to access
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0602Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0604Improving or facilitating administration, e.g. storage management
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/78Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0602Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/062Securing storage systems
    • G06F3/0623Securing storage systems in relation to content
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0628Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0638Organizing or formatting or addressing of data
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0628Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0646Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
    • G06F3/0652Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0668Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671In-line storage system
    • G06F3/0673Single storage device
    • G06F3/0679Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Definitions

  • the invention relates to a storage method and system for data self-destruction based on physical hardware design, and belongs to the technical field of data self-destruction.
  • a method for physical self-destruction of electronic data disclosed in Chinese patent document CN107608915A is to lay a slow gunpowder layer on the side of the electronic data storage medium that is not in contact with the circuit, and connect the slow gunpowder layer to the ignition device. After the slow gunpowder is ignited by the igniting device, high temperature is generated on the surface of the storage medium, thereby causing physical damage inside the medium to achieve the purpose of data self-destruction.
  • CN105095797A discloses a "physical self-destruction control circuit for an electronic data storage unit".
  • a data encryption management system capable of self-destructing data disclosed by CN105279457A firstly automatically shards data information input by a user. Any data that reaches a certain length is divided into a data interval. For the data in each data interval, Different data encryption algorithms are used for automatic encryption, and the encryption keys for each interval are encrypted again. At the same time, the user can create a ciphertext password encrypted by the decryptable key.
  • password verification is required for the ciphertext to be browsed. If the verification is successful, the system will automatically decrypt the ciphertext and restore the originally written data information. The user can easily check the data information. If the password verification fails or a malicious crack is detected, the system will activate the data self-destruct function to forcefully and thoroughly erase the data.
  • CN102571949A discloses a "network-based data self-destruction method".
  • CN101615235 discloses a "memory data self-destructing system" including: a cover body for physically closing the memory and a microcontroller; an anti-attack circuit wound around the cover body to form a serpentine wiring arrangement; the anti-attack One end of the line is connected to a power source, and the other end is connected to a microcontroller and grounded through a resistor; the microcontroller is used to detect the level change at the other end of the anti-attack line, and if it changes, erase at least the data stored in the memory Part of the data; a memory for storing data and connecting to the microcontroller, and performing an erasing operation on the data under the control of the microcontroller.
  • Flash memory is currently the most widely used memory.
  • the global market demand for flash memory has increased dramatically.
  • NAND flash memory has a faster erasing and writing time, and the area of each memory cell is also smaller, which makes NAND flash memory have a lower cost per bit and higher storage density than NOR flash memory.
  • NAND flash memory provides extremely high cell density, can achieve high storage density, and write and erase speeds are fast.
  • RRAM resistive-change memory
  • CMOS complementary metal-oxide-semiconductor
  • the invention aims at the shortcomings of the existing data self-destruction technology, and combines the physical and hardware properties of the memory (taking RRAM and NAND flash memory as examples) to provide a non-volatile based on data self-destruction that can achieve different time and realize data storage convenience.
  • a method for self-destructing data in a memory and a system for implementing the method is a method for self-destructing data in a memory and a system for implementing the method.
  • the non-volatile memory-based data self-destruction method of the present invention is:
  • This method is based on non-volatile memory (NVM).
  • NVM non-volatile memory
  • the storage module different storage areas are divided and different data storage times are set (one storage area sets one storage time); different processes are used in different storage areas or
  • the physical material enables the data to self-destruct within a specific storage time; or each storage area dynamically selects a read-write mode for different read-write operations, and the user sets the self-destruct time.
  • the non-volatile memory is RRAM, and different processes or physical materials are used in different storage areas.
  • the specific processes refer to thin film preparation processes, material characterization techniques, and the like.
  • the physical materials are specifically made of electrical level layers and resistive storage layer materials.
  • the choices are mainly resistive storage layer materials.
  • the material system is very rich, including most insulators and semiconductor materials, but the resistance change characteristics are very different.
  • binary oxides are the first choice materials for research.
  • the hardware design itself achieves poor device retention characteristics. You can choose the materials you need to make the data self-destruct within a certain time.
  • the non-volatile memory is RRAM.
  • the read and write operations refer to the writing of data in the storage area under different current states and different voltage pulses.
  • the relationship between the voltage and current is balanced, according to user requirements. Achieve self-destruction of data.
  • the non-volatile memory is a NAND flash memory, and different processes or physical materials are used in different storage areas.
  • the manufacturing process of the chip refers to the thin film process, patterning process, hybridization and heat treatment, etc.
  • the physical material refers to the floating gate, tunnel, etc.
  • the non-volatile memory is a NAND flash memory, and the data retention time of the TLC or MLC device relative to the SLC is short, or the read and write operations refer to writing under high pressure to improve data resident errors and achieve fixed short-term data self-destruction. the goal of.
  • the system includes a storage data interface, a nonvolatile memory controller, a storage area, and a storage data conversion center; the storage data interface is connected to the nonvolatile memory controller; a nonvolatile memory controller is provided with a storage area analysis module and a storage device; Mode control module and storage area analysis module are used to divide different self-destruct time and manage storage area.
  • the storage mode control module is responsible for corresponding working modes of different storage areas.
  • the storage data conversion center is used to realize the dynamic setting of data storage time. The time storage mode is limited at the beginning or dynamically adjusted during the process of reading and writing to the memory.
  • the invention provides a method for deteriorating the device holding characteristics, and achieves the purpose of data self-destruction within a fixed time.
  • the specific method includes: according to the material selection of the RRAM, the device maintains poor characteristics from the process itself. For example, the selection of materials for the electrical level layer and the resistive memory layer. It can also include: writing data in different current states will cause changes in data retention characteristics. If the retention characteristics are poor, write with low current, if the retention characteristics are good, write with high current, and at low current. When writing, the data will be more easily lost, and the data will be self-destructed.
  • the retention time of RRAM is proportional to the write current (voltage), and it can be fixed in the hardware circuit.
  • the storage time of the memory can be changed according to user needs. Under different voltage pulses, the data retention characteristics will also be affected. When data is written under short pulses, the data retention characteristics are poor. Balance the relationship between voltage and current, and realize self-destruction of data according to user requirements.
  • the invention can be based not only on the characteristics of RRAM, but also on the characteristics of NAND flash memory. Aiming at the characteristics of NAND flash memory, combined with the hardware design of the device, the data is self-destructed according to its use time. Specifically, it includes selecting materials with relatively poor data retention characteristics, writing data according to user selection in an actual system, setting a storage time limit, and erasing the original data of the device.
  • the high electric field stress caused by high-voltage operation will cause the tunnel oxide layer to degenerate, resulting in piezo-induced tunnel leakage current. As the tunnel layer continues to shrink, the leakage current becomes more serious, resulting in degradation of retention characteristics and A series of reliability issues such as read crosstalk.
  • writing under high pressure will increase the data resident error and achieve the purpose of fixed data destruction in a short period of time.
  • the memory cells in the MLC mode and the TLC mode are easily degraded, so the data destruction of the memory device of the present invention can be based on multi-value storage, thereby improving the working efficiency of the memory as a whole.
  • the invention is based on the physical properties of the non-volatile memory, and realizes self-destruction within a fixed time through the physical properties of the process and the memory itself. By making the device retention characteristics worse, it achieves data self-destruction within a fixed time. To achieve data self-destruction at different times, the convenience of data storage is realized.
  • Figure 1 is a schematic diagram of the structure of RRAM.
  • FIG. 2 is a resistance transition characteristic diagram of RRAM.
  • FIG. 3 is an I-V (current-voltage) characteristic diagram of RRAM under different holding currents.
  • FIG. 4 is a graph showing the relationship between the duration and voltage of the RRAM voltage pulse and the holding characteristics.
  • FIG. 5 is a structural diagram of a NAND flash memory.
  • FIG. 6 is a schematic diagram of various operation modes of the NAND flash memory.
  • FIG. 7 is a schematic diagram of state transitions of various memory cells of a NAND flash memory.
  • FIG. 8 is a region selection mode of a memory chip.
  • Figure 8 (a) shows the selection mode of self-destructed area and ordinary area for one hour and one day.
  • 8 (b) is a selection mode of a plurality of regions.
  • FIG. 9 is an embodiment of a data self-destructing system.
  • FIG. 10 is an embodiment of dynamic data storage area selection based on data self-destruction.
  • the present invention aims at designing a device for data self-destruction.
  • the present invention selectively keeps the information for a fixed time.
  • the specific implementation is designed by physical hardware, not software design.
  • the invention takes NAND flash memory and RRAM as examples to realize self-destruction of data in hardware design.
  • the non-volatile memory-based data self-destruction method of the present invention is based on a non-volatile memory (NVM).
  • NVM non-volatile memory
  • different storage areas are divided and different storage times are set. Different processes or processes are used in different storage areas. It is a physical material that causes it to self-destruct within a certain time or different read and write operations. The user sets the self-destruct time by itself. Each area dynamically selects the read and write method to achieve data self-destruction.
  • NAND flash memory and RRAM different storage areas are set, and the materials used for each layer of the device and the manufacturing process of the device are determined according to the retention time.
  • the self-destruction of data is realized from the physical characteristics of the device. Take NAND flash memory as an example. High-voltage writing. Selecting MLC or TLC will deteriorate the data retention characteristics and achieve self-destruction of data in a short period of time. RRAM As an example, if data is written under a short pulse and low current, the data retention characteristics will deteriorate, thereby achieving self-destruction of the data in a short time.
  • a fixed area can be divided into a fixed self-destruct time, or the data conversion center of the memory can be used to change the writing mode of the device and adjust the storage time.
  • Figure 1 shows the structure of RRAM.
  • the material structure of the RRAM includes upper and lower electrodes and a resistive function layer, and the resistive function layer material is the core.
  • the material of the resistance change function layer can be selected from many, such as complex multiple oxides, solid electrolyte materials, organic materials, and binary oxides.
  • the specific process refers to the thin film preparation process, material characterization technology, etc. With the optimization of semiconductor manufacturing processes, changes in materials, and differences in device structure design, materials can be used to achieve self-destruction of data within a specific time, and it is more economical. Materials and processes can be flexibly used according to different storage times and different storage characteristics.
  • FIG. 2 shows the resistance transition characteristics of RRAM.
  • RRAM uses the resistance of thin film materials to reversibly switch between high and low resistance states under the effect of electrical excitation to achieve data storage.
  • RRAM includes unipolar and bipolar operation modes. With the proper electrical signal, the resistance of the device will switch between high-resistance state and low-resistance state, so as to realize "0" and "1" storage.
  • a limiting current needs to be applied. The size of the limiting current will affect the retention characteristics of the RRAM.
  • I-V characteristics can generally be divided into three different regions: the current and voltage are linearly related; the current is proportional to the square of the voltage; and the current increases rapidly with the increase of the voltage. Therefore, in actual applications, although the data retention characteristics will deteriorate when the voltage is large, the relationship between the current and the current should be balanced. When the current is small, the data retention characteristics will be deteriorated. According to the relationship between the current and the voltage, determine the required The current and voltage values.
  • Figure 3 shows the I-V characteristics of RRAM under different holding currents. Because of its simple structure and high speed and density, RRAM has attracted widespread attention.
  • the purpose of the present invention is to make the retention characteristics of the RRAM worse, so as to achieve the purpose of data self-destruction. In practical applications, the operating current and performance uniformity are balanced. The performance of the device is better under the condition of larger current. On the contrary, the holding characteristic of the device is worse when the current is relatively small.
  • Figure 4 shows the relationship between the duration and voltage of the RRAM voltage pulse and the retention characteristics.
  • the high-resistance resistor gives reset voltage or the low-resistance resistor gives set voltage for too long or the voltage pulse is too high, the holding characteristics of the resistance change resistor will be deteriorated, and even the resistance state error will occur. This phenomenon not only causes write interference, but also causes waste of energy.
  • the invention can write data in a short pulse according to the needs of the user, the holding characteristics of the device are deteriorated, and the magnitude of the balanced voltage and the current are reaching the economical and economical purpose.
  • Figure 5 shows the structure of a NAND flash memory.
  • Traditional floating gate structure type memory includes: substrate, source, drain, tunneling layer, floating gate, barrier layer (polycrystalline dielectric layer) and control gate and other structures.
  • the floating gate can be replaced with other materials, and the material of the tunneling layer and the barrier layer can be changed. It can be changed according to the specific needs of users. Performance and reliability of NAND flash.
  • Figure 6 shows the different operation modes of NAND flash memory.
  • the current memory operation modes mainly include three read-write modes: single-value storage (SLC), multi-value storage (MLC), and ternary storage (TLC), and quad-value storage (QLC) is also obtained in three-dimensional stereo flash memory application.
  • SLC single-value storage
  • MLC multi-value storage
  • TLC ternary storage
  • QLC quad-value storage
  • SLC means one bit is stored in each unit, with fast erasing and writing speed, large data read window, extremely low byte misread rate, long erasable and rewritable life, but it is expensive; MLC means two bits per unit, density Increased, reduces the cost of storing data on the MLC component, the erasing speed is reduced, and the life is average; TLC means that three bits are stored per unit, the erasing speed is slow, and the erasable life is short. It is very good for a limited consumer market.
  • Each cell of QLC stores four bits, the storage density is 16 times that of SLC mode, but the erasing and writing speed is very slow, and the data read error rate is high, and the number of erasable and erasable times is extremely limited.
  • the present invention just uses MLC and TLC, which is cheap and has a limited number of times of erasing data.
  • Figure 7 shows the state transitions of various memory cells in a NAND flash memory.
  • the device undergoes degradation in the tunneling oxide layer in a high-voltage operation mode (program / erase mode).
  • the state where the threshold voltage is high (right side) in the memory cell is more prone to data resident errors, especially the "01" state and the next highest state "00" with the highest threshold voltage.
  • Figure 8 shows the region selection mode of the memory chip.
  • a single memory chip has many sectors and can be divided into three parts. Several of them are selected as the exclusive area for fixed time self-destruction.
  • Figure 8 (a) shows only one hour and one day. Self-destructed area and ordinary area. Users can be divided into multiple areas according to their needs, as shown in Figure 8 (b).
  • the non-volatile memory-based data self-destruct system of the present invention is shown in FIG. 9 and FIG. 10. Including storage data interface, non-volatile memory controller, storage area and storage data conversion center.
  • the non-volatile memory controller is provided with a storage area analysis module and a storage mode control module.
  • the storage area analysis module is used to divide different self-destruct time and manage the storage area.
  • the storage mode control module is responsible for corresponding to the working mode of different storage areas.
  • the data conversion center is used to realize the dynamic setting of data storage time. Different time storage modes are limited at the initial stage or dynamically adjusted during the process of reading and writing in the memory.
  • Figure 9 shows an embodiment of a data self-destruct system.
  • After obtaining the data input instruction store the data to be saved in the buffer storage space, and then determine the address of the data storage according to the user's storage time requirements, save the data in the set storage area, and then proceed with the data
  • the write operation realizes the self-destruction of the data while maintaining the specified time without error.
  • different write voltages and currents are set through the processing of the storage data conversion center to dynamically determine its storage time and realize the conversion of the data self-destruct time.
  • FIG. 10 shows an embodiment of selecting a data self-destructing dynamic storage area. After designing the self-destruct time, the user can dynamically determine the read-write mode in the storage area according to the requirements. Through the processing of the storage data conversion center, set the required action mode to achieve the data self-destruct time conversion.

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Abstract

一种基于非挥发性存储器的数据自毁方法及系统,该方法是在存储模块中,划分不同的存储区域,设置不同的存储时间;在不同的存储区域使数据在特定的存储时间内自毁,或者是每一存储区域动态的选择读写方式,进行不同的读写操作,用户自行设置自毁时间;该系统包括存储数据接口、非挥发性存储器控制器、存储区域和存储数据转换中心,非挥发性存储器控制器中设置有存储区域分析模块和存储模式控制模块。基于非挥发性存储器物理性质,通过工艺和存储器本身的物理性质来实现数据固定时间内的自毁,通过使器件保持特性变差,实现了固定时间内数据自毁,可以根据用户的需求来实现不同时间的数据自毁,实现了数据存储的方便性。

Description

一种基于非挥发性存储器的数据自毁方法及系统 技术领域
本发明涉及一种基于物理硬件设计的用于数据自毁的存储方法及系统,属于数据自毁技术领域。
背景技术
随着存储性能的提高,大多数人关注于提高数据保持特性及器件的可靠性,但是往往忽略了对于信息安全性的要求。对于某些时效性的信息或是冷信息而言,数据存储在固定时间内自毁即可。一般来说,数据的自毁需要人为的通过软件或是物理硬件来实现。
中国专利文献CN107608915A公开的一种电子数据物理自毁方法,在电子数据存储介质不与电路相接触的一面上铺层一层慢速火药层,并使该慢速火药层与引燃装置相连,慢速火药经引燃装置引燃后在存储介质表面产生高温从而使介质内部产生物理损毁而达到数据自毁的目的。CN105095797A公开了一种《电子数据存储单元的物理自毁控制电路》。
CN105279457A公开的《一种可自毁数据的数据加密管理系统》,首先将用户输入的数据信息进行自动分片,凡是到达一定长度的数据即将其划分为一个数据区间,对于每个数据区间的数据分别采取不同的数据加密算法进行自动加密,各区间的加密的密钥再进行一次加密,同时由用户创建可解密密钥加密后的密文的密码。每当用户进入数据库浏览数据时都需要对所要浏览的密文进行密码验证,凡是验证通过,系统会自动解密密文同时还原初始写入的数据信息,用户可很方便地查阅数据信息。如果密码验证失败或检测到恶意破解,系统将激活数据自毁功能,对数据进行强力彻底的擦除。CN102571949A公开了一种《基于网络的数据自毁方法》。
CN101615235公开的《一种存储器数据自毁系统》包括:罩体,用于物理上封闭所述存储器及微控制器;防攻击线路,缠绕于所述罩体形成蛇形走线排列;该防攻击线路的一端连接电源,另一端连接至微控制器并通过电阻接地;微控制器,用于检测所述防攻击线路的另一端的电平变化,若发生变化,则擦除存储器中所存储至少部分数据;存储器,用于存储数据并连接所述微控制器,在微控制器的控制下对数据进行擦除操作。
人们对数据存储的需求越来越大,对低价格存储器的需求十分强烈,闪存存储器是目前使用最为广泛的存储器。闪存存储器的全球市场需求急剧增加。闪存存储器分为NAND和NOR两种类型。NAND闪存具有较快的擦写时间,而且每个存储单元的面积也较小,这让NAND闪存相较于NOR闪存具有较低的每比特成本与较高的存储密度。NAND闪存提供极高的单元密度,可以达到高存储密度,并且写入和擦除的速度也很快。
RRAM(阻变式存储器)在闪存的特征尺寸无法持续缩小的情况下,作为下一代新型非挥发性存储器,具有结构简单、操作速度快、低功耗、易于三维集成以及与传统CMOS工艺兼容等特征。经过多年的发展,RRAM的可靠性、稳定性和均一性在不断的接近产业化的要求, 学术界和工业界的研究热点已经从RRAM器件的改善转向大规模集成技术的研究。
现有的数据自毁技术均是来自存储器外部以及使用软件编程实现,不能在存储器自身硬件设计上实现对数据的自毁,而且不能选择性的使其保持固定的时间。
发明内容
本发明针对现有数据自毁技术存在的不足,结合存储器物理硬件性质(以RRAM和NAND闪存为例),提供一种能够实现不同时间的数据自毁,实现数据存储方便性的基于非挥发性存储器的数据自毁方法,同时提供一种实现该方法的系统。
本发明的基于非挥发性存储器的数据自毁方法,是:
该方法,基于非挥发性存储器(NVM),在存储模块中,划分不同的存储区域,设置不同的数据存储时间(一个存储区域设置一个存储时间);在不同的存储区域使用不同的工艺或是物理材料,使数据在特定的存储时间内自毁;或者是每一存储区域动态的选择读写方式,进行不同的读写操作,用户自行设置自毁时间。
所述非挥发性存储器为RRAM,在不同的存储区域使用不同的工艺或是物理材料,具体工艺指薄膜制备工艺,材料表征技术等,物理材料具体是通过电级层与阻变存储层材料的选择,主要是阻变存储层材料,材料体系非常丰富,包括了大部分的绝缘体和半导体材料,但是阻变特性千差万别,目前二元氧化物为研究首选材料,从硬件设计本身实现器件保持特性差,可以根据需要选择所需材料,使数据在特定时间内自毁。
所述非挥发性存储器为RRAM,读写操作是指存储区域在不同大小的电流状态下和不同的电压脉冲下实现数据的写入,平衡电压大小与电流大小之间的关系,根据用户的要求实现数据的自毁。
所述非挥发性存储器为NAND闪存,在不同的存储区域使用不同的工艺或是物理材料,芯片的制造工艺是指薄膜工艺,图形化工艺,参杂和热处理等,物理材料指浮栅,隧穿层和阻挡层材料的电阻率,材料的物理特征,以及器件的物理尺寸。选择数据保持特性相对差的材料,根据用户选择来进行数据写入,根据设定的存储时限,对器件的原有数据进行擦除。
所述非挥发性存储器为NAND闪存,TLC或是MLC器件相对于SLC的数据保持时间短,或是读写操作是指高压下进行写入,提高数据驻留错误,达到固定短时间数据自毁的目的。
实现上述方法的数据自毁系统,采用以下技术方案:
该系统,包括存储数据接口、非挥发性存储器控制器、存储区域和存储数据转换中心;存储数据接口与非挥发性存储器控制器连接;非挥发性存储器控制器中设置有存储区域分析模块和存储模式控制模块,存储区域分析模块用于划分不同自毁时间和管理存储区域,存储模式控制模块负责与不同存储区域的工作模式对应,存储数据转换中心用于实现数据保存时间的动态设定,不同的时间存储模式在初期限定,或者在存储器读写的过程中动态调整。
在获得数据输入指令后,将需要保存的数据存储在缓冲存储空间中,然后根据用户保存时间的要求来确定数据存储的地址,将数据保存在所设定的存储区域中,接下来就进行数据的写入操作,在确定无误的情况下在保持特定时间下实现数据的自毁;当用户设计好自毁时 间后,在存储区域根据需求,通过存储数据转换中心的处理设定不同的写入电压电流,动态的决定其存储时间,实现数据自毁时间的转换。
以非挥发性存储器中RRAM和NAND闪存为例,来介绍此系统。
本发明针对RRAM的器件特性,结合存储器物理硬件性质,提供了器件保持特性变差的方法,实现了固定时间内数据自毁的目的。具体方法包括:针对于RRAM的材料选择,从工艺本身实现器件保持特性差。例如电级层与阻变存储层材料的选择。还可以包括:在不同大小的电流状态下实现数据的写入,会导致数据保持特性的变化,保持特性差的就用低电流写入,保持特性好的就用高电流写入,在低电流下写入时,数据会更加容易丢失,进而实现数据的自毁。RRAM的保存时间与写入电流(电压)成比例关系,可以把其工作方式固定到硬件电路中。当读写的时候就可以根据用户需求来改变存储器的存储时间。在不同的电压脉冲下,对数据保持特性也会产生影响,在短脉冲下写入数据,数据的保持特性就较差。平衡电压大小与电流大小之间的关系,根据用户的要求实现数据的自毁。
本发明不仅可以基于RRAM特性,还可以基于NAND闪存的特性。针对于NAND闪存特性,结合器件的硬件设计,根据其使用时限,实现数据的自毁。具体包括:选择数据保持特性相对差的材料,在实际系统中根据用户选择来进行数据写入,设定的存储时限,对器件的原有数据进行擦除。具体还包括:高压操作带来的高电场应力会使隧穿氧化层发生退化,产生压致隧穿层漏电流,随着隧穿层的不断缩小,泄漏电流越发严重,从而产生保持特性退化和读取串扰等一系列可靠性问题。在具体的实施方式中,高压下进行写入,会使得数据驻留错误就会提高,达到固定短时间数据自毁的目的。在存储单元擦写的过程中,MLC模式和TLC模式下的存储单元容易退化,所以本发明的存储器件数据自毁可基于多值存储,从而整体上提高存储器的工作效率。
本发明基于非挥发性存储器物理性质,通过工艺和存储器本身的物理性质来实现数据固定时间内的自毁,通过使器件保持特性变差,实现了固定时间内数据自毁,可以根据用户的需求来实现不同时间的数据自毁,实现了数据存储的方便性。
附图说明
图1是RRAM的结构示意图。
图2是RRAM的电阻转变特性图。
图3是RRAM在不同的保持电流下的I-V(电流-电压)特性图。
图4是RRAM电压脉冲持续时间和电压大小与保持特性的关系图。
图5是NAND闪存的结构示意图。
图6是NAND闪存各种不同动作模式的示意图。
图7是NAND闪存各种不同存储单元状态转换示意图。
图8是存储器芯片的区域选择模式。图8(a)是一个小时,一天的自毁区域和普通区域的选择模式。8(b)是多个区域的选择模式。
图9是基于数据自毁系统的一个实施例。
图10是基于数据自毁动态存储区域选择的一个实施例。
具体实施方式
本发明旨在设计一种数据自毁的器件,对于信息内容本发明有选择性的使其保持固定的时间,具体的实现是通过物理硬件进行设计,而不是软件设计。本发明以NAND闪存及RRAM为例,在硬件设计上实现对数据的自毁。
本发明的基于非挥发性存储器的数据自毁方法,基于非挥发性存储器(NVM),在存储模块中,划分不同的存储区域,设置不同的存储时间;在不同的存储区域使用不同的工艺或是物理材料,使其在特定时间内自毁,或者是不同的读写操作,用户自行设置自毁时间,每一区域动态的选择读写方式,实现数据自毁。
以NAND闪存和RRAM为例,设定不同的存储区域,根据保持时间的不同,来确定其器件每一层所用的材料及器件的制造工艺。从器件的物理特性来实现数据的自毁,以NAND闪存为例,高压写入,选择MLC或是TLC,会使数据的保持特性变差,从而达到短时间内数据数据的自毁;以RRAM为例,在短脉冲低电流下写入数据,数据的保持特性就会变差,从而达到短时间内数据数据的自毁。在存储器的存储区域设计中,可以划分固定的区域固定的自毁时间,也可以通过存储器的数据转换中心,改变器件其写入方式,调整存储时间。
以下以非挥发性存储器中RRAM和NAND闪存为例,对本发明详细说明。
图1给出了RRAM的结构。RRAM的材料结构包括上下电极以及阻变功能层,阻变功能层材料是核心。选择不同的材料组合,器件的性能参数会发生很大的差异。阻变功能层的材料可选择的非常多,比如复杂多元氧化物、固态电解液材料、有机材料以及二元氧化物等。具体工艺指薄膜制备工艺,材料表征技术等。随着半导体制造工艺的优化,材料的变化,器件结构设计的不同,可以通过材料来实现特定时间内数据的自毁,并且更加经济。可以根据不同存储时间、不同的存储特点来灵活的使用材料及工艺。
图2给出了RRAM的电阻转变特性。RRAM以薄膜材料的电阻在电激励的作用下在高低阻态之间可逆转换,来实现数据的存储。RRAM包括单极性和双极性两种操作方式。在适当的电信号作用下,器件的电阻会在高阻态和低阻态之间相互转换,从而实现“0”和“1”的存储。为了避免SET过程中造成器件的永久性击穿,需要施加一个限制电流,限制电流的大小会影响RRAM的保持特性。
I-V特性一般可以分为三个不同的区域:电流电压成线性关系;电流与电压的平方成正比;电流随电压的增大迅速增加。所以在实际的应用中,虽然电压较大时,数据的保持特性会变差,但是要平衡与电流的关系,电流较小时,数据保持特性会变差,根据电流和电压的关系,确定所需的电流和电压的数值。
图3给出了RRAM在不同的保持电流下的I-V特性。由于RRAM的结构简单,速度快密度高,所以RRAM得到了广泛的关注。本发明的目的是使RRAM的保持特性变差,从而使之达到数据自毁的目的,实际的应用中在平衡操作电流和性能的均匀性。在电流较大的状态下,器件的性能较好,相反,在电流相对较小的情况下,器件的保持特性较差。
图4给出了RRAM电压脉冲持续时间和电压大小与保持特性的关系。当高阻态电阻给reset电压或者对低阻态电阻给set电压时间过长或者电压脉冲过高造成阻变电阻的保持特性变差,甚至会发生阻态翻转错误的情况。此种现象不仅会造成写干扰,也会造成能量的浪费。本发明可以根据用户的需要,在短脉冲内写入数据,器件的保持特性变差,平衡电压大小和电流大小,正达到了经济实惠的目的。
图5给出了NAND闪存的结构。传统的浮栅结构类型存储器包括:衬底,源极,漏极,隧穿层,浮栅,阻挡层(多晶间介质层)和控制栅等结构。随着工艺(薄膜工艺,图形化工艺,参杂和热处理等)改变和优化,浮栅可以用其它材料代替,隧穿层和阻挡层材料都可以发生改变,可以根据用户的特定需求,改变了NAND闪存的性能和可靠性。
图6给出了NAND闪存的各种不同动作模式。目前存储器动作模式中,主要包括三种读写方式单值存储(SLC)、多值存储(MLC)和三值存储(TLC),而四值存储(QLC)在三维立体闪存存储器中也得到了应用。SLC即每个单元存储一个比特,擦写速度快,数据读取窗口大,字节误读率极低,可擦写寿命长,但是其价格昂贵;MLC即每个单元存储两个比特,密度增大,降低了在MLC组件上存储数据的成本,擦写速度下降,寿命一般;TLC即每个单元存储三个比特,擦写速度慢,可擦写寿命短,TLC的低成本对于写入有限的消费者市场来说是非常好的。QLC每个单元存储四个比特,存储密度是SLC模式的16倍,但擦写速度很慢,而且数据读取错误率高,其可擦写次数也极为有限。本发明恰恰使用MLC及TLC的价格便宜以及擦写数据次数有限。
图7给出了NAND闪存各种不同存储单元状态转换。一般来说,器件在高压操作模式(编程/擦除模式)下,隧穿氧化层发生退化。存储单元中处于阈值电压较高(右侧)的状态更容易发生数据驻留错误,尤其是阈值电压最高的“01”状态和次高态“00”。处于阈值电压最低侧的擦除状态“11”是不存在数据驻留错误的。所以从NAND闪存使用者的角度来看,如果能够通过一定的数据处理手段来提高存储胞元中“01”状态的占比,那么NAND闪存所面临的数据驻留错误就会提高。
图8给出了存储器芯片的区域选择模式。一个单一的存储芯片,有很多的扇区(Block),可以分成三个部分,选择其中的几个Block为固定时间自毁的专属区域,图8(a)中只给出了一个小时,一天的自毁区域和普通区域。用户可以根据自己的需求,分为多个区域,如图8(b)。
本发明的基于非挥发性存储器的数据自毁系统,参见图9和图10。包括存储数据接口、非挥发性存储器控制器、存储区域和存储数据转换中心。非挥发性存储器控制器中设置有存储区域分析模块和存储模式控制模块,存储区域分析模块用于划分不同自毁时间和管理存储区域,存储模式控制模块负责与不同存储区域的工作模式对应,存储数据转换中心用于实现数据保存时间的动态设定,不同的时间存储模式在初期限定,或者在存储器读写的过程中动态调整。
图9给出了数据自毁系统的一个实施例。在获得数据输入指令后,将需要保存的数据存储在缓冲存储空间中,然后根据用户保存时间的要求来确定数据存储的地址,将数据保存在所设定的存储区域中,接下来就进行数据的写入操作,在确定无误的情况下在保持特定时间 下实现数据的自毁。当用户设计好自毁时间后,在存储区域根据需求,通过存储数据转换中心的处理设定不同的写入电压电流,动态的决定其存储时间,实现数据自毁时间的转换。
图10给出了数据自毁动态存储区域选择的一个实施例。当用户设计好自毁时间后,可以在存储区域根据需求,动态的决定其读写方式,通过存储数据转换中心的处理,设定其所需的动作模式,实现数据自毁时间的转换。
本发明中未详细叙述的部分均为现有技术。

Claims (6)

  1. 一种基于非挥发性存储器的数据自毁方法,其特征是:基于非挥发性存储器,在存储模块中,划分不同的存储区域,设置不同的存储时间;在不同的存储区域使用不同的工艺或是物理材料,使数据在特定的存储时间内自毁,或者是每一存储区域动态的选择读写方式,进行不同的读写操作,用户自行设置自毁时间。
  2. 根据权利要求1所述的基于非挥发性存储器的数据自毁方法,其特征是:所述非挥发性存储器为RRAM,在不同的存储区域使用不同的工艺或是物理材料,从工艺本身实现器件保持特性差,使数据在特定时间内自毁。
  3. 根据权利要求1所述的基于非挥发性存储器的数据自毁方法,其特征是:所述非挥发性存储器为RRAM,读写操作是指存储区域在不同大小的电流状态下和不同的电压脉冲下实现数据的写入。
  4. 根据权利要求1所述的基于非挥发性存储器的数据自毁方法,其特征是:所述非挥发性存储器为NAND闪存,在不同的存储区域使用不同的工艺或是物理材料,是指选择数据保持特性相对差的材料,根据用户选择来进行数据写入,根据设定的存储时限,对器件的原有数据进行擦除。
  5. 根据权利要求1所述的基于非挥发性存储器的数据自毁方法,其特征是:所述非挥发性存储器为NAND闪存,读写操作是指高压下进行写入,提高数据驻留错误,达到固定短时间数据自毁的目的。
  6. 一种基于非挥发性存储器的数据自毁系统,其特征是:包括存储数据接口、非挥发性存储器控制器、存储区域和存储数据转换中心;非挥发性存储器控制器中设置有存储区域分析模块和存储模式控制模块,存储区域分析模块用于划分不同自毁时间和管理存储区域,存储模式控制模块负责与不同存储区域的工作模式对应,存储数据转换中心用于实现数据保存时间的动态设定,不同的时间存储模式在初期限定,或者在存储器读写的过程中动态调整。
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Publication number Priority date Publication date Assignee Title
CN111994456A (zh) * 2020-08-20 2020-11-27 天地融科技股份有限公司 一种液体容器的发电自毁式防伪装置和系统
CN113779650A (zh) * 2021-09-16 2021-12-10 北京理工大学 一种用于非易失性存储器的微冲击瞬态自毁芯片及其自毁方法

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2021094844A1 (ja) * 2019-11-11 2021-05-20 株式会社半導体エネルギー研究所 情報処理装置、および情報処理装置の動作方法
JP2021140847A (ja) * 2020-03-05 2021-09-16 キオクシア株式会社 半導体記憶装置
CN112213969B (zh) * 2020-06-01 2024-05-31 广州云利数码科技有限公司 基于军事化物联网的智能辅助执法管理辅助系统
TWI829053B (zh) * 2021-12-22 2024-01-11 彭昭雄 銷毀通訊設備內記憶體用的銷毀裝置
CN116774905A (zh) * 2022-03-07 2023-09-19 华为技术有限公司 一种存储装置及相关数据分区管理方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101329894A (zh) * 2008-07-24 2008-12-24 中国科学院上海微系统与信息技术研究所 一种新型存储系统
US20090287893A1 (en) * 2008-05-16 2009-11-19 Skymedi Corporation Method for managing memory
CN102194518A (zh) * 2010-03-08 2011-09-21 上海宏力半导体制造有限公司 存储器
CN105427886A (zh) * 2015-12-01 2016-03-23 清华大学 NAND Flash存储系统保存期间数据分步加重方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03137897A (ja) * 1989-10-23 1991-06-12 Matsushita Giken Kk 擬似神経機能素子
CN201788500U (zh) * 2009-11-20 2011-04-06 西安奇维测控科技有限公司 一种具有加密和数据自毁功能的电子硬盘
US9952809B2 (en) * 2013-11-01 2018-04-24 Dell Products, L.P. Self destroying LUN
JP2017058913A (ja) * 2015-09-16 2017-03-23 ルネサスエレクトロニクス株式会社 記憶装置及び記憶方法
JP6717024B2 (ja) * 2016-04-18 2020-07-01 富士通株式会社 メモリおよびメモリの制御方法
CN106557283A (zh) * 2016-11-16 2017-04-05 郑州云海信息技术有限公司 一种固态硬盘自毁方法及装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090287893A1 (en) * 2008-05-16 2009-11-19 Skymedi Corporation Method for managing memory
CN101329894A (zh) * 2008-07-24 2008-12-24 中国科学院上海微系统与信息技术研究所 一种新型存储系统
CN102194518A (zh) * 2010-03-08 2011-09-21 上海宏力半导体制造有限公司 存储器
CN105427886A (zh) * 2015-12-01 2016-03-23 清华大学 NAND Flash存储系统保存期间数据分步加重方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111994456A (zh) * 2020-08-20 2020-11-27 天地融科技股份有限公司 一种液体容器的发电自毁式防伪装置和系统
CN113779650A (zh) * 2021-09-16 2021-12-10 北京理工大学 一种用于非易失性存储器的微冲击瞬态自毁芯片及其自毁方法

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