WO2019220782A1 - Failure diagnostic method, power converting device, motor module, and electric power steering device - Google Patents

Failure diagnostic method, power converting device, motor module, and electric power steering device Download PDF

Info

Publication number
WO2019220782A1
WO2019220782A1 PCT/JP2019/013062 JP2019013062W WO2019220782A1 WO 2019220782 A1 WO2019220782 A1 WO 2019220782A1 JP 2019013062 W JP2019013062 W JP 2019013062W WO 2019220782 A1 WO2019220782 A1 WO 2019220782A1
Authority
WO
WIPO (PCT)
Prior art keywords
switch element
failed
phase
failure
inverter
Prior art date
Application number
PCT/JP2019/013062
Other languages
French (fr)
Japanese (ja)
Inventor
アハマッド ガデリー
Original Assignee
日本電産株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電産株式会社 filed Critical 日本電産株式会社
Priority to JP2020519495A priority Critical patent/JPWO2019220782A1/en
Publication of WO2019220782A1 publication Critical patent/WO2019220782A1/en

Links

Images

Classifications

    • BPERFORMING OPERATIONS; TRANSPORTING
    • B62LAND VEHICLES FOR TRAVELLING OTHERWISE THAN ON RAILS
    • B62DMOTOR VEHICLES; TRAILERS
    • B62D5/00Power-assisted or power-driven steering
    • B62D5/04Power-assisted or power-driven steering electrical, e.g. using an electric servo-motor connected to, or forming part of, the steering gear
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode

Definitions

  • the present disclosure relates to a failure diagnosis method, a power conversion device, a motor module, and an electric power steering device.
  • Patent Document 1 discloses a motor drive device having a first system and a second system.
  • the first system is connected to the first winding set of the motor and includes a first inverter unit, a power supply relay, a reverse connection protection relay, and the like.
  • the second system is connected to the second winding set of the motor and includes a second inverter unit, a power supply relay, a reverse connection protection relay, and the like.
  • the power relay is connected to the failed system or from the power source. The power supply to the system connected to the winding set is cut off. It is possible to continue motor driving using the other system that has not failed.
  • Patent Documents 2 and 3 also disclose a motor drive device having a first system and a second system. Even if one system or one winding set fails, motor drive can be continued by a system that does not fail.
  • Embodiment of this indication provides the failure diagnostic method which can diagnose appropriately the failure of the switch element with which a power converter is provided.
  • An exemplary failure diagnosis method of the present disclosure is a failure diagnosis method for diagnosing a failure in a power conversion device that converts electric power from a power source into electric power supplied to a motor having at least one phase winding, the electric power
  • the converter includes a first inverter connected to one end of the at least one phase winding, a second inverter connected to the other end of the at least one phase winding, each of which is a first high-side switch element, At least one H-bridge having a first low-side switch element, a second high-side switch element, and a second low-side switch element, and the failure diagnosis method determines whether there is a failed phase in the at least one phase Determining whether there is a failed part in the high side and low side of the at least one H-bridge; and And whether there is a faulty inverter in the data and the second inverter, a judgment result of whether there is a faulty phase, a judgment result of whether there is a faulty part, and whether there is a faulty in
  • An exemplary power conversion device of the present disclosure is a power conversion device that converts power from a power source into power supplied to a motor having at least one phase winding, the power conversion device including the at least one phase.
  • a first inverter connected to one end of the first winding, a second inverter connected to the other end of the at least one-phase winding, a first high-side switch element, a first low-side switch element, a second And at least one H-bridge having a high-side switch element and a second low-side switch element, and a control circuit for controlling operations of the first inverter and the second inverter, the control circuit comprising the at least one phase Determine if there is a faulty phase and determine if there is a faulty part in the high side and low side of the at least one H-bridge.
  • a failure diagnosis method capable of appropriately diagnosing a failure of a switch element included in a power conversion device, a power conversion device, a motor module including the power conversion device, and the motor module are provided.
  • An electric power steering apparatus is provided.
  • FIG. 1 is a block diagram schematically illustrating a motor module according to an embodiment.
  • FIG. 2 is a circuit diagram schematically showing the inverter unit according to the embodiment.
  • FIG. 3A is a schematic diagram showing an A-phase H-bridge.
  • FIG. 3B is a schematic diagram showing a B-phase H-bridge.
  • FIG. 3C is a schematic diagram showing a C-phase H-bridge.
  • FIG. 4 is a functional block diagram showing a controller that performs overall motor control.
  • FIG. 5 is a diagram illustrating functional blocks for performing fault diagnosis of the A phase, the B phase, and the C phase.
  • FIG. 6 is a diagram illustrating functional blocks for performing a phase A failure diagnosis.
  • FIG. 7 is a diagram illustrating functional blocks for performing a B-phase failure diagnosis.
  • FIG. 1 is a block diagram schematically illustrating a motor module according to an embodiment.
  • FIG. 2 is a circuit diagram schematically showing the inverter unit according to the embodiment.
  • FIG. 8 is a diagram illustrating functional blocks for performing a C-phase failure diagnosis.
  • FIG. 9 is a diagram illustrating functional blocks for performing failure diagnosis of the first inverter and the second inverter.
  • FIG. 10 is a diagram illustrating functional blocks for performing failure diagnosis of the first inverter.
  • FIG. 11 is a diagram illustrating functional blocks for performing failure diagnosis of the second inverter.
  • FIG. 12 is a diagram showing functional blocks for performing a fault diagnosis on the low side of the H-bridge.
  • FIG. 13 is a diagram illustrating functional blocks for performing failure diagnosis on the high side of the H bridge.
  • FIG. 14 is a diagram illustrating functional blocks for performing failure diagnosis of the switch element of the first inverter.
  • FIG. 15 is a diagram illustrating functional blocks for performing failure diagnosis of the switch element of the second inverter.
  • FIG. 16 is a schematic diagram showing a look-up table for determining the saturation voltage Vsat from the rotation speed ⁇ and the current amplitude value.
  • FIG. 17 is a graph illustrating a current waveform (sine wave) obtained by plotting the current values flowing through the windings of the A phase, B phase, and C phase of the motor when the power conversion device is controlled according to the three-phase energization control. It is.
  • FIG. 18 is a graph illustrating a current waveform obtained by plotting the current values flowing through the B-phase and C-phase windings of the motor when the A-phase has failed and the power converter is controlled according to the two-phase energization control. It is.
  • FIG. 19 is a graph exemplifying a current waveform obtained by plotting the current value flowing in each of the C-phase and A-phase windings of the motor when the B-phase has failed and the power conversion device is controlled according to the two-phase energization control. It is.
  • FIG. 19 is a graph exemplifying a current waveform obtained by plotting the current value flowing in each of the C-phase and A-phase windings of the motor when the B-phase has failed and the power conversion device is controlled according to the two-phase energization control. It is.
  • FIG. 19 is a graph exemplifying a current waveform obtained by plotting the current value flowing in each of the C-phase and A-phase winding
  • FIG. 20 is a graph illustrating a current waveform obtained by plotting the current values flowing through the windings of the A phase and B phase of the motor when the power conversion device is controlled according to the two-phase energization control when the C phase fails. It is.
  • FIG. 21 is a graph showing waveforms of simulation results of the actual voltage VA1 (upper side) and the actual voltage VA2 (lower side) when the low-side switch element SW_A1L has an open failure.
  • FIG. 22 is a graph showing waveforms of simulation results of the actual voltage VB1 (upper side) and the actual voltage VB2 (lower side) when the low-side switch element SW_A1L has an open failure.
  • FIG. 21 is a graph showing waveforms of simulation results of the actual voltage VA1 (upper side) and the actual voltage VA2 (lower side) when the low-side switch element SW_A1L has an open failure.
  • FIG. 22 is a graph showing waveforms of simulation results of the actual voltage VB1 (upper
  • FIG. 23 is a graph showing waveforms of simulation results of the actual voltage VC1 (upper side) and the actual voltage VC2 (lower side) when the low-side switch element SW_A1L has an open failure.
  • FIG. 24 is a graph showing waveforms of simulation results of the actual voltage VA1 (upper side) and the actual voltage VA2 (lower side) when the high-side switch element SW_A1H has an open failure.
  • FIG. 25 is a graph showing waveforms of simulation results of the actual voltage VB1 (upper side) and the actual voltage VB2 (lower side) when the high-side switch element SW_A1H has an open failure.
  • FIG. 24 is a graph showing waveforms of simulation results of the actual voltage VA1 (upper side) and the actual voltage VA2 (lower side) when the high-side switch element SW_A1H has an open failure.
  • FIG. 25 is a graph showing waveforms of simulation results of the actual voltage VB1 (upper side) and the actual voltage VB2 (low
  • FIG. 26 is a graph showing waveforms of simulation results of the actual voltage VC1 (upper side) and the actual voltage VC2 (lower side) when the high-side switch element SW_A1H has an open failure.
  • FIG. 27 is a schematic diagram illustrating an electric power steering apparatus according to an exemplary embodiment.
  • a power conversion device that converts power from a power source into power to be supplied to a three-phase motor having three-phase (A-phase, B-phase, and C-phase) windings.
  • a form is demonstrated.
  • a power conversion device that converts electric power from a power source into electric power to be supplied to an n-phase motor having an n-phase winding (n is an integer of 4 or more) such as four-phase or five-phase, and a switch used in the device
  • An element failure diagnosis method is also included in the scope of the present disclosure.
  • FIG. 1 schematically shows a typical block configuration of a motor module 2000 according to the present embodiment.
  • the motor module 2000 typically includes a power converter 1000 having the inverter unit 100 and a control circuit 300 and a motor 200.
  • the motor module 2000 is modularized and can be manufactured and sold as, for example, an electromechanically integrated motor having a motor, a sensor, a driver, and a controller.
  • the power conversion apparatus 1000 can convert power from the power source 101 (see FIG. 2) into power supplied to the motor 200.
  • the power conversion apparatus 1000 is connected to the motor 200.
  • the power conversion apparatus 1000 can convert DC power into three-phase AC power that is pseudo-sine waves of A phase, B phase, and C phase.
  • connection between components (components) mainly means electrical connection.
  • the motor 200 is, for example, a three-phase AC motor.
  • the motor 200 includes an A-phase winding M1, a B-phase winding M2, and a C-phase winding M3, and is connected to the first inverter 120 and the second inverter 130 of the inverter unit 100. More specifically, the first inverter 120 is connected to one end of each phase winding of the motor 200, and the second inverter 130 is connected to the other end of each phase winding.
  • the control circuit 300 includes, for example, a power supply circuit 310, an angle sensor 320, an input circuit 330, a controller 340, a drive circuit 350, and a ROM 360. Each component of the control circuit 300 is mounted on, for example, one circuit board (typically a printed board).
  • the control circuit 300 is connected to the inverter unit 100 and controls the inverter unit 100 based on input signals from the current sensor 150 and the angle sensor 320. Examples of the control method include vector control, pulse width modulation (PWM), and direct torque control (DTC). However, the angle sensor 320 may be unnecessary depending on the motor control method (for example, sensorless control).
  • the control circuit 300 can realize the closed loop control by controlling the target position, rotation speed, current, etc. of the rotor of the motor 200.
  • the control circuit 300 may include a torque sensor instead of the angle sensor 320. In this case, the control circuit 300 can control the target motor torque.
  • the power supply circuit 310 generates a power supply voltage (for example, 3V, 5V) necessary for each block in the circuit based on the voltage of the power supply 101, for example, 12V.
  • a power supply voltage for example, 3V, 5V
  • the angle sensor 320 is, for example, a resolver or a Hall IC. Alternatively, the angle sensor 320 is also realized by a combination of an MR sensor having a magnetoresistive (MR) element and a sensor magnet. The angle sensor 320 detects the rotation angle of the rotor (hereinafter referred to as “rotation signal”) and outputs the rotation signal to the controller 340.
  • rotation signal the rotation angle of the rotor
  • the input circuit 330 receives the phase current detected by the current sensor 150 (hereinafter sometimes referred to as “actual current value”), and changes the level of the actual current value to the input level of the controller 340 as necessary.
  • the actual current value is output to the controller 340.
  • the input circuit 330 is, for example, an analog / digital (AD) conversion circuit.
  • the controller 340 is an integrated circuit that controls the entire power conversion apparatus 1000, and is, for example, a microcontroller or an FPGA (Field Programmable Gate Array).
  • the controller 340 controls the switching operation (turn-on or turn-off) of each switch element (typically a semiconductor switch element) in the first and second inverters 120 and 130 of the inverter unit 100.
  • the controller 340 sets the target current value according to the actual current value and the rotation signal of the rotor, generates a PWM signal, and outputs it to the drive circuit 350.
  • the drive circuit 350 is typically a pre-driver (sometimes called a “gate driver”).
  • the drive circuit 350 generates a control signal (gate control signal) for controlling the switching operation of each switch element in the first and second inverters 120 and 130 of the inverter unit 100 according to the PWM signal, and supplies a control signal to the gate of each switch element.
  • the pre-driver may not be necessarily required. In that case, the function of the pre-driver can be implemented in the controller 340.
  • the ROM 360 is, for example, a writable memory (for example, PROM), a rewritable memory (for example, flash memory), or a read-only memory.
  • the ROM 360 stores a control program including a command group for causing the controller 340 to control the power conversion apparatus 1000.
  • the control program is temporarily expanded in a RAM (not shown) at the time of booting.
  • FIG. 2 schematically shows a circuit configuration of the inverter unit 100 according to the present embodiment.
  • the power supply 101 generates a predetermined power supply voltage (for example, 12V).
  • a DC power source is used as the power source 101.
  • the power source 101 may be an AC-DC converter, a DC-DC converter, or a battery (storage battery).
  • the power source 101 may be a single power source common to the first and second inverters 120 and 130 as shown in the figure, or may be a first power source (not shown) for the first inverter 120 and for the second inverter 130.
  • a second power source (not shown) may be provided.
  • coils are provided between the power source 101 and the first inverter 120 and between the power source 101 and the second inverter 130.
  • the coil functions as a noise filter, and smoothes the high frequency noise included in the voltage waveform supplied to each inverter or the high frequency noise generated by each inverter so as not to flow out to the power supply 101 side.
  • a capacitor is connected to the power supply terminal of each inverter.
  • the capacitor is a so-called bypass capacitor and suppresses voltage ripple.
  • the capacitor is, for example, an electrolytic capacitor, and the capacity and the number to be used are appropriately determined according to design specifications.
  • the first inverter 120 has a bridge circuit composed of three legs. Each leg has a high-side switch element, a low-side switch element, and a shunt resistor.
  • the A-phase leg includes a high-side switch element SW_A1H, a low-side switch element SW_A1L, and a first shunt resistor S_A1.
  • the B-phase leg has a high-side switch element SW_B1H, a low-side switch element SW_B1L, and a first shunt resistor S_B1.
  • the C-phase leg has a high-side switch element SW_C1H, a low-side switch element SW_C1L, and a first shunt resistor S_C1.
  • a field effect transistor typically MOSFET having a parasitic diode formed therein, or a combination of an insulated gate bipolar transistor (IGBT) and a free-wheeling diode connected in parallel thereto can be used.
  • MOSFET field effect transistor
  • IGBT insulated gate bipolar transistor
  • the first shunt resistor S_A1 is used to detect the A-phase current IA1 flowing through the A-phase winding M1, and is connected, for example, between the low-side switch element SW_A1L and the GND line GL.
  • the first shunt resistor S_B1 is used to detect the B-phase current IB1 flowing through the B-phase winding M2, and is connected between the low-side switch element SW_B1L and the GND line GL, for example.
  • the first shunt resistor S_C1 is used to detect the C-phase current IC1 flowing through the C-phase winding M3, and is connected between, for example, the low-side switch element SW_C1L and the GND line GL.
  • the three shunt resistors S_A1, S_B1, and S_C1 are connected in common with the GND line GL of the first inverter 120.
  • the second inverter 130 has a bridge circuit composed of three legs. Each leg has a high-side switch element, a low-side switch element, and a shunt resistor.
  • the A-phase leg has a high-side switch element SW_A2H, a low-side switch element SW_A2L, and a shunt resistor S_A2.
  • the B-phase leg has a high-side switch element SW_B2H, a low-side switch element SW_B2L, and a shunt resistor S_B2.
  • the C-phase leg has a high-side switch element SW_C2H, a low-side switch element SW_C2L, and a shunt resistor S_C2.
  • the shunt resistor S_A2 is used to detect the A-phase current IA2, and is connected, for example, between the low-side switch element SW_A2L and the GND line GL.
  • the shunt resistor S_B2 is used to detect the B-phase current IB2, and is connected between, for example, the low-side switch element SW_B2L and the GND line GL.
  • the shunt resistor S_C2 is used to detect the C-phase current IC2, and is connected, for example, between the low-side switch element SW_C2L and the GND line GL.
  • the three shunt resistors S_A2, S_B2, and S_C2 are connected in common with the GND line GL of the second inverter 130.
  • the current sensor 150 described above includes, for example, a shunt resistor S_A1, S_B1, S_C1, S_A2, S_B2, S_C2, and a current detection circuit (not shown) that detects a current flowing through each shunt resistor.
  • the A-phase leg of the first inverter 120 (specifically, a node between the high-side switch element SW_A1H and the low-side switch element SW_A1L) is connected to one end A1 of the A-phase winding M1 of the motor 200, and the second inverter The 130 A-phase leg is connected to the other end A2 of the A-phase winding M1.
  • the B-phase leg of the first inverter 120 is connected to one end B1 of the B-phase winding M2 of the motor 200, and the B-phase leg of the second inverter 130 is connected to the other end B2 of the winding M2.
  • the C-phase leg of the first inverter 120 is connected to one end C1 of the C-phase winding M3 of the motor 200, and the C-phase leg of the second inverter 130 is connected to the other end C2 of the winding M3.
  • FIG. 3A schematically shows the configuration of the A-phase H-bridge BA.
  • FIG. 3B schematically shows the configuration of a B-phase H-bridge BB.
  • FIG. 3C schematically shows the configuration of a C-phase H-bridge BC.
  • the inverter unit 100 includes A-phase, B-phase, and C-phase H-bridges BA, BB, and BC.
  • the A-phase H bridge BA includes a high-side switch element SW_A1H and a low-side switch element SW_A1L in the leg on the first inverter 120 side, a high-side switch element SW_A2H, a low-side switch element SW_A2L in the leg on the second inverter 130 side, and a winding Has M1.
  • the B-phase H-bridge BB includes a high-side switch element SW_B1H and a low-side switch element SW_B1L in the leg on the first inverter 120 side, a high-side switch element SW_B2H, a low-side switch element SW_B2L in the leg on the second inverter 130 side, and a winding Has M2.
  • the C-phase H-bridge BC includes a high-side switch element SW_C1H and a low-side switch element SW_C1L in the leg on the first inverter 120 side, a high-side switch element SW_C2H, a low-side switch element SW_C2L in the leg on the second inverter 130 side, and a winding M3.
  • the control circuit 300 (specifically, the controller 340) can specify a failed switch element in the power conversion apparatus 1000 by executing a failure diagnosis described below.
  • the control circuit 300 can switch to motor control in which a two-phase winding is energized using a two-phase H bridge other than the H bridge including the faulty switch element.
  • energizing the three-phase winding is referred to as “three-phase energization control”
  • energizing the two-phase winding is referred to as “two-phase energization control”. Details of the failure diagnosis will be described below.
  • failure diagnosis method for diagnosing the presence or absence of a failure of the switch element of the power conversion apparatus 1000 shown in FIG. 1
  • the failure diagnosis method of the present disclosure can be suitably used for a power conversion device including at least one H bridge, for example, a full bridge type power conversion device.
  • the failure of a switch element refers to the open failure of a switch element.
  • An open failure is a failure in which the switch element always has a high impedance.
  • a failure occurring in a switching element of an A-phase H-bridge may be referred to as an A-phase failure.
  • the outline of the failure diagnosis method of this embodiment is as follows.
  • failure diagnosis it is determined whether there is a failed phase in the A phase, the B phase, or the C phase. Further, it is determined whether there is a failed part in the high side and the low side of the H bridges BA, BB, and BC. Further, it is determined whether there is a failed inverter in the first inverter 120 and the second inverter 130. Based on these determination results, it is determined whether there is a failed switch element among the high-side switch element and the low-side switch element included in the power conversion device 1000.
  • the current and voltage expressed in the dq coordinate system the actual voltage indicating the voltage across the low-side switch element, and the rotational speed ⁇ of the motor are acquired.
  • the current and voltage expressed in the dq coordinate system include a d-axis voltage Vd, a q-axis voltage Vq, a d-axis current Id, and a q-axis current Iq.
  • the axis corresponding to the zero phase is represented as the z axis.
  • the rotation speed ⁇ is represented by a rotation speed (rpm) at which the rotor of the motor rotates per unit time (for example, 1 minute) or a rotation speed (rps) at which the rotor rotates at unit time (for example, 1 second).
  • a first actual voltage and a second actual voltage are defined for each of the A-phase, B-phase, and C-phase H-bridges BA, BB, and BC.
  • the first actual voltage indicates the voltage across the first low-side switch element in the leg on the first inverter 120 side in the H bridge of each phase. In other words, the first actual voltage corresponds to the node potential between the first high-side switch element and the first low-side switch element in the leg on the first inverter 120 side.
  • the second actual voltage indicates the voltage across the second low-side switch element in the leg on the second inverter 130 side. In other words, the second actual voltage corresponds to the node potential between the second high-side switch element and the second low-side switch element in the leg on the second inverter 130 side.
  • the voltage across the switch element is equal to the voltage Vds between the source and drain of the FET that is the switch element.
  • the first actual voltage indicates the voltage VA1 across the low-side switch element SW_A1L shown in FIG. 3A, and the second actual voltage points across the voltage VA2 across the low-side switch element SW_A2L shown in FIG. 3A.
  • the first actual voltage indicates the voltage VB1 across the low-side switch element SW_B1L shown in FIG. 3B
  • the second actual voltage indicates the voltage VB2 across the low-side switch element SW_B2L shown in FIG. 3B.
  • the first actual voltage indicates the voltage VC1 across the low-side switch element SW_C1L illustrated in FIG. 3C
  • the second actual voltage indicates the voltage VC2 across the low-side switch element SW_C2L illustrated in FIG. 3C. .
  • a failure is diagnosed based on the acquired current and voltage in the dq coordinate system, the first actual voltage, the second actual voltage, and the rotation speed.
  • a fault signal indicating a fault of the switch element is generated and output to a motor control unit described later.
  • a failure signal is a signal that is asserted when a failure occurs.
  • the above-described failure diagnosis is repeatedly executed in synchronization with, for example, a period in which each phase current is measured by the current sensor 150, that is, an AD conversion period.
  • the algorithm for realizing the fault diagnosis method according to the present embodiment can be realized only by hardware such as an application specific integrated circuit (ASIC) or FPGA, or can be realized by a combination of a microcontroller and software. Can do.
  • the operation subject of failure diagnosis is the controller 340 of the control circuit 300.
  • FIG. 4 exemplifies functional blocks of the controller 340 for performing overall motor control.
  • FIG. 5 exemplifies functional blocks for performing fault diagnosis of the A phase, the B phase, and the C phase.
  • each block in the functional block diagram is shown not in hardware units but in functional block units.
  • the software used for motor control and failure diagnosis may be a module constituting a computer program for executing specific processing corresponding to each functional block, for example.
  • Such a computer program is stored in the ROM 360, for example.
  • the controller 340 can read out commands from the ROM 360 and sequentially execute each process.
  • the controller 340 includes, for example, a failure diagnosis unit 800 and a motor control unit 900.
  • the failure diagnosis of the present disclosure can be suitably combined with motor control (for example, vector control), and can be incorporated into a series of processes of motor control.
  • Failure diagnosis unit 800 obtains d-axis current Id, q-axis current Iq, d-axis voltage Vd, q-axis voltage Vq, and rotation speed ⁇ of motor 200 in the dq coordinate system.
  • the fault diagnosis unit 800 further obtains the first actual voltages VA1, VB1, VC1, and the second actual voltages VA2, VB2, and VC2.
  • the failure diagnosis unit 800 may include a pre-computation unit (not shown) that acquires Vpeak.
  • the pre-computation unit uses the Clark transformation to convert the three-phase currents Ia, Ib and Ic obtained based on the measured value of the current sensor 150 into the currents I ⁇ and ⁇ on the ⁇ axis in the ⁇ fixed coordinate system.
  • To a current I ⁇ of The pre-computation unit converts the currents I ⁇ and I ⁇ into a d-axis current Id and a q-axis current Iq in the dq coordinate system by using park conversion (dq coordinate conversion).
  • the pre-calculation unit acquires the d-axis voltage Vd and the q-axis voltage Vq based on the currents Id and Iq, and calculates the voltage peak value Vpeak from the acquired Vd and Vq based on the following formula (1).
  • the pre-computation unit can also receive Vd and Vq necessary for calculating Vpeak from the motor control unit 900 that performs vector control.
  • the pre-computation unit acquires Vpeak in synchronization with the period in which each phase current is measured by the current sensor 150.
  • Vpeak (2/3) 1/2 (Vd 2 + Vq 2 ) 1/2 formula (1)
  • Failure diagnosis unit 800 refers to look-up table 940 (FIG. 16) and determines saturation voltage Vsat based on currents Id and Iq and rotation speed ⁇ .
  • FIG. 16 schematically shows a look-up table (LUT) 940 that determines the saturation voltage Vsat from the rotation speed ⁇ and the current amplitude value.
  • the LUT 940 associates the relationship between the saturation voltage Vsat and the input of the current amplitude value (Id 2 + Iq 2 ) 1/2 determined based on the d-axis current and the q-axis current and the rotational speed ⁇ of the motor 200.
  • the rotation speed ⁇ is calculated based on, for example, a rotation signal from the angle sensor 320.
  • the rotational speed ⁇ can be estimated using, for example, a known sensorless control method.
  • the actual voltage of each switch element is measured by a drive circuit (predriver) 350, for example.
  • Table 1 illustrates the configuration of the LUT 940 that can be used for failure diagnosis.
  • Id is generally treated as zero. Therefore, the current amplitude value is equal to Iq.
  • Table 1 lists Iq (A).
  • the saturation voltage Vsat is determined from the acquired current amplitude value Iq and the rotational speed ⁇ .
  • a value set in advance before driving may be used as the saturation voltage Vsat.
  • a constant value for example, about 0.1 V) depending on the system may be used as the saturation voltage Vsat.
  • the failure diagnosis unit 800 diagnoses the presence or absence of a switch element failure based on the above-described actual voltage, voltage peak value Vpeak, and saturation voltage Vsat.
  • the failure diagnosis unit 800 generates a failure signal indicating the failed switch element based on the diagnosis result, and outputs the failure signal to the motor control unit 900.
  • the motor control unit 900 generates a PWM signal that controls the overall switching operation of the switch elements of the first and second inverters 120 and 130 using, for example, vector control.
  • the motor control unit 900 outputs a PWM signal to the drive circuit 350. For example, when a failure signal is asserted, the motor control unit 900 can switch the motor control from the three-phase energization control to the two-phase energization control.
  • each functional block may be expressed as a unit. Naturally, these notations are not used with the intention of restricting each functional block to hardware or software.
  • the execution subject of the software may be the core of the controller 340, for example.
  • the controller 340 can be realized by an FPGA. In that case, all or some of the functional blocks may be realized by hardware.
  • the computing load of a specific computer can be distributed.
  • all or part of the functional blocks shown in FIGS. 4 to 16 may be distributed and implemented in a plurality of FPGAs.
  • the plurality of FPGAs can be connected to each other by, for example, an in-vehicle control area network (CAN), and can transmit and receive data.
  • CAN in-vehicle control area network
  • the failure diagnosis unit 800 includes a failure diagnosis unit 800A for diagnosing a failure of the A-phase H bridge BA, a failure diagnosis unit 800B for diagnosing a failure of the B-phase H bridge BB, and a C-phase H bridge shown in FIG.
  • a failure diagnosis unit 800C for diagnosing a failure of the bridge BC is included.
  • FIG. 6 is a block diagram illustrating a failure diagnosis unit 800A for diagnosing a failure of the A-phase H bridge BA.
  • FIG. 7 is a block diagram illustrating a failure diagnosis unit 800B for diagnosing a failure of the B-phase H-bridge BB.
  • FIG. 8 is a block diagram illustrating a failure diagnosis unit 800C for diagnosing a failure of the C-phase H-bridge BC.
  • Failure diagnosis units 800A, B, and C are constituted by substantially the same functional blocks. However, the input signals of the first actual voltage and the second actual voltage differ between the blocks.
  • the fault diagnosis of the H bridge will be described in detail with reference to FIG. 6, taking the fault diagnosis of the A-phase H bridge BA as an example.
  • the fault diagnosis unit 800A includes multipliers 810 and 811, adders 812, 813_1 and 813_2, signal generation units 814_1 and 814_2, multipliers 820 and 821, adders 822, 823_1 and 823_2, signal generation units 824_1 and 824_2, and a logic circuit. OR830.
  • Multipliers 810 and 811, adders 812, 813_1 and 813_2, and signal generation units 814_1 and 814_2 constitute a low-side fault diagnosis unit.
  • the multipliers 820 and 821, the adders 822, 823_1 and 823_2, and the signal generation units 824_1 and 824_2 constitute a high side failure diagnosis unit.
  • the low side failure diagnosis unit specifies an open failure of the low side switch elements SW_A1L and SW_A2L.
  • the high side failure diagnosis unit specifies an open failure of the high side switch elements SW_A1H and SW_A2H.
  • the high side failure diagnosis unit includes a first failure diagnosis for diagnosing an open failure of the high side switch element SW_A2H based on the voltage peak value Vpeak, the saturation voltage Vsat and the first actual voltage VA1, and the voltage peak value Vpeak, the saturation voltage Vsat and Based on the second actual voltage VA2, the second failure diagnosis for diagnosing an open failure of the high-side switch element SW_A1H is performed.
  • Multiplier 820 multiplies voltage peak value Vpeak by a constant “1/2”.
  • the voltage peak value Vpeak is calculated based on the above equation (1).
  • the multiplier 821 multiplies the saturation voltage Vsat by a constant “1”.
  • the adder 822 adds the output Vsat of the multiplier 821 to the output Vpeak / 2 of the multiplier 820.
  • the adder 823_1 calculates the first failure diagnosis voltage VA2H_FD by adding the first actual voltage VA1 to the output (Vpeak / 2) + Vsat from the adder 822 (formula (2)).
  • the adder 823_2 calculates the second failure diagnosis voltage VA1H_FD by adding the second actual voltage VA2 to the output (Vpeak / 2) + Vsat from the adder 822 (formula (3)).
  • the first actual voltage VA1 and the second actual voltage VA2 are measured by a drive circuit (predriver) 350, for example.
  • VA2H_FD VA1 + [(Vpeak / 2) + Vsat] Formula (2)
  • VA1H_FD VA2 + [(Vpeak / 2) + Vsat] Formula (3)
  • the signal generation unit 824_1 diagnoses an open failure of the high-side switch element SW_A2H based on the first failure diagnosis voltage VA2H_FD. Specifically, the signal generation unit 824_1 identifies an open failure of the high side switch element SW_A2H when the first failure diagnosis voltage VA2H_FD is less than zero (VA2H_FD ⁇ 0). When the first failure diagnosis voltage VA2H_FD is greater than or equal to zero (VA2H_FD ⁇ 0), the signal generation unit 824_1 determines that no open failure has occurred in the high-side switch element SW_A2H.
  • the signal generation unit 824_1 generates a first failure signal A2H_FD indicating an open failure of the high side switch element SW_A2H based on the diagnosis result in the first failure diagnosis.
  • the first failure signal A2H_FD can be assigned to a 1-bit signal.
  • the level of the first failure signal A2H_FD is Low.
  • the signal generation unit 824_1 identifies an open failure of the high-side switch element SW_A2H, the signal generation unit 824_1 asserts the first failure signal A2H_FD.
  • the signal generation unit 824_2 diagnoses an open failure of the high-side switch element SW_A1H based on the second failure diagnosis voltage VA1H_FD. Specifically, the signal generation unit 824_2 identifies an open failure of the high side switch element SW_A1H when the second failure diagnosis voltage VA1H_FD is less than zero (VA1H_FD ⁇ 0). When the second failure diagnosis voltage VA1H_FD is zero or more (VA1H_FD ⁇ 0), the signal generation unit 824_2 determines that no open failure has occurred in the high-side switch element SW_A1H.
  • the signal generation unit 824_2 generates a second failure signal A1H_FD indicating an open failure of the high-side switch element SW_A1H based on the diagnosis result in the second failure diagnosis.
  • the second failure signal A1H_FD can be assigned to a 1-bit signal.
  • the level of the second failure signal A1H_FD is Low.
  • the signal generation unit 824_2 specifies the open failure of the high-side switch element SW_A1H, the signal generation unit 824_2 asserts the second failure signal A1H_FD.
  • the low-side failure diagnosis unit performs third failure diagnosis for diagnosing an open failure of the low-side switch element SW_A2L based on the voltage peak value Vpeak, the saturation voltage Vsat, and the first actual voltage VA1, and the voltage peak value Vpeak, saturation voltage Vsat, and second Based on the actual voltage VA2, a fourth failure diagnosis for diagnosing an open failure of the low-side switch element SW_A1L is performed.
  • Multiplier 810 multiplies voltage peak value Vpeak by a constant “ ⁇ 1/2”.
  • the multiplier 811 multiplies the saturation voltage Vsat by a constant “ ⁇ 1”. Considering that the currents flowing between the low-side switch element and the high-side switch element are reversed, the low-side failure diagnosis unit has a sign opposite to that of the multipliers 820 and 821 of the high-side failure diagnosis unit. A constant is used.
  • the adder 812 adds the output ( ⁇ Vsat) of the multiplier 811 to the output ( ⁇ Vpeak / 2) of the multiplier 810.
  • the adder 813_1 calculates the third failure diagnosis voltage VA2L_FD by adding the first actual voltage VA1 to the output from the adder 812:-[(Vpeak / 2) + Vsat] (formula (4)).
  • the adder 813_2 calculates the fourth fault diagnosis voltage VA1L_FD by adding the second actual voltage VA2 to the output from the adder 812:-[(Vpeak / 2) + Vsat] (formula (5)).
  • VA2L_FD VA1-[(Vpeak / 2) + Vsat] Formula (4)
  • VA1L_FD VA2-[(Vpeak / 2) + Vsat] Formula (5)
  • the signal generation unit 814_1 diagnoses an open failure of the low-side switch element SW_A2L based on the third failure diagnosis voltage VA2L_FD. Specifically, the signal generation unit 814_1 identifies an open failure of the low-side switch element SW_A2L when the third failure diagnosis voltage VA2L_FD is greater than zero (VA2L_FD> 0). The signal generation unit 814_1 determines that an open failure has not occurred in the low-side switch element SW_A2L when the third failure diagnosis voltage VA2L_FD is equal to or less than zero (VA2L_FD ⁇ 0).
  • the signal generation unit 814_1 generates a third failure signal A2L_FD indicating an open failure of the low-side switch element SW_A2L based on the diagnosis result in the third failure diagnosis.
  • the third failure signal A2L_FD can be assigned to a 1-bit signal.
  • the level of the third failure signal A2L_FD is Low.
  • the signal generation unit 814_1 specifies the open failure of the low-side switch element SW_A2L, the signal generation unit 814_1 asserts the third failure signal A2L_FD.
  • the signal generation unit 814_2 diagnoses an open failure of the low-side switch element SW_A1L based on the fourth failure diagnosis voltage VA1L_FD. Specifically, the signal generation unit 814_2 specifies an open failure of the low-side switch element SW_A1L when the fourth failure diagnosis voltage VA1L_FD is greater than zero (VA1L_FD> 0). When the fourth failure diagnosis voltage VA1L_FD is equal to or lower than zero (VA1L_FD ⁇ 0), the signal generation unit 814_2 determines that an open failure has not occurred in the low-side switch element SW_A1L.
  • the signal generation unit 814_2 generates a fourth failure signal A1L_FD indicating an open failure of the low-side switch element SW_A1L based on the diagnosis result in the fourth failure diagnosis.
  • the fourth failure signal A1L_FD can be assigned to a 1-bit signal.
  • the level of the fourth failure signal A1L_FD is Low.
  • the signal generation unit 814_2 specifies the open failure of the low-side switch element SW_A1L, the signal generation unit 814_2 asserts the fourth failure signal A1L_FD.
  • the failure diagnosis unit 800A can identify a switch element that has an open failure among the high-side switch elements SW_A1H, SW_A2H, the low-side switch elements SW_A1L, and SW_A2L.
  • the logic circuit OR830 takes a logical sum of the first to fourth failure signals A2H_FD, A1H_FD, A2L_FD, and A1L_FD.
  • the logic circuit OR 830 outputs a failure signal A_FD indicating whether or not the A-phase H bridge BA has failed. For example, when all of the first to fourth failure signals A2H_FD, A1H_FD, A2L_FD, and A1L_FD are “0” indicating normality, the logic circuit OR830 outputs “0” indicating normality as the failure signal A_FD.
  • the logic circuit OR 830 When at least one of the first to fourth failure signals A2H_FD, A1H_FD, A2L_FD, and A1L_FD is “1” indicating abnormality, the logic circuit OR 830 outputs “1” indicating failure as the failure signal A_FD.
  • failure diagnosis unit 800B detects that an open failure has occurred in at least one of high-side switch elements SW_B1H, SW_B2H, low-side switch elements SW_B1L, and SW_B2L. Is output as a failure signal B_FD. When no open failure is detected, “0” indicating that the B-phase H-bridge BB is normal is output as the failure signal B_FD.
  • the failure diagnosis unit 800C When the failure diagnosis unit 800C detects that at least one of the high-side switch elements SW_C1H, SW_C2H, the low-side switch elements SW_C1L and SW_C2L has an open failure, the failure diagnosis unit 800C outputs “1” indicating a failure of the C-phase H-bridge BC as a failure signal. Output as C_FD. When an open failure is not detected, “0” indicating that the C-phase H-bridge BC is normal is output as a failure signal C_FD.
  • the failure diagnosis unit 800 includes a failure diagnosis unit 810A for diagnosing the presence or absence of a failure in the first inverter 120 and a failure diagnosis unit 810B for diagnosing the presence or absence of a failure in the second inverter 130 shown in FIG.
  • FIG. 10 shows functional blocks of the failure diagnosis unit 810A.
  • FIG. 11 shows functional blocks of the failure diagnosis unit 810B.
  • Fault diagnosis units 810A and 810B have substantially the same functional blocks, but input actual voltages are different from each other.
  • Each of failure diagnosis units 810A and 810B includes absolute value calculators 831, 834, 837, multipliers 832, 833, 835, 836, 838, 839, adders 841, 842, 843, and comparators 844, 845. , 846 and a logic circuit OR847.
  • the absolute value calculator 831 of the failure diagnosis unit 810A calculates the absolute value of the actual voltage VA2.
  • the multiplier 832 multiplies the voltage peak value Vpeak by a constant “ ⁇ 1/2”.
  • the multiplier 833 multiplies the saturation voltage Vsat by a constant “ ⁇ 1”.
  • the adder 841 adds the output values of the absolute value calculator 831 and the multipliers 832 and 833 to calculate the failure diagnosis voltage VA2_FD represented by the following formula (6).
  • VA2_FD
  • the comparator 844 compares “VA2_FD” with “zero”. When VA2_FD is equal to or less than zero (VA2_FD ⁇ 0), the comparator 844 outputs “0” indicating that the actual voltage VA2 is normal to the logic circuit OR847. When VA2_FD is larger than zero (VA2_FD> 0), the comparator 844 outputs “1” indicating that the actual voltage VA2 is abnormal to the logic circuit OR847.
  • the absolute value calculator 834 of the failure diagnosis unit 810A calculates the absolute value of the actual voltage VB2.
  • the multiplier 835 multiplies the voltage peak value Vpeak by a constant “ ⁇ 1/2”.
  • the multiplier 836 multiplies the saturation voltage Vsat by a constant “ ⁇ 1”.
  • the adder 842 adds the output values of the absolute value calculator 834 and the multipliers 835 and 836 to calculate a failure diagnosis voltage VB2_FD represented by the following formula (7).
  • VB2_FD
  • the comparator 845 compares “VB2_FD” with “zero”. When VB2_FD is equal to or smaller than zero, the comparator 845 outputs “0” indicating that the actual voltage VB2 is normal to the logic circuit OR847. When VB2_FD is greater than zero, the comparator 845 outputs “1” indicating that the actual voltage VB2 is abnormal to the logic circuit OR847.
  • the absolute value calculator 837 of the failure diagnosis unit 810A calculates the absolute value of the actual voltage VC2.
  • the multiplier 838 multiplies the voltage peak value Vpeak by a constant “ ⁇ 1/2”.
  • the multiplier 839 multiplies the saturation voltage Vsat by a constant “ ⁇ 1”.
  • the adder 843 adds the output values of the absolute value calculator 837 and the multipliers 838 and 839 to calculate a failure diagnosis voltage VC2_FD represented by the following formula (8).
  • VC2_FD
  • the comparator 846 compares “VC2_FD” with “zero”. When VC2_FD is equal to or smaller than zero, the comparator 846 outputs “0” indicating that the actual voltage VC2 is normal to the logic circuit OR847. When VC2_FD is greater than zero, the comparator 846 outputs “1” indicating that the actual voltage VC2 is abnormal to the logic circuit OR847.
  • the logic circuit OR 847 takes the logical sum of the output signals of the comparators 844, 845, 846.
  • the logic circuit OR847 outputs a logical sum as a failure signal 1_FD indicating whether or not the first inverter 120 has failed.
  • the logic circuit OR847 When the output signals of the comparators 844, 845, and 846 are all “0”, the logic circuit OR847 outputs “0” indicating that the first inverter 120 is normal as the failure signal 1_FD. When at least one of the output signals of the comparators 844, 845, and 846 is “1”, the logic circuit OR847 outputs “1” indicating that the first inverter 120 has failed as the failure signal 1_FD.
  • the failure diagnosis unit 810B shown in FIG. 11 performs the same processing as the failure diagnosis unit 810A, and diagnoses the presence or absence of a failure of the second inverter 130.
  • the actual voltages VA1, VB1, and VC1 are input to the failure diagnosis unit 810B instead of the actual voltages VA2, VB2, and VC2.
  • the logic circuit OR847 outputs a failure signal 2_FD indicating whether or not the second inverter 130 has failed. Since the other processing of the failure diagnosis unit 810B is the same as that of the failure diagnosis unit 810A, detailed description is omitted here.
  • H bridge high side and low side failure diagnosis Next, a process for determining whether there is a failed part on the high side and the low side of the H bridges BA, BB, and BC will be described.
  • FIG. 12 shows a failure diagnosis unit 820A for diagnosing the presence or absence of a low-side failure of the H bridges BA, BB, and BC.
  • FIG. 13 shows a failure diagnosis unit 820B for diagnosing the presence or absence of a high-side failure of the H bridges BA, BB, and BC.
  • the failure diagnosis unit 800 includes failure diagnosis units 820A and 820B shown in FIGS.
  • the fault diagnosis unit 820A includes multipliers 851, 852, adders 853, 854, 855, 856, 857, 858, 859, comparators 861, 862, 863, 864, 865, 866, and a logic circuit OR867. Have.
  • the multiplier 851 multiplies the voltage peak value Vpeak by a constant “ ⁇ 1/2”.
  • the multiplier 852 multiplies the saturation voltage Vsat by a constant “ ⁇ 1”.
  • Adder 853 adds the output values of multipliers 851 and 852.
  • the adder 854 adds the actual voltage VA1 and the output value of the adder 853 to calculate a failure diagnosis voltage VA1L_FD represented by the following equation (9). Equation (9) is the same as Equation (4) described above.
  • VA1L_FD VA1-[(Vpeak / 2) + Vsat] Formula (9)
  • the comparator 861 compares “VA1L_FD” with “zero”. When VA1L_FD is equal to or less than zero (VA1L_FD ⁇ 0), the comparator 861 outputs “0” indicating that the actual voltage VA1 is normal to the logic circuit OR867. When VA1L_FD is greater than zero (VA1L_FD> 0), the comparator 861 outputs “1” indicating that the actual voltage VA1 is abnormal to the logic circuit OR867.
  • the adder 855 adds the actual voltage VA2 and the output value of the adder 853 to calculate the failure diagnosis voltage VA2L_FD.
  • the comparator 862 compares “VA2L_FD” with “zero”. When VA2L_FD is equal to or less than zero (VA2L_FD ⁇ 0), the comparator 862 outputs “0” indicating that the actual voltage VA2 is normal to the logic circuit OR867. When VA2L_FD is larger than zero (VA2L_FD> 0), the comparator 862 outputs “1” indicating that the actual voltage VA2 is abnormal to the logic circuit OR867.
  • the adder 856 adds the actual voltage VB1 and the output value of the adder 853 to calculate the failure diagnosis voltage VB1L_FD.
  • the comparator 863 compares “VB1L_FD” with “zero”. When VB1L_FD is equal to or less than zero (VB1L_FD ⁇ 0), the comparator 863 outputs “0” indicating that the actual voltage VB1 is normal to the logic circuit OR867. When VB1L_FD is greater than zero (VB1L_FD> 0), the comparator 863 outputs “1” indicating that the actual voltage VB1 is abnormal to the logic circuit OR867.
  • the adder 857 adds the actual voltage VB2 and the output value of the adder 853 to calculate the failure diagnosis voltage VB2L_FD.
  • the comparator 864 compares “VB2L_FD” with “zero”. When VB2L_FD is equal to or smaller than zero (VB2L_FD ⁇ 0), the comparator 864 outputs “0” indicating that the actual voltage VB2 is normal to the logic circuit OR867. When VB2L_FD is greater than zero (VB2L_FD> 0), the comparator 864 outputs “1” indicating that the actual voltage VB2 is abnormal to the logic circuit OR867.
  • the adder 858 adds the actual voltage VC1 and the output value of the adder 853 to calculate the fault diagnosis voltage VC1L_FD.
  • the comparator 865 compares “VC1L_FD” with “zero”. When VC1L_FD is equal to or lower than zero (VC1L_FD ⁇ 0), the comparator 865 outputs “0” indicating that the actual voltage VC1 is normal to the logic circuit OR867. When VC1L_FD is greater than zero (VC1L_FD> 0), the comparator 865 outputs “1” indicating that the actual voltage VC1 is abnormal to the logic circuit OR867.
  • the adder 859 adds the actual voltage VC2 and the output value of the adder 853 to calculate the failure diagnosis voltage VC2L_FD.
  • the comparator 866 compares “VC2L_FD” with “zero”. When VC2L_FD is equal to or lower than zero (VC2L_FD ⁇ 0), the comparator 866 outputs “0” indicating that the actual voltage VC2 is normal to the logic circuit OR867. When VC2L_FD is greater than zero (VC2L_FD> 0), the comparator 866 outputs “1” indicating that the actual voltage VC2 is abnormal to the logic circuit OR867.
  • the logic circuit OR867 takes the logical sum of the output signals of the comparators 861, 862, 863, 864, 865, and 866.
  • the logic circuit OR867 outputs a failure signal L_FD indicating whether or not there is a failure on the low side of the H bridge.
  • the logic circuit OR867 When the output signals of the comparators 861, 862, 863, 864, 865, and 866 are all “0”, the logic circuit OR867 outputs “0” indicating normality as the failure signal L_FD. When at least one of the output signals of the comparators 861, 862, 863, 864, 865, and 866 is “1”, the logic circuit OR867 outputs “1” indicating a failure as the failure signal L_FD.
  • the fault diagnosis unit 820B shown in FIG. 13 includes multipliers 871, 872, adders 873, 874, 875, 876, 877, 878, 879, comparators 881, 882, 883, 884, 885, 886, logic Circuit OR887.
  • the multiplier 871 multiplies the voltage peak value Vpeak by a constant “1/2”.
  • the multiplier 872 multiplies the saturation voltage Vsat by a constant “1”.
  • Adder 873 adds the output values of multipliers 871 and 872.
  • the adder 874 adds the actual voltage VA1 and the output value of the adder 873 to calculate a failure diagnosis voltage VA1H_FD represented by the following equation (10).
  • Expression (10) is the same as Expression (2) described above.
  • VA1H_FD VA1 + [(Vpeak / 2) + Vsat] Formula (10)
  • the comparator 881 compares “VA1H_FD” with “zero”. When VA1H_FD is equal to or greater than zero (VA1H_FD ⁇ 0), the comparator 881 outputs “0” indicating that the actual voltage VA1 is normal to the logic circuit OR887. When VA1H_FD is less than zero (VA1H_FD ⁇ 0), the comparator 881 outputs “1” indicating that the actual voltage VA1 is abnormal to the logic circuit OR881.
  • the adder 875 adds the actual voltage VA2 and the output value of the adder 873 to calculate the failure diagnosis voltage VA2H_FD.
  • the comparator 882 compares “VA2H_FD” with “zero”. When VA2H_FD is equal to or larger than zero (VA2H_FD ⁇ 0), the comparator 882 outputs “0” indicating that the actual voltage VA2 is normal to the logic circuit OR887. When VA2H_FD is less than zero (VA2H_FD ⁇ 0), the comparator 882 outputs “1” indicating that the actual voltage VA2 is abnormal to the logic circuit OR887.
  • the adder 876 adds the actual voltage VB1 and the output value of the adder 873 to calculate the failure diagnosis voltage VB1H_FD.
  • the comparator 883 compares “VB1H_FD” with “zero”. When VB1H_FD is equal to or larger than zero (VB1H_FD ⁇ 0), the comparator 883 outputs “0” indicating that the actual voltage VB1 is normal to the logic circuit OR887. When VB1H_FD is less than zero (VB1H_FD ⁇ 0), the comparator 883 outputs “1” indicating that the actual voltage VB1 is abnormal to the logic circuit OR887.
  • the adder 877 adds the actual voltage VB2 and the output value of the adder 873 to calculate the failure diagnosis voltage VB2H_FD.
  • the comparator 884 compares “VB2H_FD” with “zero”. The comparator 884 outputs “0” indicating that the actual voltage VB2 is normal to the logic circuit OR887 when VB2H_FD is zero or more (VB2H_FD ⁇ 0). When VB2H_FD is less than zero (VB2H_FD ⁇ 0), the comparator 884 outputs “1” indicating that the actual voltage VB2 is abnormal to the logic circuit OR887.
  • the adder 878 calculates the failure diagnosis voltage VC1H_FD by adding the actual voltage VC1 and the output value of the adder 873.
  • the comparator 885 compares “VC1H_FD” with “zero”. When VC1H_FD is equal to or greater than zero (VC1H_FD ⁇ 0), the comparator 885 outputs “0” indicating that the actual voltage VC1 is normal to the logic circuit OR887. When VC1H_FD is less than zero (VC1H_FD ⁇ 0), the comparator 885 outputs “1” indicating that the actual voltage VC1 is abnormal to the logic circuit OR887.
  • the adder 879 adds the actual voltage VC2 and the output value of the adder 873 to calculate the failure diagnosis voltage VC2H_FD.
  • Comparator 886 compares “VC2H_FD” with “zero”. When VC2H_FD is equal to or greater than zero (VC2H_FD ⁇ 0), the comparator 886 outputs “0” indicating that the actual voltage VC2 is normal to the logic circuit OR887. When VC2H_FD is less than zero (VC2H_FD ⁇ 0), the comparator 886 outputs “1” indicating that the actual voltage VC2 is abnormal to the logic circuit OR887.
  • the logic circuit OR 887 takes the logical sum of the output signals of the comparators 881, 882, 883, 884, 885, 886.
  • the logic circuit OR887 outputs a failure signal H_FD indicating whether or not there is a failure on the high side of the H bridge.
  • the logic circuit OR 887 outputs “0” indicating normality as the failure signal H_FD.
  • the logic circuit OR887 outputs “1” indicating a failure as a failure signal H_FD.
  • FIG. 14 shows a failure diagnosis unit 830A for diagnosing the presence or absence of a failure of the switch element of the first inverter 120.
  • FIG. 15 shows a failure diagnosis unit 830B that diagnoses the presence or absence of a failure of the switch element of the second inverter 130.
  • Failure diagnosis units 830A and 830B have substantially the same functional blocks, but input signals are different from each other.
  • the failure diagnosis unit 800 includes failure diagnosis units 830A and 830B shown in FIGS.
  • Each of the failure diagnosis units 830A and 830B includes logic circuits AND891, 892, 893, 894, 895, 896, 901, 902, 903, 904, 905, and 906.
  • the logic circuit AND 891 receives a failure signal A_FD indicating the presence / absence of a failure of the A phase H bridge BA and a failure signal H_FD indicating the presence / absence of a failure of the high side of the H bridge.
  • the logic circuit AND 891 When both the failure signal A_FD and the failure signal H_FD are “1” indicating the failure, the logic circuit AND 891 outputs “1”. When at least one of the failure signal A_FD and the failure signal H_FD is “0” indicating normality, the logic circuit AND 891 outputs “0”.
  • a failure signal 1_FD indicating whether or not the first inverter 120 has failed and an output signal of the logic circuit AND891 are input to the logic circuit AND901.
  • the logic circuit AND901 outputs a failure signal A1H_FD indicating whether or not the A-phase high-side switch element SW_A1H in the first inverter 120 has failed to the motor control unit 900.
  • the logic circuit AND901 When both the failure signal 1_FD and the output signal of the logic circuit AND891 are “1”, the logic circuit AND901 outputs “1” indicating that the switch element SW_A1H has failed. When at least one of the failure signal 1_FD and the output signal of the logic circuit AND891 is “0” indicating normality, the logic circuit AND901 outputs “0” indicating that the switch element SW_A1H is normal.
  • the failure signal A1H_FD output from the logic circuit AND901 is “1”, it can be specified that the high-side switch element SW_A1H has failed.
  • the logic circuit AND 892 receives a failure signal A_FD indicating whether or not the A-phase H bridge BA has failed, and a failure signal L_FD indicating whether or not the H bridge has a low-side failure.
  • the logic circuit AND 892 When both the failure signal A_FD and the failure signal L_FD are “1” indicating failure, the logic circuit AND 892 outputs “1”. When at least one of the failure signal A_FD and the failure signal L_FD is “0” indicating normality, the logic circuit AND 892 outputs “0”.
  • the logic circuit AND902 outputs a failure signal A1L_FD indicating whether or not the A-phase low-side switch element SW_A1L in the first inverter 120 has failed to the motor control unit 900.
  • the logic circuit AND902 When both the failure signal 1_FD and the output signal of the logic circuit AND892 are “1”, the logic circuit AND902 outputs “1” indicating that the switch element SW_A1L has failed. When at least one of the failure signal 1_FD and the output signal of the logic circuit AND892 is “0” indicating normality, the logic circuit AND902 outputs “0” indicating that the switch element SW_A1L is normal.
  • the logic circuit AND 893 receives a failure signal B_FD indicating the presence / absence of a failure in the B-phase H bridge BB and a failure signal H_FD indicating the presence / absence of a failure on the high side of the H bridge.
  • the logic circuit AND 893 When both the failure signal B_FD and the failure signal H_FD are “1” indicating a failure, the logic circuit AND 893 outputs “1”. When at least one of the failure signal B_FD and the failure signal H_FD is “0” indicating normality, the logic circuit AND 893 outputs “0”.
  • a failure signal 1_FD indicating whether or not the first inverter 120 has failed and an output signal of the logic circuit AND893 are input to the logic circuit AND903.
  • the logic circuit AND903 outputs a failure signal B1H_FD indicating whether or not the B-phase high-side switch element SW_B1H in the first inverter 120 has failed to the motor control unit 900.
  • the logic circuit AND903 When both the failure signal 1_FD and the output signal of the logic circuit AND893 are “1”, the logic circuit AND903 outputs “1” indicating that the switch element SW_B1H has failed. When at least one of the failure signal 1_FD and the output signal of the logic circuit AND893 is “0” indicating normality, the logic circuit AND903 outputs “0” indicating that the switch element SW_B1H is normal.
  • the logic circuit AND 894 receives a failure signal B_FD indicating the presence / absence of a failure of the B-phase H bridge BB and a failure signal L_FD indicating the presence / absence of a low-side failure of the H bridge.
  • the logic circuit AND 894 When both the failure signal B_FD and the failure signal L_FD are “1” indicating failure, the logic circuit AND 894 outputs “1”. When at least one of the failure signal B_FD and the failure signal L_FD is “0” indicating normality, the logic circuit AND 894 outputs “0”.
  • a failure signal 1_FD indicating whether or not the first inverter 120 has failed and an output signal of the logic circuit AND894 are input to the logic circuit AND904.
  • the logic circuit AND904 outputs a failure signal B1L_FD indicating whether or not the B-phase low-side switch element SW_B1L in the first inverter 120 has failed to the motor control unit 900.
  • the logic circuit AND 904 When both the failure signal 1_FD and the output signal of the logic circuit AND 894 are “1”, the logic circuit AND 904 outputs “1” indicating that the switch element SW_B1L has failed. When at least one of the failure signal 1_FD and the output signal of the logic circuit AND 894 is “0” indicating normality, the logic circuit AND904 outputs “0” indicating that the switch element SW_B1L is normal.
  • the logic circuit AND 895 receives a failure signal C_FD indicating whether or not the C-phase H-bridge BC has failed and a failure signal H_FD indicating whether or not the H-bridge has a high-side failure.
  • the logic circuit AND895 When both the failure signal C_FD and the failure signal H_FD are “1” indicating a failure, the logic circuit AND895 outputs “1”. When at least one of the failure signal C_FD and the failure signal H_FD is “0” indicating normality, the logic circuit AND895 outputs “0”.
  • a failure signal 1_FD indicating whether or not the first inverter 120 has failed and an output signal of the logic circuit AND895 are input to the logic circuit AND905.
  • the logic circuit AND905 outputs to the motor control unit 900 a failure signal C1H_FD indicating whether or not the C-phase high-side switch element SW_C1H in the first inverter 120 has failed.
  • the logic circuit AND905 When both the failure signal 1_FD and the output signal of the logic circuit AND895 are “1”, the logic circuit AND905 outputs “1” indicating that the switch element SW_C1H has failed. When at least one of the failure signal 1_FD and the output signal of the logic circuit AND895 is “0” indicating normality, the logic circuit AND905 outputs “0” indicating that the switch element SW_C1H is normal.
  • a failure signal C_FD indicating whether or not the C-phase H-bridge BC has failed and a failure signal L_FD indicating whether or not the H-bridge has a low-side failure are input.
  • the logic circuit AND896 When both the failure signal C_FD and the failure signal L_FD are “1” indicating failure, the logic circuit AND896 outputs “1”. When at least one of the failure signal C_FD and the failure signal L_FD is “0” indicating normality, the logic circuit AND896 outputs “0”.
  • the logic circuit AND906 outputs a failure signal C1L_FD indicating whether or not the C-phase low-side switch element SW_C1L in the first inverter 120 has failed to the motor control unit 900.
  • the logic circuit AND906 When both the failure signal 1_FD and the output signal of the logic circuit AND896 are “1”, the logic circuit AND906 outputs “1” indicating that the switch element SW_C1L has failed. When at least one of the failure signal 1_FD and the output signal of the logic circuit AND896 is “0” indicating normality, the logic circuit AND906 outputs “0” indicating that the switch element SW_C1L is normal.
  • the process executed by the failure diagnosis unit 830B shown in FIG. 15 is the same as that of the failure diagnosis unit 830A, and thus detailed description thereof is omitted here.
  • the failure diagnosis unit 830B executes the same process as the failure diagnosis unit 830A, and executes a diagnosis process for the presence or absence of a failure of the switch element of the second inverter 130.
  • the failure diagnosis unit 830B outputs the failure signals A2H_FD, A2L_FD, B2H_FD, B2L_FD, C2H_FD, and C2L_FD that indicate whether or not the switch elements SW_A2H, SW_A2L, SW_B2H, SW_B2L, SW_C2H, and SW_C2L have failed.
  • a failure has occurred in the second inverter 130, it can be specified which switch element has failed.
  • the motor control unit 900 changes the motor control according to the failure signal output by the failure diagnosis unit 800. For example, the motor control is switched from three-phase energization control to two-phase energization control. For example, when a failed switch element is specified, two-phase energization control using the remaining two phases other than the phase including the failed switch element is performed. For example, when it is determined that a switch element of the A-phase H bridge BA has failed, the motor control unit 900 turns off all the switch elements of the A-phase H bridge BA. Then, two-phase energization control using the remaining B-phase and C-phase H bridges BB and BC is performed. Therefore, even if one of the three phases fails, the power conversion apparatus 1000 can continue to drive the motor.
  • FIG. 17 exemplifies a current waveform (sine wave) obtained by plotting the current values flowing in the A-phase, B-phase, and C-phase windings of the motor 200 when the power conversion apparatus 1000 is controlled according to the three-phase energization control.
  • FIG. 18 is obtained by plotting the values of current flowing through the B-phase and C-phase windings of the motor 200 when the power converter 1000 is controlled according to the two-phase energization control when the A-phase H-bridge BA fails.
  • the current waveform is illustrated.
  • the horizontal axis represents the motor electrical angle (deg), and the vertical axis represents the current value (A).
  • Ipk represents the maximum current value (peak current value) of each phase.
  • FIG. 19 plots the values of current flowing through the A-phase and C-phase windings of the motor 200 when the power converter 1000 is controlled according to the two-phase energization control when the B-phase H-bridge BB fails.
  • the current waveform obtained in this way is illustrated.
  • FIG. 20 when the C-phase H-bridge BC fails, it is obtained by plotting the values of currents flowing in the A-phase and B-phase windings of the motor 200 when the power converter 1000 is controlled according to the two-phase energization control.
  • the current waveform is illustrated.
  • the order of processing among the above-described failure diagnosis units 800A, 800B, 800C, 810A, 810B, 820A, and 820B is arbitrary. For example, after determining whether there is a failed phase, it may be determined whether there is a failed part on the high side and low side of the H-bridge, or vice versa. Further, for example, after determining whether there is a failed inverter, it may be determined whether there is a failed phase or vice versa. These determinations may be processed in parallel.
  • failure diagnosis units 800A, 800B, 800C, 810A, 810B, 820A, and 820B it is not necessary to execute all the processes of the failure diagnosis units 800A, 800B, 800C, 810A, 810B, 820A, and 820B.
  • the process of determining whether there is a faulty phase if it is determined that there is a faulty phase before determining the presence or absence of all three-phase faults, it is not necessary to determine whether there are faults in the remaining phases. Good.
  • the determination of the presence / absence of the failure of the B phase and the C phase may not be performed.
  • the faulty switch element can be identified even if the processing related to the B phase and the C phase is omitted.
  • the process of determining whether there is a failed part in the high side and low side of the H bridge it is determined that there is a failed part before determining whether there is a failure in both the high side and low side parts. In this case, it is not necessary to determine whether there is a failure in the remaining part. For example, if it is determined that the high side has failed before determining whether there is a failure on both the high side and the low side, it is not necessary to determine whether there is a failure on the low side. If it is determined that the high side has failed, it is possible to identify the failed switch element even if the processing related to the low side is omitted.
  • the remaining inverters It is not necessary to determine whether or not there is a failure. For example, if it is determined that the first inverter 120 has failed before determining whether both the first inverter 120 and the second inverter 130 have failed, the determination of whether the second inverter 130 has failed is not performed. May be. If it is determined that the first inverter 120 has failed, it is possible to identify the failed switch element even if the processing related to the second inverter 130 is omitted.
  • failure diagnosis is performed only for two phases. May be executed. For example, when it is determined that the A phase and the B phase have not failed, it is possible to specify that the C phase has failed without performing a failure diagnosis of the C phase.
  • Fault diagnosis may be performed. For example, if it is determined that the high side has not failed, it can be determined that the low side has failed without performing a low-side failure diagnosis.
  • the first inverter 120 and the second inverter Failure diagnosis may be executed for only one of the inverters 130. For example, if it is determined that the first inverter 120 has not failed, it can be determined that the second inverter 130 has failed without performing failure diagnosis of the second inverter 130.
  • failure diagnosis units 830A and 830B may be performed only for the inverter that is determined to have a failure.
  • the amount of calculation can be reduced by omitting some of the plurality of processes.
  • the amount of calculation can be reduced by omitting some of the plurality of processes.
  • FIG. 21 shows waveforms of the actual voltage VA1 (upper side) and the actual voltage VA2 (lower side) when the low-side switch element SW_A1L has an open failure.
  • FIG. 22 shows waveforms of the actual voltage VB1 (upper side) and the actual voltage VB2 (lower side) when the low-side switch element SW_A1L has an open failure.
  • FIG. 23 shows waveforms of the actual voltage VC1 (upper side) and the actual voltage VC2 (lower side) when the low-side switch element SW_A1L has an open failure.
  • the low-side switch element SW_A1L After the low-side switch element SW_A1L has an open failure at time 1.641s, it can be seen that the lower peak value of the actual voltage VA1 increases as shown in FIG. It can also be seen that the upper peak value of the actual voltage VA2 is increasing. That is, the absolute value of the upper peak value of the actual voltage VA2 increases. As shown in FIGS. 22 and 23, the actual voltages VB1, VB2, VC1, and VC2 have a small degree of change.
  • FIG. 24 shows waveforms of the first actual voltage VA1 (upper side) and the second actual voltage VA2 (lower side) of the A phase when the high-side switch element SW_A1H in the A-phase H bridge BA has an open failure.
  • FIG. 25 shows the waveforms of the B-phase first actual voltage VB1 (upper side) and the second actual voltage VB2 (lower side) when the high-side switch element SW_A1H has an open failure.
  • FIG. 26 shows waveforms of the first actual voltage VC1 (upper side) and the second actual voltage VC2 (lower side) of the C phase when the high-side switch element SW_A1H has an open failure.
  • the middle of the determination process whether there is a faulty phase in the middle of the determination process whether there is a faulty part in the high side and low side of the H-bridge, and the determination process whether there is a faulty inverter In the middle of this, a failure of the switch element is detected. However, the failure of the switch element is not determined at those times. In this embodiment, based on the determination result of whether there is a failed phase, the determination result of whether there is a failed part in the high side and low side of the H-bridge, and the determination result of whether there is a failed inverter Then, the failed switch element is determined. Therefore, the accuracy of failure diagnosis can be increased.
  • the failure diagnosis of the present disclosure can be realized by a simple algorithm. For this reason, for example, an advantage of reducing the circuit size or the memory size can be obtained in mounting 340 to the controller.
  • the failure diagnosis method of the present disclosure can be suitably used for a full bridge type power conversion device.
  • the full bridge includes a one-phase H-bridge structure, for example, the circuit structure shown in FIG. 3A.
  • the full-bridge type power converter controls the switching operation of the H-bridge BA having the high-side switch element SW_A1H, the high-side switch element SW_A2H, the low-side switch element SW_A1L, and the low-side switch element SW_A2L, and the switch element of the H-bridge BA.
  • a control circuit 300 acquires the current / voltage expressed in the dq coordinate system, and acquires the first actual voltage VA1 indicating the voltage across the low-side switch element SW_A1L and the second actual voltage VA2 indicating the voltage across the low-side switch element SW_A2L. Then, the rotational speed ⁇ of the motor is obtained.
  • the control circuit 300 Based on the acquired current and voltage in the dq coordinate system, the first actual voltage VA1, the second actual voltage VA2, and the rotational speed ⁇ , the control circuit 300 generates the high-side switch element SW_A1H, the high-side switch element SW_A2H, and the low-side switch element. An open failure of SW_A1L and low-side switch element SW_A2L is diagnosed.
  • the above-described failure diagnosis need not be performed for all three phases, and the failure diagnosis may be performed only for one phase or two phases.
  • the failure diagnosis may be performed only for one phase or two phases.
  • the process related to the A phase among the processes described with reference to FIGS. 5 to 15 is performed, and the processes related to the B phase and the C phase may not be performed.
  • FIG. 27 schematically shows a typical configuration of the electric power steering apparatus 3000 according to the present embodiment.
  • a vehicle such as an automobile generally has an electric power steering device.
  • the electric power steering apparatus 3000 includes a steering system 520 and an auxiliary torque mechanism 540 that generates auxiliary torque.
  • the electric power steering device 3000 generates auxiliary torque that assists the steering torque of the steering system that is generated when the driver operates the steering wheel. The burden on the driver's operation is reduced by the auxiliary torque.
  • the steering system 520 includes, for example, a steering handle 521, a steering shaft 522, universal shaft joints 523A and 523B, a rotating shaft 524, a rack and pinion mechanism 525, a rack shaft 526, left and right ball joints 552A and 552B, tie rods 527A and 527B, and a knuckle. 528A and 528B, and left and right steering wheels 529A and 529B.
  • the auxiliary torque mechanism 540 includes, for example, a steering torque sensor 541, an automotive electronic control unit (ECU) 542, a motor 543, a speed reduction mechanism 544, and the like.
  • the steering torque sensor 541 detects the steering torque in the steering system 520.
  • the ECU 542 generates a drive signal based on the detection signal of the steering torque sensor 541.
  • the motor 543 generates an auxiliary torque corresponding to the steering torque based on the drive signal.
  • the motor 543 transmits the generated auxiliary torque to the steering system 520 via the speed reduction mechanism 544.
  • the ECU 542 includes, for example, the controller 340 and the drive circuit 350 according to the first embodiment.
  • an electronic control system with an ECU as a core is constructed.
  • a motor drive unit is constructed by the ECU 542, the motor 543, and the inverter 545.
  • the motor module 2000 according to the first embodiment can be suitably used for the system.
  • an EPS that implements a fault diagnosis method according to an embodiment of the present disclosure is an autonomous driving vehicle that corresponds to levels 0 to 5 (standards for automation) defined by the Japanese government and the US Department of Transportation's Road Traffic Safety Administration (NHTSA). Can be mounted.
  • levels 0 to 5 standards for automation
  • NHTSA US Department of Transportation's Road Traffic Safety Administration
  • the embodiment of the present disclosure can be widely used in various devices including various motors such as a vacuum cleaner, a dryer, a ceiling fan, a washing machine, a refrigerator, and an electric power steering device.
  • various motors such as a vacuum cleaner, a dryer, a ceiling fan, a washing machine, a refrigerator, and an electric power steering device.

Abstract

This failure diagnostic method according to an embodiment of the present disclosure diagnoses a failure of a power converting device 1000 which converts power from a power source 101 into power to be supplied to a motor 200. The failure diagnostic method includes: a step for determining whether there is a failed phase among one or more phases; a step for determining whether there is a failed part among the high side and the low side of at least one H-bridge; a step for determining whether there is a failed inverter among a first inverter and a second inverter; and a step for determining whether there is a failed switching element on the basis of the determination result of whether there is a failed phase, the determination result of whether there is a failed part, and the determination result of whether there is a failed inverter.

Description

故障診断方法、電力変換装置、モータモジュールおよび電動パワーステアリング装置Failure diagnosis method, power conversion device, motor module, and electric power steering device
 本開示は、故障診断方法、電力変換装置、モータモジュールおよび電動パワーステアリング装置に関する。 The present disclosure relates to a failure diagnosis method, a power conversion device, a motor module, and an electric power steering device.
 近年、電動モータ(以下、単に「モータ」と表記する。)、インバータおよびECUが一体化された機電一体型モータが開発されている。特に車載分野において、安全性の観点から高い品質保証が要求される。そのため、部品の一部が故障した場合でも安全動作を継続できる冗長設計が取り入れられている。冗長設計の一例として、1つのモータに対して2つの電力変換装置を設けることが検討されている。他の一例として、メインのマイクロコントローラにバックアップ用マイクロコントローラを設けることが検討されている。 In recent years, an electromechanical integrated motor in which an electric motor (hereinafter simply referred to as “motor”), an inverter, and an ECU are integrated has been developed. Particularly in the in-vehicle field, high quality assurance is required from the viewpoint of safety. Therefore, a redundant design that can continue safe operation even when a part of the component fails is adopted. As an example of a redundant design, it is considered to provide two power conversion devices for one motor. As another example, it is considered to provide a backup microcontroller in the main microcontroller.
 特許文献1は、第1系統および第2系統を有するモータ駆動装置を開示する。第1系統は、モータの第1巻線組に接続され、第1インバータ部、電源リレーおよび逆接続保護リレーなどを有する。第2系統は、モータの第2巻線組に接続され、第2インバータ部、電源リレーおよび逆接続保護リレーなどを有する。モータ駆動装置に故障が生じていないとき、第1系統および第2系統の両方を用いてモータを駆動することが可能である。これに対し、第1系統および第2系統の一方、または、第1巻線組および第2巻線組の一方に故障が生じたとき、電源リレーは、電源から、故障した系統、または、故障した巻線組に接続された系統への電力供給を遮断する。故障していない他方の系統を用いてモータ駆動を継続させることが可能である。 Patent Document 1 discloses a motor drive device having a first system and a second system. The first system is connected to the first winding set of the motor and includes a first inverter unit, a power supply relay, a reverse connection protection relay, and the like. The second system is connected to the second winding set of the motor and includes a second inverter unit, a power supply relay, a reverse connection protection relay, and the like. When there is no failure in the motor drive device, it is possible to drive the motor using both the first system and the second system. On the other hand, when a failure occurs in one of the first system and the second system, or one of the first winding group and the second winding group, the power relay is connected to the failed system or from the power source. The power supply to the system connected to the winding set is cut off. It is possible to continue motor driving using the other system that has not failed.
 特許文献2および3も、第1系統および第2系統を有するモータ駆動装置を開示する。一方の系統または一方の巻線組が故障したとしても、故障していない系統によってモータ駆動を継続させることができる。 Patent Documents 2 and 3 also disclose a motor drive device having a first system and a second system. Even if one system or one winding set fails, motor drive can be continued by a system that does not fail.
日本国公開公報:特開2016-34204号公報Japan Publication: JP-A-2016-34204 日本国公開公報:特開2016-32977号公報Japan publication: JP-A-2016-32977 日本国公開公報:特開2008-132919号公報Japanese publication: JP-A-2008-132919
 上述した従来の技術では、電力変換装置が備えるスイッチ素子の故障を適切に検出することが求められていた。 In the conventional technology described above, it has been required to appropriately detect a failure of a switch element included in the power conversion device.
 本開示の実施形態は、電力変換装置が備えるスイッチ素子の故障を適切に診断することが可能な故障診断方法を提供する。 Embodiment of this indication provides the failure diagnostic method which can diagnose appropriately the failure of the switch element with which a power converter is provided.
 本開示の例示的な故障診断方法は、電源からの電力を、少なくとも一相の巻線を有するモータに供給する電力に変換する電力変換装置の故障を診断する故障診断方法であって、前記電力変換装置は、前記少なくとも一相の巻線の一端に接続される第1インバータと、前記少なくとも一相の巻線の他端に接続される第2インバータと、各々が第1ハイサイドスイッチ素子、第1ローサイドスイッチ素子、第2ハイサイドスイッチ素子および第2ローサイドスイッチ素子を有する少なくとも1つのHブリッジと、を備え、前記故障診断方法は、前記少なくとも一相の中に故障した相があるか判定するステップと、前記少なくとも1つのHブリッジのハイサイドおよびローサイドの中に故障したパートがあるか判定するステップと、前記第1インバータおよび前記第2インバータの中に故障したインバータがあるか判定するステップと、前記故障した相があるかの判定結果、前記故障したパートがあるかの判定結果および前記故障したインバータがあるかの判定結果に基づいて、前記第1ハイサイドスイッチ素子、前記第1ローサイドスイッチ素子、前記第2ハイサイドスイッチ素子および前記第2ローサイドスイッチ素子の中に故障したスイッチ素子があるか判定するステップと、を包含する。 An exemplary failure diagnosis method of the present disclosure is a failure diagnosis method for diagnosing a failure in a power conversion device that converts electric power from a power source into electric power supplied to a motor having at least one phase winding, the electric power The converter includes a first inverter connected to one end of the at least one phase winding, a second inverter connected to the other end of the at least one phase winding, each of which is a first high-side switch element, At least one H-bridge having a first low-side switch element, a second high-side switch element, and a second low-side switch element, and the failure diagnosis method determines whether there is a failed phase in the at least one phase Determining whether there is a failed part in the high side and low side of the at least one H-bridge; and And whether there is a faulty inverter in the data and the second inverter, a judgment result of whether there is a faulty phase, a judgment result of whether there is a faulty part, and whether there is a faulty inverter Determining whether there is a failed switch element among the first high-side switch element, the first low-side switch element, the second high-side switch element, and the second low-side switch element, based on the determination result of .
 本開示の例示的な電力変換装置は、電源からの電力を、少なくとも一相の巻線を有するモータに供給する電力に変換する電力変換装置であって、前記電力変換装置は、前記少なくとも一相の巻線の一端に接続される第1インバータと、前記少なくとも一相の巻線の他端に接続される第2インバータと、各々が第1ハイサイドスイッチ素子、第1ローサイドスイッチ素子、第2ハイサイドスイッチ素子および第2ローサイドスイッチ素子を有する少なくとも1つのHブリッジと、前記第1インバータおよび前記第2インバータの動作を制御する制御回路と、を備え、前記制御回路は、前記少なくとも一相の中に故障した相があるか判定し、前記少なくとも1つのHブリッジのハイサイドおよびローサイドの中に故障したパートがあるか判定し、前記第1インバータおよび前記第2インバータの中に故障したインバータがあるか判定し、前記故障した相があるかの判定結果、前記故障したパートがあるかの判定結果および前記故障したインバータがあるかの判定結果に基づいて、前記第1ハイサイドスイッチ素子、前記第1ローサイドスイッチ素子、前記第2ハイサイドスイッチ素子および前記第2ローサイドスイッチ素子の中に故障したスイッチ素子があるか判定する。 An exemplary power conversion device of the present disclosure is a power conversion device that converts power from a power source into power supplied to a motor having at least one phase winding, the power conversion device including the at least one phase. A first inverter connected to one end of the first winding, a second inverter connected to the other end of the at least one-phase winding, a first high-side switch element, a first low-side switch element, a second And at least one H-bridge having a high-side switch element and a second low-side switch element, and a control circuit for controlling operations of the first inverter and the second inverter, the control circuit comprising the at least one phase Determine if there is a faulty phase and determine if there is a faulty part in the high side and low side of the at least one H-bridge. It is determined whether there is a failed inverter in the first inverter and the second inverter, the determination result whether there is the failed phase, the determination result whether there is the failed part, and whether there is the failed inverter Based on the determination result, it is determined whether there is a failed switch element among the first high-side switch element, the first low-side switch element, the second high-side switch element, and the second low-side switch element.
 本開示の例示的な実施形態によると、電力変換装置が備えるスイッチ素子の故障を適切に診断することが可能な故障診断方法、電力変換装置、当該電力変換装置を備えるモータモジュールおよび当該モータモジュールを備える電動パワーステアリング装置が提供される。 According to an exemplary embodiment of the present disclosure, a failure diagnosis method capable of appropriately diagnosing a failure of a switch element included in a power conversion device, a power conversion device, a motor module including the power conversion device, and the motor module are provided. An electric power steering apparatus is provided.
図1は、実施形態に係るモータモジュールを模式的に示すブロック図である。FIG. 1 is a block diagram schematically illustrating a motor module according to an embodiment. 図2は、実施形態に係るインバータユニットを模式的に示す回路図である。FIG. 2 is a circuit diagram schematically showing the inverter unit according to the embodiment. 図3Aは、A相のHブリッジを示す模式図である。FIG. 3A is a schematic diagram showing an A-phase H-bridge. 図3Bは、B相のHブリッジを示す模式図である。FIG. 3B is a schematic diagram showing a B-phase H-bridge. 図3Cは、C相のHブリッジを示す模式図である。FIG. 3C is a schematic diagram showing a C-phase H-bridge. 図4は、モータ制御全般を行うコントローラを示す機能ブロック図である。FIG. 4 is a functional block diagram showing a controller that performs overall motor control. 図5は、A相、B相、C相の故障診断を行うための機能ブロックを示す図である。FIG. 5 is a diagram illustrating functional blocks for performing fault diagnosis of the A phase, the B phase, and the C phase. 図6は、A相の故障診断を行うための機能ブロックを示す図である。FIG. 6 is a diagram illustrating functional blocks for performing a phase A failure diagnosis. 図7は、B相の故障診断を行うための機能ブロックを示す図である。FIG. 7 is a diagram illustrating functional blocks for performing a B-phase failure diagnosis. 図8は、C相の故障診断を行うための機能ブロックを示す図である。FIG. 8 is a diagram illustrating functional blocks for performing a C-phase failure diagnosis. 図9は、第1インバータおよび第2インバータの故障診断を行うための機能ブロックを示す図である。FIG. 9 is a diagram illustrating functional blocks for performing failure diagnosis of the first inverter and the second inverter. 図10は、第1インバータの故障診断を行うための機能ブロックを示す図である。FIG. 10 is a diagram illustrating functional blocks for performing failure diagnosis of the first inverter. 図11は、第2インバータの故障診断を行うための機能ブロックを示す図である。FIG. 11 is a diagram illustrating functional blocks for performing failure diagnosis of the second inverter. 図12は、Hブリッジのローサイドの故障診断を行うための機能ブロックを示す図である。FIG. 12 is a diagram showing functional blocks for performing a fault diagnosis on the low side of the H-bridge. 図13は、Hブリッジのハイサイドの故障診断を行うための機能ブロックを示す図である。FIG. 13 is a diagram illustrating functional blocks for performing failure diagnosis on the high side of the H bridge. 図14は、第1インバータのスイッチ素子の故障診断を行うための機能ブロックを示す図である。FIG. 14 is a diagram illustrating functional blocks for performing failure diagnosis of the switch element of the first inverter. 図15は、第2インバータのスイッチ素子の故障診断を行うための機能ブロックを示す図である。FIG. 15 is a diagram illustrating functional blocks for performing failure diagnosis of the switch element of the second inverter. 図16は、回転速度ωおよび電流振幅値から飽和電圧Vsatを決定するルックアップテーブルを示す模式図である。FIG. 16 is a schematic diagram showing a look-up table for determining the saturation voltage Vsat from the rotation speed ω and the current amplitude value. 図17は、三相通電制御に従って電力変換装置を制御したときにモータのA相、B相およびC相の各巻線に流れる電流値をプロットして得られる電流波形(正弦波)を例示するグラフである。FIG. 17 is a graph illustrating a current waveform (sine wave) obtained by plotting the current values flowing through the windings of the A phase, B phase, and C phase of the motor when the power conversion device is controlled according to the three-phase energization control. It is. 図18は、A相が故障した場合、二相通電制御に従って電力変換装置を制御したときにモータのB相、C相の各巻線に流れる電流値をプロットして得られる電流波形を例示するグラフである。FIG. 18 is a graph illustrating a current waveform obtained by plotting the current values flowing through the B-phase and C-phase windings of the motor when the A-phase has failed and the power converter is controlled according to the two-phase energization control. It is. 図19は、B相が故障した場合、二相通電制御に従って電力変換装置を制御したときにモータのC相、A相の各巻線に流れる電流値をプロットして得られる電流波形を例示するグラフである。FIG. 19 is a graph exemplifying a current waveform obtained by plotting the current value flowing in each of the C-phase and A-phase windings of the motor when the B-phase has failed and the power conversion device is controlled according to the two-phase energization control. It is. 図20は、C相が故障した場合、二相通電制御に従って電力変換装置を制御したときにモータのA相、B相の各巻線に流れる電流値をプロットして得られる電流波形を例示するグラフである。FIG. 20 is a graph illustrating a current waveform obtained by plotting the current values flowing through the windings of the A phase and B phase of the motor when the power conversion device is controlled according to the two-phase energization control when the C phase fails. It is. 図21は、ローサイドスイッチ素子SW_A1Lがオープン故障した場合の実電圧VA1(上側)および実電圧VA2(下側)のシミュレーション結果の波形を示すグラフである。FIG. 21 is a graph showing waveforms of simulation results of the actual voltage VA1 (upper side) and the actual voltage VA2 (lower side) when the low-side switch element SW_A1L has an open failure. 図22は、ローサイドスイッチ素子SW_A1Lがオープン故障した場合の実電圧VB1(上側)および実電圧VB2(下側)のシミュレーション結果の波形を示すグラフである。FIG. 22 is a graph showing waveforms of simulation results of the actual voltage VB1 (upper side) and the actual voltage VB2 (lower side) when the low-side switch element SW_A1L has an open failure. 図23は、ローサイドスイッチ素子SW_A1Lがオープン故障した場合の実電圧VC1(上側)および実電圧VC2(下側)のシミュレーション結果の波形を示すグラフである。FIG. 23 is a graph showing waveforms of simulation results of the actual voltage VC1 (upper side) and the actual voltage VC2 (lower side) when the low-side switch element SW_A1L has an open failure. 図24は、ハイサイドスイッチ素子SW_A1Hがオープン故障した場合の実電圧VA1(上側)および実電圧VA2(下側)のシミュレーション結果の波形を示すグラフである。FIG. 24 is a graph showing waveforms of simulation results of the actual voltage VA1 (upper side) and the actual voltage VA2 (lower side) when the high-side switch element SW_A1H has an open failure. 図25は、ハイサイドスイッチ素子SW_A1Hがオープン故障した場合の実電圧VB1(上側)および実電圧VB2(下側)のシミュレーション結果の波形を示すグラフである。FIG. 25 is a graph showing waveforms of simulation results of the actual voltage VB1 (upper side) and the actual voltage VB2 (lower side) when the high-side switch element SW_A1H has an open failure. 図26は、ハイサイドスイッチ素子SW_A1Hがオープン故障した場合の実電圧VC1(上側)および実電圧VC2(下側)のシミュレーション結果の波形を示すグラフである。FIG. 26 is a graph showing waveforms of simulation results of the actual voltage VC1 (upper side) and the actual voltage VC2 (lower side) when the high-side switch element SW_A1H has an open failure. 図27は、例示的な実施形態に係る電動パワーステアリング装置を示す模式図である。FIG. 27 is a schematic diagram illustrating an electric power steering apparatus according to an exemplary embodiment.
 以下、添付の図面を参照しながら、本開示のスイッチ素子の故障診断方法、電力変換装置、モータモジュールおよび電動パワーステアリング装置の実施形態を詳細に説明する。但し、以下の説明が不必要に冗長になるのを避け、当業者の理解を容易にするため、必要以上に詳細な説明は省略する場合がある。例えば、既によく知られた事項の詳細説明や実質的に同一の構成に対する重複説明を省略する場合がある。 Hereinafter, embodiments of a switch element failure diagnosis method, a power conversion device, a motor module, and an electric power steering device according to the present disclosure will be described in detail with reference to the accompanying drawings. However, in order to avoid the following description from being unnecessarily redundant and to facilitate understanding by those skilled in the art, a more detailed description than necessary may be omitted. For example, detailed descriptions of already well-known matters and repeated descriptions for substantially the same configuration may be omitted.
 本明細書において、電源からの電力を、三相(A相、B相、C相)の巻線を有する三相モータに供給する電力に変換する電力変換装置を例にして、本開示の実施形態を説明する。ただし、電源からの電力を、四相または五相などのn相(nは4以上の整数)の巻線を有するn相モータに供給する電力に変換する電力変換装置、およびその装置に用いるスイッチ素子の故障診断方法も本開示の範疇である。 In the present specification, implementation of the present disclosure will be described by taking, as an example, a power conversion device that converts power from a power source into power to be supplied to a three-phase motor having three-phase (A-phase, B-phase, and C-phase) windings. A form is demonstrated. However, a power conversion device that converts electric power from a power source into electric power to be supplied to an n-phase motor having an n-phase winding (n is an integer of 4 or more) such as four-phase or five-phase, and a switch used in the device An element failure diagnosis method is also included in the scope of the present disclosure.
 (実施形態1)
 〔1.モータモジュール2000および電力変換装置1000の構造〕
 図1は、本実施形態によるモータモジュール2000の典型的なブロック構成を模式的に示している。
(Embodiment 1)
[1. Structure of motor module 2000 and power conversion apparatus 1000]
FIG. 1 schematically shows a typical block configuration of a motor module 2000 according to the present embodiment.
 モータモジュール2000は、典型的に、インバータユニット100と制御回路300とを有する電力変換装置1000およびモータ200を備える。モータモジュール2000は、モジュール化され、例えば、モータ、センサ、ドライバおよびコントローラを有する機電一体型モータとして製造および販売され得る。 The motor module 2000 typically includes a power converter 1000 having the inverter unit 100 and a control circuit 300 and a motor 200. The motor module 2000 is modularized and can be manufactured and sold as, for example, an electromechanically integrated motor having a motor, a sensor, a driver, and a controller.
 電力変換装置1000は、電源101(図2を参照)からの電力をモータ200に供給する電力に変換することが可能である。電力変換装置1000は、モータ200に接続される。例えば、電力変換装置1000は、直流電力を、A相、B相およびC相の擬似正弦波である三相交流電力に変換することが可能である。本明細書において、部品(構成要素)同士の間の「接続」とは、主に電気的な接続を意味する。 The power conversion apparatus 1000 can convert power from the power source 101 (see FIG. 2) into power supplied to the motor 200. The power conversion apparatus 1000 is connected to the motor 200. For example, the power conversion apparatus 1000 can convert DC power into three-phase AC power that is pseudo-sine waves of A phase, B phase, and C phase. In this specification, “connection” between components (components) mainly means electrical connection.
 モータ200は、例えば三相交流モータである。モータ200は、A相の巻線M1、B相の巻線M2およびC相の巻線M3を備え、インバータユニット100の第1インバータ120と第2インバータ130とに接続される。具体的に説明すると、第1インバータ120はモータ200の各相の巻線の一端に接続され、第2インバータ130は各相の巻線の他端に接続される。 The motor 200 is, for example, a three-phase AC motor. The motor 200 includes an A-phase winding M1, a B-phase winding M2, and a C-phase winding M3, and is connected to the first inverter 120 and the second inverter 130 of the inverter unit 100. More specifically, the first inverter 120 is connected to one end of each phase winding of the motor 200, and the second inverter 130 is connected to the other end of each phase winding.
 制御回路300は、例えば、電源回路310と、角度センサ320と、入力回路330と、コントローラ340と、駆動回路350と、ROM360とを備える。制御回路300の各部品は、例えば1枚の回路基板(典型的にはプリント基板)に実装される。制御回路300は、インバータユニット100に接続され、電流センサ150および角度センサ320からの入力信号に基づいてインバータユニット100を制御する。その制御手法として、例えばベクトル制御、パルス幅変調(PWM)または直接トルク制御(DTC)がある。ただし、モータ制御手法(例えばセンサレス制御)によっては、角度センサ320は不要な場合がある。 The control circuit 300 includes, for example, a power supply circuit 310, an angle sensor 320, an input circuit 330, a controller 340, a drive circuit 350, and a ROM 360. Each component of the control circuit 300 is mounted on, for example, one circuit board (typically a printed board). The control circuit 300 is connected to the inverter unit 100 and controls the inverter unit 100 based on input signals from the current sensor 150 and the angle sensor 320. Examples of the control method include vector control, pulse width modulation (PWM), and direct torque control (DTC). However, the angle sensor 320 may be unnecessary depending on the motor control method (for example, sensorless control).
 制御回路300は、目的とする、モータ200のロータの位置、回転速度、および電流などを制御してクローズドループ制御を実現することができる。なお、制御回路300は、角度センサ320に代えてトルクセンサを備えてもよい。この場合、制御回路300は、目的とするモータトルクを制御することができる。 The control circuit 300 can realize the closed loop control by controlling the target position, rotation speed, current, etc. of the rotor of the motor 200. Note that the control circuit 300 may include a torque sensor instead of the angle sensor 320. In this case, the control circuit 300 can control the target motor torque.
 電源回路310は、電源101の例えば12Vの電圧に基づいて回路内の各ブロックに必要な電源電圧(例えば3V、5V)を生成する。 The power supply circuit 310 generates a power supply voltage (for example, 3V, 5V) necessary for each block in the circuit based on the voltage of the power supply 101, for example, 12V.
 角度センサ320は、例えばレゾルバまたはホールICである。または、角度センサ320は、磁気抵抗(MR)素子を有するMRセンサとセンサマグネットとの組み合わせによっても実現される。角度センサ320は、ロータの回転角(以下、「回転信号」と表記する。)を検出し、回転信号をコントローラ340に出力する。 The angle sensor 320 is, for example, a resolver or a Hall IC. Alternatively, the angle sensor 320 is also realized by a combination of an MR sensor having a magnetoresistive (MR) element and a sensor magnet. The angle sensor 320 detects the rotation angle of the rotor (hereinafter referred to as “rotation signal”) and outputs the rotation signal to the controller 340.
 入力回路330は、電流センサ150によって検出された相電流(以下、「実電流値」と表記する場合がある。)を受け取って、実電流値のレベルをコントローラ340の入力レベルに必要に応じて変換し、実電流値をコントローラ340に出力する。入力回路330は、例えばアナログデジタル(AD)変換回路である。 The input circuit 330 receives the phase current detected by the current sensor 150 (hereinafter sometimes referred to as “actual current value”), and changes the level of the actual current value to the input level of the controller 340 as necessary. The actual current value is output to the controller 340. The input circuit 330 is, for example, an analog / digital (AD) conversion circuit.
 コントローラ340は、電力変換装置1000の全体を制御する集積回路であり、例えば、マイクロコントローラまたはFPGA(Field Programmable Gate Array)である。コントローラ340は、インバータユニット100の第1および第2インバータ120、130における各スイッチ素子(典型的には半導体スイッチ素子)のスイッチング動作(ターンオンまたはターンオフ)を制御する。コントローラ340は、実電流値およびロータの回転信号などに従って目標電流値を設定してPWM信号を生成し、それを駆動回路350に出力する。 The controller 340 is an integrated circuit that controls the entire power conversion apparatus 1000, and is, for example, a microcontroller or an FPGA (Field Programmable Gate Array). The controller 340 controls the switching operation (turn-on or turn-off) of each switch element (typically a semiconductor switch element) in the first and second inverters 120 and 130 of the inverter unit 100. The controller 340 sets the target current value according to the actual current value and the rotation signal of the rotor, generates a PWM signal, and outputs it to the drive circuit 350.
 駆動回路350は典型的にはプリドライバ(「ゲートドライバ」と呼ばれることもある)である。駆動回路350は、インバータユニット100の第1および第2インバータ120、130における各スイッチ素子のスイッチング動作を制御する制御信号(ゲート制御信号)をPWM信号に従って生成し、各スイッチ素子のゲートに制御信号を与える。駆動対象が低電圧で駆動可能なモータであるとき、プリドライバは必ずしも必要とされない場合がある。その場合、プリドライバの機能はコントローラ340に実装され得る。 The drive circuit 350 is typically a pre-driver (sometimes called a “gate driver”). The drive circuit 350 generates a control signal (gate control signal) for controlling the switching operation of each switch element in the first and second inverters 120 and 130 of the inverter unit 100 according to the PWM signal, and supplies a control signal to the gate of each switch element. give. When the driving target is a motor that can be driven at a low voltage, the pre-driver may not be necessarily required. In that case, the function of the pre-driver can be implemented in the controller 340.
 ROM360は、例えば書き込み可能なメモリ(例えばPROM)、書き換え可能なメ
モリ(例えばフラッシュメモリ)または読み出し専用のメモリである。ROM360は、コントローラ340に電力変換装置1000を制御させるための命令群を含む制御プログラムを格納している。例えば、制御プログラムはブート時にRAM(不図示)に一旦展開される。
The ROM 360 is, for example, a writable memory (for example, PROM), a rewritable memory (for example, flash memory), or a read-only memory. The ROM 360 stores a control program including a command group for causing the controller 340 to control the power conversion apparatus 1000. For example, the control program is temporarily expanded in a RAM (not shown) at the time of booting.
 図2を参照しインバータユニット100の具体的な回路構成を説明する。 A specific circuit configuration of the inverter unit 100 will be described with reference to FIG.
 図2は、本実施形態によるインバータユニット100の回路構成を模式的に示している。 FIG. 2 schematically shows a circuit configuration of the inverter unit 100 according to the present embodiment.
 電源101は、所定の電源電圧(例えば12V)を生成する。電源101として、例えば直流電源が用いられる。ただし、電源101は、AC-DCコンバータまたはDC―DCコンバータであってもよいし、バッテリー(蓄電池)であってもよい。電源101は、図示するように、第1および第2インバータ120、130に共通の単一電源であってもよいし、第1インバータ120用の第1電源(不図示)および第2インバータ130用の第2電源(不図示)を備えていてもよい。 The power supply 101 generates a predetermined power supply voltage (for example, 12V). As the power source 101, for example, a DC power source is used. However, the power source 101 may be an AC-DC converter, a DC-DC converter, or a battery (storage battery). The power source 101 may be a single power source common to the first and second inverters 120 and 130 as shown in the figure, or may be a first power source (not shown) for the first inverter 120 and for the second inverter 130. A second power source (not shown) may be provided.
 図示されていないが、電源101と第1インバータ120の間、および、電源101と第2インバータ130の間にコイルが設けられる。コイルは、ノイズフィルタとして機能し、各インバータに供給する電圧波形に含まれる高周波ノイズ、または各インバータで発生する高周波ノイズを電源101側に流出させないように平滑化する。また、各インバータの電源端子には、コンデンサが接続される。コンデンサは、いわゆるバイパスコンデンサであり、電圧リプルを抑制する。コンデンサは、例えば電解コンデンサであり、容量および使用する個数は設計仕様などによって適宜決定される。 Although not shown, coils are provided between the power source 101 and the first inverter 120 and between the power source 101 and the second inverter 130. The coil functions as a noise filter, and smoothes the high frequency noise included in the voltage waveform supplied to each inverter or the high frequency noise generated by each inverter so as not to flow out to the power supply 101 side. A capacitor is connected to the power supply terminal of each inverter. The capacitor is a so-called bypass capacitor and suppresses voltage ripple. The capacitor is, for example, an electrolytic capacitor, and the capacity and the number to be used are appropriately determined according to design specifications.
 第1インバータ120は、3個のレグから構成されるブリッジ回路を有する。各レグは、ハイサイドスイッチ素子、ローサイドスイッチ素子およびシャント抵抗を有する。A相レグは、ハイサイドスイッチ素子SW_A1H、ローサイドスイッチ素子SW_A1Lおよび第1シャント抵抗S_A1を有する。B相レグは、ハイサイドスイッチ素子SW_B1H、ローサイドスイッチ素子SW_B1Lおよび第1シャント抵抗S_B1を有する。C相レグは、ハイサイドスイッチ素子SW_C1H、ローサイドスイッチ素子SW_C1Lおよび第1シャント抵抗S_C1を有する。 The first inverter 120 has a bridge circuit composed of three legs. Each leg has a high-side switch element, a low-side switch element, and a shunt resistor. The A-phase leg includes a high-side switch element SW_A1H, a low-side switch element SW_A1L, and a first shunt resistor S_A1. The B-phase leg has a high-side switch element SW_B1H, a low-side switch element SW_B1L, and a first shunt resistor S_B1. The C-phase leg has a high-side switch element SW_C1H, a low-side switch element SW_C1L, and a first shunt resistor S_C1.
 スイッチ素子として、例えば、寄生ダイオードが内部に形成された電界効果トランジスタ(典型的にはMOSFET)、または、絶縁ゲートバイポーラトランジスタ(IGBT)とそれに並列接続された還流ダイオードとの組み合わせを用いることができる。 As the switch element, for example, a field effect transistor (typically MOSFET) having a parasitic diode formed therein, or a combination of an insulated gate bipolar transistor (IGBT) and a free-wheeling diode connected in parallel thereto can be used. .
 第1シャント抵抗S_A1は、A相の巻線M1を流れるA相電流IA1を検出するために用いられ、例えば、ローサイドスイッチ素子SW_A1LとGNDラインGLの間に接続される。第1シャント抵抗S_B1は、B相の巻線M2を流れるB相電流IB1を検出するために用いられ、例えば、ローサイドスイッチ素子SW_B1LとGNDラインGLの間に接続される。第1シャント抵抗S_C1は、C相の巻線M3を流れるC相電流IC1を検出するために用いられ、例えば、ローサイドスイッチ素子SW_C1LとGNDラインGLの間に接続される。3個のシャント抵抗S_A1、S_B1およびS_C1は、第1インバータ120のGNDラインGLと共通に接続されている。 The first shunt resistor S_A1 is used to detect the A-phase current IA1 flowing through the A-phase winding M1, and is connected, for example, between the low-side switch element SW_A1L and the GND line GL. The first shunt resistor S_B1 is used to detect the B-phase current IB1 flowing through the B-phase winding M2, and is connected between the low-side switch element SW_B1L and the GND line GL, for example. The first shunt resistor S_C1 is used to detect the C-phase current IC1 flowing through the C-phase winding M3, and is connected between, for example, the low-side switch element SW_C1L and the GND line GL. The three shunt resistors S_A1, S_B1, and S_C1 are connected in common with the GND line GL of the first inverter 120.
 第2インバータ130は、3個のレグから構成されるブリッジ回路を有する。各レグは、ハイサイドスイッチ素子、ローサイドスイッチ素子およびシャント抵抗を有する。A相レグは、ハイサイドスイッチ素子SW_A2H、ローサイドスイッチ素子SW_A2Lおよびシャント抵抗S_A2を有する。B相レグは、ハイサイドスイッチ素子SW_B2H、ローサイドスイッチ素子SW_B2Lおよびシャント抵抗S_B2を有する。C相レグは、ハイサイドスイッチ素子SW_C2H、ローサイドスイッチ素子SW_C2Lおよびシャント抵抗S_C2を有する。 The second inverter 130 has a bridge circuit composed of three legs. Each leg has a high-side switch element, a low-side switch element, and a shunt resistor. The A-phase leg has a high-side switch element SW_A2H, a low-side switch element SW_A2L, and a shunt resistor S_A2. The B-phase leg has a high-side switch element SW_B2H, a low-side switch element SW_B2L, and a shunt resistor S_B2. The C-phase leg has a high-side switch element SW_C2H, a low-side switch element SW_C2L, and a shunt resistor S_C2.
 シャント抵抗S_A2は、A相電流IA2を検出するために用いられ、例えば、ローサイドスイッチ素子SW_A2LとGNDラインGLの間に接続される。シャント抵抗S_B2は、B相電流IB2を検出するために用いられ、例えば、ローサイドスイッチ素子SW_B2LとGNDラインGLの間に接続される。シャント抵抗S_C2は、C相電流IC2を検出するために用いられ、例えば、ローサイドスイッチ素子SW_C2LとGNDラインGLの間に接続される。3個のシャント抵抗S_A2、S_B2およびS_C2は、第2インバータ130のGNDラインGLと共通に接続されている。 The shunt resistor S_A2 is used to detect the A-phase current IA2, and is connected, for example, between the low-side switch element SW_A2L and the GND line GL. The shunt resistor S_B2 is used to detect the B-phase current IB2, and is connected between, for example, the low-side switch element SW_B2L and the GND line GL. The shunt resistor S_C2 is used to detect the C-phase current IC2, and is connected, for example, between the low-side switch element SW_C2L and the GND line GL. The three shunt resistors S_A2, S_B2, and S_C2 are connected in common with the GND line GL of the second inverter 130.
 上述した電流センサ150は、例えば、シャント抵抗S_A1、S_B1、S_C1、S_A2、S_B2、S_C2および各シャント抵抗に流れる電流を検出する電流検出回路(不図示)を備える。 The current sensor 150 described above includes, for example, a shunt resistor S_A1, S_B1, S_C1, S_A2, S_B2, S_C2, and a current detection circuit (not shown) that detects a current flowing through each shunt resistor.
 第1インバータ120のA相レグ(具体的には、ハイサイドスイッチ素子SW_A1Hおよびローサイドスイッチ素子SW_A1Lの間のノード)は、モータ200のA相の巻線M1の一端A1に接続され、第2インバータ130のA相レグは、A相の巻線M1の他端A2に接続される。第1インバータ120のB相レグは、モータ200のB相の巻線M2の一端B1に接続され、第2インバータ130のB相レグは、巻線M2の他端B2に接続される。第1インバータ120のC相レグは、モータ200のC相の巻線M3の一端C1に接続され、第2インバータ130のC相レグは、巻線M3の他端C2に接続される。 The A-phase leg of the first inverter 120 (specifically, a node between the high-side switch element SW_A1H and the low-side switch element SW_A1L) is connected to one end A1 of the A-phase winding M1 of the motor 200, and the second inverter The 130 A-phase leg is connected to the other end A2 of the A-phase winding M1. The B-phase leg of the first inverter 120 is connected to one end B1 of the B-phase winding M2 of the motor 200, and the B-phase leg of the second inverter 130 is connected to the other end B2 of the winding M2. The C-phase leg of the first inverter 120 is connected to one end C1 of the C-phase winding M3 of the motor 200, and the C-phase leg of the second inverter 130 is connected to the other end C2 of the winding M3.
 図3Aは、A相のHブリッジBAの構成を模式的に示している。図3Bは、B相のHブリッジBBの構成を模式的に示している。図3Cは、C相のHブリッジBCの構成を模式的に示している。 FIG. 3A schematically shows the configuration of the A-phase H-bridge BA. FIG. 3B schematically shows the configuration of a B-phase H-bridge BB. FIG. 3C schematically shows the configuration of a C-phase H-bridge BC.
 インバータユニット100は、A相、B相およびC相のHブリッジBA、BBおよびBCを備える。A相のHブリッジBAは、第1インバータ120側のレグにおけるハイサイドスイッチ素子SW_A1H、ローサイドスイッチ素子SW_A1L、第2インバータ130側のレグにおけるハイサイドスイッチ素子SW_A2H、ローサイドスイッチ素子SW_A2L、および、巻線M1を有する。 The inverter unit 100 includes A-phase, B-phase, and C-phase H-bridges BA, BB, and BC. The A-phase H bridge BA includes a high-side switch element SW_A1H and a low-side switch element SW_A1L in the leg on the first inverter 120 side, a high-side switch element SW_A2H, a low-side switch element SW_A2L in the leg on the second inverter 130 side, and a winding Has M1.
 B相のHブリッジBBは、第1インバータ120側のレグにおけるハイサイドスイッチ素子SW_B1H、ローサイドスイッチ素子SW_B1L、第2インバータ130側のレグにおけるハイサイドスイッチ素子SW_B2H、ローサイドスイッチ素子SW_B2L、および、巻線M2を有する。 The B-phase H-bridge BB includes a high-side switch element SW_B1H and a low-side switch element SW_B1L in the leg on the first inverter 120 side, a high-side switch element SW_B2H, a low-side switch element SW_B2L in the leg on the second inverter 130 side, and a winding Has M2.
 C相のHブリッジBCは、第1インバータ120側のレグにおけるハイサイドスイッチ素子SW_C1H、ローサイドスイッチ素子SW_C1L、第2インバータ130側のレグにおけるハイサイドスイッチ素子SW_C2H、ローサイドスイッチ素子SW_C2L、および、巻線M3を有する。 The C-phase H-bridge BC includes a high-side switch element SW_C1H and a low-side switch element SW_C1L in the leg on the first inverter 120 side, a high-side switch element SW_C2H, a low-side switch element SW_C2L in the leg on the second inverter 130 side, and a winding M3.
 制御回路300(具体的にはコントローラ340)は、以下で説明する故障診断を実行することにより、電力変換装置1000内の故障したスイッチ素子を特定することができる。 The control circuit 300 (specifically, the controller 340) can specify a failed switch element in the power conversion apparatus 1000 by executing a failure diagnosis described below.
 例えば、制御回路300は、故障したスイッチ素子を特定すると、故障したスイッチ素子を含むHブリッジ以外の二相のHブリッジを用いて二相の巻線に通電するモータ制御に切替えることができる。本明細書において、三相の巻線に通電することを「三相通電制御」と呼び、二相の巻線に通電することを「二相通電制御」と呼ぶこととする。以下、故障診断の詳細を説明する。 For example, when the faulty switch element is identified, the control circuit 300 can switch to motor control in which a two-phase winding is energized using a two-phase H bridge other than the H bridge including the faulty switch element. In this specification, energizing the three-phase winding is referred to as “three-phase energization control”, and energizing the two-phase winding is referred to as “two-phase energization control”. Details of the failure diagnosis will be described below.
 〔2.故障診断方法〕
 図4から図16を参照しながら、例えば、図1に示す電力変換装置1000のスイッチ素子の故障の有無を診断する故障診断方法の具体例を説明する。本開示の故障診断方法は、少なくとも1つのHブリッジを備える電力変換装置、例えばフルブリッジタイプの電力変換装置に好適に用いることができる。本明細書中において、スイッチ素子の故障は、スイッチ素子のオープン故障を指す。オープン故障とは、スイッチ素子が常時ハイインピーダンスになる故障である。本明細書では、例えばA相のHブリッジのスイッチ素子に故障が生じることを、A相の故障と呼ぶ場合がある。
[2. (Failure diagnosis method)
With reference to FIGS. 4 to 16, for example, a specific example of a failure diagnosis method for diagnosing the presence or absence of a failure of the switch element of the power conversion apparatus 1000 shown in FIG. 1 will be described. The failure diagnosis method of the present disclosure can be suitably used for a power conversion device including at least one H bridge, for example, a full bridge type power conversion device. In this specification, the failure of a switch element refers to the open failure of a switch element. An open failure is a failure in which the switch element always has a high impedance. In the present specification, for example, a failure occurring in a switching element of an A-phase H-bridge may be referred to as an A-phase failure.
 本実施形態の故障診断方法の概要は、下記のとおりである。 The outline of the failure diagnosis method of this embodiment is as follows.
 故障診断では、A相、B相、C相の中に故障した相があるか判定する。また、HブリッジBA、BB、BCのハイサイドおよびローサイドの中に故障したパートがあるか判定する。また、第1インバータ120および第2インバータ130の中に故障したインバータがあるか判定する。これらの判定結果に基づいて、電力変換装置1000が備えるハイサイドスイッチ素子およびローサイドスイッチ素子の中に故障したスイッチ素子があるか判定する。 In failure diagnosis, it is determined whether there is a failed phase in the A phase, the B phase, or the C phase. Further, it is determined whether there is a failed part in the high side and the low side of the H bridges BA, BB, and BC. Further, it is determined whether there is a failed inverter in the first inverter 120 and the second inverter 130. Based on these determination results, it is determined whether there is a failed switch element among the high-side switch element and the low-side switch element included in the power conversion device 1000.
 故障診断では、例えば、dq座標系において表現される電流および電圧と、ローサイドスイッチ素子の両端電圧を示す実電圧と、モータの回転速度ωとを獲得する。dq座標系において表現される電流および電圧は、d軸電圧Vd、q軸電圧Vq、d軸電流Idおよびq軸電流Iqを含む。なお、dq座標系において、零相に対応した軸をz軸として表している。回転速度ωは、単位時間(例えば1分間)にモータのロータが回転する回転数(rpm)または単位時間(例えば1秒間)にロータが回転する回転数(rps)で表される。 In the failure diagnosis, for example, the current and voltage expressed in the dq coordinate system, the actual voltage indicating the voltage across the low-side switch element, and the rotational speed ω of the motor are acquired. The current and voltage expressed in the dq coordinate system include a d-axis voltage Vd, a q-axis voltage Vq, a d-axis current Id, and a q-axis current Iq. In the dq coordinate system, the axis corresponding to the zero phase is represented as the z axis. The rotation speed ω is represented by a rotation speed (rpm) at which the rotor of the motor rotates per unit time (for example, 1 minute) or a rotation speed (rps) at which the rotor rotates at unit time (for example, 1 second).
 図3Aから図3Cを用いて、スイッチ素子の実電圧を説明する。 The actual voltage of the switch element will be described with reference to FIGS. 3A to 3C.
 A相、B相およびC相のHブリッジBA、BBおよびBCのそれぞれに対し、第1実電圧および第2実電圧を定義する。第1実電圧は、各相のHブリッジにおいて、第1インバータ120側のレグにおける第1ローサイドスイッチ素子の両端電圧を示す。換言すると、第1実電圧は、第1インバータ120側のレグにおける第1ハイサイドスイッチ素子と第1ローサイドスイッチ素子の間のノード電位に相当する。第2実電圧は、第2インバータ130側のレグにおける第2ローサイドスイッチ素子の両端電圧を示す。換言すると、第2実電圧は、第2インバータ130側のレグにおける第2ハイサイドスイッチ素子と第2ローサイドスイッチ素子の間のノード電位に相当する。スイッチ素子の両端電圧は、スイッチ素子であるFETのソース-ドレイン間の電圧Vdsに等しい。 A first actual voltage and a second actual voltage are defined for each of the A-phase, B-phase, and C-phase H-bridges BA, BB, and BC. The first actual voltage indicates the voltage across the first low-side switch element in the leg on the first inverter 120 side in the H bridge of each phase. In other words, the first actual voltage corresponds to the node potential between the first high-side switch element and the first low-side switch element in the leg on the first inverter 120 side. The second actual voltage indicates the voltage across the second low-side switch element in the leg on the second inverter 130 side. In other words, the second actual voltage corresponds to the node potential between the second high-side switch element and the second low-side switch element in the leg on the second inverter 130 side. The voltage across the switch element is equal to the voltage Vds between the source and drain of the FET that is the switch element.
 A相のHブリッジBAに対し、第1実電圧は、図3Aに示すローサイドスイッチ素子SW_A1Lの両端電圧VA1を指し、第2実電圧は、図3Aに示すローサイドスイッチ素子SW_A2Lの両端電圧VA2を指す。B相のHブリッジBBに対し、第1実電圧は、図3Bに示すローサイドスイッチ素子SW_B1Lの両端電圧VB1を指し、第2実電圧は、図3Bに示すローサイドスイッチ素子SW_B2Lの両端電圧VB2を指す。C相のHブリッジBCに対し、第1実電圧は、図3Cに示すローサイドスイッチ素子SW_C1Lの両端電圧VC1を指し、第2実電圧は、図3Cに示すローサイドスイッチ素子SW_C2Lの両端電圧VC2を指す。 For the A-phase H bridge BA, the first actual voltage indicates the voltage VA1 across the low-side switch element SW_A1L shown in FIG. 3A, and the second actual voltage points across the voltage VA2 across the low-side switch element SW_A2L shown in FIG. 3A. . For the B-phase H-bridge BB, the first actual voltage indicates the voltage VB1 across the low-side switch element SW_B1L shown in FIG. 3B, and the second actual voltage indicates the voltage VB2 across the low-side switch element SW_B2L shown in FIG. 3B. . For the C-phase H-bridge BC, the first actual voltage indicates the voltage VC1 across the low-side switch element SW_C1L illustrated in FIG. 3C, and the second actual voltage indicates the voltage VC2 across the low-side switch element SW_C2L illustrated in FIG. 3C. .
 次に、獲得した、dq座標系の電流および電圧、第1実電圧、第2実電圧および回転速度に基づいて、故障を診断する。 Next, a failure is diagnosed based on the acquired current and voltage in the dq coordinate system, the first actual voltage, the second actual voltage, and the rotation speed.
 故障しているスイッチ素子があると判定した場合、スイッチ素子の故障を示す故障信号を生成し、後述するモータ制御ユニットに出力する。例えば、故障信号は、故障が生じるとアサートされる信号である。 If it is determined that there is a faulty switch element, a fault signal indicating a fault of the switch element is generated and output to a motor control unit described later. For example, a failure signal is a signal that is asserted when a failure occurs.
 上記の故障診断は、例えば、電流センサ150によって各相電流を測定する周期、すなわちAD変換の周期に同期して繰り返し実行される。 The above-described failure diagnosis is repeatedly executed in synchronization with, for example, a period in which each phase current is measured by the current sensor 150, that is, an AD conversion period.
 本実施形態による故障診断方法を実現するためのアルゴリズムは、例えば特定用途向け集積回路(ASIC)またはFPGAなどのハードウェアのみで実現することもできるし、マイクロコントローラおよびソフトウェアの組み合わせによっても実現することができる。本実施形態では、故障診断の動作主体を制御回路300のコントローラ340とする。 The algorithm for realizing the fault diagnosis method according to the present embodiment can be realized only by hardware such as an application specific integrated circuit (ASIC) or FPGA, or can be realized by a combination of a microcontroller and software. Can do. In the present embodiment, the operation subject of failure diagnosis is the controller 340 of the control circuit 300.
 図4は、モータ制御全般を行うためのコントローラ340の機能ブロックを例示している。図5は、A相、B相およびC相の故障診断を行うための機能ブロックを例示している。 FIG. 4 exemplifies functional blocks of the controller 340 for performing overall motor control. FIG. 5 exemplifies functional blocks for performing fault diagnosis of the A phase, the B phase, and the C phase.
 本明細書において、機能ブロック図における各ブロックは、ハードウェア単位ではなく機能ブロック単位で示される。モータ制御および故障診断に用いるソフトウェアは、例えば、各機能ブロックに対応した特定の処理を実行させるためのコンピュータプログラムを構成するモジュールであり得る。そのようなコンピュータプログラムは、例えばROM360に格納される。コントローラ340は、ROM360から命令を読み出して各処理を逐次実行することができる。 In this specification, each block in the functional block diagram is shown not in hardware units but in functional block units. The software used for motor control and failure diagnosis may be a module constituting a computer program for executing specific processing corresponding to each functional block, for example. Such a computer program is stored in the ROM 360, for example. The controller 340 can read out commands from the ROM 360 and sequentially execute each process.
 コントローラ340は、例えば、故障診断ユニット800およびモータ制御ユニット900を有する。このように、本開示の故障診断は、モータ制御(例えばベクトル制御)と好適に組み合わせることができ、モータ制御の一連の処理の中に組み込むことが可能である。 The controller 340 includes, for example, a failure diagnosis unit 800 and a motor control unit 900. As described above, the failure diagnosis of the present disclosure can be suitably combined with motor control (for example, vector control), and can be incorporated into a series of processes of motor control.
 故障診断ユニット800は、dq座標系におけるd軸電流Id、q軸電流Iq、d軸電圧Vd、q軸電圧Vq、およびモータ200の回転速度ωを獲得する。故障診断ユニット800は、さらに、第1実電圧VA1、VB1、VC1、第2実電圧VA2、VB2およびVC2を獲得する。 Failure diagnosis unit 800 obtains d-axis current Id, q-axis current Iq, d-axis voltage Vd, q-axis voltage Vq, and rotation speed ω of motor 200 in the dq coordinate system. The fault diagnosis unit 800 further obtains the first actual voltages VA1, VB1, VC1, and the second actual voltages VA2, VB2, and VC2.
 例えば、故障診断ユニット800は、Vpeakを獲得するプレ演算ユニット(不図示)を有し得る。プレ演算ユニットは、クラーク変換を用いて、電流センサ150の測定値に基づいて取得された三相電流Ia、IbおよびIcを、αβ固定座標系における、α軸上の電流Iαおよびβ軸上の電流Iβに変換する。プレ演算ユニットは、パーク変換(dq座標変換)を用いて、電流Iα、Iβを、dq座標系におけるd軸電流Idおよびq軸電流Iqに変換する。プレ演算ユニットは、電流IdおよびIqに基づいてd軸電圧Vdおよびq軸電圧Vqを取得し、取得したVd、Vqから下記式(1)に基づいて電圧ピーク値Vpeakを算出する。または、プレ演算ユニットは、ベクトル制御を行うモータ制御ユニット900から、Vpeakの算出に必要なVd、Vqを受け取ることも可能である。例えば、プレ演算ユニットは、電流センサ150によって各相電流を測定する周期に同期してVpeakを獲得する。
  Vpeak=(2/3)1/2(Vd+Vq1/2   式(1)
For example, the failure diagnosis unit 800 may include a pre-computation unit (not shown) that acquires Vpeak. The pre-computation unit uses the Clark transformation to convert the three-phase currents Ia, Ib and Ic obtained based on the measured value of the current sensor 150 into the currents I α and β on the α axis in the αβ fixed coordinate system. To a current I β of The pre-computation unit converts the currents I α and I β into a d-axis current Id and a q-axis current Iq in the dq coordinate system by using park conversion (dq coordinate conversion). The pre-calculation unit acquires the d-axis voltage Vd and the q-axis voltage Vq based on the currents Id and Iq, and calculates the voltage peak value Vpeak from the acquired Vd and Vq based on the following formula (1). Alternatively, the pre-computation unit can also receive Vd and Vq necessary for calculating Vpeak from the motor control unit 900 that performs vector control. For example, the pre-computation unit acquires Vpeak in synchronization with the period in which each phase current is measured by the current sensor 150.
Vpeak = (2/3) 1/2 (Vd 2 + Vq 2 ) 1/2 formula (1)
 故障診断ユニット800は、ルックアップテーブル940(図16)を参照して、電流Id、Iqおよび回転速度ωに基づいて飽和電圧Vsatを決定する。 Failure diagnosis unit 800 refers to look-up table 940 (FIG. 16) and determines saturation voltage Vsat based on currents Id and Iq and rotation speed ω.
 図16は、回転速度ωおよび電流振幅値から飽和電圧Vsatを決定するルックアップテーブル(LUT)940を模式的に示している。LUT940は、d軸電流およびq軸電流に基づいて決定される電流振幅値(Id+Iq1/2およびモータ200の回転速度ωの入力と、飽和電圧Vsatとの関係を関連付ける。 FIG. 16 schematically shows a look-up table (LUT) 940 that determines the saturation voltage Vsat from the rotation speed ω and the current amplitude value. The LUT 940 associates the relationship between the saturation voltage Vsat and the input of the current amplitude value (Id 2 + Iq 2 ) 1/2 determined based on the d-axis current and the q-axis current and the rotational speed ω of the motor 200.
 回転速度ωは、例えば角度センサ320からの回転信号に基づいて算出される。または、回転速度ωは、例えば公知のセンサレス制御手法を用いて推定することができる。各スイッチ素子の実電圧は、例えば駆動回路(プリドライバ)350によって測定される。 The rotation speed ω is calculated based on, for example, a rotation signal from the angle sensor 320. Alternatively, the rotational speed ω can be estimated using, for example, a known sensorless control method. The actual voltage of each switch element is measured by a drive circuit (predriver) 350, for example.
 表1は、故障診断に用いることが可能なLUT940の構成を例示している。モータ制御では、一般的にIdはゼロとして扱われる。そのため、電流振幅値はIqに等しくなる。表1には、Iq(A)を記載している。飽和電圧Vsatは、獲得された電流振幅値Iqおよび回転速度ωから決定される。あるいは、飽和電圧Vsatとして、例えば、駆動前に予め設定した値を用いてもよい。例えば、飽和電圧Vsatとして、システムに依存する一定の値(例えば0.1V程度)を用いてもよい。 Table 1 illustrates the configuration of the LUT 940 that can be used for failure diagnosis. In motor control, Id is generally treated as zero. Therefore, the current amplitude value is equal to Iq. Table 1 lists Iq (A). The saturation voltage Vsat is determined from the acquired current amplitude value Iq and the rotational speed ω. Alternatively, for example, a value set in advance before driving may be used as the saturation voltage Vsat. For example, a constant value (for example, about 0.1 V) depending on the system may be used as the saturation voltage Vsat.
Figure JPOXMLDOC01-appb-T000001
Figure JPOXMLDOC01-appb-T000001
 故障診断ユニット800は、上述した実電圧、電圧ピーク値Vpeak、飽和電圧Vsatに基づいてスイッチ素子の故障の有無を診断する。 The failure diagnosis unit 800 diagnoses the presence or absence of a switch element failure based on the above-described actual voltage, voltage peak value Vpeak, and saturation voltage Vsat.
 故障診断ユニット800は、故障したスイッチ素子を示す故障信号を診断結果に基づいて生成し、モータ制御ユニット900に出力する。 The failure diagnosis unit 800 generates a failure signal indicating the failed switch element based on the diagnosis result, and outputs the failure signal to the motor control unit 900.
 モータ制御ユニット900は、例えばベクトル制御を用いて、第1および第2インバータ120、130のスイッチ素子のスイッチング動作の全般を制御するPWM信号を生成する。モータ制御ユニット900は、PWM信号を駆動回路350に出力する。また、モータ制御ユニット900は、例えば故障信号がアサートされると、モータ制御を三相通電制御から二相通電制御に切替えることが可能である。 The motor control unit 900 generates a PWM signal that controls the overall switching operation of the switch elements of the first and second inverters 120 and 130 using, for example, vector control. The motor control unit 900 outputs a PWM signal to the drive circuit 350. For example, when a failure signal is asserted, the motor control unit 900 can switch the motor control from the three-phase energization control to the two-phase energization control.
 本明細書において、説明の便宜上、各機能ブロックをユニットと表記する場合がある。当然に、各機能ブロックをハードウェアまたはソフトウェアに限定解釈する意図で、これらの表記を用いてはいない。 In this specification, for convenience of explanation, each functional block may be expressed as a unit. Naturally, these notations are not used with the intention of restricting each functional block to hardware or software.
 各機能ブロックはソフトウェアとしてコントローラ340に実装される場合、そのソフトウェアの実行主体は、例えばコントローラ340のコアであり得る。上述したように、コントローラ340は、FPGAによって実現され得る。その場合、全てまたは一部の機能ブロックは、ハードウェアで実現され得る。 When each functional block is implemented as software in the controller 340, the execution subject of the software may be the core of the controller 340, for example. As described above, the controller 340 can be realized by an FPGA. In that case, all or some of the functional blocks may be realized by hardware.
 複数のFPGAを用いて処理を分散させることにより、特定のコンピュータの演算負荷を分散できる。その場合、図4から図16に示される機能ブロックの全てまたは一部は、複数のFPGAに分散して実装され得る。複数のFPGAは、例えば車載のコントロールエリアネットワーク(CAN)によって互いに通信可能に接続され、データの送受信を行うことができる。 演算 By distributing processing using multiple FPGAs, the computing load of a specific computer can be distributed. In that case, all or part of the functional blocks shown in FIGS. 4 to 16 may be distributed and implemented in a plurality of FPGAs. The plurality of FPGAs can be connected to each other by, for example, an in-vehicle control area network (CAN), and can transmit and receive data.
 (相の故障診断)
 故障診断ユニット800は、図5に示すA相のHブリッジBAの故障を診断するための故障診断ユニット800A、B相のHブリッジBBの故障を診断するための故障診断ユニット800B、C相のHブリッジBCの故障を診断するための故障診断ユニット800Cを有する。
(Phase failure diagnosis)
The failure diagnosis unit 800 includes a failure diagnosis unit 800A for diagnosing a failure of the A-phase H bridge BA, a failure diagnosis unit 800B for diagnosing a failure of the B-phase H bridge BB, and a C-phase H bridge shown in FIG. A failure diagnosis unit 800C for diagnosing a failure of the bridge BC is included.
 図6は、A相のHブリッジBAの故障を診断するための故障診断ユニット800Aを例示するブロック図である。図7は、B相のHブリッジBBの故障を診断するための故障診断ユニット800Bを例示するブロック図である。図8は、C相のHブリッジBCの故障を診断するための故障診断ユニット800Cを例示するブロック図である。 FIG. 6 is a block diagram illustrating a failure diagnosis unit 800A for diagnosing a failure of the A-phase H bridge BA. FIG. 7 is a block diagram illustrating a failure diagnosis unit 800B for diagnosing a failure of the B-phase H-bridge BB. FIG. 8 is a block diagram illustrating a failure diagnosis unit 800C for diagnosing a failure of the C-phase H-bridge BC.
 故障診断ユニット800A、BおよびCは、実質的に同じ機能ブロックから構成される。ただし、第1実電圧および第2実電圧の入力信号は各ブロック間で異なる。以下、図6を参照しながら、A相のHブリッジBAの故障診断を例に、Hブリッジの故障診断を詳細に説明する。 Failure diagnosis units 800A, B, and C are constituted by substantially the same functional blocks. However, the input signals of the first actual voltage and the second actual voltage differ between the blocks. Hereinafter, the fault diagnosis of the H bridge will be described in detail with reference to FIG. 6, taking the fault diagnosis of the A-phase H bridge BA as an example.
 故障診断ユニット800Aは、乗算器810、811、加算器812、813_1、813_2、信号生成ユニット814_1、814_2、乗算器820、821、加算器822、823_1、823_2、信号生成ユニット824_1、824_2、論理回路OR830を有する。 The fault diagnosis unit 800A includes multipliers 810 and 811, adders 812, 813_1 and 813_2, signal generation units 814_1 and 814_2, multipliers 820 and 821, adders 822, 823_1 and 823_2, signal generation units 824_1 and 824_2, and a logic circuit. OR830.
 乗算器810、811、加算器812、813_1、813_2、信号生成ユニット814_1および814_2は、ローサイド故障診断ユニットを構成する。乗算器820、821、加算器822、823_1、823_2、信号生成ユニット824_1および824_2は、ハイサイド故障診断ユニットを構成する。 Multipliers 810 and 811, adders 812, 813_1 and 813_2, and signal generation units 814_1 and 814_2 constitute a low-side fault diagnosis unit. The multipliers 820 and 821, the adders 822, 823_1 and 823_2, and the signal generation units 824_1 and 824_2 constitute a high side failure diagnosis unit.
 ローサイド故障診断ユニットは、ローサイドスイッチ素子SW_A1L、SW_A2Lのオープン故障を特定する。ハイサイド故障診断ユニットは、ハイサイドスイッチ素子SW_A1H、SW_A2Hのオープン故障を特定する。 The low side failure diagnosis unit specifies an open failure of the low side switch elements SW_A1L and SW_A2L. The high side failure diagnosis unit specifies an open failure of the high side switch elements SW_A1H and SW_A2H.
 まず、ハイサイド故障診断ユニットを説明する。 First, the high-side fault diagnosis unit will be explained.
 ハイサイド故障診断ユニットは、電圧ピーク値Vpeak、飽和電圧Vsatおよび第1実電圧VA1に基づいてハイサイドスイッチ素子SW_A2Hのオープン故障を診断する第1故障診断と、電圧ピーク値Vpeak、飽和電圧Vsatおよび第2実電圧VA2に基づいてハイサイドスイッチ素子SW_A1Hのオープン故障を診断する第2故障診断とを行う。 The high side failure diagnosis unit includes a first failure diagnosis for diagnosing an open failure of the high side switch element SW_A2H based on the voltage peak value Vpeak, the saturation voltage Vsat and the first actual voltage VA1, and the voltage peak value Vpeak, the saturation voltage Vsat and Based on the second actual voltage VA2, the second failure diagnosis for diagnosing an open failure of the high-side switch element SW_A1H is performed.
 乗算器820は電圧ピーク値Vpeakに定数「1/2」を乗算する。電圧ピーク値Vpeakは、上述の式(1)に基づいて算出される。乗算器821は飽和電圧Vsatに定数「1」を乗算する。加算器822は乗算器820の出力Vpeak/2に乗算器821の出力Vsatを加算する。 Multiplier 820 multiplies voltage peak value Vpeak by a constant “1/2”. The voltage peak value Vpeak is calculated based on the above equation (1). The multiplier 821 multiplies the saturation voltage Vsat by a constant “1”. The adder 822 adds the output Vsat of the multiplier 821 to the output Vpeak / 2 of the multiplier 820.
 加算器823_1は、第1故障診断において、加算器822からの出力(Vpeak/2)+Vsatに第1実電圧VA1を加算することにより、第1故障診断電圧VA2H_FDを算出する(式(2))。加算器823_2は、第2故障診断において、加算器822からの出力(Vpeak/2)+Vsatに第2実電圧VA2を加算することにより、第2故障診断電圧VA1H_FDを算出する(式(3))。第1実電圧VA1および第2実電圧VA2は、例えば駆動回路(プリドライバ)350によって測定される。
  VA2H_FD=VA1+〔(Vpeak/2)+Vsat〕   式(2)
  VA1H_FD=VA2+〔(Vpeak/2)+Vsat〕   式(3)
In the first failure diagnosis, the adder 823_1 calculates the first failure diagnosis voltage VA2H_FD by adding the first actual voltage VA1 to the output (Vpeak / 2) + Vsat from the adder 822 (formula (2)). . In the second failure diagnosis, the adder 823_2 calculates the second failure diagnosis voltage VA1H_FD by adding the second actual voltage VA2 to the output (Vpeak / 2) + Vsat from the adder 822 (formula (3)). . The first actual voltage VA1 and the second actual voltage VA2 are measured by a drive circuit (predriver) 350, for example.
VA2H_FD = VA1 + [(Vpeak / 2) + Vsat] Formula (2)
VA1H_FD = VA2 + [(Vpeak / 2) + Vsat] Formula (3)
 第1故障診断において、信号生成ユニット824_1は、第1故障診断電圧VA2H_FDに基づいてハイサイドスイッチ素子SW_A2Hのオープン故障を診断する。具体的に説明すると、信号生成ユニット824_1は、第1故障診断電圧VA2H_FDがゼロ未満(VA2H_FD<0)である場合、ハイサイドスイッチ素子SW_A2Hのオープン故障を特定する。信号生成ユニット824_1は、第1故障診断電圧VA2H_FDがゼロ以上である場合(VA2H_FD≧0)、ハイサイドスイッチ素子SW_A2Hにオープン故障は生じていないと判定する。 In the first failure diagnosis, the signal generation unit 824_1 diagnoses an open failure of the high-side switch element SW_A2H based on the first failure diagnosis voltage VA2H_FD. Specifically, the signal generation unit 824_1 identifies an open failure of the high side switch element SW_A2H when the first failure diagnosis voltage VA2H_FD is less than zero (VA2H_FD <0). When the first failure diagnosis voltage VA2H_FD is greater than or equal to zero (VA2H_FD ≧ 0), the signal generation unit 824_1 determines that no open failure has occurred in the high-side switch element SW_A2H.
 信号生成ユニット824_1は第1故障診断における診断結果に基づいてハイサイドスイッチ素子SW_A2Hのオープン故障を示す第1故障信号A2H_FDを生成する。例えば第1故障信号A2H_FDを1ビットの信号に割り当てることができる。ハイサイドスイッチ素子SW_A2Hにオープン故障が生じていないとき、第1故障信号A2H_FDのレベルはLowである。信号生成ユニット824_1はハイサイドスイッチ素子SW_A2Hのオープン故障を特定すると、第1故障信号A2H_FDをアサートする。 The signal generation unit 824_1 generates a first failure signal A2H_FD indicating an open failure of the high side switch element SW_A2H based on the diagnosis result in the first failure diagnosis. For example, the first failure signal A2H_FD can be assigned to a 1-bit signal. When no open failure has occurred in the high-side switch element SW_A2H, the level of the first failure signal A2H_FD is Low. When the signal generation unit 824_1 identifies an open failure of the high-side switch element SW_A2H, the signal generation unit 824_1 asserts the first failure signal A2H_FD.
 例えば、ハイサイドスイッチ素子SW_A2Hがオープン故障すると、そのスイッチ素子に電流は流れない。その結果、モータ200の逆起電力の影響を受けて、第1実電圧の下側ピーク値は下がる。ハイサイドスイッチ素子SW_A2Hにオープン故障は生じていないとき、VA1≒-〔(Vpeak/2)+Vsat〕となり、第1実電圧VA1の大きさは、|(Vpeak/2)+Vsat|に等しくなる。これに対し、ハイサイドスイッチ素子SW_A2Hにオープン故障が生じると、この均衡が崩れる。VA1は下がるために、第1故障診断電圧VA2H_FD<0となる。本開示は、この現象を利用してスイッチ素子のオープン故障を特定する。 For example, when the high side switch element SW_A2H has an open failure, no current flows through the switch element. As a result, under the influence of the back electromotive force of the motor 200, the lower peak value of the first actual voltage decreases. When no open failure occurs in the high-side switch element SW_A2H, VA1≈ − [(Vpeak / 2) + Vsat], and the magnitude of the first actual voltage VA1 is equal to | (Vpeak / 2) + Vsat |. On the other hand, when an open failure occurs in the high-side switch element SW_A2H, this balance is lost. Since VA1 decreases, the first failure diagnosis voltage VA2H_FD <0. The present disclosure uses this phenomenon to identify an open failure of the switch element.
 第1故障診断と同様に第2故障診断において、信号生成ユニット824_2は、第2故障診断電圧VA1H_FDに基づいてハイサイドスイッチ素子SW_A1Hのオープン故障を診断する。具体的に説明すると、信号生成ユニット824_2は、第2故障診断電圧VA1H_FDがゼロ未満(VA1H_FD<0)である場合、ハイサイドスイッチ素子SW_A1Hのオープン故障を特定する。信号生成ユニット824_2は、第2故障診断電圧VA1H_FDがゼロ以上である場合(VA1H_FD≧0)、ハイサイドスイッチ素子SW_A1Hにオープン故障は生じていないと判定する。 Similarly to the first failure diagnosis, in the second failure diagnosis, the signal generation unit 824_2 diagnoses an open failure of the high-side switch element SW_A1H based on the second failure diagnosis voltage VA1H_FD. Specifically, the signal generation unit 824_2 identifies an open failure of the high side switch element SW_A1H when the second failure diagnosis voltage VA1H_FD is less than zero (VA1H_FD <0). When the second failure diagnosis voltage VA1H_FD is zero or more (VA1H_FD ≧ 0), the signal generation unit 824_2 determines that no open failure has occurred in the high-side switch element SW_A1H.
 信号生成ユニット824_2は第2故障診断における診断結果に基づいてハイサイドスイッチ素子SW_A1Hのオープン故障を示す第2故障信号A1H_FDを生成する。例えば第2故障信号A1H_FDを1ビットの信号に割り当てることができる。ハイサイドスイッチ素子SW_A1Hにオープン故障は生じていないとき、第2故障信号A1H_FDのレベルはLowである。信号生成ユニット824_2はハイサイドスイッチ素子SW_A1Hのオープン故障を特定すると、第2故障信号A1H_FDをアサートする。 The signal generation unit 824_2 generates a second failure signal A1H_FD indicating an open failure of the high-side switch element SW_A1H based on the diagnosis result in the second failure diagnosis. For example, the second failure signal A1H_FD can be assigned to a 1-bit signal. When no open failure has occurred in the high-side switch element SW_A1H, the level of the second failure signal A1H_FD is Low. When the signal generation unit 824_2 specifies the open failure of the high-side switch element SW_A1H, the signal generation unit 824_2 asserts the second failure signal A1H_FD.
 次に、ローサイド故障診断ユニットを説明する。 Next, the low-side fault diagnosis unit will be described.
 ローサイド故障診断ユニットは、電圧ピーク値Vpeak、飽和電圧Vsatおよび第1実電圧VA1に基づいてローサイドスイッチ素子SW_A2Lのオープン故障を診断する第3故障診断と、電圧ピーク値Vpeak、飽和電圧Vsatおよび第2実電圧VA2に基づいてローサイドスイッチ素子SW_A1Lのオープン故障を診断する第4故障診断とを行う。 The low-side failure diagnosis unit performs third failure diagnosis for diagnosing an open failure of the low-side switch element SW_A2L based on the voltage peak value Vpeak, the saturation voltage Vsat, and the first actual voltage VA1, and the voltage peak value Vpeak, saturation voltage Vsat, and second Based on the actual voltage VA2, a fourth failure diagnosis for diagnosing an open failure of the low-side switch element SW_A1L is performed.
 乗算器810は、電圧ピーク値Vpeakに定数「-1/2」を乗算する。乗算器811は、飽和電圧Vsatに定数「-1」を乗算する。ローサイド側のスイッチ素子とハイサイド側のスイッチ素子の間で流れる電流などが逆になることを考慮し、ローサイド故障診断ユニットでは、ハイサイド故障診断ユニットの乗算器820、821とは逆の符号の定数が用いられる。 Multiplier 810 multiplies voltage peak value Vpeak by a constant “−1/2”. The multiplier 811 multiplies the saturation voltage Vsat by a constant “−1”. Considering that the currents flowing between the low-side switch element and the high-side switch element are reversed, the low-side failure diagnosis unit has a sign opposite to that of the multipliers 820 and 821 of the high-side failure diagnosis unit. A constant is used.
 加算器812は、乗算器810の出力(-Vpeak/2)に乗算器811の出力(-Vsat)を加算する。 The adder 812 adds the output (−Vsat) of the multiplier 811 to the output (−Vpeak / 2) of the multiplier 810.
 加算器813_1は、第3故障診断において、加算器812からの出力:-〔(Vpeak/2)+Vsat〕に第1実電圧VA1を加算することにより、第3故障診断電圧VA2L_FDを算出する(式(4))。加算器813_2は、第4故障診断において、加算器812からの出力:-〔(Vpeak/2)+Vsat〕に第2実電圧VA2を加算することにより、第4故障診断電圧VA1L_FDを算出する(式(5))。
 VA2L_FD=VA1-〔(Vpeak/2)+Vsat〕 式(4)
 VA1L_FD=VA2-〔(Vpeak/2)+Vsat〕 式(5)
In the third failure diagnosis, the adder 813_1 calculates the third failure diagnosis voltage VA2L_FD by adding the first actual voltage VA1 to the output from the adder 812:-[(Vpeak / 2) + Vsat] (formula (4)). In the fourth fault diagnosis, the adder 813_2 calculates the fourth fault diagnosis voltage VA1L_FD by adding the second actual voltage VA2 to the output from the adder 812:-[(Vpeak / 2) + Vsat] (formula (5)).
VA2L_FD = VA1-[(Vpeak / 2) + Vsat] Formula (4)
VA1L_FD = VA2-[(Vpeak / 2) + Vsat] Formula (5)
 第3故障診断において、信号生成ユニット814_1は、第3故障診断電圧VA2L_FDに基づいてローサイドスイッチ素子SW_A2Lのオープン故障を診断する。具体的に説明すると、信号生成ユニット814_1は、第3故障診断電圧VA2L_FDがゼロよりも大きい場合(VA2L_FD>0)、ローサイドスイッチ素子SW_A2Lのオープン故障を特定する。信号生成ユニット814_1は、第3故障診断電圧VA2L_FDがゼロ以下である場合(VA2L_FD≦0)、ローサイドスイッチ素子SW_A2Lにオープン故障は生じていないと判定する。 In the third failure diagnosis, the signal generation unit 814_1 diagnoses an open failure of the low-side switch element SW_A2L based on the third failure diagnosis voltage VA2L_FD. Specifically, the signal generation unit 814_1 identifies an open failure of the low-side switch element SW_A2L when the third failure diagnosis voltage VA2L_FD is greater than zero (VA2L_FD> 0). The signal generation unit 814_1 determines that an open failure has not occurred in the low-side switch element SW_A2L when the third failure diagnosis voltage VA2L_FD is equal to or less than zero (VA2L_FD ≦ 0).
 信号生成ユニット814_1は第3故障診断における診断結果に基づいてローサイドスイッチ素子SW_A2Lのオープン故障を示す第3故障信号A2L_FDを生成する。例えば第3故障信号A2L_FDを1ビットの信号に割り当てることができる。ローサイドスイッチ素子SW_A2Lにオープン故障は生じていないとき、第3故障信号A2L_FDのレベルはLowである。信号生成ユニット814_1はローサイドスイッチ素子SW_A2Lのオープン故障を特定すると、第3故障信号A2L_FDをアサートする。 The signal generation unit 814_1 generates a third failure signal A2L_FD indicating an open failure of the low-side switch element SW_A2L based on the diagnosis result in the third failure diagnosis. For example, the third failure signal A2L_FD can be assigned to a 1-bit signal. When no open failure has occurred in the low-side switch element SW_A2L, the level of the third failure signal A2L_FD is Low. When the signal generation unit 814_1 specifies the open failure of the low-side switch element SW_A2L, the signal generation unit 814_1 asserts the third failure signal A2L_FD.
 例えば、ローサイドスイッチ素子SW_A2Lがオープン故障すると、そのスイッチ素子に電流は流れない。その結果、モータ200の逆起電力の影響を受けて、第1実電圧の上側ピーク値は上がる。ローサイドスイッチ素子SW_A2Lにオープン故障は生じていないとき、VA1≒〔(Vpeak/2)+Vsat〕となり、第1実電圧VA1の大きさは、|(Vpeak/2)+Vsat|に等しくなる。これに対し、ローサイドスイッチ素子SW_A2Lにオープン故障が生じると、この均衡が崩れる。VA1は上がるために、第3故障診断電圧VA2L_FD>0となる。 For example, when the low-side switch element SW_A2L has an open failure, no current flows through the switch element. As a result, the upper peak value of the first actual voltage increases under the influence of the back electromotive force of the motor 200. When an open failure has not occurred in the low-side switch element SW_A2L, VA1≈ [(Vpeak / 2) + Vsat], and the magnitude of the first actual voltage VA1 is equal to | (Vpeak / 2) + Vsat |. On the other hand, when an open failure occurs in the low-side switch element SW_A2L, this balance is lost. Since VA1 increases, the third failure diagnosis voltage VA2L_FD> 0.
 第3故障診断と同様に第4故障診断において、信号生成ユニット814_2は、第4故障診断電圧VA1L_FDに基づいてローサイドスイッチ素子SW_A1Lのオープン故障を診断する。具体的に説明すると、信号生成ユニット814_2は、第4故障診断電圧VA1L_FDがゼロよりも大きい場合(VA1L_FD>0)、ローサイドスイッチ素子SW_A1Lのオープン故障を特定する。信号生成ユニット814_2は、第4故障診断電圧VA1L_FDがゼロ以下である場合(VA1L_FD≦0)、ローサイドスイッチ素子SW_A1Lにオープン故障は生じていないと判定する。 Similarly to the third failure diagnosis, in the fourth failure diagnosis, the signal generation unit 814_2 diagnoses an open failure of the low-side switch element SW_A1L based on the fourth failure diagnosis voltage VA1L_FD. Specifically, the signal generation unit 814_2 specifies an open failure of the low-side switch element SW_A1L when the fourth failure diagnosis voltage VA1L_FD is greater than zero (VA1L_FD> 0). When the fourth failure diagnosis voltage VA1L_FD is equal to or lower than zero (VA1L_FD ≦ 0), the signal generation unit 814_2 determines that an open failure has not occurred in the low-side switch element SW_A1L.
 信号生成ユニット814_2は、第4故障診断における診断結果に基づいてローサイドスイッチ素子SW_A1Lのオープン故障を示す第4故障信号A1L_FDを生成する。例えば、第4故障信号A1L_FDを1ビットの信号に割り当てることができる。ローサイドスイッチ素子SW_A1Lにオープン故障は生じていないとき、第4故障信号A1L_FDのレベルはLowである。信号生成ユニット814_2は、ローサイドスイッチ素子SW_A1Lのオープン故障を特定すると、第4故障信号A1L_FDをアサートする。 The signal generation unit 814_2 generates a fourth failure signal A1L_FD indicating an open failure of the low-side switch element SW_A1L based on the diagnosis result in the fourth failure diagnosis. For example, the fourth failure signal A1L_FD can be assigned to a 1-bit signal. When no open failure has occurred in the low-side switch element SW_A1L, the level of the fourth failure signal A1L_FD is Low. When the signal generation unit 814_2 specifies the open failure of the low-side switch element SW_A1L, the signal generation unit 814_2 asserts the fourth failure signal A1L_FD.
 このように、故障診断ユニット800Aは、ハイサイドスイッチ素子SW_A1H、SW_A2H、ローサイドスイッチ素子SW_A1LおよびSW_A2Lの中でオープン故障したスイッチ素子を特定することができる。 As described above, the failure diagnosis unit 800A can identify a switch element that has an open failure among the high-side switch elements SW_A1H, SW_A2H, the low-side switch elements SW_A1L, and SW_A2L.
 論理回路OR830は、第1から第4故障信号A2H_FD、A1H_FD、A2L_FDおよびA1L_FDの論理和をとる。論理回路OR830は、A相のHブリッジBAの故障の有無を示す故障信号A_FDを出力する。例えば、第1から第4故障信号A2H_FD、A1H_FD、A2L_FDおよびA1L_FDの全てが正常を示す“0”である場合、論理回路OR830は、正常を示す“0”を故障信号A_FDとして出力する。第1から第4故障信号A2H_FD、A1H_FD、A2L_FDおよびA1L_FDの少なくとも1つが異常を示す“1”である場合、論理回路OR830は、故障を示す“1”を故障信号A_FDとして出力する。 The logic circuit OR830 takes a logical sum of the first to fourth failure signals A2H_FD, A1H_FD, A2L_FD, and A1L_FD. The logic circuit OR 830 outputs a failure signal A_FD indicating whether or not the A-phase H bridge BA has failed. For example, when all of the first to fourth failure signals A2H_FD, A1H_FD, A2L_FD, and A1L_FD are “0” indicating normality, the logic circuit OR830 outputs “0” indicating normality as the failure signal A_FD. When at least one of the first to fourth failure signals A2H_FD, A1H_FD, A2L_FD, and A1L_FD is “1” indicating abnormality, the logic circuit OR 830 outputs “1” indicating failure as the failure signal A_FD.
 故障診断ユニット800Aと同様に、故障診断ユニット800Bは、ハイサイドスイッチ素子SW_B1H、SW_B2H、ローサイドスイッチ素子SW_B1LおよびSW_B2Lの少なくとも1つがオープン故障していることを検出すると、B相のHブリッジBBの故障を示す“1”を故障信号B_FDとして出力する。オープン故障を検出しない場合は、B相のHブリッジBBは正常であることを示す“0”を故障信号B_FDとして出力する。 Similar to failure diagnosis unit 800A, failure diagnosis unit 800B detects that an open failure has occurred in at least one of high-side switch elements SW_B1H, SW_B2H, low-side switch elements SW_B1L, and SW_B2L. Is output as a failure signal B_FD. When no open failure is detected, “0” indicating that the B-phase H-bridge BB is normal is output as the failure signal B_FD.
 故障診断ユニット800Cは、ハイサイドスイッチ素子SW_C1H、SW_C2H、ローサイドスイッチ素子SW_C1LおよびSW_C2Lの少なくとも1つがオープン故障していることを検出すると、C相のHブリッジBCの故障を示す“1”を故障信号C_FDとして出力する。オープン故障を検出しない場合は、C相のHブリッジBCは正常であることを示す“0”を故障信号C_FDとして出力する。 When the failure diagnosis unit 800C detects that at least one of the high-side switch elements SW_C1H, SW_C2H, the low-side switch elements SW_C1L and SW_C2L has an open failure, the failure diagnosis unit 800C outputs “1” indicating a failure of the C-phase H-bridge BC as a failure signal. Output as C_FD. When an open failure is not detected, “0” indicating that the C-phase H-bridge BC is normal is output as a failure signal C_FD.
 (インバータの故障診断)
 次に、第1インバータ120および第2インバータ130の故障診断を説明する。
(Inverter failure diagnosis)
Next, failure diagnosis of the first inverter 120 and the second inverter 130 will be described.
 故障診断ユニット800は、図9に示す第1インバータ120の故障の有無を診断する故障診断ユニット810A、第2インバータ130の故障の有無を診断する故障診断ユニット810Bを有する。図10は、故障診断ユニット810Aの機能ブロックを示している。図11は、故障診断ユニット810Bの機能ブロックを示している。故障診断ユニット810Aおよび810Bは、実質的に同じ機能ブロックを有するが、入力される実電圧が互いに異なる。 The failure diagnosis unit 800 includes a failure diagnosis unit 810A for diagnosing the presence or absence of a failure in the first inverter 120 and a failure diagnosis unit 810B for diagnosing the presence or absence of a failure in the second inverter 130 shown in FIG. FIG. 10 shows functional blocks of the failure diagnosis unit 810A. FIG. 11 shows functional blocks of the failure diagnosis unit 810B. Fault diagnosis units 810A and 810B have substantially the same functional blocks, but input actual voltages are different from each other.
 故障診断ユニット810Aおよび810Bのそれぞれは、絶対値演算器831、834、837と、乗算器832、833、835、836、838、839と、加算器841、842、843と、比較器844、845、846と、論理回路OR847とを有する。 Each of failure diagnosis units 810A and 810B includes absolute value calculators 831, 834, 837, multipliers 832, 833, 835, 836, 838, 839, adders 841, 842, 843, and comparators 844, 845. , 846 and a logic circuit OR847.
 まず、第1インバータ120の故障の有無の診断処理を説明する。 First, diagnostic processing for the presence or absence of a failure in the first inverter 120 will be described.
 故障診断ユニット810Aの絶対値演算器831は実電圧VA2の絶対値を演算する。乗算器832は電圧ピーク値Vpeakに定数「-1/2」を乗算する。乗算器833は、飽和電圧Vsatに定数「-1」を乗算する。加算器841は絶対値演算器831、乗算器832および833の出力値を加算して、下記式(6)で表される故障診断電圧VA2_FDを算出する。
  VA2_FD=|VA2|-〔(Vpeak/2)+Vsat〕   式(6)
The absolute value calculator 831 of the failure diagnosis unit 810A calculates the absolute value of the actual voltage VA2. The multiplier 832 multiplies the voltage peak value Vpeak by a constant “−1/2”. The multiplier 833 multiplies the saturation voltage Vsat by a constant “−1”. The adder 841 adds the output values of the absolute value calculator 831 and the multipliers 832 and 833 to calculate the failure diagnosis voltage VA2_FD represented by the following formula (6).
VA2_FD = | VA2 | − [(Vpeak / 2) + Vsat] Equation (6)
 比較器844は、“VA2_FD”と“ゼロ”とを比較する。比較器844は、VA2_FDがゼロ以下である(VA2_FD≦0)場合、実電圧VA2は正常であることを示す“0”を論理回路OR847に出力する。比較器844はVA2_FDがゼロより大きい(VA2_FD>0)場合、実電圧VA2は異常であることを示す“1”を論理回路OR847に出力する。 The comparator 844 compares “VA2_FD” with “zero”. When VA2_FD is equal to or less than zero (VA2_FD ≦ 0), the comparator 844 outputs “0” indicating that the actual voltage VA2 is normal to the logic circuit OR847. When VA2_FD is larger than zero (VA2_FD> 0), the comparator 844 outputs “1” indicating that the actual voltage VA2 is abnormal to the logic circuit OR847.
 同様に、故障診断ユニット810Aの絶対値演算器834は、実電圧VB2の絶対値を演算する。乗算器835は、電圧ピーク値Vpeakに定数「-1/2」を乗算する。乗算器836は、飽和電圧Vsatに定数「-1」を乗算する。加算器842は、絶対値演算器834、乗算器835および836の出力値を加算して、下記式(7)で表される故障診断電圧VB2_FDを算出する。
  VB2_FD=|VB2|-〔(Vpeak/2)+Vsat〕   式(7)
Similarly, the absolute value calculator 834 of the failure diagnosis unit 810A calculates the absolute value of the actual voltage VB2. The multiplier 835 multiplies the voltage peak value Vpeak by a constant “−1/2”. The multiplier 836 multiplies the saturation voltage Vsat by a constant “−1”. The adder 842 adds the output values of the absolute value calculator 834 and the multipliers 835 and 836 to calculate a failure diagnosis voltage VB2_FD represented by the following formula (7).
VB2_FD = | VB2 | − [(Vpeak / 2) + Vsat] Equation (7)
 比較器845は、“VB2_FD”と“ゼロ”とを比較する。比較器845は、VB2_FDがゼロ以下である場合、実電圧VB2は正常であることを示す“0”を論理回路OR847に出力する。比較器845は、VB2_FDがゼロより大きい場合、実電圧VB2は異常であることを示す“1”を論理回路OR847に出力する。 The comparator 845 compares “VB2_FD” with “zero”. When VB2_FD is equal to or smaller than zero, the comparator 845 outputs “0” indicating that the actual voltage VB2 is normal to the logic circuit OR847. When VB2_FD is greater than zero, the comparator 845 outputs “1” indicating that the actual voltage VB2 is abnormal to the logic circuit OR847.
 故障診断ユニット810Aの絶対値演算器837は実電圧VC2の絶対値を演算する。乗算器838は電圧ピーク値Vpeakに定数「-1/2」を乗算する。乗算器839は飽和電圧Vsatに定数「-1」を乗算する。加算器843は、絶対値演算器837、乗算器838および839の出力値を加算して、下記式(8)で表される故障診断電圧VC2_FDを算出する。
  VC2_FD=|VC2|-〔(Vpeak/2)+Vsat〕   式(8)
The absolute value calculator 837 of the failure diagnosis unit 810A calculates the absolute value of the actual voltage VC2. The multiplier 838 multiplies the voltage peak value Vpeak by a constant “−1/2”. The multiplier 839 multiplies the saturation voltage Vsat by a constant “−1”. The adder 843 adds the output values of the absolute value calculator 837 and the multipliers 838 and 839 to calculate a failure diagnosis voltage VC2_FD represented by the following formula (8).
VC2_FD = | VC2 | − [(Vpeak / 2) + Vsat] Equation (8)
 比較器846は、“VC2_FD”と“ゼロ”とを比較する。比較器846は、VC2_FDがゼロ以下である場合、実電圧VC2は正常であることを示す“0”を論理回路OR847に出力する。比較器846は、VC2_FDがゼロより大きい場合、実電圧VC2は異常であることを示す“1”を論理回路OR847に出力する。 The comparator 846 compares “VC2_FD” with “zero”. When VC2_FD is equal to or smaller than zero, the comparator 846 outputs “0” indicating that the actual voltage VC2 is normal to the logic circuit OR847. When VC2_FD is greater than zero, the comparator 846 outputs “1” indicating that the actual voltage VC2 is abnormal to the logic circuit OR847.
 論理回路OR847は、比較器844、845、846の出力信号の論理和をとる。論理回路OR847は、第1インバータ120の故障の有無を示す故障信号1_FDとして、論理和を出力する。 The logic circuit OR 847 takes the logical sum of the output signals of the comparators 844, 845, 846. The logic circuit OR847 outputs a logical sum as a failure signal 1_FD indicating whether or not the first inverter 120 has failed.
 比較器844、845、846の出力信号が全て“0”である場合、論理回路OR847は、第1インバータ120は正常であることを示す“0”を故障信号1_FDとして出力する。比較器844、845、846の出力信号の少なくとも1つが“1”である場合、論理回路OR847は、第1インバータ120は故障していることを示す“1”を故障信号1_FDとして出力する。 When the output signals of the comparators 844, 845, and 846 are all “0”, the logic circuit OR847 outputs “0” indicating that the first inverter 120 is normal as the failure signal 1_FD. When at least one of the output signals of the comparators 844, 845, and 846 is “1”, the logic circuit OR847 outputs “1” indicating that the first inverter 120 has failed as the failure signal 1_FD.
 例えば、ローサイドスイッチ素子SW_A1Lがオープン故障すると、そのスイッチ素子に電流は流れない。その結果、モータ200の逆起電力の影響を受けて、実電圧VA1の下側ピーク値(負の値)は上がり、その絶対値は小さくなる。ローサイドスイッチ素子SW_A1Lにオープン故障が生じていないとき、VA2≒〔(Vpeak/2)+Vsat〕となり、実電圧VA2の大きさは、|(Vpeak/2)+Vsat|に等しくなる。これに対し、ローサイドスイッチ素子SW_A1Lにオープン故障が生じると、この均衡が崩れる。例えば、スイッチ素子SW_A1Lに電流が流れないためにスイッチ素子SW_A2Lに余分な電圧が掛かる。実電圧VA2は大きくなり、VA2_FD>0となる。 For example, when the low-side switch element SW_A1L has an open failure, no current flows through the switch element. As a result, under the influence of the counter electromotive force of the motor 200, the lower peak value (negative value) of the actual voltage VA1 increases and the absolute value thereof decreases. When no open failure has occurred in the low-side switch element SW_A1L, VA2≈ [(Vpeak / 2) + Vsat], and the magnitude of the actual voltage VA2 is equal to | (Vpeak / 2) + Vsat |. On the other hand, when an open failure occurs in the low-side switch element SW_A1L, this balance is lost. For example, since no current flows through the switch element SW_A1L, an extra voltage is applied to the switch element SW_A2L. The actual voltage VA2 increases and VA2_FD> 0.
 図11に示す故障診断ユニット810Bは、故障診断ユニット810Aと同様の処理を実行し、第2インバータ130の故障の有無を診断する。故障診断ユニット810Bには、実電圧VA2、VB2、VC2の代わりに、実電圧VA1、VB1、VC1が入力される。論理回路OR847は、第2インバータ130の故障の有無を示す故障信号2_FDを出力する。故障診断ユニット810Bのそれ以外の処理は故障診断ユニット810Aと同様であるため、ここでは詳細な説明は省略する。 The failure diagnosis unit 810B shown in FIG. 11 performs the same processing as the failure diagnosis unit 810A, and diagnoses the presence or absence of a failure of the second inverter 130. The actual voltages VA1, VB1, and VC1 are input to the failure diagnosis unit 810B instead of the actual voltages VA2, VB2, and VC2. The logic circuit OR847 outputs a failure signal 2_FD indicating whether or not the second inverter 130 has failed. Since the other processing of the failure diagnosis unit 810B is the same as that of the failure diagnosis unit 810A, detailed description is omitted here.
 (Hブリッジのハイサイドおよびローサイドの故障診断)
 次に、HブリッジBA、BB、BCのハイサイドおよびローサイドの中に故障したパートがあるか判定する処理を説明する。
(H bridge high side and low side failure diagnosis)
Next, a process for determining whether there is a failed part on the high side and the low side of the H bridges BA, BB, and BC will be described.
 図12は、HブリッジBA、BB、BCのローサイドの故障の有無を診断する故障診断ユニット820Aを示している。図13は、HブリッジBA、BB、BCのハイサイドの故障の有無を診断する故障診断ユニット820Bを示している。故障診断ユニット800は、図12および図13に示す故障診断ユニット820A、820Bを有する。 FIG. 12 shows a failure diagnosis unit 820A for diagnosing the presence or absence of a low-side failure of the H bridges BA, BB, and BC. FIG. 13 shows a failure diagnosis unit 820B for diagnosing the presence or absence of a high-side failure of the H bridges BA, BB, and BC. The failure diagnosis unit 800 includes failure diagnosis units 820A and 820B shown in FIGS.
 故障診断ユニット820Aは、乗算器851、852と、加算器853、854、855、856、857、858、859と、比較器861、862、863、864、865、866と、論理回路OR867とを有する。 The fault diagnosis unit 820A includes multipliers 851, 852, adders 853, 854, 855, 856, 857, 858, 859, comparators 861, 862, 863, 864, 865, 866, and a logic circuit OR867. Have.
 乗算器851は、電圧ピーク値Vpeakに定数「-1/2」を乗算する。乗算器852は、飽和電圧Vsatに定数「-1」を乗算する。加算器853は、乗算器851および852の出力値を加算する。加算器854は、実電圧VA1と加算器853の出力値とを加算して、下記式(9)で表される故障診断電圧VA1L_FDを算出する。式(9)は上述した式(4)と同じである。
 VA1L_FD=VA1-〔(Vpeak/2)+Vsat〕 式(9)
The multiplier 851 multiplies the voltage peak value Vpeak by a constant “−1/2”. The multiplier 852 multiplies the saturation voltage Vsat by a constant “−1”. Adder 853 adds the output values of multipliers 851 and 852. The adder 854 adds the actual voltage VA1 and the output value of the adder 853 to calculate a failure diagnosis voltage VA1L_FD represented by the following equation (9). Equation (9) is the same as Equation (4) described above.
VA1L_FD = VA1-[(Vpeak / 2) + Vsat] Formula (9)
 比較器861は、“VA1L_FD”と“ゼロ”とを比較する。比較器861は、VA1L_FDがゼロ以下である(VA1L_FD≦0)場合、実電圧VA1は正常であることを示す“0”を論理回路OR867に出力する。比較器861は、VA1L_FDがゼロより大きい(VA1L_FD>0)場合、実電圧VA1は異常であることを示す“1”を論理回路OR867に出力する。 The comparator 861 compares “VA1L_FD” with “zero”. When VA1L_FD is equal to or less than zero (VA1L_FD ≦ 0), the comparator 861 outputs “0” indicating that the actual voltage VA1 is normal to the logic circuit OR867. When VA1L_FD is greater than zero (VA1L_FD> 0), the comparator 861 outputs “1” indicating that the actual voltage VA1 is abnormal to the logic circuit OR867.
 同様に、加算器855は、実電圧VA2と加算器853の出力値とを加算して、故障診断電圧VA2L_FDを算出する。 Similarly, the adder 855 adds the actual voltage VA2 and the output value of the adder 853 to calculate the failure diagnosis voltage VA2L_FD.
 比較器862は、“VA2L_FD”と“ゼロ”とを比較する。比較器862は、VA2L_FDがゼロ以下である(VA2L_FD≦0)場合、実電圧VA2は正常であることを示す“0”を論理回路OR867に出力する。比較器862は、VA2L_FDがゼロより大きい(VA2L_FD>0)場合、実電圧VA2は異常であることを示す“1”を論理回路OR867に出力する。 The comparator 862 compares “VA2L_FD” with “zero”. When VA2L_FD is equal to or less than zero (VA2L_FD ≦ 0), the comparator 862 outputs “0” indicating that the actual voltage VA2 is normal to the logic circuit OR867. When VA2L_FD is larger than zero (VA2L_FD> 0), the comparator 862 outputs “1” indicating that the actual voltage VA2 is abnormal to the logic circuit OR867.
 加算器856は、実電圧VB1と加算器853の出力値とを加算して、故障診断電圧VB1L_FDを算出する。 The adder 856 adds the actual voltage VB1 and the output value of the adder 853 to calculate the failure diagnosis voltage VB1L_FD.
 比較器863は、“VB1L_FD”と“ゼロ”とを比較する。比較器863は、VB1L_FDがゼロ以下である(VB1L_FD≦0)場合、実電圧VB1は正常であることを示す“0”を論理回路OR867に出力する。比較器863は、VB1L_FDがゼロより大きい(VB1L_FD>0)場合、実電圧VB1は異常であることを示す“1”を論理回路OR867に出力する。 The comparator 863 compares “VB1L_FD” with “zero”. When VB1L_FD is equal to or less than zero (VB1L_FD ≦ 0), the comparator 863 outputs “0” indicating that the actual voltage VB1 is normal to the logic circuit OR867. When VB1L_FD is greater than zero (VB1L_FD> 0), the comparator 863 outputs “1” indicating that the actual voltage VB1 is abnormal to the logic circuit OR867.
 加算器857は、実電圧VB2と加算器853の出力値とを加算して、故障診断電圧VB2L_FDを算出する。 The adder 857 adds the actual voltage VB2 and the output value of the adder 853 to calculate the failure diagnosis voltage VB2L_FD.
 比較器864は、“VB2L_FD”と“ゼロ”とを比較する。比較器864は、VB2L_FDがゼロ以下である(VB2L_FD≦0)場合、実電圧VB2は正常であることを示す“0”を論理回路OR867に出力する。比較器864は、VB2L_FDがゼロより大きい(VB2L_FD>0)場合、実電圧VB2は異常であることを示す“1”を論理回路OR867に出力する。 The comparator 864 compares “VB2L_FD” with “zero”. When VB2L_FD is equal to or smaller than zero (VB2L_FD ≦ 0), the comparator 864 outputs “0” indicating that the actual voltage VB2 is normal to the logic circuit OR867. When VB2L_FD is greater than zero (VB2L_FD> 0), the comparator 864 outputs “1” indicating that the actual voltage VB2 is abnormal to the logic circuit OR867.
 加算器858は、実電圧VC1と加算器853の出力値とを加算して、故障診断電圧VC1L_FDを算出する。 The adder 858 adds the actual voltage VC1 and the output value of the adder 853 to calculate the fault diagnosis voltage VC1L_FD.
 比較器865は、“VC1L_FD”と“ゼロ”とを比較する。比較器865は、VC1L_FDがゼロ以下である(VC1L_FD≦0)場合、実電圧VC1は正常であることを示す“0”を論理回路OR867に出力する。比較器865は、VC1L_FDがゼロより大きい(VC1L_FD>0)場合、実電圧VC1は異常であることを示す“1”を論理回路OR867に出力する。 The comparator 865 compares “VC1L_FD” with “zero”. When VC1L_FD is equal to or lower than zero (VC1L_FD ≦ 0), the comparator 865 outputs “0” indicating that the actual voltage VC1 is normal to the logic circuit OR867. When VC1L_FD is greater than zero (VC1L_FD> 0), the comparator 865 outputs “1” indicating that the actual voltage VC1 is abnormal to the logic circuit OR867.
 加算器859は、実電圧VC2と加算器853の出力値とを加算して、故障診断電圧VC2L_FDを算出する。 The adder 859 adds the actual voltage VC2 and the output value of the adder 853 to calculate the failure diagnosis voltage VC2L_FD.
 比較器866は、“VC2L_FD”と“ゼロ”とを比較する。比較器866は、VC2L_FDがゼロ以下である(VC2L_FD≦0)場合、実電圧VC2は正常であることを示す“0”を論理回路OR867に出力する。比較器866は、VC2L_FDがゼロより大きい(VC2L_FD>0)場合、実電圧VC2は異常であることを示す“1”を論理回路OR867に出力する。 The comparator 866 compares “VC2L_FD” with “zero”. When VC2L_FD is equal to or lower than zero (VC2L_FD ≦ 0), the comparator 866 outputs “0” indicating that the actual voltage VC2 is normal to the logic circuit OR867. When VC2L_FD is greater than zero (VC2L_FD> 0), the comparator 866 outputs “1” indicating that the actual voltage VC2 is abnormal to the logic circuit OR867.
 論理回路OR867は、比較器861、862、863、864、865、866の出力信号の論理和をとる。論理回路OR867は、Hブリッジのローサイドの故障の有無を示す故障信号L_FDを出力する。 The logic circuit OR867 takes the logical sum of the output signals of the comparators 861, 862, 863, 864, 865, and 866. The logic circuit OR867 outputs a failure signal L_FD indicating whether or not there is a failure on the low side of the H bridge.
 比較器861、862、863、864、865、866の出力信号が全て“0”である場合、論理回路OR867は、正常を示す“0”を故障信号L_FDとして出力する。比較器861、862、863、864、865、866の出力信号の少なくとも1つが“1”である場合、論理回路OR867は、故障を示す“1”を故障信号L_FDとして出力する。 When the output signals of the comparators 861, 862, 863, 864, 865, and 866 are all “0”, the logic circuit OR867 outputs “0” indicating normality as the failure signal L_FD. When at least one of the output signals of the comparators 861, 862, 863, 864, 865, and 866 is “1”, the logic circuit OR867 outputs “1” indicating a failure as the failure signal L_FD.
 例えば、ローサイドスイッチ素子SW_A2Lがオープン故障した場合、そのスイッチ素子SW_A2Lはオン状態でも電流はほとんど流れない。スイッチ素子SW_A2Lに電流がほとんど流れないためにスイッチ素子SW_A1Lに余分な電圧が掛かる。実電圧VA1は大きくなり、VA1_FD>0となる。 For example, when an open failure occurs in the low-side switch element SW_A2L, current hardly flows even if the switch element SW_A2L is in an ON state. Since almost no current flows through the switch element SW_A2L, an extra voltage is applied to the switch element SW_A1L. The actual voltage VA1 increases and VA1_FD> 0.
 図13に示す故障診断ユニット820Bは、乗算器871、872と、加算器873、874、875、876、877、878、879と、比較器881、882、883、884、885、886と、論理回路OR887とを有する。 The fault diagnosis unit 820B shown in FIG. 13 includes multipliers 871, 872, adders 873, 874, 875, 876, 877, 878, 879, comparators 881, 882, 883, 884, 885, 886, logic Circuit OR887.
 乗算器871は、電圧ピーク値Vpeakに定数「1/2」を乗算する。乗算器872は、飽和電圧Vsatに定数「1」を乗算する。加算器873は、乗算器871および872の出力値を加算する。加算器874は、実電圧VA1と加算器873の出力値とを加算して、下記式(10)で表される故障診断電圧VA1H_FDを算出する。式(10)は上述した式(2)と同じである。
 VA1H_FD=VA1+〔(Vpeak/2)+Vsat〕   式(10)
The multiplier 871 multiplies the voltage peak value Vpeak by a constant “1/2”. The multiplier 872 multiplies the saturation voltage Vsat by a constant “1”. Adder 873 adds the output values of multipliers 871 and 872. The adder 874 adds the actual voltage VA1 and the output value of the adder 873 to calculate a failure diagnosis voltage VA1H_FD represented by the following equation (10). Expression (10) is the same as Expression (2) described above.
VA1H_FD = VA1 + [(Vpeak / 2) + Vsat] Formula (10)
 比較器881は、“VA1H_FD”と“ゼロ”とを比較する。比較器881は、VA1H_FDがゼロ以上である(VA1H_FD≧0)場合、実電圧VA1は正常であることを示す“0”を論理回路OR887に出力する。比較器881は、VA1H_FDがゼロ未満(VA1H_FD<0)の場合、実電圧VA1は異常であることを示す“1”を論理回路OR881に出力する。 The comparator 881 compares “VA1H_FD” with “zero”. When VA1H_FD is equal to or greater than zero (VA1H_FD ≧ 0), the comparator 881 outputs “0” indicating that the actual voltage VA1 is normal to the logic circuit OR887. When VA1H_FD is less than zero (VA1H_FD <0), the comparator 881 outputs “1” indicating that the actual voltage VA1 is abnormal to the logic circuit OR881.
 同様に、加算器875は、実電圧VA2と加算器873の出力値とを加算して、故障診断電圧VA2H_FDを算出する。 Similarly, the adder 875 adds the actual voltage VA2 and the output value of the adder 873 to calculate the failure diagnosis voltage VA2H_FD.
 比較器882は“VA2H_FD”と“ゼロ”とを比較する。比較器882はVA2H_FDがゼロ以上である(VA2H_FD≧0)場合、実電圧VA2は正常であることを示す“0”を論理回路OR887に出力する。比較器882はVA2H_FDがゼロ未満(VA2H_FD<0)場合、実電圧VA2は異常であることを示す“1”を論理回路OR887に出力する。 The comparator 882 compares “VA2H_FD” with “zero”. When VA2H_FD is equal to or larger than zero (VA2H_FD ≧ 0), the comparator 882 outputs “0” indicating that the actual voltage VA2 is normal to the logic circuit OR887. When VA2H_FD is less than zero (VA2H_FD <0), the comparator 882 outputs “1” indicating that the actual voltage VA2 is abnormal to the logic circuit OR887.
 加算器876は、実電圧VB1と加算器873の出力値とを加算して、故障診断電圧VB1H_FDを算出する。 The adder 876 adds the actual voltage VB1 and the output value of the adder 873 to calculate the failure diagnosis voltage VB1H_FD.
 比較器883は“VB1H_FD”と“ゼロ”とを比較する。比較器883はVB1H_FDがゼロ以上である(VB1H_FD≧0)場合、実電圧VB1は正常であることを示す“0”を論理回路OR887に出力する。比較器883はVB1H_FDがゼロ未満(VB1H_FD<0)場合、実電圧VB1は異常であることを示す“1”を論理回路OR887に出力する。 The comparator 883 compares “VB1H_FD” with “zero”. When VB1H_FD is equal to or larger than zero (VB1H_FD ≧ 0), the comparator 883 outputs “0” indicating that the actual voltage VB1 is normal to the logic circuit OR887. When VB1H_FD is less than zero (VB1H_FD <0), the comparator 883 outputs “1” indicating that the actual voltage VB1 is abnormal to the logic circuit OR887.
 加算器877は、実電圧VB2と加算器873の出力値とを加算して、故障診断電圧VB2H_FDを算出する。 The adder 877 adds the actual voltage VB2 and the output value of the adder 873 to calculate the failure diagnosis voltage VB2H_FD.
 比較器884は、“VB2H_FD”と“ゼロ”とを比較する。比較器884は、VB2H_FDがゼロ以上である(VB2H_FD≧0)場合、実電圧VB2は正常であることを示す“0”を論理回路OR887に出力する。比較器884は、VB2H_FDがゼロ未満(VB2H_FD<0)場合、実電圧VB2は異常であることを示す“1”を論理回路OR887に出力する。 The comparator 884 compares “VB2H_FD” with “zero”. The comparator 884 outputs “0” indicating that the actual voltage VB2 is normal to the logic circuit OR887 when VB2H_FD is zero or more (VB2H_FD ≧ 0). When VB2H_FD is less than zero (VB2H_FD <0), the comparator 884 outputs “1” indicating that the actual voltage VB2 is abnormal to the logic circuit OR887.
 加算器878は、実電圧VC1と加算器873の出力値とを加算して、故障診断電圧VC1H_FDを算出する。 The adder 878 calculates the failure diagnosis voltage VC1H_FD by adding the actual voltage VC1 and the output value of the adder 873.
 比較器885は“VC1H_FD”と“ゼロ”とを比較する。比較器885はVC1H_FDがゼロ以上である(VC1H_FD≧0)場合、実電圧VC1は正常であることを示す“0”を論理回路OR887に出力する。比較器885はVC1H_FDがゼロ未満(VC1H_FD<0)場合、実電圧VC1は異常であることを示す“1”を論理回路OR887に出力する。 The comparator 885 compares “VC1H_FD” with “zero”. When VC1H_FD is equal to or greater than zero (VC1H_FD ≧ 0), the comparator 885 outputs “0” indicating that the actual voltage VC1 is normal to the logic circuit OR887. When VC1H_FD is less than zero (VC1H_FD <0), the comparator 885 outputs “1” indicating that the actual voltage VC1 is abnormal to the logic circuit OR887.
 加算器879は、実電圧VC2と加算器873の出力値とを加算して、故障診断電圧VC2H_FDを算出する。 The adder 879 adds the actual voltage VC2 and the output value of the adder 873 to calculate the failure diagnosis voltage VC2H_FD.
 比較器886は“VC2H_FD”と“ゼロ”とを比較する。比較器886はVC2H_FDがゼロ以上である(VC2H_FD≧0)場合、実電圧VC2は正常であることを示す“0”を論理回路OR887に出力する。比較器886はVC2H_FDがゼロ未満(VC2H_FD<0)場合、実電圧VC2は異常であることを示す“1”を論理回路OR887に出力する。 Comparator 886 compares “VC2H_FD” with “zero”. When VC2H_FD is equal to or greater than zero (VC2H_FD ≧ 0), the comparator 886 outputs “0” indicating that the actual voltage VC2 is normal to the logic circuit OR887. When VC2H_FD is less than zero (VC2H_FD <0), the comparator 886 outputs “1” indicating that the actual voltage VC2 is abnormal to the logic circuit OR887.
 論理回路OR887は、比較器881、882、883、884、885、886の出力信号の論理和をとる。論理回路OR887は、Hブリッジのハイサイドの故障の有無を示す故障信号H_FDを出力する。 The logic circuit OR 887 takes the logical sum of the output signals of the comparators 881, 882, 883, 884, 885, 886. The logic circuit OR887 outputs a failure signal H_FD indicating whether or not there is a failure on the high side of the H bridge.
 比較器881、882、883、884、885、886の出力信号が全て“0”である場合、論理回路OR887は、正常を示す“0”を故障信号H_FDとして出力する。比較器881、882、883、884、885、886の出力信号の少なくとも1つが“1”である場合、論理回路OR887は、故障を示す“1”を故障信号H_FDとして出力する。 When the output signals of the comparators 881, 882, 883, 884, 885, 886 are all “0”, the logic circuit OR 887 outputs “0” indicating normality as the failure signal H_FD. When at least one of the output signals of the comparators 881, 882, 883, 884, 885, 886 is “1”, the logic circuit OR887 outputs “1” indicating a failure as a failure signal H_FD.
 (故障したスイッチ素子の特定)
 次に、電力変換装置1000が備えるハイサイドスイッチ素子およびローサイドスイッチ素子の中に故障したスイッチ素子があるか判定する処理を説明する。
(Identification of failed switch element)
Next, a process for determining whether there is a failed switch element among the high-side switch element and the low-side switch element included in the power conversion device 1000 will be described.
 図14は、第1インバータ120のスイッチ素子の故障の有無を診断する故障診断ユニット830Aを示している。図15は、第2インバータ130のスイッチ素子の故障の有無を診断する故障診断ユニット830Bを示している。 FIG. 14 shows a failure diagnosis unit 830A for diagnosing the presence or absence of a failure of the switch element of the first inverter 120. FIG. 15 shows a failure diagnosis unit 830B that diagnoses the presence or absence of a failure of the switch element of the second inverter 130.
 故障診断ユニット830A、830Bは、実質的に同じ機能ブロックを有するが、入力される信号が互いに異なる。故障診断ユニット800は、図14、図15に示す故障診断ユニット830A、830Bを有する。故障診断ユニット830A、830Bのそれぞれは、論理回路AND891、892、893、894、895、896、901、902、903、904、905、906を備える。 Failure diagnosis units 830A and 830B have substantially the same functional blocks, but input signals are different from each other. The failure diagnosis unit 800 includes failure diagnosis units 830A and 830B shown in FIGS. Each of the failure diagnosis units 830A and 830B includes logic circuits AND891, 892, 893, 894, 895, 896, 901, 902, 903, 904, 905, and 906.
 まず、第1インバータ120のスイッチ素子の故障の有無の診断処理を説明する。 First, diagnosis processing for the presence or absence of a failure of the switch element of the first inverter 120 will be described.
 論理回路AND891には、A相のHブリッジBAの故障の有無を示す故障信号A_FDと、Hブリッジのハイサイドの故障の有無を示す故障信号H_FDとが入力される。 The logic circuit AND 891 receives a failure signal A_FD indicating the presence / absence of a failure of the A phase H bridge BA and a failure signal H_FD indicating the presence / absence of a failure of the high side of the H bridge.
 故障信号A_FDと故障信号H_FDの両方が故障を示す“1”である場合、論理回路AND891は“1”を出力する。故障信号A_FDと故障信号H_FDの少なくとも一方が正常を示す“0”である場合、論理回路AND891は“0”を出力する。 When both the failure signal A_FD and the failure signal H_FD are “1” indicating the failure, the logic circuit AND 891 outputs “1”. When at least one of the failure signal A_FD and the failure signal H_FD is “0” indicating normality, the logic circuit AND 891 outputs “0”.
 論理回路AND901には、第1インバータ120の故障の有無を示す故障信号1_FDと、論理回路AND891の出力信号とが入力される。論理回路AND901は、第1インバータ120におけるA相のハイサイドスイッチ素子SW_A1Hの故障の有無を示す故障信号A1H_FDをモータ制御ユニット900に出力する。 A failure signal 1_FD indicating whether or not the first inverter 120 has failed and an output signal of the logic circuit AND891 are input to the logic circuit AND901. The logic circuit AND901 outputs a failure signal A1H_FD indicating whether or not the A-phase high-side switch element SW_A1H in the first inverter 120 has failed to the motor control unit 900.
 故障信号1_FDと論理回路AND891の出力信号の両方が“1”である場合、論理回路AND901は、スイッチ素子SW_A1Hは故障していることを示す“1”を出力する。故障信号1_FDと論理回路AND891の出力信号の少なくとも一方が正常を示す“0”である場合、論理回路AND901は、スイッチ素子SW_A1Hは正常であることを示す“0”を出力する。 When both the failure signal 1_FD and the output signal of the logic circuit AND891 are “1”, the logic circuit AND901 outputs “1” indicating that the switch element SW_A1H has failed. When at least one of the failure signal 1_FD and the output signal of the logic circuit AND891 is “0” indicating normality, the logic circuit AND901 outputs “0” indicating that the switch element SW_A1H is normal.
 A相が故障しており、且つHブリッジのハイサイドが故障しており、且つ第1インバータ120が故障しているということは、ハイサイドスイッチ素子SW_A1Hが故障していることを表している。論理回路AND901が出力する故障信号A1H_FDが“1”である場合、ハイサイドスイッチ素子SW_A1Hが故障していることを特定することができる。 The fact that the A phase has failed, the high side of the H-bridge has failed, and the first inverter 120 has failed indicates that the high-side switch element SW_A1H has failed. When the failure signal A1H_FD output from the logic circuit AND901 is “1”, it can be specified that the high-side switch element SW_A1H has failed.
 論理回路AND892には、A相のHブリッジBAの故障の有無を示す故障信号A_FDと、Hブリッジのローサイドの故障の有無を示す故障信号L_FDとが入力される。 The logic circuit AND 892 receives a failure signal A_FD indicating whether or not the A-phase H bridge BA has failed, and a failure signal L_FD indicating whether or not the H bridge has a low-side failure.
 故障信号A_FDと故障信号L_FDの両方が故障を示す“1”である場合、論理回路AND892は“1”を出力する。故障信号A_FDと故障信号L_FDの少なくとも一方が正常を示す“0”である場合、論理回路AND892は“0”を出力する。 When both the failure signal A_FD and the failure signal L_FD are “1” indicating failure, the logic circuit AND 892 outputs “1”. When at least one of the failure signal A_FD and the failure signal L_FD is “0” indicating normality, the logic circuit AND 892 outputs “0”.
 論理回路AND902には、第1インバータ120の故障の有無を示す故障信号1_FDと、論理回路AND892の出力信号とが入力される。論理回路AND902は、第1インバータ120におけるA相のローサイドスイッチ素子SW_A1Lの故障の有無を示す故障信号A1L_FDをモータ制御ユニット900に出力する。 A failure signal 1_FD indicating whether or not the first inverter 120 has failed and an output signal of the logic circuit AND892 are input to the logic circuit AND902. The logic circuit AND902 outputs a failure signal A1L_FD indicating whether or not the A-phase low-side switch element SW_A1L in the first inverter 120 has failed to the motor control unit 900.
 故障信号1_FDと論理回路AND892の出力信号の両方が“1”である場合、論理回路AND902は、スイッチ素子SW_A1Lは故障していることを示す“1”を出力する。故障信号1_FDと論理回路AND892の出力信号の少なくとも一方が正常を示す“0”である場合、論理回路AND902は、スイッチ素子SW_A1Lは正常であることを示す“0”を出力する。 When both the failure signal 1_FD and the output signal of the logic circuit AND892 are “1”, the logic circuit AND902 outputs “1” indicating that the switch element SW_A1L has failed. When at least one of the failure signal 1_FD and the output signal of the logic circuit AND892 is “0” indicating normality, the logic circuit AND902 outputs “0” indicating that the switch element SW_A1L is normal.
 論理回路AND893には、B相のHブリッジBBの故障の有無を示す故障信号B_FDと、Hブリッジのハイサイドの故障の有無を示す故障信号H_FDとが入力される。 The logic circuit AND 893 receives a failure signal B_FD indicating the presence / absence of a failure in the B-phase H bridge BB and a failure signal H_FD indicating the presence / absence of a failure on the high side of the H bridge.
 故障信号B_FDと故障信号H_FDの両方が故障を示す“1”である場合、論理回路AND893は“1”を出力する。故障信号B_FDと故障信号H_FDの少なくとも一方が正常を示す“0”である場合、論理回路AND893は“0”を出力する。 When both the failure signal B_FD and the failure signal H_FD are “1” indicating a failure, the logic circuit AND 893 outputs “1”. When at least one of the failure signal B_FD and the failure signal H_FD is “0” indicating normality, the logic circuit AND 893 outputs “0”.
 論理回路AND903には、第1インバータ120の故障の有無を示す故障信号1_FDと、論理回路AND893の出力信号とが入力される。論理回路AND903は、第1インバータ120におけるB相のハイサイドスイッチ素子SW_B1Hの故障の有無を示す故障信号B1H_FDをモータ制御ユニット900に出力する。 A failure signal 1_FD indicating whether or not the first inverter 120 has failed and an output signal of the logic circuit AND893 are input to the logic circuit AND903. The logic circuit AND903 outputs a failure signal B1H_FD indicating whether or not the B-phase high-side switch element SW_B1H in the first inverter 120 has failed to the motor control unit 900.
 故障信号1_FDと論理回路AND893の出力信号の両方が“1”である場合、論理回路AND903は、スイッチ素子SW_B1Hは故障していることを示す“1”を出力する。故障信号1_FDと論理回路AND893の出力信号の少なくとも一方が正常を示す“0”である場合、論理回路AND903は、スイッチ素子SW_B1Hは正常であることを示す“0”を出力する。 When both the failure signal 1_FD and the output signal of the logic circuit AND893 are “1”, the logic circuit AND903 outputs “1” indicating that the switch element SW_B1H has failed. When at least one of the failure signal 1_FD and the output signal of the logic circuit AND893 is “0” indicating normality, the logic circuit AND903 outputs “0” indicating that the switch element SW_B1H is normal.
 論理回路AND894には、B相のHブリッジBBの故障の有無を示す故障信号B_FDと、Hブリッジのローサイドの故障の有無を示す故障信号L_FDとが入力される。 The logic circuit AND 894 receives a failure signal B_FD indicating the presence / absence of a failure of the B-phase H bridge BB and a failure signal L_FD indicating the presence / absence of a low-side failure of the H bridge.
 故障信号B_FDと故障信号L_FDの両方が故障を示す“1”である場合、論理回路AND894は“1”を出力する。故障信号B_FDと故障信号L_FDの少なくとも一方が正常を示す“0”である場合、論理回路AND894は“0”を出力する。 When both the failure signal B_FD and the failure signal L_FD are “1” indicating failure, the logic circuit AND 894 outputs “1”. When at least one of the failure signal B_FD and the failure signal L_FD is “0” indicating normality, the logic circuit AND 894 outputs “0”.
 論理回路AND904には、第1インバータ120の故障の有無を示す故障信号1_FDと、論理回路AND894の出力信号とが入力される。論理回路AND904は、第1インバータ120におけるB相のローサイドスイッチ素子SW_B1Lの故障の有無を示す故障信号B1L_FDをモータ制御ユニット900に出力する。 A failure signal 1_FD indicating whether or not the first inverter 120 has failed and an output signal of the logic circuit AND894 are input to the logic circuit AND904. The logic circuit AND904 outputs a failure signal B1L_FD indicating whether or not the B-phase low-side switch element SW_B1L in the first inverter 120 has failed to the motor control unit 900.
 故障信号1_FDと論理回路AND894の出力信号の両方が“1”である場合、論理回路AND904は、スイッチ素子SW_B1Lは故障していることを示す“1”を出力する。故障信号1_FDと論理回路AND894の出力信号の少なくとも一方が正常を示す“0”である場合、論理回路AND904は、スイッチ素子SW_B1Lは正常であることを示す“0”を出力する。 When both the failure signal 1_FD and the output signal of the logic circuit AND 894 are “1”, the logic circuit AND 904 outputs “1” indicating that the switch element SW_B1L has failed. When at least one of the failure signal 1_FD and the output signal of the logic circuit AND 894 is “0” indicating normality, the logic circuit AND904 outputs “0” indicating that the switch element SW_B1L is normal.
 論理回路AND895には、C相のHブリッジBCの故障の有無を示す故障信号C_FDと、Hブリッジのハイサイドの故障の有無を示す故障信号H_FDとが入力される。 The logic circuit AND 895 receives a failure signal C_FD indicating whether or not the C-phase H-bridge BC has failed and a failure signal H_FD indicating whether or not the H-bridge has a high-side failure.
 故障信号C_FDと故障信号H_FDの両方が故障を示す“1”である場合、論理回路AND895は“1”を出力する。故障信号C_FDと故障信号H_FDの少なくとも一方が正常を示す“0”である場合、論理回路AND895は“0”を出力する。 When both the failure signal C_FD and the failure signal H_FD are “1” indicating a failure, the logic circuit AND895 outputs “1”. When at least one of the failure signal C_FD and the failure signal H_FD is “0” indicating normality, the logic circuit AND895 outputs “0”.
 論理回路AND905には、第1インバータ120の故障の有無を示す故障信号1_FDと、論理回路AND895の出力信号とが入力される。論理回路AND905は、第1インバータ120におけるC相のハイサイドスイッチ素子SW_C1Hの故障の有無を示す故障信号C1H_FDをモータ制御ユニット900に出力する。 A failure signal 1_FD indicating whether or not the first inverter 120 has failed and an output signal of the logic circuit AND895 are input to the logic circuit AND905. The logic circuit AND905 outputs to the motor control unit 900 a failure signal C1H_FD indicating whether or not the C-phase high-side switch element SW_C1H in the first inverter 120 has failed.
 故障信号1_FDと論理回路AND895の出力信号の両方が“1”である場合、論理回路AND905は、スイッチ素子SW_C1Hは故障していることを示す“1”を出力する。故障信号1_FDと論理回路AND895の出力信号の少なくとも一方が正常を示す“0”である場合、論理回路AND905は、スイッチ素子SW_C1Hは正常であることを示す“0”を出力する。 When both the failure signal 1_FD and the output signal of the logic circuit AND895 are “1”, the logic circuit AND905 outputs “1” indicating that the switch element SW_C1H has failed. When at least one of the failure signal 1_FD and the output signal of the logic circuit AND895 is “0” indicating normality, the logic circuit AND905 outputs “0” indicating that the switch element SW_C1H is normal.
 論理回路AND896には、C相のHブリッジBCの故障の有無を示す故障信号C_FDと、Hブリッジのローサイドの故障の有無を示す故障信号L_FDとが入力される。 To the logic circuit AND896, a failure signal C_FD indicating whether or not the C-phase H-bridge BC has failed and a failure signal L_FD indicating whether or not the H-bridge has a low-side failure are input.
 故障信号C_FDと故障信号L_FDの両方が故障を示す“1”である場合、論理回路AND896は“1”を出力する。故障信号C_FDと故障信号L_FDの少なくとも一方が正常を示す“0”である場合、論理回路AND896は“0”を出力する。 When both the failure signal C_FD and the failure signal L_FD are “1” indicating failure, the logic circuit AND896 outputs “1”. When at least one of the failure signal C_FD and the failure signal L_FD is “0” indicating normality, the logic circuit AND896 outputs “0”.
 論理回路AND906には、第1インバータ120の故障の有無を示す故障信号1_FDと、論理回路AND896の出力信号とが入力される。論理回路AND906は、第1インバータ120におけるC相のローサイドスイッチ素子SW_C1Lの故障の有無を示す故障信号C1L_FDをモータ制御ユニット900に出力する。 A failure signal 1_FD indicating whether or not the first inverter 120 has failed and an output signal of the logic circuit AND896 are input to the logic circuit AND906. The logic circuit AND906 outputs a failure signal C1L_FD indicating whether or not the C-phase low-side switch element SW_C1L in the first inverter 120 has failed to the motor control unit 900.
 故障信号1_FDと論理回路AND896の出力信号の両方が“1”である場合、論理回路AND906は、スイッチ素子SW_C1Lは故障していることを示す“1”を出力する。故障信号1_FDと論理回路AND896の出力信号の少なくとも一方が正常を示す“0”である場合、論理回路AND906は、スイッチ素子SW_C1Lは正常であることを示す“0”を出力する。 When both the failure signal 1_FD and the output signal of the logic circuit AND896 are “1”, the logic circuit AND906 outputs “1” indicating that the switch element SW_C1L has failed. When at least one of the failure signal 1_FD and the output signal of the logic circuit AND896 is “0” indicating normality, the logic circuit AND906 outputs “0” indicating that the switch element SW_C1L is normal.
 図15に示す故障診断ユニット830Bが実行する処理は、故障診断ユニット830Aと同様であるため、ここでは詳細な説明は省略する。故障診断ユニット830Bは、故障診断ユニット830Aと同様の処理を実行し、第2インバータ130のスイッチ素子の故障の有無の診断処理を実行する。故障診断ユニット830Bは、スイッチ素子SW_A2H、SW_A2L、SW_B2H、SW_B2L、SW_C2H、SW_C2Lの故障の有無を示す故障信号A2H_FD、A2L_FD、B2H_FD、B2L_FD、C2H_FD、C2L_FDをモータ制御ユニット900に出力する。第2インバータ130に故障が発生している場合は、どのスイッチ素子が故障したのか特定することができる。 The process executed by the failure diagnosis unit 830B shown in FIG. 15 is the same as that of the failure diagnosis unit 830A, and thus detailed description thereof is omitted here. The failure diagnosis unit 830B executes the same process as the failure diagnosis unit 830A, and executes a diagnosis process for the presence or absence of a failure of the switch element of the second inverter 130. The failure diagnosis unit 830B outputs the failure signals A2H_FD, A2L_FD, B2H_FD, B2L_FD, C2H_FD, and C2L_FD that indicate whether or not the switch elements SW_A2H, SW_A2L, SW_B2H, SW_B2L, SW_C2H, and SW_C2L have failed. When a failure has occurred in the second inverter 130, it can be specified which switch element has failed.
 モータ制御ユニット900は、故障診断ユニット800が出力する故障信号に応じてモータ制御を変更する。例えば、モータ制御を三相通電制御から二相通電制御に切替える。例えば、故障したスイッチ素子が特定されると、その故障したスイッチ素子を含む相以外の残りの二相を用いた二相通電制御を行う。例えば、A相のHブリッジBAのスイッチ素子が故障したことが特定されると、モータ制御ユニット900は、A相のHブリッジBAの全てのスイッチ素子をオフにする。そして、残りのB相およびC相のHブリッジBBおよびBCを用いた二相通電制御を行う。よって、三相のうちの一相が故障したとしても、電力変換装置1000はモータ駆動を継続できる。 The motor control unit 900 changes the motor control according to the failure signal output by the failure diagnosis unit 800. For example, the motor control is switched from three-phase energization control to two-phase energization control. For example, when a failed switch element is specified, two-phase energization control using the remaining two phases other than the phase including the failed switch element is performed. For example, when it is determined that a switch element of the A-phase H bridge BA has failed, the motor control unit 900 turns off all the switch elements of the A-phase H bridge BA. Then, two-phase energization control using the remaining B-phase and C-phase H bridges BB and BC is performed. Therefore, even if one of the three phases fails, the power conversion apparatus 1000 can continue to drive the motor.
 図17は、三相通電制御に従って電力変換装置1000を制御したときにモータ200のA相、B相およびC相の各巻線に流れる電流値をプロットして得られる電流波形(正弦波)を例示している。図18は、A相のHブリッジBAが故障した場合、二相通電制御に従って電力変換装置1000を制御したときにモータ200のB相、C相の各巻線に流れる電流値をプロットして得られる電流波形を例示している。横軸は、モータ電気角(deg)を示し、縦軸は電流値(A)を示す。図17、図18の電流波形において、電気角30°毎に電流値をプロットしている。Ipkは各相の最大電流値(ピーク電流値)を表す。 FIG. 17 exemplifies a current waveform (sine wave) obtained by plotting the current values flowing in the A-phase, B-phase, and C-phase windings of the motor 200 when the power conversion apparatus 1000 is controlled according to the three-phase energization control. doing. FIG. 18 is obtained by plotting the values of current flowing through the B-phase and C-phase windings of the motor 200 when the power converter 1000 is controlled according to the two-phase energization control when the A-phase H-bridge BA fails. The current waveform is illustrated. The horizontal axis represents the motor electrical angle (deg), and the vertical axis represents the current value (A). In the current waveforms of FIGS. 17 and 18, current values are plotted every 30 electrical angles. Ipk represents the maximum current value (peak current value) of each phase.
 参考として、図19に、B相のHブリッジBBが故障した場合、二相通電制御に従って電力変換装置1000を制御したときにモータ200のA相、C相の各巻線に流れる電流値をプロットして得られる電流波形を例示する。図20に、C相のHブリッジBCが故障した場合、二相通電制御に従って電力変換装置1000を制御したときにモータ200のA相、B相の各巻線に流れる電流値をプロットして得られる電流波形を例示する。 As a reference, FIG. 19 plots the values of current flowing through the A-phase and C-phase windings of the motor 200 when the power converter 1000 is controlled according to the two-phase energization control when the B-phase H-bridge BB fails. The current waveform obtained in this way is illustrated. In FIG. 20, when the C-phase H-bridge BC fails, it is obtained by plotting the values of currents flowing in the A-phase and B-phase windings of the motor 200 when the power converter 1000 is controlled according to the two-phase energization control. The current waveform is illustrated.
 本実施形態において、上述した故障診断ユニット800A、800B、800C、810A、810B、820A、820Bの間での処理の順番は任意である。例えば、故障した相があるか判定してから、Hブリッジのハイサイドおよびローサイドの中に故障したパートがあるか判定してもよいし、逆でもよい。また、例えば、故障したインバータがあるか判定してから、故障した相があるか判定してもよいし、逆でもよい。また、それらの判定を並列に処理してもよい。 In the present embodiment, the order of processing among the above-described failure diagnosis units 800A, 800B, 800C, 810A, 810B, 820A, and 820B is arbitrary. For example, after determining whether there is a failed phase, it may be determined whether there is a failed part on the high side and low side of the H-bridge, or vice versa. Further, for example, after determining whether there is a failed inverter, it may be determined whether there is a failed phase or vice versa. These determinations may be processed in parallel.
 また、故障診断ユニット800A、800B、800C、810A、810B、820A、820Bの全ての処理を実行しなくてもよい。例えば故障した相があるか判定する処理において、三相の全ての故障の有無を判定する前に故障した相があると判定した場合は、残りの相の故障の有無の判定は行わなくてもよい。例えば、三相全ての故障の有無を判定する前にA相が故障していると判定した場合は、B相およびC相の故障の有無の判定は行わなくてもよい。A相が故障していると判定した場合は、B相およびC相に関係する処理は省略しても故障したスイッチ素子を特定することは可能である。 Further, it is not necessary to execute all the processes of the failure diagnosis units 800A, 800B, 800C, 810A, 810B, 820A, and 820B. For example, in the process of determining whether there is a faulty phase, if it is determined that there is a faulty phase before determining the presence or absence of all three-phase faults, it is not necessary to determine whether there are faults in the remaining phases. Good. For example, if it is determined that the A phase has failed before determining the presence / absence of all three phases of failure, the determination of the presence / absence of the failure of the B phase and the C phase may not be performed. When it is determined that the A phase is faulty, the faulty switch element can be identified even if the processing related to the B phase and the C phase is omitted.
 また、例えば、Hブリッジのハイサイドおよびローサイドの中に故障したパートがあるか判定する処理において、ハイサイドおよびローサイドの両方のパートの故障の有無を判定する前に故障したパートがあると判定した場合は、残りのパートの故障の有無の判定は行わなくてもよい。例えば、ハイサイドおよびローサイドの両方の故障の有無を判定する前に、ハイサイドが故障している判定した場合は、ローサイドの故障の有無の判定は行わなくてもよい。ハイサイドが故障していると判定した場合は、ローサイドに関係する処理は省略しても、故障したスイッチ素子を特定することは可能である。 Further, for example, in the process of determining whether there is a failed part in the high side and low side of the H bridge, it is determined that there is a failed part before determining whether there is a failure in both the high side and low side parts. In this case, it is not necessary to determine whether there is a failure in the remaining part. For example, if it is determined that the high side has failed before determining whether there is a failure on both the high side and the low side, it is not necessary to determine whether there is a failure on the low side. If it is determined that the high side has failed, it is possible to identify the failed switch element even if the processing related to the low side is omitted.
 また、例えば、故障したインバータがあるか判定するステップにおいて、第1インバータ120および第2インバータ130の両方の故障の有無を判定する前に故障したインバータがあると判定した場合は、残りのインバータの故障の有無の判定は行わなくてもよい。例えば、第1インバータ120および第2インバータ130の両方の故障の有無を判定する前に、第1インバータ120が故障している判定した場合は、第2インバータ130の故障の有無の判定は行わなくてもよい。第1インバータ120が故障していると判定した場合は、第2インバータ130に関係する処理は省略しても、故障したスイッチ素子を特定することは可能である。 For example, in the step of determining whether there is a failed inverter, if it is determined that there is a failed inverter before determining whether there is a failure in both the first inverter 120 and the second inverter 130, the remaining inverters It is not necessary to determine whether or not there is a failure. For example, if it is determined that the first inverter 120 has failed before determining whether both the first inverter 120 and the second inverter 130 have failed, the determination of whether the second inverter 130 has failed is not performed. May be. If it is determined that the first inverter 120 has failed, it is possible to identify the failed switch element even if the processing related to the second inverter 130 is omitted.
 また、Hブリッジのハイサイドおよびローサイドの中に故障したパートがあるか判定する処理および故障したインバータがあるか判定する処理の少なくとも一方において故障があると判定した場合は、二相についてのみ故障診断を実行してもよい。例えば、A相およびB相は故障していないと判定した場合は、C相の故障診断を行わなくても、C相が故障していることを特定することができる。 If it is determined that there is a failure in at least one of the process for determining whether there is a failed part on the high side and the low side of the H-bridge and the process for determining whether there is a failed inverter, failure diagnosis is performed only for two phases. May be executed. For example, when it is determined that the A phase and the B phase have not failed, it is possible to specify that the C phase has failed without performing a failure diagnosis of the C phase.
 また、故障した相があるか判定する処理および故障したインバータがあるか判定する処理の少なくとも一方において故障があると判定した場合は、Hブリッジのハイサイドおよびローサイドのうちの一方のパートについてのみ、故障診断を実行してもよい。例えば、ハイサイドは故障していないと判定した場合は、ローサイドの故障診断を行わなくても、ローサイドが故障していることを特定することができる。 Further, when it is determined that there is a failure in at least one of the process for determining whether there is a failed phase and the process for determining whether there is a failed inverter, only for one part of the high side and the low side of the H-bridge, Fault diagnosis may be performed. For example, if it is determined that the high side has not failed, it can be determined that the low side has failed without performing a low-side failure diagnosis.
 また、故障した相があるか判定する処理およびHブリッジのハイサイドおよびローサイドの中に故障したパートがあるか判定する処理の少なくとも一方において故障があると判定した場合、第1インバータ120および第2インバータ130のうちの一方についてのみ、故障診断を実行してもよい。例えば、第1インバータ120は故障していないと判定した場合は、第2インバータ130の故障診断を行わなくても、第2インバータ130が故障していることを特定することができる。 When it is determined that there is a failure in at least one of the process for determining whether there is a failed phase and the process for determining whether there is a failed part on the high side and the low side of the H bridge, the first inverter 120 and the second inverter Failure diagnosis may be executed for only one of the inverters 130. For example, if it is determined that the first inverter 120 has not failed, it can be determined that the second inverter 130 has failed without performing failure diagnosis of the second inverter 130.
 また、故障診断ユニット830A、830Bの処理は、故障していると判定されたインバータについてのみ行ってもよい。 Further, the processing of the failure diagnosis units 830A and 830B may be performed only for the inverter that is determined to have a failure.
 このように、複数の処理の一部を省略することにより、演算量を削減することができる。演算量削減により、故障が発生したときに、より短い時間で故障に対処することができる。 Thus, the amount of calculation can be reduced by omitting some of the plurality of processes. By reducing the amount of calculation, when a failure occurs, the failure can be dealt with in a shorter time.
 以下に、本開示による故障診断に用いられるアルゴリズムの妥当性を、dSPACE社の“ラピッドコントロールプロトタイピング(RCP)システム”およびMathWorks社のMatlab/Simulinkを用いて検証した結果を示す。この検証には、ベクトル制御により制御を受ける、電動パワーステアリング(EPS)装置に用いる表面磁石型(SPM)モータのモデルが用いられた。検証においてq軸の電流指令値Iq_refを3Aに設定し、d軸の電流指令値Id_refおよび零相の電流指令値Iz_refを0Aに設定した。モータの回転速度ωは1200rpmに設定した。シミュレーションでは、第1インバータ120のローサイドスイッチ素子SW_A1Lにオープン故障を時刻1.641sで発生させている。 Hereinafter, the validity of the algorithm used for the failure diagnosis according to the present disclosure will be shown using the “Rapid Control Prototyping (RCP) System” of dSPACE and the Matlab / Simlink of MathWorks. For this verification, a model of a surface magnet type (SPM) motor used in an electric power steering (EPS) apparatus, which is controlled by vector control, was used. In the verification, the q-axis current command value Iq_ref was set to 3A, and the d-axis current command value Id_ref and the zero-phase current command value Iz_ref were set to 0A. The rotation speed ω of the motor was set to 1200 rpm. In the simulation, an open failure occurs in the low-side switch element SW_A1L of the first inverter 120 at time 1.641s.
 図21から図26に、各信号の波形のシミュレーション結果を示している。各グラフの縦軸は電圧(V)を示し、横軸は時間(s)を示している。 21 to 26 show the simulation results of the waveform of each signal. The vertical axis of each graph represents voltage (V), and the horizontal axis represents time (s).
 図21は、ローサイドスイッチ素子SW_A1Lがオープン故障した場合の実電圧VA1(上側)および実電圧VA2(下側)の波形を示している。図22は、ローサイドスイッチ素子SW_A1Lがオープン故障した場合の実電圧VB1(上側)および実電圧VB2(下側)の波形を示している。図23は、ローサイドスイッチ素子SW_A1Lがオープン故障した場合の実電圧VC1(上側)および実電圧VC2(下側)の波形を示している。 FIG. 21 shows waveforms of the actual voltage VA1 (upper side) and the actual voltage VA2 (lower side) when the low-side switch element SW_A1L has an open failure. FIG. 22 shows waveforms of the actual voltage VB1 (upper side) and the actual voltage VB2 (lower side) when the low-side switch element SW_A1L has an open failure. FIG. 23 shows waveforms of the actual voltage VC1 (upper side) and the actual voltage VC2 (lower side) when the low-side switch element SW_A1L has an open failure.
 時刻1.641sでローサイドスイッチ素子SW_A1Lがオープン故障した後、図21に示すように実電圧VA1の下側ピーク値は上昇していることが分かる。また、実電圧VA2の上側ピーク値は上昇していることが分かる。すなわち、実電圧VA2の上側ピーク値の絶対値は大きくなる。図22、図23に示すように、実電圧VB1、VB2、VC1、VC2は変化の度合いは小さい。 After the low-side switch element SW_A1L has an open failure at time 1.641s, it can be seen that the lower peak value of the actual voltage VA1 increases as shown in FIG. It can also be seen that the upper peak value of the actual voltage VA2 is increasing. That is, the absolute value of the upper peak value of the actual voltage VA2 increases. As shown in FIGS. 22 and 23, the actual voltages VB1, VB2, VC1, and VC2 have a small degree of change.
 正常時の動作においても、実電圧がVpeak/2よりもわずかに大きくなることは発生し得る。しかし、本実施形態では、Vpeak/2に飽和電圧Vsatを加算した値と、実電圧との比較を行う。このため、図21に示す実電圧VA2のように大きく変化した実電圧が発生した場合にのみ、故障と判定することができる。正常時の動作において実電圧がVpeak/2より大きくなる場合は故障と判定しないことにより、故障判定の精度を高めることができる。 Even in normal operation, it may occur that the actual voltage becomes slightly higher than Vpeak / 2. However, in this embodiment, the value obtained by adding the saturation voltage Vsat to Vpeak / 2 is compared with the actual voltage. For this reason, it can be determined that a failure has occurred only when an actual voltage that has changed significantly, such as the actual voltage VA2 shown in FIG. When the actual voltage is higher than Vpeak / 2 in the normal operation, the failure determination accuracy can be improved by not determining the failure.
 図24は、A相のHブリッジBAにおけるハイサイドスイッチ素子SW_A1Hがオープン故障した場合のA相の第1実電圧VA1(上側)および第2実電圧VA2(下側)の波形を示している。図25は、ハイサイドスイッチ素子SW_A1Hがオープン故障した場合のB相の第1実電圧VB1(上側)および第2実電圧VB2(下側)の波形を示している。図26は、ハイサイドスイッチ素子SW_A1Hがオープン故障した場合のC相の第1実電圧VC1(上側)および第2実電圧VC2(下側)の波形を示している。 FIG. 24 shows waveforms of the first actual voltage VA1 (upper side) and the second actual voltage VA2 (lower side) of the A phase when the high-side switch element SW_A1H in the A-phase H bridge BA has an open failure. FIG. 25 shows the waveforms of the B-phase first actual voltage VB1 (upper side) and the second actual voltage VB2 (lower side) when the high-side switch element SW_A1H has an open failure. FIG. 26 shows waveforms of the first actual voltage VC1 (upper side) and the second actual voltage VC2 (lower side) of the C phase when the high-side switch element SW_A1H has an open failure.
 時刻1.543sでA相のHブリッジBAのハイサイドスイッチ素子SW_A1Hがオープン故障した後、図24に示すように第1実電圧VA1の上側ピーク値は低下していることが分かる。また、第2実電圧VA2の下側ピーク値は低下していることが分かる(下側ピーク値の絶対値は大きくなる)。図25、図26に示すように、第1実電圧VB1、VC1、第2実電圧VB2、VC2の変化の度合いは小さい。 After the open side failure of the high-side switch element SW_A1H of the A-phase H-bridge BA at time 1.543s, it can be seen that the upper peak value of the first actual voltage VA1 is lowered as shown in FIG. It can also be seen that the lower peak value of the second actual voltage VA2 is decreasing (the absolute value of the lower peak value is increased). As shown in FIGS. 25 and 26, the degree of change in the first actual voltages VB1 and VC1, and the second actual voltages VB2 and VC2 is small.
 上記の実施形態では、故障した相があるかの判定処理の途中、Hブリッジのハイサイドおよびローサイドの中に故障したパートがあるかの判定処理の途中、および故障したインバータがあるかの判定処理の途中において、スイッチ素子の故障を検出している。しかしそれらの時点ではスイッチ素子の故障を確定させない。本実施形態では、故障した相があるかの判定結果と、Hブリッジのハイサイドおよびローサイドの中に故障したパートがあるかの判定結果と、故障したインバータがあるかの判定結果とに基づいて、故障したスイッチ素子の確定を行う。よって故障診断の精度を高めることができる。 In the above embodiment, in the middle of the determination process whether there is a faulty phase, in the middle of the determination process whether there is a faulty part in the high side and low side of the H-bridge, and the determination process whether there is a faulty inverter In the middle of this, a failure of the switch element is detected. However, the failure of the switch element is not determined at those times. In this embodiment, based on the determination result of whether there is a failed phase, the determination result of whether there is a failed part in the high side and low side of the H-bridge, and the determination result of whether there is a failed inverter Then, the failed switch element is determined. Therefore, the accuracy of failure diagnosis can be increased.
 本実施形態によると、Hブリッジが有するスイッチ素子のうちオープン故障したスイッチ素子を特定することができる。本開示の故障診断は、簡易なアルゴリズムにより実現できる。そのため、例えばコントローラへ340の実装において回路規模またはメモリサイズの縮小といった利点が得られる。 According to this embodiment, it is possible to identify a switch element that has an open failure among the switch elements of the H bridge. The failure diagnosis of the present disclosure can be realized by a simple algorithm. For this reason, for example, an advantage of reducing the circuit size or the memory size can be obtained in mounting 340 to the controller.
 本開示の故障診断方法は、フルブリッジタイプの電力変換装置にも好適に用いることができる。フルブリッジは、一相のHブリッジ構造、例えば図3Aに示す回路構造を備える。上述した故障診断方法をフルブリッジの故障診断に利用することにより、フルブリッジの故障を検知することができる。 The failure diagnosis method of the present disclosure can be suitably used for a full bridge type power conversion device. The full bridge includes a one-phase H-bridge structure, for example, the circuit structure shown in FIG. 3A. By utilizing the above-described failure diagnosis method for full bridge failure diagnosis, a full bridge failure can be detected.
 例えば、フルブリッジタイプの電力変換装置は、ハイサイドスイッチ素子SW_A1H、ハイサイドスイッチ素子SW_A2H、ローサイドスイッチ素子SW_A1Lおよびローサイドスイッチ素子SW_A2Lを有するHブリッジBAと、HブリッジBAのスイッチ素子のスイッチング動作を制御する制御回路300と、を備える。制御回路300は、dq座標系において表現される電流・電圧を獲得し、ローサイドスイッチ素子SW_A1Lの両端電圧を示す第1実電圧VA1およびローサイドスイッチ素子SW_A2Lの両端電圧を示す第2実電圧VA2を獲得し、モータの回転速度ωを獲得する。制御回路300は、獲得した、dq座標系の電流・電圧、第1実電圧VA1、第2実電圧VA2および回転速度ωに基づいて、ハイサイドスイッチ素子SW_A1H、ハイサイドスイッチ素子SW_A2H、ローサイドスイッチ素子SW_A1Lおよびローサイドスイッチ素子SW_A2Lのオープン故障を診断する。 For example, the full-bridge type power converter controls the switching operation of the H-bridge BA having the high-side switch element SW_A1H, the high-side switch element SW_A2H, the low-side switch element SW_A1L, and the low-side switch element SW_A2L, and the switch element of the H-bridge BA. And a control circuit 300. The control circuit 300 acquires the current / voltage expressed in the dq coordinate system, and acquires the first actual voltage VA1 indicating the voltage across the low-side switch element SW_A1L and the second actual voltage VA2 indicating the voltage across the low-side switch element SW_A2L. Then, the rotational speed ω of the motor is obtained. Based on the acquired current and voltage in the dq coordinate system, the first actual voltage VA1, the second actual voltage VA2, and the rotational speed ω, the control circuit 300 generates the high-side switch element SW_A1H, the high-side switch element SW_A2H, and the low-side switch element. An open failure of SW_A1L and low-side switch element SW_A2L is diagnosed.
 本実施形態においては、三相全てについて上述した故障診断を行わなくてもよく、一相または二相についてのみ故障診断を行ってもよい。例えば、A相についてのみ故障診断を行う場合は、図5から図15を用いて説明した処理のうちのA相に関する処理のみを行い、B相およびC相に関する処理は行わなくてもよい。 In the present embodiment, the above-described failure diagnosis need not be performed for all three phases, and the failure diagnosis may be performed only for one phase or two phases. For example, when failure diagnosis is performed only for the A phase, only the process related to the A phase among the processes described with reference to FIGS. 5 to 15 is performed, and the processes related to the B phase and the C phase may not be performed.
 (実施形態2)
 図27は、本実施形態による電動パワーステアリング装置3000の典型的な構成を模式的に示す。
(Embodiment 2)
FIG. 27 schematically shows a typical configuration of the electric power steering apparatus 3000 according to the present embodiment.
 自動車等の車両は一般に、電動パワーステアリング装置を有する。本実施形態による電動パワーステアリング装置3000は、ステアリングシステム520、および補助トルクを生成する補助トルク機構540を有する。電動パワーステアリング装置3000は運転者がステアリングハンドルを操作することによって発生するステアリングシステムの操舵トルクを補助する補助トルクを生成する。補助トルクにより運転者の操作の負担は軽減される。 A vehicle such as an automobile generally has an electric power steering device. The electric power steering apparatus 3000 according to the present embodiment includes a steering system 520 and an auxiliary torque mechanism 540 that generates auxiliary torque. The electric power steering device 3000 generates auxiliary torque that assists the steering torque of the steering system that is generated when the driver operates the steering wheel. The burden on the driver's operation is reduced by the auxiliary torque.
 ステアリングシステム520は、例えば、ステアリングハンドル521、ステアリングシャフト522、自在軸継手523A、523B、回転軸524、ラックアンドピニオン機構525、ラック軸526、左右のボールジョイント552A、552B、タイロッド527A、527B、ナックル528A、528B、および左右の操舵車輪529A、529Bから構成され得る。 The steering system 520 includes, for example, a steering handle 521, a steering shaft 522, universal shaft joints 523A and 523B, a rotating shaft 524, a rack and pinion mechanism 525, a rack shaft 526, left and right ball joints 552A and 552B, tie rods 527A and 527B, and a knuckle. 528A and 528B, and left and right steering wheels 529A and 529B.
 補助トルク機構540は、例えば、操舵トルクセンサ541、自動車用電子制御ユニット(ECU)542、モータ543および減速機構544などから構成される。操舵トルクセンサ541はステアリングシステム520における操舵トルクを検出する。ECU542は操舵トルクセンサ541の検出信号に基づいて駆動信号を生成する。モータ543は駆動信号に基づいて操舵トルクに応じた補助トルクを生成する。モータ543は減速機構544を介してステアリングシステム520に、生成した補助トルクを伝達する。 The auxiliary torque mechanism 540 includes, for example, a steering torque sensor 541, an automotive electronic control unit (ECU) 542, a motor 543, a speed reduction mechanism 544, and the like. The steering torque sensor 541 detects the steering torque in the steering system 520. The ECU 542 generates a drive signal based on the detection signal of the steering torque sensor 541. The motor 543 generates an auxiliary torque corresponding to the steering torque based on the drive signal. The motor 543 transmits the generated auxiliary torque to the steering system 520 via the speed reduction mechanism 544.
 ECU542は、例えば、実施形態1によるコントローラ340および駆動回路350などを有する。自動車ではECUを核とした電子制御システムが構築される。電動パワーステアリング装置3000では、例えば、ECU542、モータ543およびインバータ545によって、モータ駆動ユニットが構築される。そのシステムに、実施形態1によるモータモジュール2000を好適に用いることができる。 The ECU 542 includes, for example, the controller 340 and the drive circuit 350 according to the first embodiment. In an automobile, an electronic control system with an ECU as a core is constructed. In the electric power steering apparatus 3000, for example, a motor drive unit is constructed by the ECU 542, the motor 543, and the inverter 545. The motor module 2000 according to the first embodiment can be suitably used for the system.
 本開示の実施形態は、シフトバイワイヤ、ステアリングバイワイヤ、ブレーキバイワイヤなどのエックスバイワイヤおよびトラクションモータなどのモータ制御システムにも好適に用いられる。例えば、本開示の実施形態による故障診断方法を実装したEPSは、日本政府および米国運輸省道路交通安全局(NHTSA)によって定められたレベル0から5(自動化の基準)に対応した自動運転車に搭載され得る。 The embodiment of the present disclosure is also suitably used for motor control systems such as X-by-wire such as shift-by-wire, steering-by-wire, and brake-by-wire, and a traction motor. For example, an EPS that implements a fault diagnosis method according to an embodiment of the present disclosure is an autonomous driving vehicle that corresponds to levels 0 to 5 (standards for automation) defined by the Japanese government and the US Department of Transportation's Road Traffic Safety Administration (NHTSA). Can be mounted.
 本開示の実施形態は、掃除機、ドライヤ、シーリングファン、洗濯機、冷蔵庫および電動パワーステアリング装置などの、各種モータを備える多様な機器に幅広く利用され得る。 The embodiment of the present disclosure can be widely used in various devices including various motors such as a vacuum cleaner, a dryer, a ceiling fan, a washing machine, a refrigerator, and an electric power steering device.

Claims (20)

  1.  電源からの電力を、少なくとも一相の巻線を有するモータに供給する電力に変換する電力変換装置の故障を診断する故障診断方法であって、
     前記電力変換装置は、
     前記少なくとも一相の巻線の一端に接続される第1インバータと、
     前記少なくとも一相の巻線の他端に接続される第2インバータと、
     各々が第1ハイサイドスイッチ素子、第1ローサイドスイッチ素子、第2ハイサイドスイッチ素子および第2ローサイドスイッチ素子を有する少なくとも1つのHブリッジと、
     を備え、
     前記故障診断方法は、
     前記少なくとも一相の中に故障した相があるか判定するステップと、
     前記少なくとも1つのHブリッジのハイサイドおよびローサイドの中に故障したパートがあるか判定するステップと、
     前記第1インバータおよび前記第2インバータの中に故障したインバータがあるか判定するステップと、
     前記故障した相があるかの判定結果、前記故障したパートがあるかの判定結果および前記故障したインバータがあるかの判定結果に基づいて、前記第1ハイサイドスイッチ素子、前記第1ローサイドスイッチ素子、前記第2ハイサイドスイッチ素子および前記第2ローサイドスイッチ素子の中に故障したスイッチ素子があるか判定するステップと、
     を包含する、故障診断方法。
    A failure diagnosis method for diagnosing a failure of a power conversion device that converts power from a power source into power supplied to a motor having at least one phase winding,
    The power converter is
    A first inverter connected to one end of the at least one phase winding;
    A second inverter connected to the other end of the at least one phase winding;
    At least one H-bridge, each having a first high-side switch element, a first low-side switch element, a second high-side switch element, and a second low-side switch element;
    With
    The failure diagnosis method includes:
    Determining whether there is a failed phase in the at least one phase;
    Determining whether there is a failed part in the high side and low side of the at least one H-bridge;
    Determining whether there is a failed inverter in the first inverter and the second inverter;
    The first high-side switch element, the first low-side switch element, based on a determination result of the failed phase, a determination result of the failed part, and a determination result of the failed inverter Determining whether there is a failed switch element in the second high-side switch element and the second low-side switch element;
    A failure diagnosis method comprising:
  2.  前記第1ローサイドスイッチ素子の両端電圧を示す第1実電圧と、前記第2ローサイドスイッチ素子の両端電圧を示す第2実電圧と、飽和電圧と、dq座標系におけるd軸電圧およびq軸電圧に基づいて決定される電圧ピーク値とを獲得するステップをさらに包含する、請求項1に記載の故障診断方法。 A first actual voltage indicating a voltage across the first low-side switch element; a second actual voltage indicating a voltage across the second low-side switch element; a saturation voltage; and a d-axis voltage and a q-axis voltage in a dq coordinate system. The fault diagnosis method according to claim 1, further comprising obtaining a voltage peak value determined based on the voltage peak value.
  3.  前記飽和電圧は、前記dq座標系におけるd軸電流、q軸電流および前記モータの回転速度に基づいて決定される、請求項2に記載の故障診断方法。 3. The failure diagnosis method according to claim 2, wherein the saturation voltage is determined based on a d-axis current, a q-axis current in the dq coordinate system, and a rotation speed of the motor.
  4.  前記d軸電流および前記q軸電流に基づいて決定される電流値および前記モータの回転速度の入力と、前記飽和電圧とを関連付けるルックアップテーブルを用いて、前記飽和電圧を決定する、請求項2または3に記載の故障診断方法。 The saturation voltage is determined using a look-up table that associates an input of a current value determined based on the d-axis current and the q-axis current and an input of a rotation speed of the motor with the saturation voltage. Or the failure diagnosis method according to 3.
  5.  前記故障した相があるか判定するステップにおいて、前記第1実電圧、前記第2実電圧、前記飽和電圧および前記電圧ピーク値に基づいて、前記故障した相があるか判定する、
    請求項2から4のいずれかに記載の故障診断方法。
    In the step of determining whether there is a failed phase, it is determined whether there is a failed phase based on the first actual voltage, the second actual voltage, the saturation voltage, and the voltage peak value.
    The fault diagnosis method according to claim 2.
  6.  前記故障したパートがあるか判定するステップにおいて、前記第1実電圧、前記第2実電圧、前記飽和電圧および前記電圧ピーク値に基づいて、前記故障したパートがあるか判定する、請求項2から5のいずれかに記載の故障診断方法。 3. In the step of determining whether or not there is a failed part, it is determined whether or not there is the failed part based on the first actual voltage, the second actual voltage, the saturation voltage, and the voltage peak value. 6. The failure diagnosis method according to any one of 5 above.
  7.  前記故障したインバータがあるか判定するステップにおいて、前記第1実電圧、前記第2実電圧、前記飽和電圧および前記電圧ピーク値に基づいて、前記故障したインバータがあるか判定する、請求項2から6のいずれかに記載の故障診断方法。 The step of determining whether or not there is a failed inverter determines whether or not there is the failed inverter based on the first actual voltage, the second actual voltage, the saturation voltage, and the voltage peak value. 7. The failure diagnosis method according to any one of 6.
  8.  前記モータはn相(nは3以上の整数)の前記巻線を有し、
     前記電力変換装置はn個の前記Hブリッジを有する、請求項1から7のいずれかに記載の故障診断方法。
    The motor has the winding of n phase (n is an integer of 3 or more),
    The fault diagnosis method according to claim 1, wherein the power conversion device includes n H bridges.
  9.  前記故障した相があるか判定するステップにおいて、前記n相の中に故障した相があるか判定し、
     前記故障したパートがあるか判定するステップにおいて、前記n個のHブリッジのハイサイドおよびローサイドの中に故障したパートがあるか判定する、請求項8に記載の故障診断方法。
    In the step of determining whether there is a failed phase, it is determined whether there is a failed phase in the n phase,
    The failure diagnosis method according to claim 8, wherein in the step of determining whether there is a failed part, it is determined whether there is a failed part in the high side and the low side of the n H bridges.
  10.  前記故障した相があるか判定するステップにおいて、前記n相の全ての故障の有無を判定する前に故障した相があると判定した場合は、残りの相の故障の有無の判定は行わない、請求項8に記載の故障診断方法。 In the step of determining whether or not there is a faulty phase, if it is determined that there is a faulty phase before determining the presence or absence of all faults of the n phase, the determination of the presence or absence of faults in the remaining phases is not performed. The failure diagnosis method according to claim 8.
  11.  前記故障したパートがあるか判定するステップにおいて、前記Hブリッジのハイサイドおよびローサイドの両方のパートの故障の有無を判定する前に故障したパートがあると判定した場合は、残りのパートの故障の有無の判定は行わない、請求項8または10に記載の故障診断方法。 In the step of determining whether there is a failed part, if it is determined that there is a failed part before determining whether there is a failure in both the high-side and low-side parts of the H-bridge, The failure diagnosis method according to claim 8 or 10, wherein the presence / absence determination is not performed.
  12.  前記故障したインバータがあるか判定するステップにおいて、前記第1インバータおよび前記第2インバータの両方の故障の有無を判定する前に故障したインバータがあると判定した場合は、残りのインバータの故障の有無の判定は行わない、請求項8、10、11のいずれかに記載の故障診断方法。 In the step of determining whether there is a failed inverter, if it is determined that there is a failed inverter before determining whether there is a failure in both the first inverter and the second inverter, whether there is a failure in the remaining inverters The failure diagnosis method according to claim 8, wherein the determination is not performed.
  13.  前記故障したパートがあるか判定するステップおよび前記故障したインバータがあるか判定するステップの少なくとも一方において故障があると判定した場合、
     n-1相について、前記故障した相があるか判定するステップを実行する、請求項8、10から12のいずれかに記載の故障診断方法。
    When it is determined that there is a failure in at least one of the step of determining whether there is the failed part and the step of determining whether there is the failed inverter,
    The failure diagnosis method according to claim 8, wherein a step of determining whether or not there is a failed phase is performed for the n−1 phase.
  14.  前記故障した相があるか判定するステップおよび前記故障したインバータがあるか判定するステップの少なくとも一方において故障があると判定した場合、
     前記Hブリッジのハイサイドおよびローサイドのうちの一方のパートについて、前記故障したパートがあるか判定するステップを実行する、請求項8、10から13のいずれかに記載の故障診断方法。
    When it is determined that there is a failure in at least one of the step of determining whether there is a failed phase and the step of determining whether there is the failed inverter,
    The failure diagnosis method according to claim 8, wherein a step of determining whether or not there is the failed part is performed on one of the high side and the low side of the H bridge.
  15.  前記故障した相があるか判定するステップおよび前記故障したパートがあるか判定するステップの少なくとも一方において故障があると判定した場合、
     前記第1インバータおよび第2インバータのうちの一方について、前記故障したインバータがあるか判定するステップを実行する、請求項8、10から14のいずれかに記載の故障診断方法。
    If it is determined that there is a failure in at least one of the step of determining whether there is a failed phase and the step of determining whether there is the failed part,
    The failure diagnosis method according to claim 8, wherein a step of determining whether there is the failed inverter is performed for one of the first inverter and the second inverter.
  16.  前記故障したスイッチ素子があるか判定するステップは、前記故障した相があるかの判定結果、前記故障したパートがあるかの判定結果および前記故障したインバータがあるかの判定結果に基づいて、前記第1ハイサイドスイッチ素子、前記第1ローサイドスイッチ素子、前記第2ハイサイドスイッチ素子および前記第2ローサイドスイッチ素子のうちのどのスイッチが故障したか判定するステップを含む、請求項1から15のいずれかに記載の故障診断方法。 The step of determining whether there is a failed switch element is based on the determination result of the failed phase, the determination result of the failed part, and the determination result of the failed inverter. 16. The method according to claim 1, further comprising a step of determining which one of the first high-side switch element, the first low-side switch element, the second high-side switch element, and the second low-side switch element has failed. The failure diagnosis method according to claim 1.
  17.  前記故障したスイッチ素子を特定した場合に、前記故障したスイッチ素子を示す故障信号を出力するステップをさらに包含する、請求項16に記載の故障診断方法。 The fault diagnosis method according to claim 16, further comprising a step of outputting a fault signal indicating the faulty switch element when the faulty switch element is specified.
  18.  電源からの電力を、少なくとも一相の巻線を有するモータに供給する電力に変換する電力変換装置であって、
     前記電力変換装置は、
     前記少なくとも一相の巻線の一端に接続される第1インバータと、
     前記少なくとも一相の巻線の他端に接続される第2インバータと、
     各々が第1ハイサイドスイッチ素子、第1ローサイドスイッチ素子、第2ハイサイドスイッチ素子および第2ローサイドスイッチ素子を有する少なくとも1つのHブリッジと、
     前記第1インバータおよび前記第2インバータの動作を制御する制御回路と、
     を備え、
     前記制御回路は、
     前記少なくとも一相の中に故障した相があるか判定し、
     前記少なくとも1つのHブリッジのハイサイドおよびローサイドの中に故障したパートがあるか判定し、
     前記第1インバータおよび前記第2インバータの中に故障したインバータがあるか判定し、
     前記故障した相があるかの判定結果、前記故障したパートがあるかの判定結果および前記故障したインバータがあるかの判定結果に基づいて、前記第1ハイサイドスイッチ素子、前記第1ローサイドスイッチ素子、前記第2ハイサイドスイッチ素子および前記第2ローサイドスイッチ素子の中に故障したスイッチ素子があるか判定する、電力変換装置。
    A power conversion device that converts electric power from a power source into electric power to be supplied to a motor having at least one phase winding,
    The power converter is
    A first inverter connected to one end of the at least one phase winding;
    A second inverter connected to the other end of the at least one phase winding;
    At least one H-bridge, each having a first high-side switch element, a first low-side switch element, a second high-side switch element, and a second low-side switch element;
    A control circuit for controlling operations of the first inverter and the second inverter;
    With
    The control circuit includes:
    Determining whether there is a failed phase in at least one of the phases;
    Determining if there is a failed part in the high side and low side of the at least one H-bridge;
    Determining whether there is a failed inverter in the first inverter and the second inverter;
    The first high-side switch element, the first low-side switch element, based on a determination result of the failed phase, a determination result of the failed part, and a determination result of the failed inverter A power conversion device that determines whether there is a failed switch element among the second high-side switch element and the second low-side switch element.
  19.  モータと、
     請求項18に記載の電力変換装置と、
    を備えるモータモジュール。
    A motor,
    The power conversion device according to claim 18,
    A motor module comprising:
  20.  請求項19に記載のモータモジュールを備える電動パワーステアリング装置。 An electric power steering apparatus comprising the motor module according to claim 19.
PCT/JP2019/013062 2018-05-15 2019-03-27 Failure diagnostic method, power converting device, motor module, and electric power steering device WO2019220782A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2020519495A JPWO2019220782A1 (en) 2018-05-15 2019-03-27 Failure diagnosis method, power conversion device, motor module and electric power steering device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2018-093826 2018-05-15
JP2018093826 2018-05-15

Publications (1)

Publication Number Publication Date
WO2019220782A1 true WO2019220782A1 (en) 2019-11-21

Family

ID=68540116

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2019/013062 WO2019220782A1 (en) 2018-05-15 2019-03-27 Failure diagnostic method, power converting device, motor module, and electric power steering device

Country Status (2)

Country Link
JP (1) JPWO2019220782A1 (en)
WO (1) WO2019220782A1 (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011025872A (en) * 2009-07-28 2011-02-10 Jtekt Corp Electric power steering device
JP2011078221A (en) * 2009-09-30 2011-04-14 Denso Corp Controller of multi-phase rotating machine, and electric power steering device using the same
JP2014192950A (en) * 2013-03-26 2014-10-06 Denso Corp Power converter
WO2017150638A1 (en) * 2016-03-04 2017-09-08 日本電産株式会社 Power conversion device, motor drive unit, and electric power steering device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011025872A (en) * 2009-07-28 2011-02-10 Jtekt Corp Electric power steering device
JP2011078221A (en) * 2009-09-30 2011-04-14 Denso Corp Controller of multi-phase rotating machine, and electric power steering device using the same
JP2014192950A (en) * 2013-03-26 2014-10-06 Denso Corp Power converter
WO2017150638A1 (en) * 2016-03-04 2017-09-08 日本電産株式会社 Power conversion device, motor drive unit, and electric power steering device

Also Published As

Publication number Publication date
JPWO2019220782A1 (en) 2021-06-17

Similar Documents

Publication Publication Date Title
US8248010B2 (en) Motor driving device, electric power steering device using the same and method for detecting failure in the same
US8659260B2 (en) Motor drive apparatus and electric power steering apparatus using the same
US8436568B2 (en) Motor drive apparatus and electric power steering system using the same
US8037964B2 (en) Electric power steering apparatus
JP7088200B2 (en) Motor control method, power converter, motor module and electric power steering device
JP7070420B2 (en) Power converter, motor drive unit and electric power steering device
US20190372502A1 (en) Power conversion device, motor drive unit, and electric power steering device
US20200274461A1 (en) Electric power conversion device, motor driver, and electric power steering device
WO2019064749A1 (en) Fault diagnosis method, power conversion device, motor module and electric power steering device
US11095233B2 (en) Electric power conversion apparatus, motor drive unit and electric motion power steering apparatus
JPWO2018061818A1 (en) Power converter, motor drive unit and electric power steering apparatus
US11476777B2 (en) Power conversion device, driving device, and power steering device
WO2020080170A1 (en) Failure diagnosis method, power conversion device, motor module, and electric power steering device
WO2019220780A1 (en) Failure diagnostic method, power converting device, motor module, and electric power steering device
WO2019240004A1 (en) Failure diagnosis method, power conversion device, motor module, and electric power steering device
WO2019220782A1 (en) Failure diagnostic method, power converting device, motor module, and electric power steering device
WO2019220781A1 (en) Failure diagnostic method, power converting device, motor module, and electric power steering device
WO2019064748A1 (en) Fault diagnosis method, power conversion device, motor module and electric power steering device
WO2019220783A1 (en) Failure diagnostic method, power converting device, motor module, and electric power steering device
JP2004312930A (en) Motor controller
US11420672B2 (en) Power conversion device, motor drive unit, and electric power steering device
WO2019058671A1 (en) Malfunction diagnosis method, motor control method, power conversion device, motor module, and electric power steering device
WO2019058677A1 (en) Malfunction diagnosis method, motor control method, power conversion device, motor module, and electric power steering device
WO2019058672A1 (en) Malfunction diagnosis method, motor control method, power conversion device, motor module, and electric power steering device
WO2019058676A1 (en) Malfunction diagnosis method, motor control method, power conversion device, motor module, and electric power steering device

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19803827

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2020519495

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 19803827

Country of ref document: EP

Kind code of ref document: A1