WO2019218954A1 - 像素电路及其驱动方法、装置、阵列基板及显示装置 - Google Patents

像素电路及其驱动方法、装置、阵列基板及显示装置 Download PDF

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Publication number
WO2019218954A1
WO2019218954A1 PCT/CN2019/086549 CN2019086549W WO2019218954A1 WO 2019218954 A1 WO2019218954 A1 WO 2019218954A1 CN 2019086549 W CN2019086549 W CN 2019086549W WO 2019218954 A1 WO2019218954 A1 WO 2019218954A1
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Prior art keywords
transistor
control
driving
signal
pole
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PCT/CN2019/086549
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English (en)
French (fr)
Inventor
王铁石
徐智强
高雪岭
羊振中
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京东方科技集团股份有限公司
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Priority to US16/605,794 priority Critical patent/US11373602B2/en
Publication of WO2019218954A1 publication Critical patent/WO2019218954A1/zh

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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a pixel circuit, a driving method thereof, an apparatus, an array substrate, and a display device.
  • the pixel circuit is a circuit for driving the OLED to emit light in an Organic Light Emitting Diode (OLED) display device.
  • OLED Organic Light Emitting Diode
  • a pixel circuit generally includes a plurality of transistors and at least one capacitor.
  • One of the plurality of transistors has a driving transistor, and the driving transistor can be used to control the magnitude of a current flowing through the OLED, thereby controlling the luminance of the OLED.
  • the capacitor is connected to the gate of the driving transistor for maintaining the gate voltage of the driving transistor, so that the driving transistor is kept turned on for one frame period, thereby ensuring continuous illumination of the OLED.
  • the present disclosure provides a pixel circuit and a driving method thereof, an apparatus, an array substrate, and a display device.
  • the technical solution is as follows:
  • a pixel circuit comprising: a driving sub-circuit and a switching sub-circuit;
  • the driving sub-circuit and the switch sub-circuit are connected in series between the power signal end and the lighting unit;
  • the driving sub-circuit is further connected to the gate line and the data line, respectively, for driving the gate driving signal provided by the gate line, the data signal provided by the data line, and the power signal provided by the power signal end. Providing a driving signal to the light emitting unit;
  • the switch sub-circuit is further connected to the switch signal end for controlling the on and off of the signal path between the power signal end and the light-emitting unit under the control of the switch signal provided by the switch signal end.
  • the power signal end is connected to the switch sub-circuit, and the light emitting unit is connected to the driving sub-circuit.
  • the switch sub-circuit includes: a switching transistor; a gate of the switching transistor is connected to the switch signal end, and a first pole of the switching transistor is connected to the power signal end, the switching transistor The second pole is coupled to the input of the driver subcircuit.
  • the power signal terminal is connected to the driving subcircuit, and the lighting unit is connected to the switch subcircuit.
  • the switch sub-circuit includes: a switching transistor, a gate of the switching transistor is connected to the signal end of the switch;
  • the first pole of the switching transistor is connected to an output end of the driving sub-circuit, and the second pole of the switching transistor is connected to the light emitting unit.
  • the power signal end and the light emitting unit are both connected to the driving subcircuit;
  • the driving subcircuit comprises at least two transistors connected in series, the switching subcircuit being connected in series between at least two of the transistors.
  • the switch sub-circuit includes: a switching transistor; a gate of the switching transistor is connected to the switch signal end, and a first pole of the switching transistor is connected to a second pole of the transistor, The second pole of the switching transistor is coupled to the first pole of the other of the transistors.
  • the driving sub-circuit includes: a driving transistor, a first control transistor, a second control transistor, and a first capacitor;
  • the driving transistor, the second control transistor and the switching transistor included in the switching sub-circuit are connected in series between the power signal terminal and the lighting unit;
  • a gate of the first control transistor is connected to the gate line, a first pole of the first control transistor is connected to the data line, a second pole of the first control transistor is connected to a gate of the driving transistor Pole connection
  • a gate of the second control transistor is connected to an emission control signal end
  • One end of the first capacitor is connected to the power signal terminal, and the other end of the first capacitor is connected to a gate of the driving transistor.
  • the driving sub-circuit includes: a third control transistor, a fourth control transistor, a fifth control transistor, a sixth control transistor, a seventh control transistor, an eighth control transistor, a second capacitor, and a driving transistor;
  • the driving transistor, the fourth control transistor, the seventh control transistor, and the switching sub-circuit include a switching transistor connected in series between the power signal terminal and the light emitting unit;
  • a gate of the third control transistor is connected to the gate line, a first pole of the third control transistor is connected to the data line, a second pole of the third control transistor and a first electrode of the driving transistor
  • a gate of the fourth control transistor is connected to an emission control signal end
  • a gate of the fifth control transistor is connected to the gate line, a first pole of the fifth control transistor is connected to a second pole of the driving transistor, and a second pole of the fifth control transistor is a gate connection of the driving transistor;
  • a gate of the sixth control transistor is connected to a reset signal terminal, a first pole of the sixth control transistor is connected to an initialization signal terminal, and a second pole of the sixth control transistor is connected to a gate of the driving transistor ;
  • a gate of the seventh control transistor is connected to the light emission control signal end
  • a gate of the eighth control transistor is connected to the gate line, a first pole of the eighth control transistor is connected to the initialization signal terminal, and a second pole of the eighth control transistor is connected to the seventh control a second pole connection of the transistor;
  • One end of the second capacitor is connected to the gate of the driving transistor, and the other end is connected to the power signal terminal.
  • a method of driving a pixel circuit which can be used to drive a pixel circuit as described in the above aspect, the method comprising:
  • a switching signal of a first potential is provided to the switching signal end, and the switching sub-circuit controls the signal path between the power signal end and the illuminating unit under the control of the switching signal, and the gate of the driving sub-circuit provided on the gate line
  • the driving signal is driven by the driving signal, the data signal provided by the data line, and the power signal provided by the power signal terminal, wherein the display image corresponding to the data signal is a dynamic image
  • control stage providing a switch signal of a second potential to the switch signal end, wherein the switch sub-circuit controls the signal path between the power signal end and the light-emitting unit to be disconnected under the control of the switch signal,
  • the light emitting unit stops emitting light.
  • the method further includes:
  • the lighting phase and the control phase are sequentially performed.
  • the method further includes:
  • the voltage value of the data signal is adjusted according to a ratio of a duration of the control phase to a duration of the illumination phase.
  • adjusting the voltage value of the data signal according to a ratio of a duration of the control phase to a duration of the illumination phase including:
  • the method further includes:
  • a gate drive signal of a first potential is supplied to the gate line to provide a data signal to the data line, and the drive subcircuit stores the data signal under the control of the gate drive signal.
  • a driving apparatus for a pixel circuit for implementing a driving method as described in the above aspect is provided.
  • an array substrate in another aspect, includes: a plurality of pixel units arranged in an array, each of the pixel units including a pixel circuit and a light emitting unit connected to the pixel circuit; Among the pixel units, the pixel circuit in at least one of the pixel units is the pixel circuit as described in the above aspect.
  • the pixel circuit in each of the plurality of pixel units is a pixel circuit as described in the above aspect
  • the array substrate includes a plurality of control regions, each of the control regions is provided with at least one pixel unit, and each of the control regions is provided with a switch signal line, each of the switch signal lines and a switch signal The terminals are connected, and the switch signal terminals connected to different switch signal lines are different;
  • At least one of the pixel units provided in each of the control regions includes a pixel circuit connected to a switching signal line disposed in the control region.
  • the plurality of control area arrays are arranged.
  • Each of the switching signal lines is disposed in parallel with the data lines in the array substrate.
  • a display device comprising: the array substrate of the above aspect, and the driving device of the above aspect.
  • FIG. 1 is a schematic structural diagram of a pixel circuit according to an embodiment of the present disclosure
  • FIG. 2 is a schematic structural diagram of another pixel circuit according to an embodiment of the present disclosure.
  • FIG. 3 is a schematic structural diagram of still another pixel circuit according to an embodiment of the present disclosure.
  • FIG. 4 is a schematic structural diagram of still another pixel circuit according to an embodiment of the present disclosure.
  • FIG. 5 is a schematic structural diagram of still another pixel circuit according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic structural diagram of still another pixel circuit according to an embodiment of the present disclosure.
  • FIG. 7 is a schematic structural diagram of still another pixel circuit according to an embodiment of the present disclosure.
  • FIG. 8 is a flowchart of a driving method of a pixel circuit according to an embodiment of the present disclosure
  • FIG. 9 is a flowchart of another driving method of a pixel circuit according to an embodiment of the present disclosure.
  • FIG. 10 is a flowchart of a method for adjusting a voltage value of a data signal according to an embodiment of the present disclosure
  • FIG. 11 is a schematic diagram of a light-emitting duration of a pixel unit in a moving image display area and a non-moving image display area according to an embodiment of the present disclosure
  • FIG. 12 is a timing diagram of signal terminals in a pixel circuit driving process according to an embodiment of the present disclosure
  • FIG. 13 is an equivalent circuit diagram of a pixel circuit in an input stage according to an embodiment of the present disclosure
  • FIG. 14 is an equivalent circuit diagram of a pixel circuit in an illumination stage according to an embodiment of the present disclosure.
  • 15 is an equivalent circuit diagram of a pixel circuit in an illuminating phase according to an embodiment of the present disclosure.
  • 16 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure.
  • 17 is a schematic diagram showing driving effects of a pixel circuit in the related art.
  • FIG. 18 is a schematic diagram of driving effects of a pixel circuit according to an embodiment of the present disclosure.
  • the transistors employed in all embodiments of the present disclosure may each be a thin film transistor or a field effect transistor or other device having the same characteristics, and the transistors employed in the embodiments of the present disclosure are mainly switching transistors according to the functions in the circuit. Since the source and drain of the switching transistor used here are symmetrical, the source and the drain are interchangeable. In the embodiments of the present disclosure, the source is referred to as a first stage, the drain is referred to as a second stage, or the drain is referred to as a first pole, and the source is referred to as a second pole. According to the form in the drawing, the middle end of the transistor is the gate, the signal input end is the source, and the signal output end is the drain.
  • the switching transistor employed in the embodiments of the present disclosure may include any one of a P-type switching transistor and an N-type switching transistor, wherein the P-type switching transistor is turned on when the gate is at a low level, and is turned off when the gate is at a high level.
  • the N-type switching transistor is turned on when the gate is at a high level and turned off when the gate is at a low level.
  • the plurality of signals in various embodiments of the present disclosure correspond to a first potential and a second potential. The first potential and the second potential only represent two state quantities of the potential of the signal, and do not mean that the first potential or the second potential has a specific value in the whole text.
  • the capacitance in the pixel circuit can maintain the gate voltage of the driving transistor, so that the driving transistor remains in an open state for a frame period, thereby ensuring that the OLED continues to emit light. Therefore, when the display screen displayed by the display device changes rapidly, due to the visual persistence effect of the human eye and the holding mode of the display device, dynamic smear may be present in the display image viewed by the human eye, and the display device The display is poor.
  • FIG. 1 is a schematic structural diagram of a pixel circuit according to an embodiment of the present disclosure.
  • the pixel circuit may include: a driving sub-circuit 10 and a switch sub-circuit 20 .
  • the drive sub-circuit 10 and the switch sub-circuit 20 are connected in series between the power supply signal terminal VDD and the light-emitting unit L.
  • the driving sub-circuit 10 is also connected to a gate line G and a data line Vd, respectively.
  • the driving sub-circuit 10 can be used for a gate driving signal provided on the gate line G and a data signal provided by the data line Vd. And driving the power supply signal provided by the power signal terminal VDD to provide a driving signal to the light emitting unit L to drive the light emitting unit L to emit light.
  • the switch sub-circuit 20 is also connected to the switch signal terminal Vr, and the switch sub-circuit 20 can be used to control the signal between the power signal terminal VDD and the light-emitting unit L under the control of the switch signal provided by the switch signal terminal Vr.
  • the passage of the passage is also connected to the switch signal terminal Vr, and the switch sub-circuit 20 can be used to control the signal between the power signal terminal VDD and the light-emitting unit L under the control of the switch signal provided by the switch signal terminal Vr.
  • the switch sub-circuit 20 can control the signal path between the power signal terminal VDD and the light-emitting unit L when the switch signal is at the first potential, so that the driving sub-circuit 10 can provide the driving signal for the light-emitting unit L. To drive the light-emitting unit L to emit light.
  • the switch sub-circuit 20 can also control the signal path between the power signal terminal VDD and the light-emitting unit L to be disconnected when the switch signal is at the second potential. At this time, the drive sub-circuit 10 cannot generate the drive signal or generate The driving signal cannot be output to the light emitting unit L, and the light emitting unit L cannot emit light.
  • the driving sub-circuit 10 may include a driving transistor M0, and the driving transistor M0 may be used to provide the driving unit L under the driving of the gate driving signal, the data signal, and the power signal. Drive current.
  • the switch sub-circuit 20 can be connected in series with the drive transistor M0.
  • the switch sub-circuit 20 can be connected to the first or second pole of the drive transistor M0.
  • the connection may be referred to as a direct connection, or may be indirectly connected through other transistors, which is not limited by the embodiment of the present disclosure.
  • the embodiment of the present disclosure provides a pixel circuit including a switch sub-circuit connected in series with a driving sub-circuit, and the switch sub-circuit can control a power signal under the control of a switching signal provided at a switch signal end.
  • the connection between the terminal and the light unit Therefore, when the image displayed by the display device is a dynamic image, the signal path between the power signal end and the light emitting unit can be controlled to be disconnected by the switch signal to reduce the light-emitting time of the light-emitting unit, thereby avoiding the occurrence of dynamic smear.
  • the display effect of the display device is ensured.
  • the input end of the switch sub-circuit 20 can be connected to the power signal terminal VDD, and the output end of the switch sub-circuit 20 can be connected to the input end of the drive sub-circuit 10.
  • the output end of the driving sub-circuit 10 is connected to one end (for example, an anode) of the light emitting unit L, and the other end (for example, a cathode) of the light emitting unit L can be connected to a DC power supply terminal VSS (not shown in FIG. 1).
  • FIG. 2 is a schematic structural diagram of another pixel circuit according to an embodiment of the present disclosure.
  • an input end of the driving sub-circuit 10 can be connected to the power signal terminal VDD.
  • the output end of the driving sub-circuit 10 is connected to the input end of the switch sub-circuit 20.
  • the output end of the switch sub-circuit 20 is connected to one end of the light-emitting unit L.
  • the other end of the light-emitting unit L can be connected to the DC power supply terminal VSS. connection.
  • FIG. 3 is a schematic structural diagram of still another pixel circuit according to an embodiment of the present disclosure.
  • the input end of the driving sub-circuit 10 is connected to the power signal terminal VDD, and the driver is connected.
  • the output of the circuit 10 is connected to one end of the light unit L.
  • the driver sub-circuit 10 can include at least two transistors in series, which can be connected in series between the at least two transistors.
  • the switch sub-circuit 20 may include a switching transistor Mr, and a gate of the switching transistor Mr may be connected to the switching signal terminal Vr.
  • the first pole of the switching transistor Mr may be connected to the second pole of one of the driving sub-circuits 10, for example, to the second pole of the second control transistor M2 in the driving sub-circuit 10.
  • the second pole of the switching transistor Mr can be connected to the first pole of the other transistor in the driving sub-circuit 10, for example, to the first pole of the driving transistor M0 in the driving sub-circuit 10.
  • the first electrode of the second transistor M2 is the input terminal of the driving sub-circuit 10
  • the second electrode of the driving transistor M0 is the output terminal of the driving sub-circuit 10.
  • the first pole of the switching transistor Mr can be connected as an input end of the switch sub-circuit 20 to the power signal terminal VDD, and the second pole of the switching transistor Mr can be used as The output is connected to the input of the drive subcircuit 10, for example to the first pole of the second control transistor M2 in the drive subcircuit 10.
  • the second pole of the driving transistor M0 can be connected as an output end of the driving sub-circuit 10 to one end of the light emitting unit L.
  • the first pole of the switching transistor Mr can be connected to the output end of the driving sub-circuit 10 as an input end of the switching sub-circuit 20, for example, with the driving sub-circuit 10.
  • the second pole of the driving transistor M0 is connected.
  • the second pole of the switching transistor Mr can be connected to the light emitting unit L as an output end of the switching sub-circuit 20.
  • the second control transistor M2 of the driving sub-circuit 10 can be connected to the power signal terminal VDD as an input terminal of the driving sub-circuit 10.
  • the switching transistor Mr when the switch signal is at the first potential, the switching transistor Mr is turned on, and the signal path between the power signal terminal VDD and the light emitting unit L is communicated. At this time, the driving sub-circuit 10 can normally drive the light emitting unit. L illuminates.
  • the switching transistor Mr When the switch signal is at the second potential, the switching transistor Mr is turned off, and the signal path between the power signal terminal VDD and the light emitting unit L is turned off. At this time, no driving current flows through the light emitting unit L, and the light emitting unit L stops emitting light. .
  • the switching transistor Mr when the switching transistor Mr is a P-type transistor, the first potential may be low relative to the second potential. Moreover, the second potential may be greater than a potential of the power signal provided by the power signal terminal VDD.
  • the driving sub-circuit 10 may include three transistors and one capacitor, that is, the driving sub-circuit 10 may adopt a 3T1C structure.
  • the driving sub-circuit 10 may include a first control transistor M1, a second control transistor M2, a driving transistor M0, and a first capacitor C1.
  • the driving transistor M0, the second control transistor M2, and the switching transistor Mr included in the switching sub-circuit 20 may be connected in series between the power signal terminal VDD and the light emitting unit L.
  • the gate of the first control transistor M1 is connected to the gate line G
  • the first pole of the first control transistor M1 is connected to the data line Vd
  • the second pole of the first control transistor M1 is connected. Connected to the gate of the drive transistor M0.
  • the gate of the second control transistor M2 is connected to the light emission control signal terminal EM, and the first and second poles of the second control transistor M2 are connected in series with the driving transistor M0 and the switching transistor Mr at the power signal terminal VDD and the light emitting unit. Between L.
  • the second control transistor M2, the switching transistor Mr, and the driving transistor M0 are sequentially connected in series.
  • the first pole of the second control transistor M2 is connected to the power signal terminal VDD, and the second pole of the second control transistor M2 is connected to the first pole of the switching transistor Mr.
  • the switching transistor Mr, the second control transistor M2, and the driving transistor M0 are sequentially connected in series.
  • the first pole of the second control transistor M2 is connected to the second pole of the switching transistor Mr, and the second pole of the second control transistor M2 is connected to the first pole of the switching transistor Mr.
  • the second control transistor M2, the driving transistor M0, and the switching transistor Mr are sequentially connected in series.
  • the first pole of the second control transistor M2 is connected to the power signal terminal VDD, and the second pole of the second control transistor M2 is connected to the first pole of the driving transistor M0.
  • one end of the first capacitor C1 is connected to the power signal terminal VDD, and the other end of the first capacitor C1 is connected to the gate of the driving transistor M0.
  • the driving sub-circuit 10 may also include seven transistors and one capacitor, that is, the driving sub-circuit 10 may adopt a 7T1C structure.
  • the driving sub-circuit 10 may include: a third control transistor M3, a fourth control transistor M4, a fifth control transistor M5, a sixth control transistor M6, a seventh control transistor M7, and an eighth control transistor M8.
  • the driving transistor M0, the fourth control transistor M4, the seventh control transistor M7, and the switching sub-circuit 20 include a switching transistor Mr connected in series between the power signal terminal VDD and the light emitting unit L.
  • the gate of the third control transistor M3 is connected to the gate line G
  • the first pole of the third control transistor M3 is connected to the data line Vd
  • the second pole of the third control transistor M3 is connected. Connected to the first pole of the drive transistor M0.
  • the gate of the fourth control transistor M4 is connected to the light emission control signal terminal EM.
  • the gate of the fifth control transistor M5 is connected to the gate line G, the first pole of the fifth control transistor M5 is connected to the second pole of the driving transistor M0, and the second pole of the fifth control transistor M5 is coupled to the driving The gate of transistor M0 is connected.
  • the gate of the sixth control transistor M6 is connected to the reset signal terminal Re, the first pole of the sixth control transistor M6 is connected to the initialization signal terminal INI, and the second pole of the sixth control transistor M6 is connected to the gate of the driving transistor M0. Extremely connected.
  • the gate of the seventh control transistor M7 is connected to the light emission control signal terminal EM.
  • the gate of the eighth control transistor M8 is connected to the gate line G, the first pole of the eighth control transistor M8 is connected to the initialization signal terminal INI, and the second electrode of the eighth control transistor M8 and the seventh control transistor The second pole of the M7 is connected.
  • One end of the second capacitor C2 is connected to the gate of the driving transistor M0, and the other end is connected to the power signal terminal VDD.
  • the fourth control transistor M4, the switching transistor Mr, the driving transistor M0, and the seventh control transistor M7 may be sequentially connected in series. That is, the first pole of the fourth control transistor M4 is directly connected to the power signal terminal VDD, the second pole of the fourth control transistor M4 is connected to the first pole of the switching transistor Mr, and the second pole of the switching transistor Mr and the driving transistor The first pole of M0 is connected, the second pole of the driving transistor M0 is connected to the first pole of the seventh control transistor M7, and the second pole of the seventh control transistor M7 is connected to the light emitting unit L.
  • the fourth control transistor M4, the driving transistor M0, the seventh control transistor M7, and the switching transistor Mr may be sequentially connected in series. That is, the first pole of the fourth control transistor M4 is directly connected to the power signal terminal VDD, the second pole of the fourth control transistor M4 is connected to the first pole of the driving transistor M0, and the second pole of the driving transistor M0 is The first pole of the seventh control transistor M7 is connected, the second pole of the seventh control transistor M7 is connected to the first pole of the switching transistor Mr, and the second pole of the switching transistor Mr is connected to the light emitting unit L.
  • the switching transistor Mr, the fourth control transistor M4, the driving transistor M0, and the seventh control transistor M7 may be connected in series. That is, the first pole of the switching transistor Mr is directly connected to the power signal terminal VDD, the second pole is connected to the first pole of the fourth control transistor M4, and the second pole of the fourth control transistor M4 is opposite to the driving transistor M0.
  • the first pole of the driving transistor M0 is connected to the first pole of the seventh control transistor M7, and the second pole of the seventh control transistor M7 is connected to the light emitting unit L.
  • the fourth control transistor M4, the driving transistor M0, the switching transistor Mr, and the seventh control transistor M7 may be connected in series. That is, the first pole of the fourth control transistor M4 is directly connected to the power signal terminal VDD, the second pole of the fourth control transistor M4 is connected to the first pole of the driving transistor M0, and the second pole of the driving transistor M0 is The first pole of the switching transistor Mr is connected, the second pole of the switching transistor Mr is connected to the first pole of the seventh control transistor M7, and the second pole of the seventh control transistor M7 is connected to the light emitting unit L.
  • the types of the transistors in the pixel circuit provided by the embodiments of the present disclosure may be both N-type transistors and P-type transistors, which are not limited in the embodiments of the present disclosure.
  • the driving sub-circuit in the pixel circuit may adopt other structures as long as the driving is ensured.
  • the sub-circuit is connected in series with the switch sub-circuit, and the structure of the drive sub-circuit is not limited in the embodiment of the present disclosure.
  • the embodiment of the present disclosure provides a pixel circuit including a switch sub-circuit connected in series with a driving sub-circuit, and the switch sub-circuit can control a power signal under the control of a switching signal provided at a switch signal end.
  • the connection between the terminal and the light unit Therefore, when the image displayed by the display device is a dynamic image, the signal path between the power signal terminal and the light emitting unit can be controlled to be disconnected by the switch signal to reduce the light-emitting time of the light-emitting unit, thereby avoiding the generation of dynamic smear. , to ensure the display effect of the display device.
  • FIG. 8 is a flowchart of a driving method of a pixel circuit according to an embodiment of the present disclosure, which may be used to drive a pixel circuit as shown in any of FIGS. 1 to 7.
  • the method can include:
  • Step 101 The light-emitting phase provides a switch signal of the first potential to the switch signal end, and the switch sub-circuit controls the signal path between the power signal end and the light-emitting unit under the control of the switch signal, and the drive sub-circuit is provided on the gate line.
  • the gate driving signal, the data signal provided by the data line, and the driving of the power signal provided by the power signal terminal output a driving signal to the light emitting unit, and the light emitting unit emits light.
  • the display image corresponding to the data signal may be a dynamic image.
  • a driving device e.g., a timing controller
  • the display device can compare the data signal of the current frame with the data signal of the previous frame.
  • the control phase shown in step 102 below may be performed after the lighting phase.
  • the driving device may compare the data signal of the current frame with the data signals of the previous frames respectively, and when detecting that the amount of change of the data signal with any frame is greater than a preset threshold, the data signal of the current frame may be determined.
  • the corresponding display image is a dynamic image, and the control phase shown in step 102 below may be performed after the illumination phase.
  • Step 102 The control stage provides a switch signal of the second potential to the switch signal end, and the switch sub-circuit controls the signal path between the power signal end and the light-emitting unit to be disconnected under the control of the switch signal, the light-emitting The unit stops emitting light.
  • the embodiment of the present disclosure provides a driving method of a pixel circuit, where the display image corresponding to the data signal provided by the data line can be controlled by the driving sub-circuit and the switch sub-circuit when the display image corresponding to the data signal is a dynamic image.
  • the unit emits light, and then controls the light emitting unit to stop emitting light through the switch sub-circuit, thereby reducing the lighting time of the light emitting unit, thereby avoiding the generation of dynamic smear and ensuring the display effect of the display device.
  • FIG. 9 is a flowchart of another driving method provided by an embodiment of the present disclosure. As shown in FIG. 9, before the illuminating phase shown in step 101 above, the method may further include:
  • Step 103 Detect whether the display image corresponding to the data signal is a dynamic image.
  • the driving device in the display device may first detect whether the display image corresponding to the data signal is For dynamic images.
  • step 104 may be performed, and then the lighting phase shown in step 101 and the control phase shown in step 102 are sequentially performed.
  • step 101 may be directly performed, and step 102 is not performed.
  • the pixel unit of the pixel unit can control the illumination unit to emit light for a period of time within a display period of one frame. After the light is stopped, the duty ratio of the light-emitting phase in one frame of display time is reduced; when the display image corresponding to the data signal of the current frame is not a dynamic image, the light-emitting unit can be controlled by the pixel circuit of the pixel unit. Continuous illumination during the display duration of one frame.
  • Step 104 When the display image is a dynamic image, adjust a voltage value of the data signal according to a ratio of a duration of the control phase to a duration of the illumination phase.
  • the driving device can pass the pixel circuit of the pixel unit, the light emitting unit that controls the pixel unit emits light for a period of time and then stops emitting light, so compared to other display non-moving images. In the pixel unit, the illumination time of the pixel unit displaying the dynamic image is reduced.
  • the driving device can compensate the voltage value of the data signal to be written to improve the brightness of the light emitting unit in the pixel unit.
  • the driving device can adjust the voltage value of the data signal according to a ratio of a duration of the control phase to a duration of the lighting phase.
  • the magnitude of the magnitude of the voltage value adjustment of the data signal is positively correlated with the magnitude of the ratio. That is, the longer the duration of the control phase is, the larger the ratio is, the larger the adjustment of the voltage value of the data signal is; the shorter the duration of the control phase is, the smaller the ratio is, the data signal is The adjustment of the voltage value is also smaller.
  • FIG. 10 is a flowchart of a method for adjusting a voltage value of a data signal according to an embodiment of the present disclosure.
  • the method may include:
  • Step 1041 Determine a brightness value corresponding to a display gray level of the data signal according to a conversion relationship between the gray level and the brightness value.
  • the driving device of the display device may calculate the brightness value corresponding to the display gray level of the data signal of the current frame according to the preset conversion relationship between the gray level and the brightness value.
  • the conversion relationship of the gray scale to the luminance value can be represented by a gamma curve.
  • the gamma curve can be used to indicate the display brightness of each pixel unit at different gray levels.
  • the commonly used gamma curve is generally a gamma 2.2 curve, that is, the luminance value of the pixel unit is 2.2 power of the gray scale.
  • Step 1042 Adjust the brightness value according to a ratio of a duration of the control phase to a duration of the illumination phase.
  • the driving device may adjust the brightness value according to the ratio of the control phase to the duration of the lighting phase, that is, increase the brightness value.
  • the magnitude of the adjustment range of the luminance value is positively correlated with the magnitude of the ratio. That is, the longer the duration of the control phase, the greater the adjustment of the luminance value.
  • the ratio of the duration of the control phase to the duration of the illumination phase is 3:1, that is, the duration of the current illumination phase of the pixel unit is 1/4 of the duration of the normal illumination. Therefore, in order to compensate for the luminance of the pixel unit, the luminance value can be adjusted to 4 times the original luminance value.
  • FIG. 11 is a schematic diagram of a light-emitting duration of a pixel unit in a moving image display area and a non-moving image display area according to an embodiment of the present disclosure.
  • the pixel unit in the non-moving image display area has a light-emitting duration (ie, the duration of the light-emitting phase) in a frame display duration of 4T, and the pixel unit in the moving image display area is displayed in one frame.
  • the duration of the illumination in the duration may be T, which is 1/4 of the length of the original illumination.
  • the luminance value of the pixel unit in the moving image display area may be four times the luminance value of the pixel unit in the non-moving image display area. Thereby, it is possible to ensure uniformity of display brightness of the display device.
  • the ratio of the duration of the control phase to the duration of the illumination phase may be adjusted according to the refresh frequency of the display device, the actual application requirement, or the actual display image to be displayed, and the embodiment of the present disclosure does not limited.
  • the display duration of one frame of image is 16.7 milliseconds.
  • the display duration of one frame of image is reduced to 1 ms, the human eye cannot see the smear, so the duration of the illumination phase can be reduced to 1/16 of the display duration of one frame of image, that is, Yes, the ratio of the duration of the control phase to the duration of the illumination phase can be 15:1.
  • the driving device may adjust the ratio of the duration of the control phase to the duration of the illumination phase according to a dynamic rate of change of the display image to be displayed transmitted by the system side (eg, a graphics processor). For example, if the dynamic change rate of the display image to be displayed is high, the ratio can be controlled to be large. If the dynamic change rate of the display image to be displayed is low, the ratio can be controlled to be small.
  • a dynamic rate of change of the display image to be displayed transmitted by the system side (eg, a graphics processor). For example, if the dynamic change rate of the display image to be displayed is high, the ratio can be controlled to be large. If the dynamic change rate of the display image to be displayed is low, the ratio can be controlled to be small.
  • the dynamic rate of change of the display image to be displayed may be the number of display images in which the image content is different in the multi-frame display image to be displayed in a unit time.
  • Step 1043 Adjust a voltage value of the data signal based on a display gray level corresponding to the adjusted brightness value.
  • the driving device can convert the adjusted brightness value according to the conversion relationship between the gray level and the brightness value to obtain a corresponding adjusted gray level.
  • the data signal voltage value can be adjusted according to the adjusted display gray scale, thereby realizing compensation for the voltage value of the data signal.
  • the pixel circuit shown in FIG. 3 is taken as an example, and the pixel circuit in the pixel circuit is a P-type transistor, and the first potential is low with respect to the second potential. Drive method.
  • FIG. 12 is a timing diagram of signal terminals in a pixel circuit driving process according to an embodiment of the present disclosure.
  • the driving process of the pixel circuit in the pixel unit may include the display duration IF of one frame.
  • FIG. 13 is an equivalent circuit diagram of a pixel circuit in an input stage according to an embodiment of the present disclosure.
  • the first control transistor M1 can be turned on under the control of the gate driving signal, and the data signal is supplied to the gate of the driving transistor M0, and the driving transistor M0 is turned on.
  • the first capacitor C1 stores the data signal.
  • the switching transistor Mr can be turned on under the control of the switching signal.
  • the second control transistor M2 since the second control transistor M2 is turned off under the control of the enable signal, the power signal terminal VDD is disconnected from the first pole of the driving transistor M0. Therefore, in the input phase T1, the potential of the node A is the first potential.
  • the light emitting unit L does not emit light.
  • the node A can be a node connected to the second pole of the switching transistor Mr.
  • FIG. 14 is an equivalent circuit diagram of a pixel circuit in an illumination stage according to an embodiment of the present disclosure. As shown in FIG. 14, in the light-emitting phase T2, the first control transistor M1 is turned off under the control of the gate drive signal. The driving transistor M0 is kept turned on by the action of the first capacitor C1, the second control transistor M2 is turned on under the control of the enable signal, and the switching transistor Mr is turned on under the control of the switching signal.
  • the driving transistor M0 can drive a driving signal, such as a driving current, for driving the light emitting unit L under the driving of the data signal and the power signal provided by the power signal terminal VDD, thereby driving the light emitting unit L to emit light.
  • a driving signal such as a driving current
  • FIG. 15 is an equivalent circuit diagram of a pixel circuit in an illumination stage according to an embodiment of the present disclosure.
  • the second control transistor M2 and the driving transistor M0 are kept turned on, but the switching transistor Mr is turned off under the control of the switching signal.
  • the signal path between the power signal terminal VDD and the light-emitting unit L is turned off, the potential of the node A returns to the first potential, the driving transistor M0 cannot supply the driving signal to the light-emitting unit L, and the light-emitting unit L stops emitting light.
  • the driving device may control the pixel circuit in the pixel unit according to a preset ratio.
  • the ratio of the duration of the control phase T3 to the duration of the illumination phase T2 may be 3:1, that is, the duration of the illumination phase T2 is one quarter of the original duration.
  • the driving device can adjust according to the preset ratio.
  • the voltage value of the data signal can be adjusted such that the light-emitting luminance of the light-emitting unit in the pixel unit is four times the original luminance to ensure brightness uniformity of the display device.
  • each transistor is a P-type transistor, and the first potential is described as an example of a low potential with respect to the second potential.
  • each of the transistors may also adopt an N-type transistor.
  • the first potential may be a high potential with respect to the second potential, and the potential change of each signal terminal may be as shown in FIG. The potential changes are reversed, that is, the timing of the signals supplied from the respective signal terminals is complementary to the timing shown in FIG.
  • the pixel circuit may be connected to each signal end through a signal line.
  • it may be connected to the switch signal end through the switch signal line, connected to the power signal end through the power signal line, connected to the illumination control signal end through the illumination control signal line, connected to the reset signal end through the reset signal line, and through the initialization signal line. Connect to the initialization signal terminal.
  • the embodiment of the present disclosure provides a driving method of a pixel circuit, where the display image corresponding to the data signal provided by the data line can be controlled by the driving sub-circuit and the switch sub-circuit when the display image corresponding to the data signal is a dynamic image.
  • the unit emits light, and then controls the light emitting unit to stop emitting light through the switch sub-circuit, thereby reducing the lighting time of the light emitting unit, thereby avoiding the generation of dynamic smear and ensuring the display effect of the display device.
  • Embodiments of the present disclosure also provide a driving device for a pixel circuit, which can be used to implement the above driving method.
  • the driving device may include: a driving integrated circuit for providing a switching signal to the switching signal terminal, a gate driving circuit for providing a gate driving signal to the gate line, and a source for providing the data signal to the data line Pole drive circuit.
  • the driving device may further include a timing controller, and the timing controller may be connected to the driving integrated circuit, and may be used to implement the methods shown in step 103 and step 104 above.
  • the driving integrated circuit may be a circuit independently provided in the display device, or may be integrated with the source driving circuit.
  • An embodiment of the present disclosure further provides an array substrate, which may include: a plurality of pixel units arranged in an array, each of the pixel units may include a pixel circuit and a light emitting unit connected to the pixel circuit.
  • the pixel circuit in at least one of the pixel units may be a pixel circuit as shown in any of FIGS. 1 to 7.
  • the pixel circuits in each of the unit pixels may be pixel circuits as shown in any one of FIGS. 1 to 7.
  • the array substrate may include a plurality of control regions, and at least one pixel unit may be disposed in each control region, and each control A switch signal line is connected in the area, and each switch signal line is connected to one switch signal end, and the switch signal ends connected to different switch signal lines are different.
  • each of the pixel circuits provided in each of the control regions may be connected to a switch signal line provided in the control region. That is, each pixel circuit of each control area can share a switch signal line.
  • the switching signal lines in the respective control regions may be connected to an integrated circuit (IC) of the display device, that is, the switching signal terminal connected to the switching signal line may be a signal terminal of the driving IC.
  • the driver IC can be used to control the level of the switching signal provided by each of the switching signal lines.
  • Each pixel circuit of each control region can adjust the illumination duration of the illumination unit under the control of the received switching signal. Thereby, independent control of the illumination duration of each pixel unit of each control region can be achieved, and the flexibility of control is effectively improved.
  • the plurality of control regions may be arranged in an array on the base substrate.
  • the plurality of switching signal lines may be disposed in parallel with the data lines in the array substrate, and may be formed by a patterning process with the data lines.
  • the array substrate can be divided into 16 control areas, and the driving IC of the display device is connected with 16 switching signal lines.
  • Each of the 16 control regions may be correspondingly provided with a switch signal line, and the switch signal line is connected to each pixel circuit in the control region.
  • the control region of the first row and the first column of the array substrate is correspondingly provided with a switching signal line Vr1, and each pixel circuit in the control region is connected to the switching signal line Vr1.
  • the control area of the fourth row and the fourth column is correspondingly provided with a switching signal line Vr16, and each pixel circuit in the control area is connected to the switching signal line Vr16.
  • Fig. 17 is a schematic diagram showing the driving effect of the pixel circuit in the related art.
  • each pixel circuit drives the light emitting unit to display the length of one frame in one frame regardless of whether the currently displayed image is a still image or a moving image.
  • dynamic smear may occur when the display device displays a moving image.
  • the small ball in the display image shown in FIG. 17 has a smear.
  • the display time of the light emitting unit in one frame can be reduced by 1F.
  • the length of time during which the light-emitting state is maintained for example, can reduce the light-emitting time of the light-emitting unit to 25% of the original length.
  • there is no smear in the small ball in the display image which effectively improves the display effect.
  • the display image displayed by the display device Due to the display image displayed by the display device, only part of the image may be a moving image, and other portions of the image may be still images. For example, in the display image shown in FIG. 18, the images displayed in the area one and the area three are both still images, and only the image displayed in the area two is a moving image. Therefore, in the embodiment of the present disclosure, by dividing the array substrate into a plurality of control regions and respectively providing one switching signal line for each control region, only the illumination time of the pixel unit of the control region for displaying the dynamic image can be performed. Control is performed without adjusting the illumination duration of the pixel unit of other control areas, which effectively improves the accuracy of the control.
  • Embodiments of the present disclosure provide a display device that can include an array substrate as shown in FIG.
  • the display device may be any product or component having a display function such as a liquid crystal panel, an electronic paper, an OLED panel, an AMOLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, or a navigator.

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Abstract

一种像素电路及其驱动方法、装置、阵列基板及显示装置，属于显示技术领域。像素电路包括：串联在电源信号端（VDD）和发光单元（L）之间的驱动子电路（10）和开关子电路（20）；驱动子电路（10）用于在栅线（G）提供的栅极驱动信号、数据线（Vd）提供的数据信号以及电源信号端（VDD）提供的电源信号的控制下，向发光单元（L）提供驱动信号；开关子电路（20）用于在开关信号端（Vr）提供的开关信号的控制下，控制电源信号端（VDD）与发光单元（L）之间的信号通路的通断。像素电路可以通过开关子电路（20）控制发光单元（l）的发光时长，避免显示装置显示动态图像时出现动态拖影，显示装置的显示效果较好。

Description

像素电路及其驱动方法、装置、阵列基板及显示装置
本公开要求于2018年5月17日提交的申请号为201810474055.4、发明名称为“像素电路及其驱动方法、阵列基板及显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及显示技术领域，特别涉及一种像素电路及其驱动方法、装置、阵列基板及显示装置。
背景技术
像素电路是有机发光二极管(Organic Light Emitting Diode，OLED)显示装置中用于驱动OLED发光的电路。
相关技术中，像素电路一般包括多个晶体管和至少一个电容，该多个晶体管中存在一个驱动晶体管，该驱动晶体管可以用于控制流过OLED的电流的大小，进而控制该OLED的发光亮度。该电容器与该驱动晶体管的栅极连接，用于维持驱动晶体管的栅极电压，使得该驱动晶体管在一帧时长内保持开启状态，进而可以保证该OLED持续发光。
发明内容
本公开提供了一种像素电路及其驱动方法、装置、阵列基板及显示装置。所述技术方案如下：
一方面，提供了一种像素电路，所述像素电路包括：驱动子电路和开关子电路；
所述驱动子电路和所述开关子电路串联在电源信号端和发光单元之间；
所述驱动子电路还分别与栅线和数据线连接，用于在所述栅线提供的栅极驱动信号、所述数据线提供的数据信号以及所述电源信号端提供的电源信号的驱动下，向所述发光单元提供驱动信号；
所述开关子电路还与开关信号端连接，用于在所述开关信号端提供的开关 信号的控制下，控制所述电源信号端与所述发光单元之间的信号通路的通断。
可选的，所述电源信号端与所述开关子电路连接，所述发光单元与所述驱动子电路连接。
可选的，所述开关子电路，包括：开关晶体管；所述开关晶体管的栅极与所述开关信号端连接，所述开关晶体管的第一极与所述电源信号端连接，所述开关晶体管的第二极与所述驱动子电路的输入端连接。
可选的，所述电源信号端与所述驱动子电路连接，所述发光单元与所述开关子电路连接。
可选的，所述开关子电路，包括：开关晶体管，所述开关晶体管的栅极与所述开关信号端连接；
所述开关晶体管的第一极与所述驱动子电路的输出端连接，所述开关晶体管的第二极与所述发光单元连接。
可选的，所述电源信号端和所述发光单元均与所述驱动子电路连接；
其中，所述驱动子电路包括至少两个串联的晶体管，所述开关子电路串联在至少两个所述晶体管之间。
可选的，所述开关子电路，包括：开关晶体管；所述开关晶体管的栅极与所述开关信号端连接，所述开关晶体管的第一极与一个所述晶体管的第二极连接，所述开关晶体管的第二极与另一个所述晶体管的第一极连接。
可选的，所述驱动子电路，包括：驱动晶体管、第一控制晶体管、第二控制晶体管以及第一电容器；
所述驱动晶体管、所述第二控制晶体管与所述开关子电路包括的开关晶体管串联在所述电源信号端和所述发光单元之间；
所述第一控制晶体管的栅极与所述栅线连接，所述第一控制晶体管的第一极与所述数据线连接，所述第一控制晶体管的第二极与所述驱动晶体管的栅极连接；
所述第二控制晶体管的栅极与发光控制信号端连接；
所述第一电容器的一端与所述电源信号端连接，所述第一电容器的另一端与所述驱动晶体管的栅极连接。
可选的，所述驱动子电路，包括：第三控制晶体管、第四控制晶体管、第五控制晶体管、第六控制晶体管、第七控制晶体管、第八控制晶体管、第二电 容器以及驱动晶体管；
所述驱动晶体管、所述第四控制晶体管、所述第七控制晶体管和所述开关子电路包括的开关晶体管串联在所述电源信号端和所述发光单元之间；
所述第三控制晶体管的栅极与所述栅线连接，所述第三控制晶体管的第一极与所述数据线连接，所述第三控制晶体管的第二极与所述驱动晶体管的第一极连接；
所述第四控制晶体管的栅极与发光控制信号端连接；
所述第五控制晶体管的栅极与所述栅线连接，所述第五控制晶体管的第一极与所述驱动晶体管的第二极连接，所述第五控制晶体管的第二极与所述驱动晶体管的栅极连接；
所述第六控制晶体管的栅极与复位信号端连接，所述第六控制晶体管的第一极与初始化信号端连接，所述第六控制晶体管的第二极与所述驱动晶体管的栅极连接；
所述第七控制晶体管的栅极与所述发光控制信号端连接；
所述第八控制晶体管的栅极与所述栅线连接，所述第八控制晶体管的第一极与所述初始化信号端连接，所述第八控制晶体管的第二极与所述第七控制晶体管的第二极连接；
所述第二电容器的一端与所述驱动晶体管的栅极连接，另一端与所述电源信号端连接。
另一方面，提供了一种像素电路的驱动方法，可以用于驱动如上述方面所述的像素电路，所述方法包括：
发光阶段，向开关信号端提供第一电位的开关信号，开关子电路在所述开关信号的控制下，控制电源信号端与发光单元之间的信号通路连通，驱动子电路在栅线提供的栅极驱动信号，数据线提供的数据信号以及电源信号端提供的电源信号的驱动下，驱动所述发光单元发光；其中所述数据信号对应的显示图像为动态图像；
控制阶段，向所述开关信号端提供第二电位的开关信号，所述开关子电路在所述开关信号的控制下，控制所述电源信号端与所述发光单元之间的信号通路断开，所述发光单元停止发光。
可选的，在所述发光阶段之前，所述方法还包括：
检测所述数据信号对应的显示图像是否为动态图像；
当所述显示图像为动态图像时，依次执行所述发光阶段和所述控制阶段。
当所述显示图像为动态图像时，在所述发光阶段之前，所述方法还包括：
根据所述控制阶段的持续时长与所述发光阶段的持续时长的比值，调整所述数据信号的电压值。
可选的，所述根据所述控制阶段的持续时长与所述发光阶段的持续时长的比值，调整所述数据信号的电压值，包括：
根据灰阶与亮度值的转换关系，确定所述数据信号的显示灰阶所对应的亮度值；
根据所述控制阶段的持续时长与所述发光阶段的持续时长的比值，对所述亮度值进行调整；
基于调整后的亮度值所对应的显示灰阶，调整所述数据信号的电压值。
可选的，在所述发光阶段之前，所述方法还包括：
输入阶段，向栅线提供第一电位的栅极驱动信号，向数据线提供数据信号，所述驱动子电路在所述栅极驱动信号的控制下，存储所述数据信号。
又一方面，提供了一种像素电路的驱动装置，所述驱动装置用于实现如上述方面所述的驱动方法。
再一方面，提供了一种阵列基板，所述阵列基板包括：阵列排布的多个像素单元，每个所述像素单元包括一个像素电路及与所述像素电路连接的发光单元；所述多个像素单元中，至少一个像素单元中的像素电路为如上述方面所述的像素电路。
可选的，所述多个像素单元中，每个单元像素中的像素电路均为如上述方面所述的像素电路；
所述阵列基板包括多个控制区域，每个所述控制区域中设置有至少一个像素单元，且每个所述控制区域中设置有一条开关信号线，每条所述开关信号线与一个开关信号端连接，且不同开关信号线连接的开关信号端不同；
每个所述控制区域中设置的至少一个所述像素单元包括的像素电路均与所述控制区域中设置的一条开关信号线连接。
可选的，所述多个控制区域阵列排布。每条所述开关信号线与所述阵列基板中的数据线平行设置。
再一方面，提供了一种显示装置，所述显示装置包括：如上述方面所述的阵列基板，以及如上述方面所述的驱动装置。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本公开实施例提供的一种像素电路的结构示意图；
图2是本公开实施例提供的另一种像素电路的结构示意图；
图3是本公开实施例提供的又一种像素电路的结构示意图；
图4是本公开实施例提供的再一种像素电路的结构示意图；
图5是本公开实施例提供的再一种像素电路的结构示意图；
图6是本公开实施例提供的再一种像素电路的结构示意图；
图7是本公开实施例提供的再一种像素电路的结构示意图；
图8是本公开实施例提供的一种像素电路的驱动方法的流程图；
图9是本公开实施例提供的另一种像素电路的驱动方法的流程图；
图10是本公开实施例提供的一种调整数据信号的电压值的方法流程图；
图11是本公开实施例提供的一种动态图像显示区域以及非动态图像显示区域中像素单元的发光时长的示意图；
图12是本公开实施例提供的一种像素电路驱动过程中各信号端的时序图；
图13是本公开实施例提供的一种像素电路在输入阶段的等效电路图；
图14是本公开实施例提供的一种像素电路在发光阶段的等效电路图；
图15是本公开实施例提供的一种像素电路在发光阶段的等效电路图；
图16是本公开实施例提供的一种阵列基板的结构示意图；
图17是相关技术中的像素电路的驱动效果示意图；
图18是本公开实施例提供的一种像素电路的驱动效果示意图。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚，下面将结合附图对本公开 实施方式作进一步地详细描述。
本公开所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件，根据在电路中的作用本公开的实施例所采用的晶体管主要为开关晶体管。由于这里采用的开关晶体管的源极、漏极是对称的，所以其源极、漏极是可以互换的。在本公开实施例中，将其中源极称为第一级，漏极称为第二级，或者漏极称为第一极，源极称为第二极。按附图中的形态规定晶体管的中间端为栅极、信号输入端为源极、信号输出端为漏极。此外，本公开实施例所采用的开关晶体管可以包括P型开关晶体管和N型开关晶体管中的任一种，其中，P型开关晶体管在栅极为低电平时导通，在栅极为高电平时截止，N型开关晶体管在栅极为高电平时导通，在栅极为低电平时截止。此外，本公开各个实施例中的多个信号都对应有第一电位和第二电位。第一电位和第二电位仅代表该信号的电位有2个状态量，不代表全文中第一电位或第二电位具有特定的数值。
相关技术中，像素电路中的电容可以维持驱动晶体管的栅极电压，使得该驱动晶体管在一帧时长内保持开启状态，进而可以保证该OLED持续发光。因此，当显示装置显示的显示画面快速变化时，由于人眼的视觉暂留效应和显示器件的保持(Holding)模式影响，人眼所观看到的显示画面中可能会存在动态拖影，显示装置的显示效果较差。
图1是本公开实施例提供的一种像素电路的结构示意图，如图1所示，该像素电路可以包括：驱动子电路10和开关子电路20。
该驱动子电路10和该开关子电路20串联在电源信号端VDD和发光单元L之间。
如图1所示，该驱动子电路10还分别与栅线G和数据线Vd连接，该驱动子电路10可以用于在栅线G提供的栅极驱动信号、该数据线Vd提供的数据信号以及电源信号端VDD提供的电源信号的驱动下，向发光单元L提供驱动信号，以驱动该发光单元L发光。
该开关子电路20还与开关信号端Vr连接，该开关子电路20可以用于在该开关信号端Vr提供的开关信号的控制下，控制该电源信号端VDD与该发光单元L之间的信号通路的通断。
示例的，该开关子电路20可以在该开关信号为第一电位时，控制电源信号端VDD与该发光单元L之间的信号通路连通，使得驱动子电路10能够为该发光单元L提供驱动信号，以驱动发光单元L发光。该开关子电路20还可以在该开关信号为第二电位时，控制该电源信号端VDD与该发光单元L之间的信号通路断开，此时驱动子电路10无法生成该驱动信号，或者生成的驱动信号无法输出至发光单元L，该发光单元L无法发光。
可选的，在本公开实施例中，该驱动子电路10中可以包括驱动晶体管M0，该驱动晶体管M0可以用于在栅极驱动信号、数据信号和电源信号的驱动下，向发光单元L提供驱动电流。开关子电路20可以与该驱动晶体管M0串联，例如该开关子电路20可以与驱动晶体管M0的第一极或者第二极连接。该连接可以是指直接连接，也可以是指通过其他晶体管间接连接，本公开实施例对此不做限定。
综上所述，本公开实施例提供了一种像素电路，该像素电路包括与驱动子电路串联的开关子电路，该开关子电路可以在开关信号端提供的开关信号的控制下，控制电源信号端与发光单元之间的通断。因此，当显示装置显示的图像为动态图像时，可以通过该开关信号控制电源信号端与发光单元之间的信号通路断开，以减少发光单元的发光时间，从而可以避免动态拖影的产生，保证了显示装置的显示效果。
作为一种可选的实现方式，如图1所示，该开关子电路20的输入端可以与该电源信号端VDD连接，该开关子电路20的输出端可以与该驱动子电路10的输入端连接，该驱动子电路10的输出端与该发光单元L的一端(例如阳极)连接，该发光单元L的另一端(例如阴极)可以与直流电源端VSS(图1中未标注)连接。
图2是本公开实施例提供的另一种像素电路的结构示意图，如图2所示，作为另一种可选的实现方式，该驱动子电路10的输入端可以与该电源信号端VDD连接，该驱动子电路10的输出端与该开关子电路20的输入端连接，该开关子电路20的输出端与该发光单元L的一端连接，该发光单元L的另一端可以与直流电源端VSS连接。
图3是本公开实施例提供的又一种像素电路的结构示意图，如图3所述，作为再一种可选的实现方式，驱动子电路10的输入端与电源信号端VDD连接， 驱动子电路10的输出端与发光单元L的一端连接。在该实现方式中，驱动子电路10可以包括至少两个串联的晶体管，该开关子电路20可以串联在该至少两个晶体管之间。
如图3所示，该开关子电路20可以包括：开关晶体管Mr，该开关晶体管Mr的栅极可以与该开关信号端Vr连接。
该开关晶体管Mr的第一极可以与该驱动子电路10中一个晶体管的第二极连接，例如可以与驱动子电路10中的第二控制晶体管M2的第二极连接。该开关晶体管Mr的第二极可以与驱动子电路10中另一个晶体管的第一极连接，例如可以与驱动子电路10中的该驱动晶体管M0的第一极连接。
在图3所示的像素电路中，第二晶体管M2的第一极即为该驱动子电路10的输入端，驱动晶体管M0的第二极即为该驱动子电路10的输出端。
对于图1所示的像素电路的结构，参考图4，该开关晶体管Mr的第一极可以作为该开关子电路20的输入端与电源信号端VDD连接，该开关晶体管Mr的第二极可以作为输出端与驱动子电路10的输入端连接，例如可以与驱动子电路10中第二控制晶体管M2的第一极连接。相应的，驱动晶体管M0的第二极可以作为驱动子电路10的输出端与发光单元L的一端连接。
对于图2所示的像素电路的结构，参考图5，该开关晶体管Mr的第一极可以作为该开关子电路20的输入端与驱动子电路10的输出端连接，例如可以与驱动子电路10中该驱动晶体管M0的第二极连接。该开关晶体管Mr的第二极可以作为该开关子电路20的输出端与该发光单元L连接。
如图5所示，该驱动子电路10中的第二控制晶体管M2可以作为该驱动子电路10的输入端与该电源信号端VDD连接。
在本公开实施例中，当该开关信号为第一电位时，该开关晶体管Mr开启，电源信号端VDD与发光单元L之间的信号通路连通，此时该驱动子电路10可以正常驱动发光单元L发光。当该开关信号为第二电位时，该开关晶体管Mr关断，电源信号端VDD与发光单元L之间的信号通路断开，此时无驱动电流流过发光单元L，该发光单元L停止发光。
示例的，当该开关晶体管Mr为P型晶体管时，该第一电位相对于该第二电位可以为低电位。并且，该第二电位可以大于该电源信号端VDD所提供的电源信号的电位。
在本公开实施例一种可选的实现方式中，该驱动子电路10可以包括三个晶体管和一个电容器，即该驱动子电路10可以采用3T1C的结构。参考图3至图5，该驱动子电路10可以包括：第一控制晶体管M1、第二控制晶体管M2、驱动晶体管M0以及第一电容器C1。
其中，驱动晶体管M0、第二控制晶体管M2与该开关子电路20包括的开关晶体管Mr可以串联在电源信号端VDD和发光单元L之间。
如图3和图5所示，该第一控制晶体管M1的栅极与栅线G连接，该第一控制晶体管M1的第一极与数据线Vd连接，该第一控制晶体管M1的第二极与该驱动晶体管M0的栅极连接。
该第二控制晶体管M2的栅极与发光控制信号端EM连接，该第二控制晶体管M2的第一极和第二极，与驱动晶体管M0和开关晶体管Mr串联在该电源信号端VDD和发光单元L之间。
示例的，在图3所示的结构中，该第二控制晶体管M2、开关晶体管Mr以及驱动晶体管M0依次串联。该第二控制晶体管M2的第一极与电源信号端VDD连接，第二控制晶体管M2的第二极与开关晶体管Mr的第一极连接。
在图4所示的结构中，开关晶体管Mr、第二控制晶体管M2以及驱动晶体管M0依次串联。该第二控制晶体管M2的第一极与开关晶体管Mr的第二极连接，第二控制晶体管M2的第二极与开关晶体管Mr的第一极连接。
在图5所示的结构中，第二控制晶体管M2、驱动晶体管M0以及开关晶体管Mr依次串联。该第二控制晶体管M2的第一极与电源信号端VDD连接，第二控制晶体管M2的第二极与驱动晶体管M0的第一极连接。
参考图3至图5可以看出，该第一电容器C1的一端与该电源信号端VDD连接，该第一电容器C1的另一端与该驱动晶体管M0的栅极连接。
在本公开实施例另一种可选的实现方式中，该驱动子电路10也可以包括七个晶体管和一个电容器，即该驱动子电路10可以采用7T1C的结构。参考图6和图7，该驱动子电路10可以包括：第三控制晶体管M3、第四控制晶体管M4、第五控制晶体管M5、第六控制晶体管M6、第七控制晶体管M7、第八控制晶体管M8、第二电容器C2以及驱动晶体管M0。
其中，驱动晶体管M0、第四控制晶体管M4、第七控制晶体管M7和开关子电路20包括的开关晶体管Mr串联在电源信号端VDD和发光单元L之间。
如图6和图7所示，该第三控制晶体管M3的栅极与栅线G连接，该第三控制晶体管M3的第一极与数据线Vd连接，该第三控制晶体管M3的第二极与该驱动晶体管M0的第一极连接。
该第四控制晶体管M4的栅极与发光控制信号端EM连接。
该第五控制晶体管M5的栅极与该栅线G连接，该第五控制晶体管M5的第一极与该驱动晶体管M0的第二极连接，该第五控制晶体管M5的第二极与该驱动晶体管M0的栅极连接。
该第六控制晶体管M6的栅极与复位信号端Re连接，该第六控制晶体管M6的第一极与初始化信号端INI连接，该第六控制晶体管M6的第二极与该驱动晶体管M0的栅极连接。
该第七控制晶体管M7的栅极与该发光控制信号端EM连接。
该第八控制晶体管M8的栅极与该栅线G连接，该第八控制晶体管M8的第一极与该初始化信号端INI连接，该第八控制晶体管M8的第二极与该第七控制晶体管M7的第二极连接。
该第二电容器C2的一端与该驱动晶体管M0的栅极连接，另一端与该电源信号端VDD连接。
作为一种可选的实现方式，参考图6，该第四控制晶体管M4、开关晶体管Mr、驱动晶体管M0以及第七控制晶体管M7可以依次串联。即该第四控制晶体管M4的第一极与该电源信号端VDD直接连接，该第四控制晶体管M4的第二极与开关晶体管Mr的第一极连接，开关晶体管Mr的第二极与驱动晶体管M0的第一极连接，驱动晶体管M0的第二极与第七控制晶体管M7的第一极连接，第七控制晶体管M7的第二极与该发光单元L连接。
作为另一种可选的实现方式，参考图7，该第四控制晶体管M4、驱动晶体管M0、第七控制晶体管M7以及开关晶体管Mr可以依次串联。即该第四控制晶体管M4的第一极与该电源信号端VDD直接连接，该第四控制晶体管M4的第二极与驱动晶体管M0的第一极连接，该驱动晶体管M0的第二极与该第七控制晶体管M7的第一极连接，该第七控制晶体管M7的第二极与该开关晶体管Mr的第一极连接，该开关晶体管Mr的第二极与该发光单元L连接。
作为再一种可选的实现方式，该开关晶体管Mr、第四控制晶体管M4、驱动晶体管M0以及第七控制晶体管M7可以依次串联。即该开关晶体管Mr的第 一极与该电源信号端VDD直接连接，第二极与该第四控制晶体管M4的第一极连接，该第四控制晶体管M4的第二极与驱动晶体管M0的第一极连接，该驱动晶体管M0的第二极与该第七控制晶体管M7的第一极连接，该第七控制晶体管M7的第二极与该发光单元L连接。
作为再一种可选的实现方式，该第四控制晶体管M4、驱动晶体管M0、开关晶体管Mr以及第七控制晶体管M7可以依次串联。即该第四控制晶体管M4的第一极与该电源信号端VDD直接连接，该第四控制晶体管M4的第二极与驱动晶体管M0的第一极连接，该驱动晶体管M0的第二极与该开关晶体管Mr的第一极连接，该开关晶体管Mr的第二极与该第七控制晶体管M7的第一极连接，该第七控制晶体管M7的第二极与该发光单元L连接。
需要说明的是，本公开实施例提供的像素电路中各晶体管的类型可以均为N型晶体管，也可以均为P型晶体管，本公开实施例对此不做限定。并且，该像素电路中的驱动子电路除了可以采用图3至图5所示的3T1C的结构，或者图6或图7所示的7T1C的结构之外，也可以采用其他结构，只要保证该驱动子电路与开关子电路串联即可，本公开实施例对该驱动子电路的结构不做限定。
综上所述，本公开实施例提供了一种像素电路，该像素电路包括与驱动子电路串联的开关子电路，该开关子电路可以在开关信号端提供的开关信号的控制下，控制电源信号端与发光单元之间的通断。因此，当显示装置显示的图像为动态图像时，可以通过该开关信号控制电源信号端与发光单元之间的信号通路断开，以减少该发光单元的发光时间，从而可以避免动态拖影的产生，保证了显示装置的显示效果。
图8是本公开实施例提供的一种像素电路的驱动方法的流程图，该方法可以用于驱动如图1至图7任一所示的像素电路。参考图8，该方法可以包括：
步骤101、发光阶段，向开关信号端提供第一电位的开关信号，开关子电路在开关信号的控制下，控制电源信号端与发光单元之间的信号通路连通，驱动子电路在栅线提供的栅极驱动信号，数据线提供的数据信号以及电源信号端提供的电源信号的驱动下向发光单元输出驱动信号，该发光单元发光。
其中，该数据信号对应的显示图像可以为动态图像。在本公开实施例中，显示装置中的驱动装置(例如时序控制器)可以将该当前一帧的数据信号与上 一帧的数据信号进行对比。当驱动装置检测到两者的变化量大于预设阈值时，可以确定当前一帧的数据信号对应的显示图像为动态图像，并可以在发光阶段之后执行下述步骤102所示的控制阶段。或者，驱动装置可以将当前一帧的数据信号与前若干帧的数据信号分别进行对比，当检测到与任一帧的数据信号的变化量大于预设阈值时，可以确定当前一帧的数据信号对应的显示图像为动态图像，并可以在发光阶段之后执行下述步骤102所示的控制阶段。
步骤102、控制阶段，向该开关信号端提供第二电位的开关信号，该开关子电路在该开关信号的控制下，控制该电源信号端与该发光单元之间的信号通路断开，该发光单元停止发光。
综上所述，本公开实施例提供了一种像素电路的驱动方法，该方法可以在数据线提供的数据信号所对应的显示图像为动态图像时，先通过驱动子电路和开关子电路控制发光单元发光，然后再通过开关子电路控制该发光单元停止发光，由此可以减少该发光单元的发光时间，从而可以避免动态拖影的产生，保证了显示装置的显示效果。
可选的，图9是本公开实施例提供的另一种驱动方法的流程图。如图9所示，在上述步骤101所示的发光阶段之前，该方法还可以包括：
步骤103、检测数据信号对应的显示图像是否为动态图像。
在本公开实施例中，显示装置中的驱动装置在获取到当前待写入至某个像素单元的一帧数据信号(也可以称为资料)后，可以先检测该数据信号对应的显示图像是否为动态图像。当该数据信号对应的显示图像为动态图像，可以执行步骤104，然后再依次执行步骤101所示的发光阶段以及步骤102所示的控制阶段。当该数据信号对应的显示图像不为动态图像时，可以直接执行步骤101，且不再执行步骤102。
也即是，在当前待写入至某个像素单元的一帧数据信号对应的显示图像为动态图像时，可以通过该像素单元的像素电路控制发光单元在一帧的显示时长内，发光一段时间后停止发光，即减小该发光阶段在一帧显示时长内的占空比；在当前一帧的数据信号对应的显示图像不为动态图像时，则可以通过该像素单元的像素电路控制发光单元在一帧的显示时长内持续发光。
步骤104、当该显示图像为动态图像时，根据该控制阶段的持续时长与该发光阶段的持续时长的比值，调整该数据信号的电压值。
当某个像素单元待显示的显示图像为动态图像时，由于驱动装置可以通过该像素单元的像素电路，控制该像素单元的发光单元发光一段时间后停止发光，因此相比于其他显示非动态图像的像素单元，显示动态图像的像素单元的发光时间会减小。为了保证显示装置显示亮度的均一性，对于该显示动态图像的像素单元，驱动装置可以对其待写入的数据信号的电压值进行补偿，以提高该像素单元中发光单元的亮度。
可选的，驱动装置可以根据该控制阶段的持续时长与该发光阶段的持续时长的比值，对该数据信号的电压值进行调整。并且，对该数据信号的电压值调整的幅度的大小，与该比值的大小正相关。即当该控制阶段的持续时长越长，该比值越大时，对该数据信号的电压值的调整幅度也越大；当该控制阶段的持续时长越短，该比值越小时，对该数据信号的电压值的调整幅度也越小。
示例的，图10是本公开实施例提供的一种调整数据信号的电压值的方法流程图，参考图10，该方法可以包括：
步骤1041、根据灰阶与亮度值的转换关系，确定数据信号的显示灰阶所对应的亮度值。
在本公开实施例中，显示装置的驱动装置可以根据预设的灰阶与亮度值的转换关系，计算得到当前一帧的数据信号的显示灰阶对应的亮度值。例如，该灰阶与亮度值的转换关系可以由伽马(gamma)曲线表示。伽马曲线可以用于表示每个像素单元在不同灰阶下的显示亮度。目前常用的伽马曲线一般为伽马2.2曲线，即像素单元的亮度值为灰阶的2.2次幂。
步骤1042、根据该控制阶段的持续时长与该发光阶段的持续时长的比值，对该亮度值进行调整。
进一步的，驱动装置可以根据该控制阶段与发光阶段的持续时长的比值，调整该亮度值，即增加该亮度值。并且，该亮度值的调整幅度的大小与该比值的大小正相关。即控制阶段的持续时长越长，该亮度值的调整幅度越大。
示例的，假设该控制阶段与发光阶段的持续时长的比值为3:1，即该像素单元当前发光阶段的持续时长为正常发光时的持续时长的1/4。因此为了补偿该像素单元的发光亮度，可以将该亮度值调整为原亮度值的4倍。
图11是本公开实施例提供的一种动态图像显示区域以及非动态图像显示区域中像素单元的发光时长的示意图。参考图11可以看出，非动态图像显示区域 中的像素单元在一帧显示时长内的发光时长(即发光阶段的持续时长)可以为4T，而动态图像显示区域中的像素单元在一帧显示时长内的发光时长可以为T，即原发光时长的1/4。并且，从图11还可以看出，该动态图像显示区域中的像素单元的亮度值可以为非动态图像显示区域中的像素单元的亮度值的4倍。由此，可以确保显示装置显示亮度的均一性。
在本公开实施例中，该控制阶段的持续时长与发光阶段的持续时长的比值可以根据显示装置的刷新频率、实际应用需求或者实际待显示的显示图像进行调整，本公开实施例对此不做限定。
例如，当显示装置的刷新频率为60赫兹(HZ)时，一帧图像的显示时长即为16.7毫秒。由于通常情况下，当一帧图像的显示时长降低到到1ms时，人眼即看不到拖影，故可以将发光阶段的持续时长降低至一帧图像的显示时长的1/16，也即是，该控制阶段与发光阶段的持续时长的比值可以为15:1。
或者，驱动装置可以根据系统端(例如图形处理器)发送的待显示的显示图像的动态变化速率调节该控制阶段与发光阶段的持续时长的比值。例如，若待显示的显示图像的动态变化速率较高，则可以控制该比值较大。若待显示的显示图像的动态变化速率较低，则可以控制该比值较小。
其中，待显示的显示图像的动态变化速率可以是指单位时间内待显示的多帧显示图像中，图像内容不同的显示图像的个数。
步骤1043、基于调整后的亮度值所对应的显示灰阶，调整该数据信号的电压值。
最后，驱动装置可以根据灰阶与亮度值的转换关系，对该调整后的亮度值进行转换，得到对应的调整后的显示灰阶。进而，可以根据该调整后的显示灰阶，调整数据信号电压值，由此实现了对该数据信号电压值的补偿。
进一步的，以图3所示的像素电路为例，并以该像素电路中各晶体管为P型晶体管，第一电位相对于第二电位为低电位为例，介绍本公开实施例提供的像素电路的驱动方法。
图12是本公开实施例提供的一种像素电路驱动过程中各信号端的时序图。参考图12可以看出，若某个像素单元中待写入的数据信号所对应的显示图像为动态图像，则在一帧的显示时长IF内，该像素单元中的像素电路的驱动过程可以包括输入阶段T1、发光阶段T2以及控制阶段T3。
在输入阶段T1中，栅线G提供的栅极驱动信号，数据线Vd提供的数据信号以及开关信号端Vr提供的开关信号均为第一电位，发光控制信号端EM提供的使能信号为第二电位。图13是本公开实施例提供的一种像素电路在输入阶段的等效电路图。如图13所示，在该输入阶段T1中，第一控制晶体管M1可以在栅极驱动信号的控制下开启，并向驱动晶体管M0的栅极提供该数据信号，该驱动晶体管M0开启。第一电容器C1存储该数据信号。该开关晶体管Mr可以在开关信号的控制下开启。但由于第二控制晶体管M2在使能信号的控制下关断，电源信号端VDD与驱动晶体管M0的第一极断开连接，因此在该输入阶段T1中，节点A的电位为第一电位，发光单元L不发光。参考图3至图7可以看出，该节点A可以为与开关晶体管Mr的第二极相连的节点。
在发光阶段T2中，如图12所示，该栅线G提供的栅极驱动信号以及数据线Vd提供的数据信号均为第二电位，开关信号端Vr提供的开关信号以及发光控制信号端EM提供的使能信号均为第一电位。图14是本公开实施例提供的一种像素电路在发光阶段的等效电路图。如图14所示，在该发光阶段T2中，第一控制晶体管M1在栅极驱动信号的控制下关断。驱动晶体管M0在第一电容器C1的作用下保持开启状态，第二控制晶体管M2在使能信号的控制下开启，开关晶体管Mr在开关信号的控制下开启。此时，电源信号端VDD与发光单元L之间的信号通路连通，节点A的电位为该电源信号的电位。该驱动晶体管M0可以在数据信号以及电源信号端VDD提供的电源信号的驱动下，为该发光单元L提供驱动信号，例如驱动电流，从而驱动该发光单元L发光。
进一步的，在控制阶段T3中，该开关信号端Vr提供的开关信号跳变为第二电位，其他各信号端提供的信号的电位保持不变。图15是本公开实施例提供的一种像素电路在发光阶段的等效电路图。如图15所示，在该控制阶段T3中，第二控制晶体管M2和驱动晶体管M0保持开启状态，但开关晶体管Mr在开关信号的控制下关断。此时，电源信号端VDD与发光单元L之间的信号通路断开，节点A的电位恢复至第一电位，驱动晶体管M0无法向发光单元L提供驱动信号，该发光单元L停止发光。
可选的，在本公开实施例中，若某个像素单元中待写入的数据信号所对应的显示图像为动态图像，则该驱动装置可以按照预设比值，控制该像素单元中像素电路在该发光阶段T2的持续时长和控制阶段T3的持续时长。
示例的，如图12所示，该控制阶段T3的持续时长与该发光阶段T2的持续时长的比值可以为3:1，即该发光阶段T2的持续时长为原时长的四分之一。相应的，该驱动装置在调整数据信号的电压值时，可以根据该预设比值进行调整。例如可以调整数据信号的电压值，使得该像素单元中发光单元的发光亮度为原亮度的四倍，以确保显示装置的亮度均一性。
需要说明的是，在上述实施例中，均是以各个晶体管为P型晶体管，且第一电位为相对于该第二电位低电位为例进行的说明。当然，该各个晶体管还可以采用N型晶体管，当该各个晶体管采用N型晶体管时，该第一电位相对于该第二电位可以为高电位，且该各个信号端的电位变化可以与图12所示的电位变化相反，即各个信号端提供的信号的时序与图12所示的时序互补。
还需要说明的是，在本公开实施例中，该像素电路可以通过信号线与各个信号端连接。例如，可以通过开关信号线与开关信号端连接，通过电源信号线与电源信号端连接，通过发光控制信号线与发光控制信号端连接，通过复位信号线与复位信号端连接，以及通过初始化信号线与初始化信号端连接。
综上所述，本公开实施例提供了一种像素电路的驱动方法，该方法可以在数据线提供的数据信号所对应的显示图像为动态图像时，先通过驱动子电路和开关子电路控制发光单元发光，然后再通过开关子电路控制该发光单元停止发光，由此可以减少该发光单元的发光时间，从而可以避免动态拖影的产生，保证了显示装置的显示效果。
本公开实施例还提供了一种像素电路的驱动装置，该驱动装置可以用于实现上述驱动方法。
示例的，该驱动装置可以包括：用于向开关信号端提供开关信号的驱动集成电路，用于向栅线提供栅极驱动信号的栅极驱动电路，以及用于向数据线提供数据信号的源极驱动电路。
可选的，该驱动装置还可以包括时序控制器，该时序控制器可以与驱动集成电路连接，且可以用于实现上述步骤103和步骤104所示的方法。其中，该驱动集成电路可以为显示装置中独立设置的电路，也可以与该源极驱动电路集成设置。
本公开实施例还提供了一种阵列基板，该阵列基板可以包括：阵列排布的 多个像素单元，每个像素单元可以包括一个像素电路及与该像素电路连接的发光单元。该多个像素单元中，至少一个像素单元中的像素电路可以为如图1至图7任一所示的像素电路。
可选的，该阵列基板上的多个像素单元中，每个单元像素中的像素电路可以均为如图1至图7任一所示的像素电路。
图16是本公开实施例提供的一种阵列基板的结构示意图，如图16所示，该阵列基板可以包括多个控制区域，每个控制区域中可以设置有至少一个像素单元，且每个控制区域中设置有一条开关信号线连接，每条开关信号线与一个开关信号端连接，且不同开关信号线连接的开关信号端不同。
该多个控制区域中，每个控制区域中设置的各个像素电路可以均与该控制区域中设置的一条开关信号线连接。即每个控制区域的各个像素电路可以共用一条开关信号线。该各个控制区域中的开关信号线可以与显示装置的驱动集成电路(integrated circuit，IC)连接，即开关信号线所连接的开关信号端可以为驱动IC的信号端。该驱动IC可以用于控制每条开关信号线提供的开关信号的电位高低。该每个控制区域的各个像素电路即可在接收到的开关信号的控制下，调整发光单元的发光时长。由此，可以实现对每个控制区域的各像素单元的发光时长的独立控制，有效提高了控制的灵活性。
可选的，参考图16，该多个控制区域可以阵列排布在衬底基板上。该多条开关信号线可以与阵列基板中的数据线平行设置，且可以与数据线通过一次构图工艺形成。
示例的，如图16所示，该阵列基板可以划分为16个控制区域，显示装置的驱动IC连接有16条开关信号线。该16个控制区域中的每个控制区域可以对应设置有一条开关信号线，且该开关信号线与该控制区域内的各个像素电路均连接。例如，参考图16，阵列基板中第一行第一列的控制区域对应设置有开关信号线Vr1，该控制区域内的各个像素电路均与该开关信号线Vr1连接。第四行第四列的控制区域对应设置有开关信号线Vr16，该控制区域内的各个像素电路均与该开关信号线Vr16连接。
图17是相关技术中的像素电路的驱动效果示意图。参考图17可以看出，显示装置中的驱动装置通过像素电路驱动发光单元发光时，不论当前显示的图像是静态图像还是动态图像，每个像素电路均会驱动发光单元在一帧的显示时 长1F内，保持发光状态。在该驱动方式下，显示装置显示动态图像时可能会产生动态拖影。例如，图17所示的显示图像中的小球存在拖影。
而在本公开实施例中，如图18所示，当显示装置当前显示的图像为动态图像时，驱动装置通过像素电路驱动发光单元发光时，可以减小该发光单元在一帧的显示时长1F内保持发光状态的时长，例如可以将发光单元的发光时长降低为原时长的25％。此时，如图18所示，显示图像中的小球不存在拖影，有效改善了显示效果。
由于显示装置显示的显示图像中，可能只有部分图像为动态图像，而其他部分的图像则为静态图像。例如，在图18所示的显示图像中，区域一和区域三显示的图像均为静态图像，仅区域二显示的图像为动态图像。因此，在本公开实施例中，通过将阵列基板划分为多个控制区域，并为每个控制区域分别设置一条开关信号线，可以仅对用于显示动态图像的控制区域的像素单元的发光时长进行控制，而无需调节其他控制区域的像素单元的发光时长，有效提高了控制的精度。并且由于减小像素单元的发光时长后，需要对应提高该像素单元的发光亮度，可能导致显示装置功耗的增加。而仅对部分控制区域的像素单元进行调整，可以有效避免增加显示装置的功耗。
本公开实施例提供一种显示装置，该显示装置可以包括如图16所示的阵列基板。该显示装置可以为：液晶面板、电子纸、OLED面板、AMOLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框或导航仪等任何具有显示功能的产品或部件。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的像素电路和各子电路的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
以上所述仅为本公开的示例性实施例，并不用以限制本公开，凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (20)

  1. 一种像素电路，所述像素电路包括：驱动子电路和开关子电路；
    所述驱动子电路和所述开关子电路串联在电源信号端和发光单元之间；
    所述驱动子电路还分别与栅线和数据线连接，用于在所述栅线提供的栅极驱动信号、所述数据线提供的数据信号以及所述电源信号端提供的电源信号的驱动下，向所述发光单元提供驱动信号；
    所述开关子电路还与开关信号端连接，用于在所述开关信号端提供的开关信号的控制下，控制所述电源信号端与所述发光单元之间的信号通路的通断。
  2. 根据权利要求1所述的像素电路，所述电源信号端与所述开关子电路连接，所述发光单元与所述驱动子电路连接。
  3. 根据权利要求2所述的像素电路，所述开关子电路，包括：开关晶体管；
    所述开关晶体管的栅极与所述开关信号端连接，所述开关晶体管的第一极与所述电源信号端连接，所述开关晶体管的第二极与所述驱动子电路的输入端连接；
    其中，所述第一极和所述第二极分别为源极和漏极中的一极。
  4. 根据权利要求1所述的像素电路，所述电源信号端与所述驱动子电路连接，所述发光单元与所述开关子电路连接。
  5. 根据权利要求4所述的像素电路，所述开关子电路，包括：开关晶体管；
    所述开关晶体管的栅极与所述开关信号端连接，所述开关晶体管的第一极与所述驱动子电路的输出端连接，所述开关晶体管的第二极与所述发光单元连接；
    其中，所述第一极和所述第二极分别为源极和漏极中的一极。
  6. 根据权利要求1所述的像素电路，所述电源信号端和所述发光单元均与所述驱动子电路连接；
    所述驱动子电路包括至少两个串联的晶体管，所述开关子电路串联在至少两个所述晶体管之间。
  7. 根据权利要求6所述的像素电路，所述开关子电路，包括：开关晶体管；
    所述开关晶体管的栅极与所述开关信号端连接，所述开关晶体管的第一极与一个所述晶体管的第二极连接，所述开关晶体管的第二极与另一个所述晶体管的第一极连接；
    其中，所述第一极和所述第二极分别为源极和漏极中的一极。
  8. 根据权利要求1至7任一所述的像素电路，所述驱动子电路，包括：驱动晶体管、第一控制晶体管、第二控制晶体管以及第一电容器；
    所述驱动晶体管、所述第二控制晶体管与所述开关子电路包括的开关晶体管串联在所述电源信号端和所述发光单元之间；
    所述第一控制晶体管的栅极与所述栅线连接，所述第一控制晶体管的第一极与所述数据线连接，所述第一控制晶体管的第二极与所述驱动晶体管的栅极连接；
    所述第二控制晶体管的栅极与发光控制信号端连接；
    所述第一电容器的一端与所述电源信号端连接，所述第一电容器的另一端与所述驱动晶体管的栅极连接。
  9. 根据权利要求1至7任一所述的像素电路，所述驱动子电路，包括：第三控制晶体管、第四控制晶体管、第五控制晶体管、第六控制晶体管、第七控制晶体管、第八控制晶体管、第二电容器以及驱动晶体管；
    所述驱动晶体管、所述第四控制晶体管、所述第七控制晶体管和所述开关子电路包括的开关晶体管串联在所述电源信号端和所述发光单元之间；
    所述第三控制晶体管的栅极与所述栅线连接，所述第三控制晶体管的第一极与所述数据线连接，所述第三控制晶体管的第二极与所述驱动晶体管的第一极连接；
    所述第四控制晶体管的栅极与发光控制信号端连接；
    所述第五控制晶体管的栅极与所述栅线连接，所述第五控制晶体管的第一 极与所述驱动晶体管的第二极连接，所述第五控制晶体管的第二极与所述驱动晶体管的栅极连接；
    所述第六控制晶体管的栅极与复位信号端连接，所述第六控制晶体管的第一极与初始化信号端连接，所述第六控制晶体管的第二极与所述驱动晶体管的栅极连接；
    所述第七控制晶体管的栅极与所述发光控制信号端连接；
    所述第八控制晶体管的栅极与所述栅线连接，所述第八控制晶体管的第一极与所述初始化信号端连接，所述第八控制晶体管的第二极与所述第七控制晶体管的第二极连接；
    所述第二电容器的一端与所述驱动晶体管的栅极连接，另一端与所述电源信号端连接。
  10. 一种像素电路的驱动方法，所述方法包括：
    发光阶段，向开关信号端提供第一电位的开关信号，开关子电路在所述开关信号的控制下，控制电源信号端与发光单元之间的信号通路连通，驱动子电路在数据线提供的数据信号以及所述电源信号端提供电源信号的驱动下向所述发光单元输出驱动信号，所述发光单元发光；其中所述数据信号对应的显示图像为动态图像；
    控制阶段，向所述开关信号端提供第二电位的开关信号，所述开关子电路在所述开关信号的控制下，控制所述电源信号端与所述发光单元之间的信号通路断开，所述发光单元停止发光。
  11. 根据权利要求10所述的方法，在所述发光阶段之前，所述方法还包括：
    检测所述数据信号对应的显示图像是否为动态图像；
    当所述显示图像为动态图像时，依次执行所述发光阶段和所述控制阶段。
  12. 根据权利要求11所述的方法，当所述显示图像为动态图像时，在所述发光阶段之前，所述方法还包括：
    根据所述控制阶段的持续时长与所述发光阶段的持续时长的比值，调整所述数据信号的电压值。
  13. 根据权利要求12所述的方法，所述根据所述控制阶段的持续时长与所述发光阶段的持续时长的比值，调整所述数据信号的电压值，包括：
    根据灰阶与亮度值的转换关系，确定所述数据信号的显示灰阶所对应的亮度值；
    根据所述控制阶段的持续时长与所述发光阶段的持续时长的比值，对所述亮度值进行调整；
    基于调整后的亮度值所对应的显示灰阶，调整所述数据信号的电压值。
  14. 根据权利要求10至13任一所述的方法，在所述发光阶段之前，所述方法还包括：
    输入阶段，向栅线提供第一电位的栅极驱动信号，向数据线提供数据信号，所述驱动子电路在所述栅极驱动信号的控制下，存储所述数据信号。
  15. 一种像素电路的驱动装置，所述驱动装置用于实现如权利要求9至14任一所述的驱动方法。
  16. 一种阵列基板，所述阵列基板包括：阵列排布的多个像素单元，每个所述像素单元包括一个像素电路及与所述像素电路连接的发光单元；
    所述多个像素单元中，至少一个像素单元中的像素电路为如权利要求1至8任一所述的像素电路。
  17. 根据权利要求16所述的阵列基板，所述多个像素单元中，每个单元像素中的像素电路均为如权利要求1至10任一所述的像素电路；
    所述阵列基板包括多个控制区域，每个所述控制区域中设置有至少一个所述像素单元，且每个所述控制区域中设置有一条开关信号线，每条所述开关信号线与一个开关信号端连接，且不同开关信号线连接的开关信号端不同；
    每个所述控制区域中设置的至少一个所述像素单元包括的像素电路均与所述控制区域中设置的一条开关信号线连接。
  18. 根据权利要求17所述的阵列基板，所述多个控制区域阵列排布。
  19. 根据权利要求18所述的阵列基板，每条所述开关信号线与所述阵列基板中的数据线平行设置。
  20. 一种显示装置，所述显示装置包括：如权利要求16至19任一所述的阵列基板，以及如权利要求15所述的驱动装置。
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