WO2019214590A1 - 显示基板及其制作方法、显示装置 - Google Patents
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
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- H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
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- H10K50/80—Constructional details
- H10K50/805—Electrodes
- H10K50/81—Anodes
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
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- H10K50/805—Electrodes
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
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- H10K59/122—Pixel-defining structures or layers, e.g. banks
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
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- H10K59/124—Insulating layers formed between TFT elements and OLED elements
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
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- H10K59/131—Interconnections, e.g. wiring lines or terminals
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
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- H—ELECTRICITY
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
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- H10K71/20—Changing the shape of the active layer in the devices, e.g. patterning
- H10K71/231—Changing the shape of the active layer in the devices, e.g. patterning by etching of existing layers
Definitions
- the present disclosure relates to the field of display technologies, and in particular, to a display substrate, a method for fabricating the same, and a display device.
- a micro display device based on technologies such as Virtual Reality (VR) or Augmented Reality (AR) needs to have high resolution, high brightness, and high contrast.
- an organic light-emitting diode (OLED) display substrate having self-luminous performance is often used for screen display.
- a display substrate has a display area and at least one binding area located at a periphery of the display area.
- the display substrate includes: a plurality of first signal vias disposed in the at least one binding region configured to provide a bonded lead channel; and a plurality of first disposed in the display region configured to provide an electrode lead channel a second signal via; wherein each of the first signal vias has a larger aperture than any of the second signal vias.
- the display substrate further includes a substrate substrate, and a display driving circuit, an insulating layer, and a pixel structure layer stacked on the substrate, wherein the pixel structure layer includes the display A plurality of light emitting devices in the region, the plurality of first signal vias and the plurality of second signal vias being disposed in the insulating layer.
- the display substrate further includes: a binding lead disposed in each of the first signal vias and configured to be bound to an input end of the display driving circuit; and disposed in each of the second signal vias And an electrode lead configured to connect an output end of the display driving circuit and a light emitting device; wherein each of the binding leads has a wire diameter larger than a wire diameter of any one of the electrode leads.
- the insulating layer includes at least two layers of insulator layers disposed in sequence away from the substrate.
- the display substrate further includes a lead sublayer disposed between each adjacent two insulating sublayers, wherein each of the lead sublayers includes a plurality of first connecting leads located in the at least one bonding region, And a plurality of second connection leads located in the display area, and the plurality of first connection leads and the plurality of second connection leads are insulated from each other.
- Each of the first signal vias includes a first signal sub-hole disposed in each layer of the insulator layer.
- Each of the binding leads includes a bonding sub-lead located within each of the first signal sub-holes, and each of the two adjacent bonding sub-leads is electrically connected to a first one of the corresponding one of the corresponding sub-layers connection.
- Each of the second signal vias includes a second signal sub-hole disposed in each of the insulating sub-layers.
- Each of the electrode leads includes an electrode sub-lead within each second signal sub-hole, and each adjacent two of the electrode sub-leads are electrically connected by a second one of the corresponding lead sub-layers.
- a binding sub-lead of each of the binding leads that is closest to the display driving circuit is coupled to an input of the display driving circuit.
- An electrode sub-lead of each of the electrode leads closest to the display driving circuit is connected to an output end of the display driving circuit, and an electrode sub-lead of each of the electrode leads closest to the pixel structure layer is connected to a A light emitting device is described.
- the orthographic projections of at least two of the first signal vias on each of the first signal vias at least partially coincide.
- An orthographic projection of at least two of the second signal sub-holes in each of the second signal vias on the substrate substrate at least partially coincides.
- each of the at least one of the lead sub-layers and each of the second connection leads comprises: a first waterproof vapor lead disposed in a layered manner away from the substrate a portion, an intermediate conductive lead portion, and a second waterproof vapor lead portion.
- each of the at least one of the lead sub-layers and each of the second connection leads are opaque conductive leads.
- the pixel structure layer further includes a pixel defining layer on a surface of the insulating layer that faces away from the display driving circuit.
- the pixel defining layer has a plurality of pixel openings, and each of the pixel openings is provided with the light emitting device.
- each of the light emitting devices includes an oppositely disposed anode and cathode, and a light emitting functional layer between the anode and the cathode, wherein the anode is located in the light emitting functional layer proximate to One side of the insulation.
- the anode includes a stacked titanium layer, a copper aluminum alloy layer, and a titanium nitride layer.
- the base substrate is a single crystal silicon wafer
- the single crystal silicon material contained in the single crystal silicon wafer has a carrier mobility of 500 cm 2 /V ⁇ s to 1500 cm 2 /V. ⁇ s.
- a method of fabricating a display substrate includes: forming a plurality of first signal vias configured to provide a bonding lead channel in at least one bonding region of the display substrate, and forming a configuration to provide an electrode lead channel in a display region of the display substrate a plurality of second signal vias, wherein each of the first signal vias has a larger aperture than any of the second signal vias. Forming a binding lead in each of the first signal vias, and forming an electrode lead in each of the second signal vias, wherein a diameter of each of the bonded leads is larger than a diameter of any of the electrode leads .
- the forming at least one bonding region of the display substrate forms a plurality of first signal vias configured to provide a bonded lead channel, and forming a plurality of electrode lead channels in a display region of the display substrate
- the second signal vias include: providing a substrate.
- a display driving circuit is formed on the base substrate, the display driving circuit including a plurality of input terminals located in the at least one binding region, and a plurality of output terminals located in the display region.
- An insulating layer is formed on a surface of the display driving circuit facing away from the base substrate.
- the plurality of first signal vias are formed in a portion of the insulating layer covering the plurality of input ends, and the at least one first signal via corresponds to one input.
- the plurality of second signal vias are formed in a portion of the insulating layer covering the plurality of output ends, and the at least one second signal via corresponds to an output terminal.
- forming an insulating layer on a surface of the display driving circuit facing away from the substrate substrate further comprising: sequentially forming at least two layers of insulators on a surface of the display driving circuit facing away from the substrate substrate Floor.
- the manufacturing method of the display substrate further includes: forming a lead sub-layer on the insulator layer formed in each of the two adjacent insulating sub-layers in the process of forming each adjacent two-layer insulator layer, wherein
- the lead sublayer includes a plurality of first connection leads located in the at least one bonding region, and a plurality of second connection leads located in the display area, and the plurality of first connection leads and the plurality of The second connecting leads are insulated two by two.
- Forming a first signal via further comprising: forming a first signal sub-hole in each of the insulating sub-layers, and forming the first signal via by each of the at least two insulating sub-layers.
- Forming a binding lead in each of the first signal vias further comprising: forming a bonding sub-lead in each of the first signal sub-holes of the first signal via, wherein each adjacent two The bond sub-leads are connected by a first one of the corresponding lead sub-layers.
- Forming a second signal via further comprising: forming a second signal sub-hole in each of the insulating sub-layers, and forming the second signal via by each of the at least two insulating sub-layers.
- Forming electrode leads in each of the second signal vias further comprising: forming an electrode sub-lead in each of the second signal sub-holes of the second signal via, wherein each of the two adjacent electrodes The sub-leads are connected by a second one of the corresponding lead sub-layers.
- the method of fabricating the display substrate further includes: forming a pixel structure layer on a surface of the insulating layer facing away from the display driving circuit, wherein the pixel structure layer includes a pixel in the display area A plurality of light emitting devices, and one light emitting device is connected to the at least one electrode lead.
- each of the light emitting devices includes an oppositely disposed anode and cathode, and a light emitting functional layer between the anode and the cathode.
- Forming a pixel structure layer on a surface of the insulating layer facing away from the display driving circuit comprising: forming a patterned plurality of anodes on a surface of the insulating layer facing away from the display driving circuit by using a dry etching process A plurality of anodes are located within the display area and each anode is coupled to at least one of the electrode leads.
- a pixel defining layer is formed on a surface of the insulating layer not covered by the plurality of anodes, and a surface of the plurality of anodes facing away from the insulating layer.
- a plurality of pixel openings are formed in the pixel defining layer, and an orthographic projection of each pixel opening on the substrate substrate is located within an orthographic projection of an anode on the substrate.
- a light emitting functional layer in contact with the anode is formed in each of the pixel openings.
- a cathode is formed on each of the luminescent functional layers facing away from the surface of the anode.
- a display device in still another aspect, includes the above display substrate.
- FIG. 1 is a schematic structural view of a display substrate in accordance with some embodiments of the present disclosure.
- FIG. 2 is a cross-sectional view of the display substrate of FIG. 1 taken along line C-C';
- FIG. 3 is a cross-sectional view of the other display substrate shown in FIG. 1 taken along line C-C';
- FIG. 4 is a schematic structural view of a first connecting lead in a display substrate shown in FIG. 3;
- FIG. 5 is a schematic structural view of an anode in a display substrate shown in FIG. 3;
- FIG. 5 is a schematic structural view of an anode in a display substrate shown in FIG. 3;
- FIG. 6 is a cross-sectional view taken along line C-C' of still another display substrate shown in FIG. 1;
- FIG. 7A to 7G are schematic structural views showing the steps of a method for fabricating a display substrate shown in FIG. 6;
- FIG. 8 is a block flow diagram of a method of fabricating a display substrate in accordance with some embodiments of the present disclosure.
- the display driving circuit in the OLED display substrate is bound to the external circuit by wire bonding to effectively reduce the volume of the micro display device.
- the configuration used is that the metal traces bound to the display driving circuit and the external circuit are relatively thin, which tends to cause the metal trace to fall off. Thereby, once the metal trace between the display driving circuit and the external circuit falls off, it is difficult for the micro display device to display normally.
- some embodiments of the present disclosure provide a display substrate.
- the display substrate having a display area AA, AA and a peripheral area located in at least a binding region (e.g., B 1 region in FIG. 1, B 2 region, B 3 or B 4 area of at least a region).
- the display substrate includes: a plurality of first signal vias 50 disposed in the at least one bonding region configured to provide a bonded lead channel; and a portion disposed within the display area AA configured to provide an electrode lead channel A plurality of second signal vias 60; wherein each of the first signal vias 50 has a larger aperture than any of the second signal vias 60.
- the apertures of the plurality of first signal vias 50 are the same or different, and the apertures of the plurality of second signal vias 60 are the same or different, which is not limited in some embodiments of the present disclosure.
- the apertures of the plurality of first signal vias 50 are different, and the apertures of the plurality of second signal vias 60 are different, and the aperture of each of the first signal vias 50 is greater than that of any of the second signal vias 60.
- the aperture means that the smallest aperture of the plurality of first signal vias 50 is greater than the largest aperture of the plurality of second signal vias 60.
- each of the first signal vias 50 is graded (eg, each of the first signal vias 50 is a tapered hole), and the aperture of each of the second signal vias 60 is tapered (eg, each second signal passes)
- the hole 60 is a tapered hole, and the aperture of each of the first signal vias 50 is larger than the aperture of any of the second signal vias 60, which means that the minimum aperture of each of the first signal vias 50 is greater than any second.
- the minimum aperture of signal via 60, or the minimum aperture of each first signal via 50 is greater than the maximum aperture of any second signal via 60.
- the display substrate further includes a substrate substrate 1, and a display driving circuit 2, an insulating layer 3, and a pixel structure layer 4 stacked on the substrate substrate 1, wherein
- the pixel structure layer 4 includes a plurality of light emitting devices 42 located within the display area AA, and the plurality of first signal vias 50 and the plurality of second signal vias 60 are disposed in the insulating layer 3.
- the display substrate is an OLED display substrate, and each of the light-emitting devices 42 in the pixel structure layer 4 is an OLED.
- each of the light-emitting devices 42 in the pixel structure layer 4 is a QLED.
- QLED Quantum Dot Light Emitting Diodes
- the display driving circuit 2 generally includes a plurality of pixel circuits and a plurality of signal lines correspondingly connected to the plurality of pixel circuits, wherein an input end of one of the signal lines corresponds to an input end of the display driving circuit 2, and each The output end of the pixel circuit is connected to a light emitting device 42, and the output end of each pixel circuit corresponds to an output end of the display driving circuit 2.
- the number of first signal vias 50 should be determined according to the type of signal that the display driver circuit 2 needs to transmit, and the number of second signal vias 60 should be determined according to the number of light-emitting devices 42 in the display substrate.
- the display substrate further includes: binding leads 5 disposed in each of the first signal vias 50 and configured to be bound to an input end of the display driving circuit 2, and disposed in each of the second signal vias 60 And configured to connect an output end of the display driving circuit 2 and the electrode lead 6 of a light emitting device 42, wherein each of the binding leads 5 has a wire diameter larger than a wire diameter of any of the electrode leads 6.
- the wire diameter of the binding lead 5 means a diameter perpendicular to the linear extension direction thereof
- the wire diameter of the electrode lead 6 means a diameter perpendicular to the linear extension direction thereof.
- each of the bond wires 5 is formed by filling a conductive material in the corresponding first signal via 50, each electrode lead 6 being formed by filling a conductive material in the corresponding second signal via 60.
- the shape of each of the bond wires 5 matches the shape of the corresponding first signal via 50
- the shape of each electrode lead 6 matches the shape of the corresponding second signal via 60.
- the definition of "the diameter of each of the binding leads 5 is larger than the diameter of any of the electrode leads 6" may refer to the foregoing "the aperture of each of the first signal vias 50 is greater than any second. The relevant definition of the aperture of the signal via 60 is not described herein.
- a plurality of first signal vias are formed in at least one bonding region of the display substrate during the process of manufacturing the display substrate, and the plurality of first signal vias 50 may be used to form a plurality of bonded leads. 5, that is, a plurality of binding leads 5 are fixed to the binding area of the display substrate to perform line bonding on the respective input ends of the display driving circuit 2.
- some embodiments of the present disclosure set the aperture of each of the first signal vias 50 to be larger than the aperture of any of the second signal vias 60 such that the wire diameter of each of the bonding leads 5 is larger than the line of any of the electrode leads 6.
- the diameter, that is, the wire diameter of each of the binding leads 5 can be effectively increased compared with the conventional electrode lead, thereby effectively improving the connection strength and the wear resistance of each of the bonding wires 5, thereby preventing the display substrate from being The binding lead between the display driving circuit 2 and the external circuit is detached.
- the display substrate provided by some embodiments of the present disclosure is applied to a micro display device, particularly a micro mobile display device, the use reliability of the micro display device can be improved, and the micro display device can be normally displayed.
- the insulating layer 3 includes at least two insulating sublayers disposed in a direction away from the substrate 1 (for example, the first insulating sublayer 31 and the second insulator shown in FIG. 3).
- the display substrate further includes a lead sublayer disposed between each adjacent two insulating sublayers, wherein each of the lead sublayers includes a plurality of first connecting leads 71 located in at least one bonding region, and is located in the display area AA a plurality of second connection leads 72, and the plurality of first connection leads 71 and the plurality of second connection leads 72 are insulated from each other.
- the plurality of first connection leads 71 are in one-to-one correspondence with the plurality of first signal vias 50
- the plurality of second connection leads 72 are in one-to-one correspondence with the plurality of second signal vias 60.
- each of the first signal vias 50 includes a first signal sub-hole disposed in each layer of the insulator layer; each binding lead 5 is included in each of the first a binding sub-lead within a signal sub-hole (for example, the first binding sub-lead 51 and the second binding sub-lead 52 shown in FIG. 3, or the first binding sub-lead 51, as shown in FIG.
- the second bonding sub-lead 52 and the third bonding sub-lead 53) are electrically connected by each of the two adjacent bonding sub-leads 71 through one of the corresponding ones of the corresponding sub-layers.
- the length and conductivity of the binding lead 5 can be equivalently increased by using the first connecting lead 71 between each adjacent two bonding sub-leads. That is, the length and the electrical conductivity of the first connecting lead 71 can be regarded as equivalent to the length and conductivity of the binding lead 5.
- the length of the binding lead 5 is increased, the wire diameter of the binding lead 5 can be correspondingly reduced, thereby reducing the binding area.
- the orthographic projection area on the base substrate 1 to achieve miniaturization of the bonding region in the display substrate.
- Each of the second signal vias 60 includes a second signal sub-hole disposed in each of the insulating sub-layers; each of the electrode leads 6 includes an electrode sub-lead within each of the second signal sub-holes (eg, as shown in FIG. 3) First electrode sub-lead 61 and second electrode sub-lead 62, or first electrode sub-lead 61, second electrode sub-lead 62 and third electrode sub-lead 63) as shown in FIG. 6, and each adjacent two The electrode sub-leads are electrically connected by a second one of the corresponding lead sub-layers.
- the length and conductivity of the electrode lead 6 can be equivalently increased by using the second connecting lead 72 between each adjacent two electrode sub-leads, that is, The length and conductivity of the second connecting lead 72 are equivalently regarded as the length and conductivity of the electrode lead 6.
- each of the binding leads 5 is composed of a plurality of binding sub-leads
- the binding sub-lead of each binding lead 5 closest to the display driving circuit 2 is connected to an input terminal of the display driving circuit 2.
- an electrode sub-lead of each of the electrode leads 6 closest to the display driving circuit 2 is connected to an output terminal of the display driving circuit 2, and each electrode lead 6
- the nearest electrode sub-lead of the intermediate-distance pixel structure layer 4 is connected to a light-emitting device 42.
- the insulating layer 3 is composed of at least two insulating sub-layers, such that the thickness of the insulating layer 3 can be effectively increased by increasing the number of layers of the insulating sub-layer to correspondingly increase the formation in the insulating layer 3.
- the holes of each of the first signal vias 50 are deep, thereby protecting the binding leads 5 in the first signal vias 50, and preventing the binding wires 5 from being broken or falling off under the action of external force or long-term wear. .
- the insulating layer 3 includes two insulating sublayers, which are a first insulating sublayer 31 and a second insulating sublayer 32, respectively.
- the display substrate further includes a lead sub-layer between the first insulating sub-layer 31 and the second insulating sub-layer 32.
- the first insulator layer 31 is located between the display driver circuit 2 and the lead sub-layer
- the second insulator sub-layer 32 is located between the lead sub-layer and the pixel structure layer 4.
- the lead sublayer comprises a plurality of first binding region B is connected to the inner lead 71, and is located within the display area AA of the second plurality of connecting lead 72, and the plurality of connection wiring 71 and the first plurality
- the second connection leads 72 are insulated two by two.
- the plurality of first connection leads 71 and the plurality of second connection leads 72 are obtained by patterning a same layer of conductive film, wherein each adjacent two connection leads may pass through the second insulator layer 32. insulation.
- Each of the first signal vias 50 includes two first signal sub-holes, one of which is opened in the first insulating sub-layer 31 and the other is opened in the second insulating sub-layer 32.
- Each of the bonding leads 5 includes a first bonding sub-lead 51 located in a first signal sub-hole of the first insulating sub-layer 31 and a second binding sub-member located in a first signal sub-hole of the second insulating sub-layer 32.
- Lead 52 The first binding sub-lead 51 and the second binding sub-lead 52 in each binding lead 5 are connected by a first connecting lead 71, and each of the first binding sub-leads 51 is away from the second binding sub-lead 52.
- each end is connected to an input end of the display driving circuit 2, and each end of the second binding sub-lead 52 away from the first binding sub-lead 51 is connected to an external circuit.
- the signals transmitted by the external circuit to each of the bonding leads 5 may be sequentially transmitted to the corresponding input terminals of the display driving circuit 2 through the second bonding sub-lead 52, the first connection wiring 71, and the first bonding sub-lead 51.
- each of the second signal vias 60 includes two second signal sub-holes, one of which is opened in the first insulating sub-layer 31 and the other is opened in the second insulating sub-layer 32.
- Each of the electrode leads 6 includes a first electrode sub-lead 61 located in a second signal sub-hole of the first insulating sub-layer 31 and a second electrode sub-lead 62 located in a second signal sub-hole of the second insulating sub-layer 32.
- the first electrode sub-lead 61 and the second electrode sub-lead 62 of each of the electrode leads 6 are connected by a second connection lead 72, and each of the first electrode sub-leads 61 is away from the end of the second electrode sub-lead 62 and the display drive An output of the circuit 2 is connected, and an end of each of the second electrode sub-leads 62 away from the first electrode sub-lead 61 is connected to a light-emitting device 42.
- the signals outputted from each of the output terminals of the display driving circuit 2 may be sequentially transmitted to the corresponding light emitting devices 42 through the first electrode sub-lead 61, the second connection lead 72, and the second electrode sub-lead 62 to drive the light-emitting device 42 to emit light.
- the insulating layer 3 includes three insulating sub-layers, which are a first insulating sub-layer 31, a second insulating sub-layer 32, and a third insulating sub-layer 33, respectively.
- the display substrate further includes a first lead sub-layer between the first insulating sub-layer 31 and the second insulating sub-layer 32, and a second lead sub-layer between the second insulating sub-layer 32 and the third insulating sub-layer 33.
- the first insulator layer 31 is located between the display driving circuit 2 and the first lead sublayer
- the second insulator layer 32 is between the first lead sublayer and the second lead sublayer
- the third insulator layer 33 is located at the second lead sublayer Between the pixel structure layer 4.
- the first lead sub-layer includes a plurality of first connection leads 711 located in the bonding area B 1 , and a plurality of second connection leads 721 located in the display area AA, and a plurality of the first lead sub-layers A connection lead 711 and a plurality of second connection leads 721 are insulated from each other.
- the plurality of first connection leads 711 and the plurality of second connection leads 721 in the first lead sub-layer are obtained by patterning the same layer of conductive film, wherein each adjacent two connection leads may pass
- the second insulator layer 32 is insulated.
- the second lead sub-layer includes a plurality of first connection leads 712 located in the bonding area B 1 , and a plurality of second connection leads 722 located in the display area AA, and a plurality of the second lead sub-layers A connection lead 712 and a plurality of second connection leads 722 are insulated from each other.
- the plurality of first connection leads 712 and the plurality of second connection leads 722 in the second lead sub-layer are obtained by patterning the same layer of conductive film, wherein each adjacent two connection leads may pass
- the third insulator layer 32 is insulated.
- Each of the first signal vias 50 includes three first signal sub-holes, one of which is opened in the first insulating sub-layer 31, one is opened in the second insulating sub-layer 32, and the other is opened in the third insulating sub-layer 33.
- Each of the bonding leads 5 includes a first binding sub-lead 51 located in a first signal sub-hole of the first insulating sub-layer 31, and a second binding sub-hole located in a first signal sub-hole of the second insulating sub-layer 32.
- Leads 52, and a third bond sub-lead 53 located in a first signal sub-hole in the third insulator layer 33.
- each of the binding leads 5 the first binding sub-lead 51 and the second binding sub-lead 52 are connected by one of the first lead sub-layers, the second binding sub-lead 52 and the third binding The stator leads 53 are connected by one of the second lead sub-layers 712. Moreover, one end of each of the first binding sub-leads 51 away from the second binding sub-lead 52 is connected to an input end of the display driving circuit 2, and each of the third binding sub-leads 53 is away from the second binding sub-lead 52. One end is connected to an external circuit.
- the signal transmitted by the external circuit to each of the bonding leads 5 may sequentially pass through the third binding sub-lead 53, the first connecting lead 712 in the second lead sub-layer, the second binding sub-lead 52, and the first lead sub-layer
- the first connection lead 711 and the first binding sub-lead 51 are transferred to corresponding input terminals of the display driving circuit 2.
- each of the second signal vias 60 includes three second signal sub-holes, one of which is opened in the first insulating sub-layer 31, one is opened in the second insulating sub-layer 32, and the other is opened in the third.
- Each of the electrode leads 6 includes a first electrode sub-lead 61 located in a second signal sub-hole of the first insulating sub-layer 31, and a second electrode sub-lead 62 located in a second signal sub-hole of the second insulating sub-layer 32, And a third electrode sub-lead 63 located in a second signal sub-hole of the third insulator layer 33.
- Device 42 is connected.
- the signal outputted from each output terminal of the display driving circuit 2 may sequentially pass through the first electrode sub-lead 61, the second connection lead 721 in the first lead sub-layer, the second electrode sub-lead 62, and the second lead sub-layer
- the two connection leads 722 and the third electrode sub-lead 63 are transmitted to the corresponding light-emitting device 42 to drive the light-emitting device 42 to emit light.
- the orthographic projections of at least two of the first signal vias in each of the first signal vias on the substrate substrate 1 at least partially coincide. That is to say, in each of the first signal sub-holes of each of the first signal vias 50, the orthographic projections of the at least two first signal sub-holes on the substrate substrate 1 coincide or slightly coincide, or at least one The portion of the signal sub-hole that is orthographically projected on the base substrate 1 is located in the orthographic projection of any of the other first signal sub-holes in the same first signal via 50 on the base substrate 1.
- the portion of the at least one first signal sub-hole that is orthographically projected on the substrate substrate 1 is located adjacent to the first one of the first signal sub-holes.
- the orthographic projection on the base substrate 1 it is convenient to realize the electrical connection of the bonding sub-leads in the adjacent two first signal sub-holes.
- the orthographic projections of at least two of the second signal sub-holes in each of the second signal vias on the substrate substrate 1 at least partially coincide. That is to say, in each second signal sub-hole of each second signal via 60, the orthographic projections of at least two second signal sub-holes on the substrate substrate 1 coincide or slightly coincide, or at least one The portion of the two signal sub-holes that are orthographically projected on the base substrate 1 is located in the orthographic projection of any other second signal sub-holes in the same second signal via 60 on the base substrate 1.
- the portion of the at least one second signal sub-hole on the substrate substrate 1 is located adjacent to the adjacent one of the second signal sub-holes.
- the orthographic projection on the base substrate 1 it is convenient to realize the electrical connection of the electrode sub-leads in the adjacent two second signal sub-holes.
- the orthographic projections of the first signal sub-holes in each of the first signal vias on the substrate substrate 1 coincide, and the second signal sub-holes in each of the second signal vias 60 The orthographic projections on the base substrate 1 coincide.
- the insulating layer 3 is composed of a plurality of insulating sub-layers
- each of the first signal sub-holes and each of the second signal sub-holes can be formed in each insulating sub-layer using the same mask, which is advantageous for simplifying the fabrication of the display substrate. Process.
- each of the insulating sub-layers included in the insulating layer 3 is formed using the same insulating light-transmitting material, such as an insulating material such as silicon oxide, silicon nitride or aluminum oxide ceramic.
- each of the at least one layer of lead sub-layers and each of the second connection leads 72 comprise: sequentially stacked in a direction away from the substrate 1
- the first waterproof steam lead portion 701, the intermediate conductive lead portion 702, and the second waterproof vapor lead portion 703 are provided.
- a water vapor isolation space can be constructed for the intermediate conductive lead portion 702, thereby preventing the intermediate conductive lead portion 702 from being corroded by water vapor, thereby It is ensured that each of the first connection leads 71 and each of the second connection leads 72 has a long service life.
- the first waterproof vapor lead portion 701 and the second waterproof vapor lead portion 703 are components of the corresponding connection lead, and the first waterproof vapor lead portion 701 and the second waterproof vapor lead portion 703 are provided with electrical conductivity.
- each of the at least one layer of lead sub-layers and each of the second connection leads 72 are opaque conductive leads, such as made of a metallic conductive material.
- the light emitted by each of the light-emitting devices 42 is irradiated to any of the first connection leads 71 or any of the second connection leads 72, the light is reflected by the first connection leads 71 or the second connection leads 72, thereby improving the display.
- the light utilization efficiency of each of the light-emitting devices 42 in the substrate increases the brightness of the screen displayed on the display substrate.
- the first waterproof vapor lead portion 701 and the second waterproof vapor lead portion 703 are formed using a titanium nitride (TiN) material, and the intermediate conductive lead portion 702 is formed using a copper-aluminum alloy material.
- TiN titanium nitride
- the pixel structure layer 4 further includes a pixel defining layer 41 on the surface of the insulating layer 3 facing away from the display driving circuit 2, the pixel defining layer 41 is generally located in the display area AA, and the pixel defining layer 41 There are a plurality of pixel openings, and a light emitting device 42 is disposed in each pixel opening.
- the pixel defines a layer 41.
- Each of the light-emitting devices 42 includes an anode 421 and a cathode 423 disposed opposite to each other, and a light-emitting function layer 422 between the anode 421 and the cathode 423, and the anode 421 is located on a side of the light-emitting function layer 422 close to the insulating layer 3.
- Each electrode lead 6 is connected to a light emitting device 42 in the sense that each electrode lead 6 is connected to the anode 421 of a light emitting device 42.
- the anode 421 of each of the light-emitting devices 42 is formed by dry etching, which is advantageous for forming the anode 421 having a smaller size, thereby forming the light-emitting device 42 having a smaller size, that is, miniaturization of the light-emitting device 42 is achieved.
- the graininess of the screen displayed by the micro display device can be reduced by using the high resolution of the display substrate.
- the anode 421 of each of the light emitting devices 42 includes at least one of a titanium (Ti) layer, a copper aluminum alloy (AlCu) layer, or a titanium nitride (TiN) layer.
- the anode 421 of each of the light emitting devices 42 includes a titanium (Ti) layer 4211, a copper aluminum alloy (AlCu) layer 4212, and a titanium nitride (TiN) layer 4213 which are stacked.
- the titanium (Ti) layer 4211 in each anode 421 is connected to the corresponding electrode lead 6, or the titanium nitride (TiN) layer 4213 in each anode 421 is connected to the corresponding electrode lead 6, either.
- the base substrate 1 of the display substrate is a single crystal silicon wafer (that is, a single crystal silicon substrate), and the single crystal silicon material contained in the single crystal silicon wafer
- the carrier mobility is 500 cm 2 /V ⁇ s to 1500 cm 2 /V ⁇ s, so that the display driving circuit 2 formed on the surface of the base substrate 1 has a relatively fast signal transmission speed.
- the screen refresh frequency of the micro display device can be effectively improved, thereby ensuring that the displayed image of the micro display device provides a better visual experience for the user.
- the method for manufacturing the display substrate includes S100 to S200.
- the at least one display substrate binding region e.g. a region B in FIG. 1
- the at least one display substrate binding region is formed configured to provide a plurality of signal channels of the first binding leads through hole 50 is formed in a display area configured to provide a substrate AA
- S100 includes S110-S140.
- a substrate substrate 1 is provided.
- the material of the substrate substrate 1 can be selected according to actual needs, which is not limited in some embodiments of the present disclosure.
- the base substrate 1 is formed using a single crystal silicon material having a material carrier mobility of 500 cm 2 /V ⁇ s to 1500 cm 2 /V ⁇ s.
- a display driving circuit 2 is formed on the base substrate 1, and the display driving circuit 2 includes a plurality of input ends located in at least one binding area (for example, the area B1 in FIG. 1 ), and is located in the display area AA. Multiple outputs.
- the display driving circuit 2 generally includes a plurality of pixel circuits and a plurality of signal lines connected to each of the pixel circuits, wherein an input end of one of the signal lines corresponds to an input end of the display driving circuit 2, and an output end of each of the pixel circuits is A light emitting device 42 is connected, and an output end of each pixel circuit corresponds to an output terminal of the display driving circuit 2.
- an insulating layer 3 is formed on the surface of the display driving circuit 2 facing away from the base substrate 1.
- S140 forming a plurality of first signal vias 50 in a portion of the insulating layer 3 covering the plurality of input ends, and at least one first signal via 50 corresponding to one input end; covering the plurality of outputs at the insulating layer 3 A plurality of second signal vias 60 are formed in the portion, and at least one second signal via 60 corresponds to one output.
- the wire diameter of the binding lead 5 means a diameter perpendicular to the linear extension direction thereof
- the wire diameter of the electrode lead 6 means a diameter perpendicular to the linear extension direction thereof.
- the manufacturing method of the display substrate provided by some embodiments of the present disclosure is the same as that of the display substrate provided by some of the above embodiments, and details are not described herein.
- the method of fabricating the display substrate further includes S300.
- a pixel structure layer 4 is formed on the surface of the insulating layer 3 facing away from the display driving circuit 2, the pixel structure layer 4 includes a plurality of light emitting devices 42 located in the display area AA, and one light emitting device 42 is connected to at least one of the electrode leads 6.
- each of the light emitting devices 42 includes an oppositely disposed anode 421 and cathode 423, and a light emitting functional layer 422 between the anode 421 and the cathode 423.
- the above S300 includes S310 to S340.
- the pixel defining layer 41 is generally formed on a surface of the insulating layer 3 located within the display area AA.
- a cathode 423 is formed on a surface of each of the light-emitting function layers 422 facing away from the anode 421.
- S130 further includes: sequentially forming at least two layers of insulator layers on a surface of the display driving circuit 2 facing away from the substrate 1 .
- the manufacturing method of the display substrate further includes: forming a lead sub-layer on the insulator layer formed first in each adjacent two-layer insulator layer in the process of forming each adjacent two-layer insulator layer, wherein
- the lead sub-layer includes a plurality of first connection leads 71 located in at least one binding region, and a plurality of second connection leads 72 located within the display area AA, and the plurality of first connection leads 71 and the plurality of The second connection leads 72 are insulated from each other.
- Forming a first signal via 50 in S140 further comprising: forming a first signal sub-hole in each of the insulating sub-layers, and forming the first signal from each of the at least two insulating sub-layers Via 50.
- the binding lead 5 is formed in each of the first signal vias 50 in the S200, and further includes: forming a binding sub-lead in each of the first signal sub-holes of the first signal via 50, wherein Each adjacent two bond sub-leads are connected by a first one of the corresponding lead sub-layers 71.
- forming a second signal via 60 in S140 further comprising: forming a second signal sub-hole in each of the insulating sub-layers, wherein the second signal sub-holes in the at least two insulating sub-layers form the The second signal is via 60.
- forming the electrode lead 6 in each of the second signal vias 60 in S200 further comprising: forming an electrode sub-lead in each of the second signal sub-holes of the second signal via 60, wherein each Adjacent two electrode sub-leads are connected by a second one of the corresponding lead sub-layers.
- the number of the lead sub-layers in the substrate is one, and the manufacturing method of the OELD display substrate is as follows.
- a base substrate 1 is provided.
- a display driving circuit 2 is formed on the base substrate 1.
- An insulating sublayer that is, a first insulating sublayer 31 is formed on the surface of the display driving circuit 2 facing away from the base substrate 1.
- a plurality of first signal sub-holes are formed in a portion of the first insulator layer 31 located in the at least one bonding region, and a plurality of second signal sub-holes are formed in a portion of the first insulator layer 31 located within the display region AA.
- a first bonding sub-lead 51 is formed in each of the first signal sub-holes in the first insulating sub-layer 31, and each of the first bonding sub-leads 51 is connected to an input terminal of the display driving circuit 2.
- First electrode sub-leads 61 are formed in each of the second signal sub-holes of the first insulating sub-layer 31, and each of the first electrode sub-leads 61 is connected to an output terminal of the display driving circuit 2.
- the lead sub-layer Forming a layer of lead sub-layers on a surface of the first insulator layer 31 facing away from the substrate 1 , the lead sub-layer comprising a plurality of first connecting leads 71 located in the at least one binding region, and located in the display area AA a plurality of second connection leads 72, the plurality of first connection leads 71 and the plurality of second connection leads 72 are insulated from each other, wherein each of the first connection leads 71 is connected to a first binding sub-lead 51
- Each of the second connection leads 72 is connected to a first electrode sub-lead 61.
- an insulator layer i.e., a second insulator layer 32, is formed on the surface of the lead sub-layer facing away from the base substrate 1.
- a second insulator layer is formed on the surface of the lead sub-layer facing away from the base substrate 1.
- a plurality of second signal sub-holes is formed in each of the first signal sub-holes in the second insulator layer 32, and each of the second bond sub-leads 52 is connected to a first connection lead 71.
- a second electrode sub-lead 62 is formed in each of the second signal sub-holes of the second insulator layer 32, and each of the second electrode sub-leads 62 is connected to a second connection lead 72.
- a pixel structure layer 4 is formed on a surface of the second insulator layer 32 facing away from the base substrate 1, and each of the light-emitting devices 42 in the pixel structure layer 4 is connected to one of the second insulator sub-layers 62.
- the insulating layer 3 is composed of the first insulating sub-layer 31 and the second insulating sub-layer 32.
- Each of the bonding leads 5 is electrically connected by a first bonding sub-lead 51 located in the first insulating sub-layer 31 and a second bonding sub-lead 52 located in the second insulating sub-layer 32.
- Each of the electrode leads 6 is electrically connected by a first electrode sub-lead 61 located in the first insulating sub-layer 31 and a second electrode sub-lead 62 located in the second insulating sub-layer 32.
- the display substrate is fabricated as follows.
- a base substrate 1 is provided.
- a display driving circuit 2 is formed on the base substrate 1.
- An insulating sublayer that is, a first insulating sublayer 31 is formed on the surface of the display driving circuit 2 facing away from the base substrate 1.
- a plurality of first signal sub-holes are formed in a portion of the first insulator layer 31 located in the at least one bonding region, and a plurality of second signal sub-holes are formed in a portion of the first insulator layer 31 located within the display region AA.
- a first bonding sub-lead 51 is formed in each of the first signal sub-holes in the first insulating sub-layer 31, and each of the first bonding sub-leads 51 is connected to an input terminal of the display driving circuit 2.
- First electrode sub-leads 61 are formed in each of the second signal sub-holes of the first insulating sub-layer 31, and each of the first electrode sub-leads 61 is connected to an output terminal of the display driving circuit 2.
- a layer of lead sub-layers that is, a first lead sub-layer is formed on the surface of the first insulator sub-layer 31 facing away from the substrate 1, and the first lead sub-layer is disposed in the at least one bonding region.
- the plurality of first connection leads 711 and the plurality of second connection leads 721 of the first lead sub-layer are insulated from each other, and each of the first connection leads 711 is connected to a first binding sub-lead 51, each second The connection lead 721 is connected to a first electrode sub-lead 61.
- an insulator layer that is, a second insulator layer 32, is further formed on the surface of the first lead sub-layer facing away from the base substrate 1.
- a plurality of second signal sub-holes are formed in portions of the second connection leads 721.
- a second bond sub-lead 52 is formed in each of the first signal sub-holes in the second insulator layer 32, and each of the second bond sub-leads 52 is connected to one of the first lead sub-layers.
- a second electrode sub-lead 62 is formed in each of the second signal sub-holes of the second insulator layer 32, and each of the second electrode sub-leads 62 is connected to one of the first lead sub-layers.
- a layer of lead sub-layers that is, a second lead sub-layer is formed on the surface of the second insulator layer 32 facing away from the substrate 1 , and the second lead sub-layer is disposed in the at least one bonding region.
- the plurality of first connection leads 712 and the plurality of second connection leads 721 of the second lead sub-layer are insulated from each other, and each of the first connection leads 712 is connected to a second binding sub-lead 52, each second The connection lead 722 is connected to a second electrode sub-lead 62.
- an insulator layer that is, a third insulator layer 33, is further formed on the surface of the second lead sub-layer facing away from the base substrate 1.
- a third insulator layer 33 is further formed on the surface of the second lead sub-layer facing away from the base substrate 1.
- a pixel structure layer 4 is formed on the surface of the third insulator layer 33 facing away from the base substrate 1, and each of the light-emitting devices 42 in the pixel structure layer 4 is connected to one of the third insulator sub-layers 33. 63.
- a plurality of first signal sub-holes are formed in portions of the third insulating sub-layer 33 covering the plurality of first connection leads 712 in the second lead sub-layer, and each of the third insulating sub-layers 33
- a third bond sub-lead 53 is formed in each of the first signal sub-holes, and each of the third bond sub-leads 53 is connected to one of the second lead sub-layers.
- the step of "forming a plurality of first signal sub-holes in the third insulating sub-layer 33" is performed in a step of "forming a plurality of second signal sub-holes in the third insulating sub-layer 33".
- the step of “forming a plurality of first signal sub-holes in the third insulator layer 33” is performed after the fabrication of the pixel structure layer 4 is completed, and the subsequent fabrication of the pixel structure layer 4 can be avoided for each of the first signal sub-holes, or
- the bonding sub-lead formed in each of the first signal sub-holes causes contamination, which is advantageous for simplifying the manufacturing process of the display substrate and improving the production yield of the display substrate.
- step of "forming a plurality of first signal sub-holes in the third insulator layer 33" is performed simultaneously with the step of "forming a plurality of second signal sub-holes in the third insulator layer 33", for example, as shown in FIG. 7E. It is also allowed to perform in the structure shown. Some embodiments of the present disclosure do not limit this.
- each bonding sub-lead after the bonding sub-leads are formed in each of the first signal sub-holes, the exposed surface of each bonding sub-lead needs to be chemically mechanically ground so that the bonding sub-leads are The exposed surface is relatively flat, which facilitates subsequent fabrication of the display substrate.
- the electrode sub-lead in each second signal sub-hole it is necessary to perform chemical mechanical polishing on the exposed surface of each electrode sub-lead, so that the exposed surface of each electrode sub-lead is relatively flat, thereby facilitating the display substrate.
- at least one of each of the binding sub-leads or each of the electrode sub-leads is formed by a metal wire bonding process.
- Some embodiments of the present disclosure also provide a display device including the display substrate provided by some of the above embodiments.
- the beneficial effects that can be achieved by the display device provided by the embodiments of the present disclosure are the same as those of the display substrate provided by the above embodiments, and are not described herein.
- the display device is an immersive near-eye display product based on VR or AR technology, including a display function such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, a smart glasses, or a smart helmet.
- a display function such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, a smart glasses, or a smart helmet.
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Abstract
Description
Claims (17)
- 一种显示基板,具有一显示区域和位于所述显示区域的外围的至少一个绑定区域;所述显示基板包括:位于所述至少一个绑定区域内的配置为提供绑定引线通道的多个第一信号过孔;以及,位于所述显示区域内的配置为提供电极引线通道的多个第二信号过孔;其中,每个第一信号过孔的孔径均大于任一第二信号过孔的孔径。
- 根据权利要求1所述的显示基板,还包括衬底基板、以及层叠设置在所述衬底基板上的显示驱动电路、绝缘层和像素结构层,其中,所述像素结构层包括位于所述显示区域内的多个发光器件,所述多个第一信号过孔和所述多个第二信号过孔设置在所述绝缘层中;所述显示基板还包括:设置在每个第一信号过孔内且配置为与所述显示驱动电路的一输入端绑定在一起的绑定引线;以及,设置在每个第二信号过孔内且配置为连接所述显示驱动电路的一输出端与一发光器件的电极引线;其中,每个所述绑定引线的线径均大于任一所述电极引线的线径。
- 根据权利要求2所述的显示基板,其中,所述绝缘层包括沿远离所述衬底基板的方向依次设置的至少两层绝缘子层;所述显示基板还包括设置在每相邻的两层绝缘子层之间的引线子层,其中,每层所述引线子层包括位于所述至少一个绑定区域内的多个第一连接引线、以及位于所述显示区域内的多个第二连接引线,且所述多个第一连接引线和所述多个第二连接引线两两绝缘;所述每个第一信号过孔包括设置在每层绝缘子层中的一第一信号子孔;每个所述绑定引线包括位于每个第一信号子孔内的一绑定子引线,且每相 邻的两个所述绑定子引线通过对应引线子层中的一个第一连接引线电连接;所述每个第二信号过孔包括设置在每层绝缘子层中的一第二信号子孔;每个所述电极引线包括位于每个第二信号子孔内的一电极子引线,且每相邻的两个所述电极子引线通过对应引线子层中的一个第二连接引线电连接。
- 根据权利要求3所述的显示基板,其中,所述每个绑定引线中距离所述显示驱动电路最近的绑定子引线连接所述显示驱动电路的一输入端;所述每个电极引线中距离所述显示驱动电路最近的电极子引线连接所述显示驱动电路的一输出端,所述每个电极引线中距离所述像素结构层最近的电极子引线连接一所述发光器件。
- 根据权利要求3所述的显示基板,其中,所述每个第一信号过孔中的至少两个第一信号子孔在所述衬底基板上的正投影至少部分重合;所述每个第二信号过孔中的至少两个第二信号子孔在所述衬底基板上的正投影至少部分重合。
- 根据权利要求3所述的显示基板,其中,至少一层所述引线子层中的每个第一连接引线和每个第二连接引线均包括:沿远离所述衬底基板的方向依次层叠设置的第一防水汽引线部、中间导电引线部和第二防水汽引线部。
- 根据权利要求3所述的显示基板,其中,至少一层所述引线子层中的每个第一连接引线和每个第二连接引线均为不透光的导电引线。
- 根据权利要求2~7任一项所述的显示基板,其中,所述像素结构层还包括位于所述绝缘层的背离所述显示驱动电路的表面的像素界定层,所述像素界定层具有多个像素开口,每个像素开口内设置有一所述发光器件。
- 根据权利要求2~8任一项所述的显示基板,其中,每个所述发光 器件包括相对设置的阳极和阴极、以及位于所述阳极和所述阴极之间的发光功能层,所述阳极位于所述发光功能层靠近所述绝缘层的一侧。
- 根据权利要求9所述的显示基板,其中,所述阳极包括钛层、铜铝合金层或氮化钛层中的至少一层。
- 根据权利要求2~10任一项所述的显示基板,其中,所述衬底基板为单晶硅晶圆,所述单晶硅晶圆所含有的单晶硅材料的载流子迁移率为500cm 2/V·s~1500cm 2/V·s。
- 一种显示基板的制作方法,包括:在显示基板的至少一个绑定区域形成配置为提供绑定引线通道的多个第一信号过孔,在显示基板的一显示区域形成配置为提供电极引线通道的多个第二信号过孔,其中,每个第一信号过孔的孔径均大于任一第二信号过孔的孔径;在每个第一信号过孔内形成绑定引线,在每个第二信号过孔内形成电极引线,其中,每个所述绑定引线的线径均大于任一所述电极引线的线径。
- 根据权利要求12所述的显示基板的制作方法,其中,所述在显示基板的至少一个绑定区域形成配置为提供绑定引线通道的多个第一信号过孔,在显示基板的一显示区域形成配置为提供电极引线通道的多个第二信号过孔,包括:提供一衬底基板;在所述衬底基板上形成显示驱动电路,所述显示驱动电路包括位于所述至少一个绑定区域内的多个输入端,以及位于所述显示区域内的多个输出端;在所述显示驱动电路的背离所述衬底基板的表面形成绝缘层;在所述绝缘层覆盖所述多个输入端的部分中形成所述多个第一信号过孔,且至少一个第一信号过孔对应一个输入端;在所述绝缘层覆盖所述多个输出端的部分中形成所述多个第二信号过孔,且至少一个第二信号过孔 对应一个输出端。
- 根据权利要求13所述的显示基板的制作方法,其中,在所述显示驱动电路的背离所述衬底基板的表面形成绝缘层,还包括:在所述显示驱动电路的背离所述衬底基板的表面,依次形成至少两层绝缘子层;所述显示基板的制作方法,还包括:在形成每相邻两层绝缘子层的过程中,在所述每相邻两层绝缘子层中先形成的绝缘子层上形成一引线子层,其中,所述引线子层包括位于所述至少一个绑定区域内的多个第一连接引线、以及位于所述显示区域内的多个第二连接引线,且所述多个第一连接引线和所述多个第二连接引线两两绝缘;形成一个第一信号过孔,还包括:在每层绝缘子层中形成一个第一信号子孔,由所述至少两层绝缘子层中的各第一信号子孔构成所述第一信号过孔;在每个第一信号过孔内形成绑定引线,还包括:在所述第一信号过孔的每个第一信号子孔内形成一绑定子引线,其中,每相邻的两个所述绑定子引线通过对应引线子层中的一个第一连接引线连接;形成一个第二信号过孔,还包括:在每层绝缘子层中形成一个第二信号子孔,由所述至少两层绝缘子层中的各第二信号子孔构成所述第二信号过孔;在每个第二信号过孔内形成电极引线,还包括:在所述第二信号过孔的每个第二信号子孔内形成一电极子引线,其中,每相邻的两个所述电极子引线通过对应引线子层中的一个第二连接引线连接。
- 根据权利要求13或14所述的显示基板的制作方法,还包括:在所述绝缘层背离所述显示驱动电路的表面形成像素结构层,所述像素结构层包括位于所述显示区域内的多个发光器件,且一个发光器件连接至少一条电极引线。
- 根据权利要求15所述的显示基板的制作方法,其中,每个所述发光器件包括相对设置的阳极和阴极、以及位于所述阳极和所述阴极之间的发光功能层;在所述绝缘层背离所述显示驱动电路的表面形成像素结构层,包括:采用干法刻蚀工艺,在所述绝缘层背离所述显示驱动电路的表面形成图案化的多个阳极,所述多个阳极位于显示区域内,且每个阳极连接至少一条电极引线;在所述绝缘层未被所述多个阳极覆盖的表面形成具有多个像素开口的像素界定层,其中,每个像素开口在所述衬底基板上的正投影位于一个阳极在所述衬底基板上的正投影内;在所述每个像素开口内形成与阳极接触的发光功能层;在每个发光功能层背离所述阳极的表面形成阴极。
- 一种显示装置,包括权利要求1~11任一项所述显示基板。
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