WO2019214572A1 - 阵列基板、显示面板、显示装置及制备阵列基板的方法 - Google Patents

阵列基板、显示面板、显示装置及制备阵列基板的方法 Download PDF

Info

Publication number
WO2019214572A1
WO2019214572A1 PCT/CN2019/085654 CN2019085654W WO2019214572A1 WO 2019214572 A1 WO2019214572 A1 WO 2019214572A1 CN 2019085654 W CN2019085654 W CN 2019085654W WO 2019214572 A1 WO2019214572 A1 WO 2019214572A1
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
stripper
array substrate
layer
emitting layer
Prior art date
Application number
PCT/CN2019/085654
Other languages
English (en)
French (fr)
Inventor
王琳琳
闫光
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/618,495 priority Critical patent/US11239293B2/en
Publication of WO2019214572A1 publication Critical patent/WO2019214572A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/60—Forming conductive regions or layers, e.g. electrodes

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to an array substrate, a display panel, a display device, and a method of preparing an array substrate.
  • the display device based on the top emission type organic light emitting diode (OLED) has become the main research direction due to the advantages of higher aperture ratio and ability to realize light extraction by using the microcavity effect.
  • Top-emitting OLEDs require a top electrode to have good light transmission.
  • highly transparent electrode materials such as indium tin oxide (ITO) and indium zinc oxide (IZO) tend to be less conductive than metals.
  • an array substrate including: a substrate substrate; a pixel defining layer formed on the substrate substrate, wherein the pixel defining layer includes a patterned retaining wall and a plurality of openings separated by walls, respective surfaces of the respective retaining walls facing away from the base substrate are provided with corresponding first grooves; a light-emitting layer formed on the retaining wall and the plurality of openings, wherein The light emitting layer conformally covers respective first grooves of each of the retaining walls to form a corresponding second groove; and a plurality of auxiliary electrodes, each of which is formed in a corresponding one of the second grooves.
  • the array substrate further includes: a first conductive layer covering the light emitting layer and the plurality of auxiliary electrodes.
  • the first conductive layer is connected to the plurality of auxiliary electrodes.
  • the array substrate further includes: a surface modifier formed on a groove bottom of each of the second grooves.
  • the surface modifier has electrical conductivity and adhesion.
  • Corresponding auxiliary electrodes are formed on the surface modifier in the respective second grooves.
  • the surface modifying agent comprises an aqueous solution of 3,4-ethylenedioxythiophene.
  • a display panel comprising the array substrate as described above.
  • a display device comprising the display panel as described above.
  • a method of fabricating an array substrate comprising: providing a substrate; forming a pixel defining layer on the substrate, wherein the pixel defining layer comprises a patterned barrier a wall and a plurality of openings separated by the retaining wall, respective surfaces of the retaining walls facing away from the base substrate are provided with corresponding first grooves; in the retaining wall and the plurality of openings Forming a light-emitting layer, wherein the light-emitting layer conformally covers respective first grooves of each of the retaining walls to form a corresponding second groove; providing a stripper template, wherein the stripper plate is provided with a plurality of protruding auxiliary electrodes Pressing the stripper onto the luminescent layer, wherein the corresponding auxiliary electrode is aligned with the corresponding second recess; and removing the stripping template, embedding and affixing the corresponding auxiliary electrode Engaged inside the corresponding second groove.
  • the method further comprises: providing a surface modifier at a groove bottom of each of the second grooves before the pressing the template onto the light-emitting layer.
  • the surface modifier has electrical conductivity and adhesion.
  • the surface modifying agent comprises an aqueous solution of 3,4-ethylenedioxythiophene.
  • the providing the stripper comprises: providing a stripper substrate having a plurality of protrusions on the surface; providing an anti-blocking agent on a corresponding surface of the plurality of protrusions facing away from the stripper substrate; Corresponding auxiliary electrodes are formed on the anti-blocking agents on the respective protrusions.
  • the providing an anti-blocking agent comprises spin-coating tetrafluoroethylene on the respective surfaces of the plurality of protrusions facing away from the stripper substrate.
  • the providing an anti-blocking agent comprises: preparing a perfluorooctyltrichlorosilane by vapor deposition on the respective surfaces of the plurality of protrusions facing away from the stripper substrate.
  • the method further includes forming a first conductive layer covering the light emitting layer and the auxiliary electrode.
  • the first conductive layer is connected to the auxiliary electrode.
  • FIG. 1 is a schematic cross-sectional view of an array substrate in accordance with an embodiment of the present disclosure
  • FIG. 2 is a flow chart of a method of preparing an array substrate in accordance with an embodiment of the present disclosure
  • FIG. 3 is a schematic cross-sectional view showing a structure obtained after forming a pixel defining layer on a base substrate in the method of FIG. 2;
  • FIG. 4 is a schematic cross-sectional view showing a structure obtained by covering a pixel defining layer with a light emitting layer in the method of FIG. 2;
  • Figure 5 is a schematic illustration of the process of preparing a stripper in the method of Figure 2;
  • Figure 6 is a schematic cross-sectional view of the structure obtained by pressing a stripper onto a light-emitting layer and then removing the stripper in the method of Figure 2;
  • FIG. 7 is a schematic block diagram of a display device in accordance with an embodiment of the present disclosure.
  • first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/ Some should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer Thus, a first element, component, region, layer, or section, which is discussed below, may be referred to as a second element, component, region, layer or section without departing from the teachings of the disclosure.
  • under and under can encompass both the ⁇ RTIgt; Terms such as “before” or “before” and “after” or “following” may be used, for example, to indicate the order in which light passes through the elements.
  • the device can be oriented in other ways (rotated 90 degrees or in other orientations) and the spatially relative descriptors used herein interpreted accordingly.
  • a layer is referred to as “between two layers,” it may be a single layer between the two layers, or one or more intermediate layers may be present.
  • a scheme of using a metal as an auxiliary electrode of a top electrode of an OLED has been proposed, in which an auxiliary electrode is formed by photolithography in a region covered by a black matrix (BM).
  • the scheme may include a BM process, a color film (CF) process, an auxiliary electrode process, a spacer (PS) process, and an ITO process.
  • FIG. 1 shows a schematic cross-sectional view of an array substrate 100 in accordance with an embodiment of the present disclosure.
  • the array substrate 100 includes a base substrate 101, a pixel defining layer 102, a light emitting layer 104, and a plurality of auxiliary electrodes 106.
  • the base substrate 101 may be made of any suitable material such as glass or resin.
  • a pixel circuit (not shown) arranged in an array is formed inside the base substrate 101.
  • Each pixel circuit includes a plurality of thin film transistors (TFTs) and other electronic components (eg, capacitors) and is used to drive OLED illumination in a corresponding sub-pixel region.
  • TFTs thin film transistors
  • other electronic components eg, capacitors
  • the pixel defining layer 102 is formed on the base substrate 101.
  • the pixel defining layer 102 includes a patterned retaining wall 102a and a plurality of openings 102b separated by the retaining walls. Each opening 102b defines a light emitting region of a corresponding sub-pixel region.
  • a corresponding surface of each of the retaining walls 102a facing away from the base substrate 101 is provided with a corresponding first recess 103.
  • the first groove has a depth in the range of, for example, 600 nm to 900 nm.
  • the size of the first groove 103 depends on the size of the retaining wall 102a.
  • the pixel defining layer 102 may be formed of a material such as polyimide, polymethyl methacrylate, organosilane, or the like.
  • a light emitting layer 104 is formed on the retaining wall 102a and in the plurality of openings 102b.
  • the luminescent layer 104 conformally covers the respective first grooves 103 of the respective retaining walls 102a to form respective second grooves 105.
  • the illuminating layer 104 follows the surface of the corresponding first groove 103 of each of the retaining walls 102a, so that the corresponding respective orthographic projections of the respective second grooves 105 on the pixel defining layer 102 are located in the corresponding first grooves 103.
  • the luminescent layer 104 is shown as extending continuously in Figure 1, this is merely illustrative and illustrative. In practice, the luminescent layer 104 is patterned, and different sub-pixel regions may include respective luminescent layers that are separated from one another.
  • a plurality of auxiliary electrodes 106 are formed in the respective second grooves 105.
  • the auxiliary electrode 106 may be made of a conductive metal such as aluminum or silver. Aluminum or silver ensures good electrical conductivity.
  • the auxiliary electrode 106 has a thickness in the range of, for example, 400 nm to 800 nm, preventing the auxiliary electrode 106 from being too thin to be easily broken.
  • the array substrate 100 further includes a first conductive layer 108 covering the light emitting layer 104 and the plurality of auxiliary electrodes 106.
  • the first conductive layer 108 may be made of a material having high transparency and conductivity such as indium tin oxide (ITO) or indium zinc oxide (IZO).
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • the first conductive layer 108 typically has a thickness between 100 nm and 200 nm.
  • the first conductive layer 108 is connected to the plurality of auxiliary electrodes 106. Due to the presence of the auxiliary electrode 106, the conductivity of the first conductive layer 108 is improved.
  • each of the second grooves 105 is covered with a surface modifier 107.
  • respective auxiliary electrodes 106 are formed on the surface modifier 107 in the corresponding second groove 105.
  • the surface modifier 107 has electrical conductivity and adhesion.
  • Surface modifier 107 can include, for example, an aqueous solution of 3,4-ethylenedioxythiophene.
  • the adhesion of the surface modifier 107 to the metal is higher than the adhesion of the metal to other organic materials, such that the auxiliary electrode 106 is more easily adhered to the interior of the second recess 105 without the phenomenon of peripheral adhesion.
  • the pixel circuit inside the base substrate 101 is not shown.
  • the second conductive layer on the upper surface of the base substrate 101 is also not shown.
  • the second conductive layer is patterned into a plurality of electrodes arranged in an array to correspond to respective sub-pixel regions. These electrodes can be used as anodes of the OLED, and each anode can be connected to the drain of the driving TFT of a corresponding pixel circuit in the substrate substrate 101.
  • a second conductive layer is first formed and patterned on the base substrate 101, and then the pixel defining layer 102 is formed and patterned on the patterned second conductive layer, forming a barrier wall 102a and an opening 102b .
  • the conductivity of the top electrode (first conductive layer 108) of the OLED is improved by forming the auxiliary electrode 106 in the second recess 105.
  • the preparation process of the array substrate 100 is simple, and the production efficiency is improved.
  • FIGS. 3 through 6 show schematic cross-sectional views of structures resulting from various steps in method 200. The processing flow of the method 200 will be described below with reference to FIGS. 2 through 6.
  • a substrate substrate such as the substrate substrate 101 shown in FIG. 3 is provided.
  • a pixel defining layer 102 is formed on the base substrate 101.
  • the pixel defining layer 102 includes a patterned retaining wall 102a and a plurality of openings 102b separated by the retaining wall 102a.
  • the pixel defining layer 102 can be formed by a one-step lithography process.
  • the pixel defining layer 102 may be made of a photoresist material such as polyimide, polymethyl methacrylate or organosilane.
  • a corresponding surface of each of the retaining walls 102a facing away from the base substrate 101 is provided with a corresponding first recess 103.
  • Each of the first grooves 103 may be formed on the corresponding retaining wall 102a by laser etching.
  • the first groove 103 may be formed by laser irradiation of the retaining wall 102a using a mask, or the first groove 103 may be formed by directly controlling laser irradiation to the retaining wall 102a. In other embodiments, the first groove 103 can also be formed by other means.
  • a second conductive layer (not shown) has been formed on the base substrate 101 before the pixel defining layer 102 is formed.
  • the second conductive layer is patterned into a plurality of electrodes that can be used as an anode of the OLED.
  • a light-emitting layer 104 is formed.
  • a light emitting layer 104 is formed on the retaining wall 102a and in the plurality of openings 102b as shown in FIG.
  • the luminescent layer 104 conformally covers the respective first grooves 103 of the respective retaining walls 102a to form respective second grooves 105.
  • An orthographic projection of the second recess 105 on the pixel defining layer 102 is located within the first recess 103.
  • a stripper template 501 is provided.
  • the stripper plate 501 is provided with a plurality of protruding auxiliary electrodes 106.
  • an exemplary preparation process for stripper template 501 includes the following steps.
  • a stripper substrate 501a having a plurality of protrusions 501b on the surface is provided.
  • Corresponding protrusions 501b correspond to corresponding second grooves 105.
  • an anti-blocking agent 502 is provided on a corresponding surface of the plurality of protrusions 501b facing away from the stripper substrate 501a.
  • corresponding auxiliary electrodes 106 are formed on the anti-blocking agent 502 on the respective protrusions 501b.
  • providing the anti-blocking agent 502 can include spin coating tetrafluoroethylene on a respective surface of the plurality of protrusions 501b that faces away from the stripper substrate 501a.
  • perfluorooctyltrichlorosilane is prepared by vapor deposition at a respective surface of the plurality of protrusions 501b facing away from the stripper substrate 501a to provide an anti-blocking agent 502.
  • the anti-blocking agent 502 can prevent the auxiliary electrode 106 from being detached from the stripper plate 501 after subsequent assembly into the second groove 105, i.e., preventing the auxiliary electrode 106 from sticking too tightly to the protrusion 501a.
  • a surface modifier 107 is formed on the bottom of the groove of the second groove 105.
  • the surface modifier 107 may be formed on the groove bottom of the second groove 105 by using an organic solution having conductivity and adhesion, as shown in FIG. This enables the auxiliary electrode layer 106 on the stripper plate 501 to be more easily adhered inside the second groove 105 without affecting the conductivity of the auxiliary electrode layer 106.
  • PDOT-PSS 3,4-ethylenedioxythiophene
  • the stripper 501 is pressed onto the luminescent layer 104.
  • the corresponding auxiliary electrode 106 is aligned with the corresponding second groove 105.
  • the prepared stripper 501 is pressed onto the luminescent layer 104 at a certain pressure (for example, 0 to 40 bar) for a certain period of time at a certain temperature (for example, 60 degrees Celsius to 90 degrees Celsius). (for example, 50s to 70s).
  • the pressure, temperature, and press time values can be adjusted based on the size of the auxiliary electrode 106 and the depth of the second groove 105.
  • step 207 the stripper plate 501 is removed, and the corresponding auxiliary electrode 106 is embedded and attached to the inside of the corresponding second groove 105. Specifically, when a certain pressure is applied to the stripper plate 501, it is removed from the light emitting layer 104, and the corresponding auxiliary electrode 106 is attached to the inside of the corresponding second groove 105, as shown in FIG. .
  • the first conductive layer 108 overlying the luminescent layer 104 and the plurality of auxiliary electrodes 106 is formed, resulting in an array template 100 as shown in FIG.
  • the thickness of the first conductive layer 108 is, for example, in the range of 1200 angstroms (A) to 1800 ⁇ .
  • the preparation process of the array substrate is simplified, and the array substrate preparation is improved. s efficiency.
  • the conductivity of the first conductive layer 108 (the top electrode of the OLED) is increased due to the presence of the auxiliary electrode 106.
  • FIG. 7 is a schematic block diagram of a display device 700 in accordance with an embodiment of the present disclosure.
  • the display device 700 can be any product or component having a display function, such as a cell phone, tablet, television, display, notebook computer, digital photo frame, navigator, and the like.
  • the display device 700 includes a display panel 710, a gate driver 720 configured to output a gate scan signal to the display panel 710, a data driver 730 configured to output a data voltage to the display panel 710, and configured to control Gate driver 720 and timing controller 740 of data driver 730.
  • the display panel 710 includes an array substrate 712 and an opposite substrate 714 opposite to the array substrate 712.
  • the opposite substrate 714 may be a cover.
  • the array substrate 712 includes a plurality of sub-pixel regions PX arranged in an array. Each of the sub-pixel regions PX is located at a corresponding intersection of the plurality of gate lines GL and the plurality of data lines DL. Each sub-pixel region includes a thin film transistor (not shown) and other associated electronic components.
  • the array substrate 712 can take the form of any of the array substrate 100 described above with respect to Figures 1 through 6 and variations thereof.
  • the gate driver 720 is electrically connected to the first ends of the respective gate lines GL, thereby sequentially applying gate scan signals to the respective gate lines GL.
  • the gate driver 720 can be mounted directly (eg, integrated) in the array substrate 712.
  • the gate driver 720 may be connected to the display panel 710 through a Tape Carrier Package (TCP).
  • TCP Tape Carrier Package
  • the data driver 730 is electrically connected to the first ends of the respective data lines DL to output data voltages to the respective data lines DL.
  • data driver 730 can include a plurality of data driven chips operating in parallel.
  • the timing controller 740 controls the operation of the gate driver 720 and the data driver 730. Specifically, the timing controller 740 outputs data control signals and image data to control the driving operation of the data driver 730, and outputs a gate control signal to control the driving operation of the gate driver 720. The data control signal and image data are applied to the data driver 730. A gate control signal is applied to the gate driver 720.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

一种阵列基板，包括衬底基板、像素界定层、发光层和多个辅助电极。像素界定层形成在所述衬底基板上，并且包括图案化的挡墙和由所述挡墙分隔出的多个开口。各挡墙的背离所述衬底基板的相应表面被提供有相应的第一凹槽。发光层形成在所述挡墙上和所述多个开口中。所述发光层适形地覆盖各挡墙的相应第一凹槽以形成相应的第二凹槽。每个辅助电极形成在相应的一个第二凹槽内。

Description

阵列基板、显示面板、显示装置及制备阵列基板的方法
相关申请的交叉引用
本申请要求2018年5月11日提交的中国专利申请第201810449127.X号的优先权，其公开内容通过引用全部并入本文。
技术领域
本公开涉及显示技术领域，特别是涉及一种阵列基板、显示面板、显示装置及制备阵列基板的方法。
背景技术
基于顶发射型有机发光二极管(OLED)的显示设备，由于更高的开口率和能够利用微腔效应实现光取出的能力等优点，成为目前研究的主要方向。顶发射型OLED要求顶电极必须具备良好的光透过率。遗憾的是，氧化铟锡(ITO)、氧化铟锌(IZO)等透明度高的电极材料，其导电性能往往弱于金属。
发明内容
根据本公开的一方面，提供了一种阵列基板，包括：衬底基板；像素界定层，形成在所述衬底基板上，其中所述像素界定层包括图案化的挡墙和由所述挡墙分隔出的多个开口，各挡墙的背离所述衬底基板的相应表面被提供有相应的第一凹槽；发光层，形成在所述挡墙上和所述多个开口中，其中所述发光层适形地覆盖各挡墙的相应第一凹槽以形成相应的第二凹槽；以及多个辅助电极，每个辅助电极形成在相应的一个第二凹槽内。
在一些实施例中，所述阵列基板还包括：覆盖所述发光层和所述多个辅助电极的第一导电层。所述第一导电层与所述多个辅助电极连接。
在一些实施例中，所述阵列基板还包括：形成在各第二凹槽的槽底的表面修饰剂。所述表面修饰剂具有导电性和粘附性。相应的辅助电极形成在相应的第二凹槽内的表面修饰剂上。
在一些实施例中，所述表面修饰剂包括3，4-乙烯二氧噻吩的水溶液。
根据本公开的另一方面，提供了一种显示面板，包括如上所述的阵列基板。
根据本公开的再另一方面，提供了一种显示装置，包括如上所述的显示面板。
根据本公开的又再另一方面，提供了一种制备阵列基板的方法，包括：提供衬底基板；在所述衬底基板上形成像素界定层，其中所述像素界定层包括图案化的挡墙和由所述挡墙分隔出的多个开口，各挡墙的背离所述衬底基板的相应表面被提供有相应的第一凹槽；在所述挡墙上和所述多个开口中形成发光层，其中所述发光层适形地覆盖各挡墙的相应第一凹槽以形成相应的第二凹槽；提供脱模板，其中所述脱模板被提供有多个凸出的辅助电极；将所述脱模板压合在所述发光层上，其中相应的辅助电极与相应的第二凹槽对位贴合；并且移除所述脱模板，使所述相应的辅助电极嵌入并贴合在所述相应的第二凹槽的内部。
在一些实施例中，所述方法在所述将所述脱模板压合在所述发光层上之前还包括：在各第二凹槽的槽底提供表面修饰剂。所述表面修饰剂具有导电性和粘附性。
在一些实施例中，所述表面修饰剂包括3，4-乙烯二氧噻吩的水溶液。
在一些实施例中，所述提供脱模板包括：提供表面具有多个凸起的脱模板基底；在所述多个凸起的背离所述脱模板基底的相应表面上提供抗粘连剂；并且在相应的凸起上的所述抗粘连剂上形成相应的辅助电极。
在一些实施例中，所述提供抗粘连剂包括：在所述多个凸起的背离所述脱模板基底的所述相应表面上旋涂四氟乙烯。
在一些实施例中，所述提供抗粘连剂包括：在所述多个凸起的背离所述脱模板基底的所述相应表面上用气相沉积法制备全氟辛基三氯硅烷。
在一些实施例中，所述方法还包括：形成覆盖所述发光层和所述辅助电极的第一导电层。所述第一导电层与所述辅助电极连接。
附图说明
图1是根据本公开实施例的一种阵列基板的示意性截面图；
图2是根据本公开实施例的一种制备阵列基板的方法的流程图；
图3是在图2的方法中在衬底基板上形成像素界定层后得到的结构的示意性截面图；
图4是在图2的方法中在像素界定层上覆盖有发光层后得到的结构的示意性截面图；
图5是在图2的方法中制备脱模板的过程的示意图；
图6是在图2的方法中将脱模板压合在发光层上并且然后移除脱模板所得到的结构的示意性截面图；并且
图7是根据本公开实施例的显示装置的示意性框图。
具体实施方式
将理解的是，尽管术语第一、第二、第三等等在本文中可以用来描述各种元件、部件、区、层和/或部分，但是这些元件、部件、区、层和/或部分不应当由这些术语限制。这些术语仅用来将一个元件、部件、区、层或部分与另一个区、层或部分相区分。因此，下面讨论的第一元件、部件、区、层或部分可以被称为第二元件、部件、区、层或部分而不偏离本公开的教导。
诸如“在...下面”、“在...之下”、“较下”、“在...下方”、“在...之上”、“较上”等等之类的空间相对术语在本文中可以为了便于描述而用来描述如图中所图示的一个元件或特征与另一个(些)元件或特征的关系。将理解的是，这些空间相对术语意图涵盖除了图中描绘的取向之外在使用或操作中的器件的不同取向。例如，如果翻转图中的器件，那么被描述为“在其他元件或特征之下”或“在其他元件或特征下面”或“在其他元件或特征下方”的元件将取向为“在其他元件或特征之上”。因此，示例性术语“在...之下”和“在...下方”可以涵盖在...之上和在...之下的取向两者。诸如“在...之前”或“在...前”和“在...之后”或“接着是”之类的术语可以类似地例如用来指示光穿过元件所依的次序。器件可以取向为其他方式(旋转90度或以其他取向)并且相应地解释本文中使用的空间相对描述符。另外，还将理解的是，当层被称为“在两个层之间”时，其可以是在该两个层之间的唯一的层，或者也可以存在一个或多个中间层。
本文中使用的术语仅出于描述特定实施例的目的并且不意图限制 本公开。如本文中使用的，单数形式“一个”、“一”和“该”意图也包括复数形式，除非上下文清楚地另有指示。将进一步理解的是，术语“包括”和/或“包含”当在本说明书中使用时指定所述及特征、整体、步骤、操作、元件和/或部件的存在，但不排除一个或多个其他特征、整体、步骤、操作、元件、部件和/或其群组的存在或添加一个或多个其他特征、整体、步骤、操作、元件、部件和/或其群组。如本文中使用的，术语“和/或”包括相关联的列出项目中的一个或多个的任意和全部组合。
将理解的是，当元件或层被称为“在另一个元件或层上”、“连接到另一个元件或层”、“耦合到另一个元件或层”或“邻近另一个元件或层”时，其可以直接在另一个元件或层上、直接连接到另一个元件或层、直接耦合到另一个元件或层或者直接邻近另一个元件或层，或者可以存在中间元件或层。相反，当元件被称为“直接在另一个元件或层上”、“直接连接到另一个元件或层”、“直接耦合到另一个元件或层”、“直接邻近另一个元件或层”时，没有中间元件或层存在。然而，在任何情况下“在...上”或“直接在...上”都不应当被解释为要求一个层完全覆盖下面的层。
本文中参考本公开的理想化实施例的示意性图示(以及中间结构)描述本公开的实施例。正因为如此，应预期例如作为制造技术和/或公差的结果而对于图示形状的变化。因此，本公开的实施例不应当被解释为限于本文中图示的区的特定形状，而应包括例如由于制造导致的形状偏差。因此，图中图示的区本质上是示意性的，并且其形状不意图图示器件的区的实际形状并且不意图限制本公开的范围。
除非另有定义，本文中使用的所有术语(包括技术术语和科学术语)具有与本公开所属领域的普通技术人员所通常理解的相同含义。将进一步理解的是，诸如那些在通常使用的字典中定义的之类的术语应当被解释为具有与其在相关领域和/或本说明书上下文中的含义相一致的含义，并且将不在理想化或过于正式的意义上进行解释，除非本文中明确地如此定义。
已经提出了将金属作为OLED的顶电极的辅助电极的方案，其中辅助电极采用光刻的方法制作在黑矩阵(BM)覆盖的区域。该方案可以包括BM工序、彩膜(CF)工序、辅助电极工序、隔垫物(PS)工 序和ITO工序。这些工序工艺过程复杂，成本较高，不适合量产。为使本公开的上述目的、特征和优点能够更加明显易懂，下面结合附图详细描述本公开的实施例。
图1示出了根据本公开实施例的一种阵列基板100的示意性截面图。
参考图1，该阵列基板100包括衬底基板101、像素界定层102、发光层104、以及多个辅助电极106。
衬底基板101可以由任何适当的材料(例如玻璃或树脂)制成。在衬底基板101的内部形成有呈阵列布置的像素电路(未示出)。每个像素电路包括多个薄膜晶体管(TFT)和其他电子元件(例如，电容器)，并且用于驱动一个对应的子像素区域中的OLED发光。
像素界定层102形成在衬底基板101上。像素界定层102包括图案化的挡墙102a和由所述挡墙分隔出的多个开口102b。每个开口102b限定一个对应的子像素区域的发光区。各挡墙102a的背离所述衬底基板101的相应表面被提供有相应的第一凹槽103。第一凹槽具有例如为600nm-900nm的范围中的深度。第一凹槽103的尺寸取决于挡墙102a的尺寸而定。像素界定层102可以由例如聚酰亚胺、聚甲基丙烯酸甲酯类、有机硅烷等材料形成。
发光层104形成在挡墙102a上和所述多个开口102b中。发光层104适形地覆盖各挡墙102a的相应第一凹槽103以形成相应的第二凹槽105。具体地，发光层104跟随各挡墙102a的相应第一凹槽103的表面，使得结果得到的各个第二凹槽105在像素界定层102上的相应正投影位于相应的第一凹槽103内。将理解的是，虽然发光层104在图1中被示出为连续地延伸，但是这只是示意性的和说明性的。在实践中，发光层104被图案化，并且不同的子像素区域可以包括彼此分离的相应发光层。
多个辅助电极106形成在各自的第二凹槽105内。辅助电极106可以由例如铝或者银的导电金属制成。铝或银能够保证良好的导电性。辅助电极106具有例如为400nm-800nm的范围中的厚度，防止辅助电极106太薄而容易碎裂。
在该实施例中，阵列基板100还包括覆盖所述发光层104和所述多个辅助电极106的第一导电层108。第一导电层108可以由例如氧化 铟锡(ITO)或氧化铟锌(IZO)等透明度高且具有导电性的材料制成。第一导电层108典型地具有在100nm-200nm之间的厚度。所述第一导电层108与所述多个辅助电极106连接。由于辅助电极106的存在，第一导电层108的导电性得以被提高。
在该实施例中，每个第二凹槽105的底部覆盖有表面修饰剂107。如图1所示，相应的辅助电极106形成在相应的第二凹槽105内的表面修饰剂107上。表面修饰剂107具有导电性和粘附性。表面修饰剂107可以包括例如3，4-乙烯二氧噻吩的水溶液。有利地，表面修饰剂107与金属的粘附性高于金属与其他有机材料的粘附性，使得辅助电极106更容易粘连到第二凹槽105内部，而不会发生周边粘连的现象。
将理解的是，为了不模糊本公开的主题，阵列基板100中的某些元件未示出于图1中。例如，衬底基板101的内部的像素电路未被示出。而且，衬底基板101的上表面上的第二导电层也未被示出。第二导电层被图案化为呈阵列布置的多个电极以对应各自的子像素区域。这些电极可以用作OLED的阳极，并且每个阳极可以与衬底基板101内的一个对应的像素电路的驱动TFT的漏极连接。在实践中，第二导电层首先被形成并且图案化在衬底基板101上，并且然后像素界定层102在经图案化的第二导电层上被形成并且图案化，形成挡墙102a和开口102b。
在阵列基板100中，通过在第二凹槽105内形成辅助电极106，提高了OLED的顶电极(第一导电层108)的导电率。而且，如稍后将进一步描述的，阵列基板100的制备过程简单，提高了生产效率。
图2示出了根据本公开实施例的一种制备阵列基板的方法200的流程图，并且图3至6示出了方法200中的各个步骤所得到的结构的示意性截面图。下面参考图2至6描述方法200的处理流程。
在步骤201，提供衬底基板，例如图3中所示的衬底基板101。
在步骤202，在所述衬底基板101上形成像素界定层102。如图3所示，所述像素界定层102包括图案化的挡墙102a和由所述挡墙102a分隔出的多个开口102b。可采取一步光刻的工艺形成像素界定层102。像素界定层102可以由聚酰亚胺、聚甲基丙烯酸甲酯类、有机硅烷等光刻胶材料制成。各挡墙102a的背离所述衬底基板101的相应表面被提供有相应的第一凹槽103。各第一凹槽103可以通过激光刻蚀的方式 形成在相应的挡墙102a上。具体地，可以采用掩膜版通过激光照射挡墙102a形成所述第一凹槽103，也可以直接控制激光照射到挡墙102a形成所述第一凹槽103。在其他实施例中，也可以通过其他方式形成第一凹槽103。
如之前描述的，在形成像素界定层102之前，第二导电层(未示出)已经被形成在衬底基板101上。所述第二导电层被图案化成多个电极，其可以用作OLED的阳极。
在步骤203，形成发光层104。发光层104形成在所述挡墙102a上和所述多个开口102b中，如图4所示。发光层104适形地覆盖各挡墙102a的相应第一凹槽103以形成相应的第二凹槽105。所述第二凹槽105在所述像素界定层102上的正投影位于所述第一凹槽103内。
在步骤204，提供脱模板501。所述脱模板501被提供有多个凸出的辅助电极106。参照图5，脱模板501的一个示例制备过程包括以下步骤。
首先，提供表面(图5中，下表面)具有多个凸起501b的脱模板基底501a。相应的凸起501b与相应的第二凹槽105对应。接着，在所述多个凸起501b的背离所述脱模板基底501a的相应表面上提供抗粘连剂502。然后，在相应的凸起501b上的所述抗粘连剂502上形成相应的辅助电极106。
在一些实施例中，提供抗粘连剂502可以包括：在所述多个凸起501b的背离所述脱模板基底501a的相应表面上旋涂四氟乙烯。替换地，在一些实施例中，在所述多个凸起501b的背离所述脱模板基底501a的相应表面用气相沉积法制备全氟辛基三氯硅烷，以便提供抗粘连剂502。
有利地，抗粘连剂502可以避免辅助电极106在后续装配入第二凹槽105之后无法从脱模板501脱落，即防止辅助电极106与凸起501a粘贴过于紧密。
在步骤205，在所述第二凹槽105的槽底形成表面修饰剂107。在该实施例中，可以利用具有导电性和粘附性的有机溶液在第二凹槽105的槽底形成表面修饰剂107，如图6所示。这使得脱模板501上的辅助电极层106能够更容易地粘连在第二凹槽105内部，而不影响辅助电极层106的导电性。在一些实施例中，可以选择3，4-乙烯二氧噻吩 (PEDOT-PSS)作为表面修饰剂107。
在步骤206，将所述脱模板501压合在所述发光层104上。具体地，相应的辅助电极106与相应的第二凹槽105对位贴合。更具体地，在一定的温度(例如，60摄氏度至90摄氏度)的氛围中，以一定的压力(例如，0bar至40bar)将制备好的脱模板501压合在发光层104上持续一定的时间(例如，50s至70s)。压力、温度和压合时间值可根据辅助电极106的尺寸和第二凹槽105的深度进行调节。
在步骤207，移除所述脱模板501，使相应的辅助电极106嵌入并贴合在相应的第二凹槽105的内部。具体地，当对脱模板501施加一定的压力后，将其从发光层104移除，此时相应的辅助电极106便会贴合在相应的第二凹槽105的内部，如图6所示。
在一些实施例中，形成覆盖发光层104和多个辅助电极106的第一导电层108，得到如图1所示的阵列模板100。第一导电层108的厚度在例如1200埃(A)至1800A的范围中。
在方法200中，通过在像素界定层102的挡墙102a上形成第一凹槽103，并且通过在第二凹槽105内形成辅助电极106，阵列基板的制备过程得以简化，提高了阵列基板制备的效率。有利地，由于辅助电极106的存在，提高了第一导电层108(OLED的顶电极)的导电率。
图7是根据本公开实施例的显示装置700的示意性框图。作为示例而非限制，该显示装置700可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
参照图7，显示装置700包括显示面板710、被配置成向显示面板710输出栅极扫描信号的栅极驱动器720、被配置成向显示面板710输出数据电压的数据驱动器730、以及被配置成控制栅极驱动器720和数据驱动器730的时序控制器740。
显示面板710包括阵列基板712和与阵列基板712相对的对向基板714。在有机发光二极管显示装置的情况下，对向基板714可以是盖板。阵列基板712包括呈阵列排布的多个子像素区域PX。各子像素区域PX位于多条栅极线GL和多条数据线DL的相应交叉处。每个子像素区域都包括薄膜晶体管(未示出)和其他相关联的电子元件。阵列基板712可以采取上面关于图1至6描述的阵列基板100及其变型中 的任一个的形式。
栅极驱动器720电连接到各栅极线GL的第一端，从而顺序地向各栅极线GL施加栅极扫描信号。在一些示例性实施例中，栅极驱动器720可以被直接安装(例如，集成)在阵列基板712中。替换地，栅极驱动器720可以通过带式载体封装(Tape Carrier Package，TCP)连接至显示面板710。
数据驱动器730电连接至各数据线DL的第一端，以将数据电压输出至各数据线DL。在一些实施例中，数据驱动器730可以包括多个并行操作的数据驱动芯片。
时序控制器740控制栅极驱动器720和数据驱动器730的操作。具体地，时序控制器740输出数据控制信号和图像数据以控制数据驱动器730的驱动操作，以及输出栅极控制信号以控制栅极驱动器720的驱动操作。数据控制信号和图像数据被施加至数据驱动器730。栅极控制信号被施加至栅极驱动器720。
以上对本公开所提供的一种阵列基板、显示面板、显示装置及阵列基板的制备方法，进行了详细介绍。本文中应用了具体个例对本公开的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本公开的核心思想。本领域的一般技术人员可以依据本公开的思想对具体实施方式做出变型和修改。因此，所描述的实施例不应理解为对本公开的限制。
虽然前述的各方法实施例，为了简单描述起见，被描述为一系列的动作组合，但是本领域技术人员应该知悉，本公开并不受所描述的动作顺序的限制，因为某些步骤可以采用其他顺序或者同时进行而不偏离本公开的范围。本领域技术人员也应该知悉，说明书中所描述的实施例均属于特定实施例，所涉及的动作和模块并不一定是本公开所必须的。因此，应当理解，本发明的实施例并不限于所公开的特定实施例，并且修改和其他的实施例也意图被包含在所附权利要求书的范围内。

Claims (13)

  1. 一种阵列基板，包括：
    衬底基板；
    像素界定层，形成在所述衬底基板上，其中所述像素界定层包括图案化的挡墙和由所述挡墙分隔出的多个开口，各挡墙的背离所述衬底基板的相应表面被提供有相应的第一凹槽；
    发光层，形成在所述挡墙上和所述多个开口中，其中所述发光层适形地覆盖各挡墙的相应第一凹槽以形成相应的第二凹槽；以及
    多个辅助电极，每个辅助电极形成在相应的一个第二凹槽内。
  2. 根据权利要求1所述的阵列基板，还包括：
    覆盖所述发光层和所述多个辅助电极的第一导电层，
    其中，所述第一导电层与所述多个辅助电极连接。
  3. 根据权利要求1所述的阵列基板，还包括：
    形成在各第二凹槽的槽底的表面修饰剂，
    其中所述表面修饰剂具有导电性和粘附性，并且
    其中相应的辅助电极形成在相应的第二凹槽内的表面修饰剂上。
  4. 根据权利要求3所述的阵列基板，其中所述表面修饰剂包括3，4-乙烯二氧噻吩的水溶液。
  5. 一种显示面板，包括如权利要求1-4中任一所述的阵列基板。
  6. 一种显示装置，包括如权利要求5所述的显示面板。
  7. 一种制备阵列基板的方法，包括：
    提供衬底基板；
    在所述衬底基板上形成像素界定层，其中所述像素界定层包括图案化的挡墙和由所述挡墙分隔出的多个开口，各挡墙的背离所述衬底基板的相应表面被提供有相应的第一凹槽；
    在所述挡墙上和所述多个开口中形成发光层，其中所述发光层适形地覆盖各挡墙的相应第一凹槽以形成相应的第二凹槽；
    提供脱模板，其中所述脱模板被提供有多个凸出的辅助电极；
    将所述脱模板压合在所述发光层上，其中相应的辅助电极与相应的第二凹槽对位贴合；并且
    移除所述脱模板，使所述相应的辅助电极嵌入并贴合在所述相应 的第二凹槽的内部。
  8. 根据权利要求7所述的方法，在所述将所述脱模板压合在所述发光层上之前，还包括：
    在各第二凹槽的槽底提供表面修饰剂，其中所述表面修饰剂具有导电性和粘附性。
  9. 根据权利要求8所述的方法，其中所述表面修饰剂包括3，4-乙烯二氧噻吩的水溶液。
  10. 根据权利要求8所述的方法，所述提供脱模板包括：
    提供表面具有多个凸起的脱模板基底；
    在所述多个凸起的背离所述脱模板基底的相应表面上提供抗粘连剂；并且
    在相应的凸起上的所述抗粘连剂上形成相应的辅助电极。
  11. 根据权利要求9所述的方法，其中所述提供抗粘连剂包括：
    在所述多个凸起的背离所述脱模板基底的所述相应表面上旋涂四氟乙烯。
  12. 根据权利要求9所述的方法，其中所述提供抗粘连剂包括：
    在所述多个凸起的背离所述脱模板基底的所述相应表面上用气相沉积法制备全氟辛基三氯硅烷。
  13. 根据权利要求7所述的方法，还包括：
    形成覆盖所述发光层和所述辅助电极的第一导电层，
    其中，所述第一导电层与所述辅助电极连接。
PCT/CN2019/085654 2018-05-11 2019-05-06 阵列基板、显示面板、显示装置及制备阵列基板的方法 WO2019214572A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US16/618,495 US11239293B2 (en) 2018-05-11 2019-05-06 Array substrate, display panel, display device and method for preparing array substrate

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201810449127.X 2018-05-11
CN201810449127.XA CN108511502B (zh) 2018-05-11 2018-05-11 一种阵列基板、显示面板、显示装置及阵列基板的制备方法

Publications (1)

Publication Number Publication Date
WO2019214572A1 true WO2019214572A1 (zh) 2019-11-14

Family

ID=63400299

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/085654 WO2019214572A1 (zh) 2018-05-11 2019-05-06 阵列基板、显示面板、显示装置及制备阵列基板的方法

Country Status (3)

Country Link
US (1) US11239293B2 (zh)
CN (1) CN108511502B (zh)
WO (1) WO2019214572A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108511502B (zh) 2018-05-11 2021-08-31 京东方科技集团股份有限公司 一种阵列基板、显示面板、显示装置及阵列基板的制备方法
CN110635064A (zh) * 2019-09-24 2019-12-31 武汉华星光电半导体显示技术有限公司 显示面板以及显示装置
CN111834419A (zh) * 2020-06-10 2020-10-27 云谷（固安）科技有限公司 显示屏及其制备方法、显示终端

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050236629A1 (en) * 2004-04-07 2005-10-27 Kwan-Hee Lee Top emission organic light emitting diode display using auxiliary electrode to prevent voltage drop of upper electrode and method of fabricating the same
CN102623644A (zh) * 2011-11-29 2012-08-01 友达光电股份有限公司 显示面板及其制作方法
CN107093680A (zh) * 2017-05-04 2017-08-25 京东方科技集团股份有限公司 金属辅助电极及使用其的显示器件的制造方法
CN107393945A (zh) * 2017-07-31 2017-11-24 京东方科技集团股份有限公司 一种有机发光二极管显示基板及其制作方法、显示装置
CN108511502A (zh) * 2018-05-11 2018-09-07 京东方科技集团股份有限公司 一种阵列基板、显示面板、显示装置及阵列基板的制备方法

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4016144B2 (ja) * 2003-09-19 2007-12-05 ソニー株式会社 有機発光素子およびその製造方法ならびに表示装置
JP4165478B2 (ja) * 2003-11-07 2008-10-15 セイコーエプソン株式会社 発光装置及び電子機器
KR101097338B1 (ko) * 2010-03-05 2011-12-21 삼성모바일디스플레이주식회사 유기 발광 표시 장치
TWI510372B (zh) * 2010-12-30 2015-12-01 Lg Chemical Ltd 電極、含其之電子裝置及其製造方法
CN102169969A (zh) * 2011-03-10 2011-08-31 中国科学院理化技术研究所 有机电致发光器件的阳极修饰方法
US9647229B2 (en) * 2011-10-26 2017-05-09 Dai Nippon Printing Co., Ltd. Color filter for organic electroluminescence display device, and organic electroluminescence display device
KR102076034B1 (ko) * 2013-05-28 2020-02-12 삼성디스플레이 주식회사 유기 발광 표시 장치 및 그 제조 방법
CN206194793U (zh) * 2016-12-01 2017-05-24 京东方科技集团股份有限公司 一种顶发光型oled显示装置
KR102663231B1 (ko) * 2016-12-30 2024-05-02 엘지디스플레이 주식회사 유기발광 표시장치
CN107331690A (zh) * 2017-08-18 2017-11-07 深圳市华星光电半导体显示技术有限公司 有机电致发光显示基板及有机电致发光显示装置
KR102421575B1 (ko) * 2017-12-01 2022-07-18 삼성디스플레이 주식회사 유기 발광 표시 장치 및 유기 발광 표시 장치의 제조 방법
KR102474205B1 (ko) * 2017-12-26 2022-12-06 삼성디스플레이 주식회사 디스플레이 장치 및 그 제조방법
CN108417609B (zh) * 2018-04-10 2022-07-12 京东方科技集团股份有限公司 显示基板及其制备方法和显示装置
KR102480092B1 (ko) * 2018-04-30 2022-12-23 삼성디스플레이 주식회사 디스플레이 장치
CN108649060B (zh) * 2018-05-16 2020-06-05 京东方科技集团股份有限公司 Oled器件及其制备方法、显示装置
KR20200102025A (ko) * 2019-02-20 2020-08-31 삼성디스플레이 주식회사 표시 장치

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050236629A1 (en) * 2004-04-07 2005-10-27 Kwan-Hee Lee Top emission organic light emitting diode display using auxiliary electrode to prevent voltage drop of upper electrode and method of fabricating the same
CN102623644A (zh) * 2011-11-29 2012-08-01 友达光电股份有限公司 显示面板及其制作方法
CN107093680A (zh) * 2017-05-04 2017-08-25 京东方科技集团股份有限公司 金属辅助电极及使用其的显示器件的制造方法
CN107393945A (zh) * 2017-07-31 2017-11-24 京东方科技集团股份有限公司 一种有机发光二极管显示基板及其制作方法、显示装置
CN108511502A (zh) * 2018-05-11 2018-09-07 京东方科技集团股份有限公司 一种阵列基板、显示面板、显示装置及阵列基板的制备方法

Also Published As

Publication number Publication date
CN108511502A (zh) 2018-09-07
CN108511502B (zh) 2021-08-31
US20200127068A1 (en) 2020-04-23
US11239293B2 (en) 2022-02-01

Similar Documents

Publication Publication Date Title
CN100483731C (zh) 包含电致发光装置的影像显示系统及其制造方法
WO2021057011A1 (zh) 显示面板及其制作方法、显示装置
TWI543360B (zh) 有機發光顯示面板及其製造方法
WO2016179940A1 (zh) Oled像素单元、透明显示装置及制作方法、显示设备
CN101752400B (zh) 影像显示装置、影像显示系统及其制造方法
WO2019214572A1 (zh) 阵列基板、显示面板、显示装置及制备阵列基板的方法
US10621909B2 (en) Display device and method of fabricating the same
US10749143B2 (en) Organic light emitting diode panel
WO2018086358A1 (zh) 有机发光二极管阵列基板及制备方法、显示装置
WO2015043269A1 (zh) Oled像素结构和oled显示装置
US20070222375A1 (en) System for displaying images including electroluminescent device and method for fabricating the same
US20100133998A1 (en) Image display device, image display system, and methods for fabricating the same
US20170244068A1 (en) Electroluminescence Display Device and Fabrication Method Thereof
US20120032582A1 (en) Organic electroluminescent display unit and method for fabricating the same
WO2018086210A1 (zh) Tft基板及其制作方法
WO2015123915A1 (zh) 有源矩阵有机发光二极管阵列基板及制作方法和显示装置
WO2021003702A1 (en) Touch control micro light emitting diode display apparatus, method of operating touch control micro light emitting diode display apparatus, and method of fabricating touch control micro light emitting diode display apparatus
TW200810170A (en) Organic light emitting display devices and methods for fabricating the same
WO2020124423A1 (zh) 显示面板及其制造方法、显示装置
TWI684270B (zh) 透明顯示面板及其製造方法
WO2015039493A1 (zh) 电致发光装置及其制备方法
WO2022247180A1 (zh) 显示面板及显示装置
US10930727B2 (en) Organic light-emitting diode display screen and electronic device
US11067845B2 (en) Liquid crystal panel and method of manufacturing same
TWI297210B (en) System for displaying images including electroluminescent device and method for fabricating the same

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19800598

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 01.04.2021)

122 Ep: pct application non-entry in european phase

Ref document number: 19800598

Country of ref document: EP

Kind code of ref document: A1