WO2019213973A1 - 一种放大器、放大电路及移相器 - Google Patents

一种放大器、放大电路及移相器 Download PDF

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WO2019213973A1
WO2019213973A1 PCT/CN2018/086614 CN2018086614W WO2019213973A1 WO 2019213973 A1 WO2019213973 A1 WO 2019213973A1 CN 2018086614 W CN2018086614 W CN 2018086614W WO 2019213973 A1 WO2019213973 A1 WO 2019213973A1
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mos transistor
amplifier
coupled
signal
input
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PCT/CN2018/086614
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English (en)
French (fr)
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崔科技
王永利
卢磊
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华为技术有限公司
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Priority to CN201880093325.5A priority Critical patent/CN112106296B/zh
Priority to PCT/CN2018/086614 priority patent/WO2019213973A1/zh
Priority to EP18917874.2A priority patent/EP3751733B1/en
Publication of WO2019213973A1 publication Critical patent/WO2019213973A1/zh
Priority to US17/037,224 priority patent/US11533031B2/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H03F3/45183—Long tailed pairs
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G1/00—Details of arrangements for controlling amplification
    • H03G1/0005—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal
    • H03G1/0017—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal the device being at least one of the amplifying solid state elements of the amplifier
    • H03G1/0029—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal the device being at least one of the amplifying solid state elements of the amplifier using FETs
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/08—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements
    • H03F1/22—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively
    • H03F1/223—Modifications of amplifiers to reduce detrimental influences of internal impedances of amplifying elements by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively with MOSFET's
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
    • H03F1/301—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters in MOSFET amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/32—Modifications of amplifiers to reduce non-linear distortion
    • H03F1/3205—Modifications of amplifiers to reduce non-linear distortion in field-effect transistor amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/56—Modifications of input or output impedances, not otherwise provided for
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F3/211—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only using a combination of several amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/24—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages
    • H03F3/245—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers of transmitter output stages with semiconductor devices only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45475—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using IC blocks as the active amplifying circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G1/00—Details of arrangements for controlling amplification
    • H03G1/0005—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal
    • H03G1/0017—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal the device being at least one of the amplifying solid state elements of the amplifier
    • H03G1/0023—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal the device being at least one of the amplifying solid state elements of the amplifier in emitter-coupled or cascode amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G1/00—Details of arrangements for controlling amplification
    • H03G1/0005—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal
    • H03G1/0088—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal using discontinuously variable devices, e.g. switch-operated
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G3/00—Gain control in amplifiers or frequency changers
    • H03G3/20—Automatic control
    • H03G3/30—Automatic control in amplifiers having semiconductor devices
    • H03G3/3052—Automatic control in amplifiers having semiconductor devices in bandpass amplifiers (H.F. or I.F.) or in frequency-changers used in a (super)heterodyne receiver
    • H03G3/3063—Automatic control in amplifiers having semiconductor devices in bandpass amplifiers (H.F. or I.F.) or in frequency-changers used in a (super)heterodyne receiver using at least one transistor as controlling device, the transistor being used as a variable impedance device
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/09—A balun, i.e. balanced to or from unbalanced converter, being present at the output of an amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/318—A matching circuit being used as coupling element between two amplifying stages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/408—Indexing scheme relating to amplifiers the output amplifying stage of an amplifier comprising three power stages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/504—Indexing scheme relating to amplifiers the supply voltage or current being continuously controlled by a controlling signal, e.g. the controlling signal of a transistor implemented as variable resistor in a supply path for, an IC-block showed amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/537—A transformer being used as coupling element between two amplifying stages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
    • H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
    • H03F3/193—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only with field-effect devices

Definitions

  • the present application relates to the field of electronic technologies, and in particular, to an amplifier, an amplifying circuit, and a phase shifter.
  • phased array antenna technology has gradually become an important research direction of 5G transceivers.
  • VGA variable gain amplifier
  • the receiving link when the signal received by the antenna is strong, the gain of the receiving link needs to be reduced to avoid saturation of its output, increase the nonlinearity of the receiving link, and increase the bit error rate.
  • the phased array system when changing the gain of the VGA, it is necessary to ensure that the phase is constant to avoid changing the receiving angle of the antenna when switching the gain. Therefore, constant phase variable gain amplifiers are becoming more and more important in 5G communication systems.
  • the traditional variable gain amplifier is mainly divided into two types.
  • the first implementation is: DSA (digital switched attenuator) + fixed gain amplifier; among them, DSA is implemented by passive components to achieve constant phase and digitally controlled attenuation.
  • the device needs to be set to compensate the phase, such as the inductor Lc, which leads to an increase in the area of the entire VGA layout, which increases the cost of the die die.
  • the device for compensating the phase set in the digitally controlled attenuator is usually a hardware device
  • the phase change of the link is usually fixed; the second method is implemented by an active circuit, and the gain is switched by switching the bias current or load of the amplifier, but the second method does not guarantee a constant phase, similarly if necessary
  • the effect of a constant phase also requires the addition of passive components or active current injection for phase compensation.
  • both methods require a separate phase compensation scheme for the link, and the amount of phase change is usually fixed and is not well suited for phase-constant requirements.
  • Embodiments of the present application provide an amplifier, an amplifying circuit, and a phase shifter, which can realize flexible adjustment of an output phase, thereby realizing a constant phase requirement of a link.
  • the present application provides an amplifier including: a first MOS transistor, a second MOS transistor, and a third MOS transistor; wherein a gate of the first MOS transistor is coupled to a signal input terminal and a bias voltage input terminal, respectively a source of the first MOS transistor is coupled to the power source, a drain of the first MOS transistor is coupled to a source of the second MOS transistor and a source of the third MOS transistor, and a drain of the third MOS transistor is coupled to the ground, a drain of the second MOS transistor is coupled to the signal output terminal; a gate of the second MOS transistor is configured to enable the second MOS transistor to be in an on state under control of the first gate control signal; and a gate of the third MOS transistor Under the control of the second gate control signal, the AC signal outputted from the drain of the first MOS transistor is bypass controlled by changing the off state or the on state of the third MOS transistor; the bias voltage input terminal is used for A bias voltage is received to adjust the phase difference between the input signal at the
  • the third MOS transistor when the second MOS transistor is in an on state, the third MOS transistor can be controlled to be turned off; when the gain of the amplifier needs to be changed, the third MOS transistor is controlled to be turned on, and the third MOS transistor bypasses part of the alternating current signal.
  • Variable gain is achieved by going to the ground GND of the power supply, causing the gain of the amplifier to drop into another gain state.
  • a bias voltage is input to the bias voltage input terminal to adjust a phase difference between the input signal of the signal input end and the output signal of the signal output end; for example, when the third MOS transistor is turned off, for the first MOS transistor Inputting a first bias voltage at the bias voltage input terminal and maintaining constant; when the gain needs to be changed, turning on the third MOS transistor while changing the bias voltage of the first MOS transistor at the bias voltage input terminal, for example, providing less than a second bias voltage of the first bias voltage.
  • the first MOS transistor reduces the first MOS transistor transconductance gm due to the decrease of the bias voltage, and the gain of the amplifier can also be reduced. Variable gain.
  • the transconductance changes of the main second MOS transistor and the third MOS transistor introduce a phase difference.
  • changing the bias voltage input to the first MOS transistor at the bias voltage input terminal causes the current signal flowing through the first MOS transistor to change.
  • the transconductance of the second MOS transistor and the third MOS transistor can be adjusted, thereby achieving flexible adjustment of the output phase, and further, when the third MOS transistor is turned off
  • the transconductance of the second MOS transistor is equal to the sum of the transconductance of the second MOS transistor in the conduction state of the third MOS transistor and the transconductance of the third MOS transistor, the need for a constant phase of the link can be achieved.
  • the bias voltage received by the bias voltage input terminal is a first bias voltage; when the third MOS transistor is in an on state, the bias voltage is The bias voltage received at the input is a second bias voltage; wherein the first bias voltage is greater than the second bias voltage.
  • the amplifier When the bias voltage input receives the first bias voltage, the amplifier is at the first gain; when the bias voltage input receives the second bias voltage, the amplifier is at the second gain; the first gain is greater than the second gain.
  • the second bias voltage is determined according to a first bias voltage and a formula g m2,max ⁇ (g m2 +g m3 ); wherein, g m2,max is an amplifier In a gain state, the transconductance of the second MOS transistor; g m2 is the transconductance of the second MOS transistor in the state of the second gain of the amplifier; g m3 is the transconductance of the third MOS transistor in the on state.
  • g m2,max g m2 +g m3 , the need to achieve a constant phase of the link.
  • the method further includes: a bias circuit including a current source and a fourth MOS transistor, one end of the current source coupled to the ground, and the other end of the current source coupled to the fourth MOS transistor
  • a bias circuit including a current source and a fourth MOS transistor, one end of the current source coupled to the ground, and the other end of the current source coupled to the fourth MOS transistor
  • the drain and the gate of the fourth MOS transistor, the gate of the fourth MOS transistor is coupled to the bias voltage input, and the source of the fourth MOS transistor is coupled to the power supply.
  • the gate of the first MOS transistor is connected to the bias voltage input through a voltage dividing resistor.
  • At least one fifth MOS transistor connected in parallel with the first MOS transistor, wherein the gate of the fifth MOS transistor is opposite to the gate of the first MOS transistor Coupling; a source of the fifth MOS transistor is coupled to a source of the first MOS transistor; and a drain of the fifth MOS transistor is coupled to a drain of the first MOS transistor.
  • the method further includes at least one sixth MOS transistor connected in parallel with the second MOS transistor, wherein a gate of the sixth MOS transistor is coupled to a gate of the second MOS transistor; a source of the sixth MOS transistor and a source of the second MOS transistor Phase coupled; the drain of the sixth MOS transistor is coupled to the drain of the second MOS transistor.
  • the method further includes at least one seventh MOS transistor connected in parallel with the third MOS transistor, wherein a gate of the seventh MOS transistor is coupled to a gate of the third MOS transistor; a source of the seventh MOS transistor and a source of the third MOS transistor Phase coupling; the drain of the seventh MOS transistor is coupled to the drain of the third MOS transistor.
  • a single-ended form of amplifier is provided.
  • embodiments of the present application also provide an amplifier based on the differential form of the single-ended form of the amplifier described above, the differential form of the amplifier comprising Two amplifiers as described above, wherein the bias voltage input of the first amplifier is coupled to the bias voltage input of the second amplifier.
  • the present application provides an amplifying circuit including at least a first amplifier and a second amplifier; an input matching network and an output matching network are disposed between the first amplifier and the second amplifier, wherein the first amplifier a signal output coupled to an input of the output matching network; an output of the output matching network coupled to an input of the input matching network; an output of the input matching network coupled to a signal input of the second amplifier; wherein the output matching network is for Converting a first voltage value of the signal output end of the first amplifier to a second voltage value; inputting a matching network for converting the second voltage value into a third voltage value; at least one of the first amplifier and the second amplifier is the first aspect Amplifier.
  • the amplifying circuit includes an amplifier of a first differential form and an amplifier of a second differential form; wherein an input matching network is disposed between the amplifier of the first differential form and the amplifier of the second differential form An output matching network, wherein a signal output of the first amplifier of the first differential form of the amplifier is coupled to a first input of the output matching network, and a signal output of the second amplifier of the first differential form of the amplifier is coupled to the output matching network a second input; a first output of the output matching network is coupled to the first input of the input matching network, a second output of the output matching network is coupled to the second input of the input matching network; and the first output of the input matching network a signal input coupled to the first amplifier of the second differential form of the amplifier, a second output of the input matching network coupled to the signal input of the second amplifier of the second differential form of the amplifier; wherein the output matching network is for Converting the first differential signal of the first differential form of the amplifier output to a second Divided signal;
  • the present application provides a phase shifter including a first amplifier, a second amplifier, a third amplifier, and a matching network; wherein a signal output end of the first amplifier is coupled to a first input end of the matching network, and a second A signal output of the amplifier is coupled to the second input of the matching network; a first output of the matching network is coupled to the signal input of the third amplifier, a second input of the matching network is coupled to ground; and the matching network is used to A first voltage difference between the signal output of the amplifier and the signal output of the second amplifier is converted to a second voltage difference, the amplifier comprising any of the amplifiers of the first aspect. At least one of the first amplifier and the second amplifier and the third amplifier is the amplifier of the first aspect.
  • the phase shifter comprises an amplifier in a first differential form, an amplifier in a second differential form, an amplifier in a third differential form, and a matching network; wherein the first amplifier of the first differential form of the amplifier a signal output coupled to the first input of the matching network, the signal output of the second amplifier of the first differential form of the amplifier being coupled to the second input of the matching network; the signal of the first amplifier of the second differential form of the amplifier The output is coupled to a third input of the matching network, the signal output of the second amplifier of the second differential form of the amplifier is coupled to a fourth input of the matching network; the first output of the matching network is coupled to the third differential a signal input of the first amplifier of the form of the amplifier, a second input of the matching network coupled to the signal input of the second amplifier of the third differential form of the amplifier; a matching network for outputting the first differential form of the amplifier a differential signal, and a second differential signal of the second differential form of the amplifier output is synthesized Differential signal.
  • the present application provides a transceiver comprising the amplifier as provided in the first aspect above, or an amplifying circuit as provided in the second aspect above, or a phase shifter provided in the third aspect.
  • the present application provides a transmitter comprising the amplifier as provided in the first aspect above, or an amplifying circuit as provided in the second aspect above, or a phase shifter provided in the third aspect.
  • the present application provides a receiver comprising the amplifier as provided in the first aspect above, or an amplification circuit as provided in the second aspect above, or a phase shifter provided in the third aspect.
  • the present application provides a communication device comprising the transceiver as provided in the fourth aspect, or the receiver provided in the fifth aspect, or the transmitter provided in the sixth aspect.
  • FIG. 1 is a schematic structural diagram of an amplifier according to an embodiment of the present application.
  • FIG. 2 is a schematic diagram of an equivalent circuit of an amplifier according to an embodiment of the present application.
  • FIG. 3 is a schematic diagram of relationship between gain and phase difference of an amplifier according to an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of an amplifier according to another embodiment of the present disclosure.
  • FIG. 5 is a circuit board diagram of an amplifier according to an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of an amplifier in a differential form according to an embodiment of the present disclosure.
  • FIG. 7 is a schematic structural diagram of an amplifying circuit according to an embodiment of the present application.
  • FIG. 8 is a schematic diagram of a connection manner of an amplifier in an amplifying circuit shown in FIG. 7 according to an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of an amplifying circuit according to another embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram of a connection manner of an amplifier in a differential form in the amplifying circuit shown in FIG. 9 according to an embodiment of the present application;
  • FIG. 11 is a schematic structural diagram showing a relationship between a phase and a gain of an output signal of an amplifying circuit according to an embodiment of the present disclosure
  • FIG. 12 is a schematic structural diagram of relationship between power consumption and gain of an amplifying circuit according to an embodiment of the present application.
  • FIG. 13 is a schematic structural diagram of relationship between input linearity and gain of an amplifying circuit according to an embodiment of the present application.
  • FIG. 14 is a schematic structural diagram of a phase shifter according to an embodiment of the present application.
  • FIG. 15 is a schematic structural diagram of a phase shifter according to another embodiment of the present application.
  • phase shifter 16 is a schematic structural diagram of a phase shifter according to another embodiment of the present application.
  • FIG. 17 is a schematic diagram of synthesizing orthogonal signals according to an embodiment of the present application.
  • Embodiments of the present application are applied to a radio frequency signal transceiver, receiver or transmitter of a communication device, wherein the communication device is a wireless communication device including, but not limited to, a user equipment, a base station, and the like.
  • the communication device can be a user device, which can be used for communication (eg, D2D communication) with one or more user devices, and can also be used to communicate with one or more base stations.
  • User equipment may also be referred to as user terminals and may include systems, subscriber units, subscriber stations, mobile stations, mobile terminals, mobile devices, nodes, devices, remote stations, remote terminals, terminals, wireless communication devices, wireless communication devices, or users Some or all of the features of the agent.
  • the user equipment can be a cellular phone, a cordless phone, a session initiation protocol (English name: session initiation protocol, SIP for short), a smart phone, a wireless local loop (English name: wireless local loop, WLL) station, personal number Assistant (full name: personal digital assistant, PDA for short), laptop computer, handheld communication device, handheld computing device, satellite wireless device, wireless modem card, and/or other processing for communicating on a wireless system device.
  • the user equipment may be a mobile terminal capable of accessing a wireless communication network such as 3G, 4G, LTE, or 5G, or may be a mobile terminal performing D2D wireless communication between devices.
  • the mobile terminal may include, an RF (Radio Frequency) transmitter (or RF circuit), a memory, other input devices, a display screen, a sensor, an audio circuit, an I/O (input/output) subsystem, and processing. Components such as a charge management chip and a power management chip.
  • the mobile terminal may also include a camera, a Bluetooth module, a virtual button, a physical button, and the like, and details are not described herein. It will be understood by those skilled in the art that the structure of the above mobile terminal is not limited, and may include more or less components, or combine some components, or split some components, or different component arrangements.
  • Common mobile terminals include, for example, mobile phones, tablets, notebook computers, PDAs (Personal Digital Assistants), handheld computers, MID (Mobile Internet Devices), POS (Point of Sales), On-board computers, wearable devices (such as smart watches, smart bracelets, pedometers, etc.).
  • the communication device may also be a base station, and the base station may be used for communicating with one or more user equipments, or for communicating with one or more base stations having partial user equipment functions (such as macro base stations and micro base stations, such as access).
  • Point, communication between; base stations may also be referred to as access points, nodes, Node Bs, evolved Node Bs (eNBs), or some other network entity, and may include some or all of the functions of the above network entities.
  • the base station can communicate with user equipment or other base stations over the air interface. This communication can be done by one or more sectors.
  • the base station can be used as a router between the wireless terminal and the rest of the access network by converting the received air interface frame into an IP (English full name: internet protocol, IP for short) packet, wherein the access network includes IP network.
  • IP International full name: internet protocol, IP for short
  • the base station can also coordinate the management of air interface attributes and can also be a gateway between the wired network and the wireless network.
  • Coupled may include directly connecting two devices that are coupled to each other, indirectly through any one or a combination of impedance networks, capacitive reactance networks, inductive networks, or other forms of connection, This application does not specifically limit the specific form of connection between two devices that are coupled to each other. Further, “coupled to ground” may refer to directly connected ground (GND) or indirectly connected.
  • a variable gain amplifier is typically placed on the transmit link or the receive link, while the phase of the signal on the link is constant and variable.
  • the gain amplifier needs to implement the phase adjustment function.
  • the amplifier can be a low noise amplifier (LNA) in the receiver.
  • LNA low noise amplifier
  • PA power amplifier
  • embodiments of the present application are applied to a transmit link or receive chain at a transceiver Amplifier set on the road.
  • an amplifier including:
  • the control mode of the above amplifier is as follows: the gate of the second MOS transistor M2 is used to make the second MOS transistor M2 in an on state under the control of the first gate control signal; the gate of the third MOS transistor M3 is used Under the control of the second gate control signal, by changing the off state or the on state of the third MOS transistor M3, the AC signal outputted from the drain of the first MOS transistor M1 is bypass controlled; the bias voltage input terminal Vbias is used to receive the bias voltage to adjust the phase difference between the input signal of the signal input terminal in and the output signal of the signal output terminal out.
  • the signal supplied from the power source V1 to the source of the first MOS transistor M1 is generally constant current, however, when the gate signal of the first MOS transistor M1 is a time varying signal, the drain of the first MOS transistor M1 The generated signal is an AC signal.
  • the first gate control signal of the gate of the second MOS transistor M2 is satisfied such that the second MOS transistor M2 is in an on state, and the third MOS transistor M3 is in a second state through the gate.
  • the gate control signal is controlled, wherein M3 has an off state and a conducting state.
  • the gate of the second MOS transistor M2 is connected to a bias voltage module
  • the gate of the third MOS transistor M3 is connected to a bias voltage module, wherein the gate bias voltage module of the second MOS transistor M2 can be M2
  • the gate provides a first gate control signal to effect state control of M2.
  • the gate bias voltage module of the third MOS transistor M3 may provide a second gate control signal for the gate of M3 to achieve state control of M3.
  • the gate of the first MOS transistor M1 is connected to the signal input terminal in through the capacitor C1, and the gate of the first MOS transistor is connected to the bias voltage input terminal Vbias through the voltage dividing resistor R1.
  • the operation principle based on the above-mentioned circuit shown in FIG. 1 is as follows: when the M2 is in the on state, the third MOS transistor can be controlled to be turned off, the amplifier is in a gain state; when the gain of the amplifier needs to be changed, the M3 is turned on. M3 bypasses part of the AC signal to the AC ground (ground GND of the power supply), so that the gain of the amplifier drops into another gain state, thereby achieving variable gain.
  • a bias voltage is input to the bias voltage input terminal to adjust the phase difference between the input signal of the signal input terminal and the output signal of the signal output terminal; for example, when M3 is turned off, and in a gain state.
  • M3 cutoff for the M1 input the first bias voltage at the Vbias end and maintain constant; when the gain needs to be changed, turn on M3 while reducing the bias voltage of M1 at the Vbias terminal, for example, providing less than the first bias voltage
  • the second bias voltage in which M1 is lowered by the bias voltage to lower the M1 transconductance gm, and the gain of the amplifier can also be lowered, thereby realizing variable gain.
  • the transconductance changes of the main second MOS transistor and the third MOS transistor introduce a phase difference.
  • changing the bias voltage input to the first MOS transistor at the bias voltage input terminal causes the current signal flowing through the first MOS transistor to change.
  • the transconductance of the second MOS transistor and the third MOS transistor can be adjusted, thereby achieving flexible adjustment of the output phase.
  • the signal Vin input to the signal input terminal in the alternating current generated by M1 is g m1 *Vin, and the alternating current is shunted at the node X.
  • g m1 *Vin I2+I3+Ix.
  • I2 is the current flowing through M2
  • I3 is the current flowing through M3
  • Ix is the current flowing through capacitor Cx
  • gm1 is the transconductance of M1.
  • g m2 and g m2,max are the transconductance of M2 under low gain and maximum gain, respectively
  • Phase1 is the phase of the amplifier input signal
  • Phase2 is the phase of the amplifier output signal
  • g m3 is the transconductance when M3 is on.
  • C x,on and C x,off are the parasitic capacitances to the ground of node X when M3 is turned on and off, respectively. Although the parasitic capacitance of M3 in the on and off states has a certain change, its influence on the phase is small, and C x, on ⁇ C x, off can be approximated.
  • the phase error of the amplifier at the time of switching the gain will be 0, that is, the gain switching of the constant phase is realized.
  • the amplifier when the bias voltage input receives the first bias voltage, the amplifier is at a first gain; when the bias voltage input receives the second bias voltage, the amplifier is at a second gain; and the first gain is greater than the second gain.
  • the second bias voltage is determined according to the first bias voltage and the formula g m2,max -(g m2 +g m3 ); g m2,max is the state of the amplifier at the first gain, and the second MOS transistor Transconductance; g m2 is the transconductance of the second MOS transistor in the state of the second gain of the amplifier; g m3 is the transconductance of the third MOS transistor in the on state.
  • FIG. 3 shows the simulation results of the amplifier proposed in the present application, with the horizontal axis being the gain and the vertical axis being the phase of the power gain (s21).
  • the curve 1 is the phase change of only the switching of M3 for gain switching. It can be seen that the phase error introduced by gain switching 4 dB (dB) is 3.9 degrees; the curve 2 is the phase change of the gain by only changing the M1 bias, it can be seen that The phase error introduced by switching the 3.2dB gain is about 4.6 degrees; the third curve is the phase error introduced by the switching gain method proposed in the present application. It can be seen from FIG. 3 that the phase error introduced by switching the 7.1dB gain is about 1.4 degrees.
  • phase error slope introduced by the switching of the M3 state is 1 degree per decibel (°/dB)
  • phase error slope introduced by the gain switching by adjusting the M1 bias mode is 1.4°. /dB
  • the phase error slope is only 0.2°/dB, which is much smaller than the first two structures. Therefore, the constant gain can be realized by using the switching gain method proposed in the present application. Switch.
  • a bias circuit SC including a current source Ibias and a fourth MOS transistor M4, one end of the current source Ibias is coupled to the ground GND, and the other end of the current source Ibias is coupled to the fourth MOS
  • the drain of the transistor M4 and the gate of the fourth MOS transistor M4, the gate of the fourth MOS transistor M4 is coupled to the bias voltage input terminal Vbias, and the source of the fourth MOS transistor M4 is coupled to the power source V1.
  • the amplifier further includes at least one fifth MOS transistor M5 connected in parallel with the first MOS transistor M1, wherein the gate of the fifth MOS transistor M5 is coupled to the gate of the first MOS transistor M1; the source of the fifth MOS transistor M5 The source of the first MOS transistor M1 is coupled; the drain of the fifth MOS transistor M5 is coupled to the drain of the first MOS transistor M1. It should be noted that, in the working state, the state of controlling at least one M5 is in the same state as M1.
  • the amplifier further includes at least one sixth MOS transistor M6 connected in parallel with the second MOS transistor M2, wherein the gate of the sixth MOS transistor M6 is coupled to the gate of the second MOS transistor M2; the source of the sixth MOS transistor M6 The source of the second MOS transistor M2 is coupled; the drain of the sixth MOS transistor M6 is coupled to the drain of the second MOS transistor M2. It should be noted that, in the working state, the state of controlling at least one M6 is in the same state as M2.
  • the amplifier further includes at least one seventh MOS transistor M7 connected in parallel with the third MOS transistor M3, wherein the gate of the seventh MOS transistor M7 is coupled to the gate of the third MOS transistor M3; and the source of the seventh MOS transistor M7 The source of the third MOS transistor M3 is coupled; the drain of the seventh MOS transistor M7 is coupled to the drain of the third MOS transistor M3. It should be noted that, in the working state, the state of controlling at least one M7 is in the same state as M3.
  • the implementation of the present application provides a circuit layout of an amplifier as shown in FIG. 5, which includes three MOS transistors, M1 (which may be a parallel connection of one or more M1s, and shows a parallel structure of eight M1s). M2 (which may be a parallel connection of one or more M2, four M2 parallel structures are shown), M3 (which may be a parallel connection of one or more M3, and four M3 parallel structures are shown). The drain of M2 is connected to the signal output, and the drain of M3 is connected to GND.
  • M1 which may be a parallel connection of one or more M1s, and shows a parallel structure of eight M1s.
  • M2 which may be a parallel connection of one or more M2, four M2 parallel structures are shown
  • M3 which may be a parallel connection of one or more M3, and four M3 parallel structures are shown.
  • the drain of M2 is connected to the signal output, and the drain of M3 is connected to GND.
  • the gates of M1, M2, and M3 are respectively connected to a bias voltage module.
  • the amplifier shown in FIG. 1 and FIG. 4 is an amplifier in a single-ended form.
  • an embodiment of the present application further provides an amplifier in a differential form, specifically including a first amplifier PA1 and a second amplifier PA2.
  • the first amplifier PA1 and the second amplifier PA2 are in the form of a single-ended amplifier as shown in FIG. 1 and FIG. 4, and are not described herein again.
  • the bias voltage input of the first amplifier PA1 is coupled to the bias voltage input of the second amplifier PA2.
  • the above amplifier can also improve the input linearity, as follows:
  • the gain is usually reduced because the input signal is too large and the gain needs to be reduced to ensure that the input signal is linearly amplified, so it is often necessary to increase the input linearity when reducing the gain.
  • VGA when only M3 is used for gain switching, the AC current is bypassed directly to the AC ground (GND of the power supply), so the linearity of the output OP1dB decreases synchronously with the gain, making the input linear. IP1dB does not change.
  • g 1 is the transconductance of M1
  • g 2 is the transconductance first derivative of M1
  • g 3 is the transconductance second derivative of M1.
  • the g 3 term is negative, so as the input signal amplitude A increases, the gain of the fundamental signal will gradually decrease, and the input signal power when the gain is reduced by 1 dB is the definition of the input IP1dB point.
  • the bias state of the MOS transistor is such that g 3 is a negative number, the gain is switched in the manner of the M3 state switching + M1 bias proposed in the embodiment of the present application.
  • the M3 state switching + M1 biasing mode adopted in the embodiment of the present application reduces the input DC offset when switching the gain, and reduces the overdrive voltage (Vgs-Vth) of M1.
  • the amplifier is gradually switched from the Class A state to the Class B state, achieving an input linearity (IP1dB) improvement of the amplifier while achieving a constant phase.
  • an embodiment of the present application provides an amplifying circuit including at least a first amplifier and a second amplifier.
  • the amplifying circuit includes a first amplifier S1 and a second amplifier S2, and a third amplifier S3 is also shown, wherein an input matching network is disposed between the first amplifier S1 and the second amplifier S2.
  • P1 and output matching network P2 wherein the signal output end of S1 is coupled to the input of the output matching network P2; the output of the output matching network P2 is coupled to the input of the input matching network P1; the output of the input matching network P1 a signal input terminal in coupled to S2; wherein the output matching network P2 is configured to convert a first voltage value of the signal output terminal of S1 into a second voltage value; and the input matching network P1 is configured to convert the second voltage value into a third voltage value value.
  • an input matching network and an output matching network are also disposed between the second amplifier S2 and the third amplifier S3; at least one of the first amplifier S1 and the second amplifier S2 and the third amplifier S3 is the amplifier provided in the above embodiment.
  • An exemplary input matching network P1 and an output matching network P2 can be transformers.
  • the input matching network P1 and the output matching network P2 are mainly used to implement conversion of an output signal and an output signal between cascaded amplifiers, such as voltage or current conversion. Thereby, the output signal of the previous stage amplifier can be used as an input signal to enter the next stage amplifier.
  • each stage of the amplifier for each stage of the amplifier, the input side is provided with an input matching network Pin, and the output side thereof is provided with an output matching network Pout.
  • each stage of the amplifier can also directly include the input matching network Pin set on the input side and the output matching network Pout set on the output side, so that the amplifier can be directly cascaded.
  • the amplifying circuit includes at least a first differential form of the amplifier and a second differential form of the amplifier.
  • the amplifying circuit includes an amplifier S1 in a first differential form, an amplifier S2 in a second differential form, and an amplifier S3 in a third differential form, wherein the first differential form amplifier and the second differential form amplifier
  • An input matching network P1 and an output matching network P2 are disposed between S2, wherein a signal output terminal out+ of the first amplifier of the first differential form of the amplifier S1 is coupled to a first input terminal of the output matching network P2, the first differential form of the amplifier
  • the signal output terminal out- of the second amplifier of S1 is coupled to the second input terminal of the output matching network P2; the first output terminal output1 of the output matching network P2 is coupled to the first input terminal input1 of the input matching network P1, and the output matching network P2
  • the second output terminal 2 is coupled to the second input terminal input2 of the input matching network P1; the first output terminal of
  • the input matching network P1 and the output matching network P2 are mainly used to implement conversion of an output signal and an input signal between amplifiers in a cascaded differential form, such as voltage or current conversion. Thereby, the output signal of the amplifier of the previous differential form can be used as an input signal to the amplifier of the next differential form.
  • an input matching network and an output matching network are also disposed between the second differential form of the amplifier S2 and the third differential form of the amplifier S3; the first differential form of the amplifier S1 and the second differential form of the amplifier S2 and the third differential At least one of the forms of amplifier S3 is the amplifier provided in the above embodiment.
  • each stage of the differential form of the amplifier for each stage of the differential form of the amplifier, the input side is provided with an input matching network Pin, and the output side thereof is provided with an output matching network Pout.
  • each stage of the differential form of the amplifier can also directly include the input matching network Pin set on its input side and the output matching network Pout set on the output side, so that the differential form of the amplifier can be directly cascaded.
  • the gain control mode of the amplifying circuit provided in FIG. 7 and FIG. 9 above is that the gain is switched in a certain stage amplifier (or differential form amplifier) by the method proposed in the present application; Changing the state switching gain of tube M3, in another stage of the amplifier (or differential form of the amplifier), the gain is switched by changing the bias voltage of M1 to achieve constant phase gain switching.
  • the input third-order intercept point IIP3 of the amplifier determines its linearity.
  • the nonlinear component of the amplifier is mainly generated by the nonlinearity of the transconductance gm1 of M1.
  • the gain is switched in a manner of changing the state of M3 + changing the bias voltage of M1 proposed in the present application, and as the bias voltage Vbias decreases, the g 3 term of the equation (3) changes from a negative number to a positive number.
  • the nonlinear term of the M1 transconductance g m1 of the two-stage amplifier (differential form of the amplifier) is offset, and the third-order intermodulation term (IM3 term) at the output is reduced, and at this time the cascode amplifier (differential form of the amplifier) The gain is reduced, so the input linear IIP3 of the cascode amplifier (differential form of the amplifier) is boosted.
  • FIG. 11 to FIG. 13 show the feature points introduced by the amplifying circuit provided in FIG. 7-10 for the signal transceiving link when the gain switching mode proposed by the present application is used.
  • the present application adopts a state of changing M3. + Change the bias voltage of M1 to switch the gain to achieve gain switching.
  • the relationship between gain and phase is shown, where the horizontal axis is the gain (the gain increases stepwise along the horizontal axis), and the vertical axis
  • the phase the phase is gradually increased along the longitudinal axis
  • the phase corresponding to the gain remains substantially constant or the change is small when the switching gain (gain change); as shown in FIG.
  • the relationship between gain and power consumption is shown, in which the horizontal axis is the gain (the gain is gradually increased along the right axis of the horizontal axis), and the vertical axis is the power consumption (the power consumption is gradually increased along the upper side of the longitudinal axis), which is obviously at a low gain.
  • the power consumption is low, and the power consumption is high at high gain;
  • FIG. 13 the relationship between the gain and the input linearity is shown, wherein the horizontal axis is the gain (the gain is gradually increased along the right axis of the horizontal axis), and the vertical axis
  • IP1dB or IIP3 is gradually increased.
  • an embodiment of the present application provides a phase shifter comprising a first amplifier S1, a second amplifier S2 and a third amplifier S3, and a matching network P1;
  • the signal output terminal out of the first amplifier S1 is coupled to the first input terminal of the matching network P1, and the signal output terminal out of the second amplifier S2 is coupled to the second input terminal of the matching network P1; the first output terminal of the matching network P1 a signal input terminal in is coupled to the third amplifier, the second input of the matching network P1 is coupled to the ground GND; the matching network P1 is configured to convert the signal output of the first amplifier S1 to the first voltage of the signal output of the second amplifier S2 The difference is converted to a second voltage difference. At least one of the first amplifier S1 and the second amplifier S2 and the third amplifier S3 is the amplifier provided in the above embodiment.
  • the matching network P1 may be a transformer, in which case the two input terminals of the primary of the transformer are respectively connected to the signal output terminal out of the first amplifier S1 and the signal output terminal out of the second amplifier S2.
  • the two outputs of the secondary of the transformer are connected to the signal input terminal in and the ground GND of the third amplifier, respectively.
  • an embodiment of the present application provides a phase shifter including an amplifier S1 in a first differential form, an amplifier S2 in a second differential form, and an amplifier S3 in a third differential form.
  • a matching network P1 wherein the signal output out+ of the first amplifier of the first differential form of the amplifier S1 is coupled to the first input of the matching network P1, the signal output of the second amplifier of the first differential form of the amplifier S1 a second input coupled to the matching network P1; a signal output out+ of the first amplifier of the second differential form of amplifier S2 coupled to a third input of the matching network P1, a second amplifier of the second differential form of the amplifier S2
  • the signal output out- is coupled to the fourth input of the matching network P1; the first output of the matching network P1 is coupled to the signal input in+ of the first amplifier of the third differential form of the amplifier S3, the second of the matching network P1
  • the input is coupled to the signal input of the second amplifier of the amplifier of the third differential form in
  • At least one of the amplifier S1 of the first differential form and the amplifier S2 of the second differential form and the amplifier S3 of the third differential form are the amplifiers provided in the above embodiments.
  • the matching network P1 may be a combined device, such as a power synthesis device, a voltage synthesis device, or a current synthesis device.
  • the phase shifter provided based on the above-mentioned FIG. 14 to FIG. 16 can realize the gain adjustment when the quadrature signal (I signal, Q signal) is synthesized.
  • the phase shifter provided in FIG. 14 is described, and the voltage of the I signal Vin_I can be Input from the signal input terminal of S1, input the voltage Vin_Q of the Q signal from the signal input end of S2, and adjust the gain and phase of Vin_I, Vin_Q through S1 and S2, respectively, thereby changing the synthesis ratio of Vin_I and Vin_Q, and finally passing S3.
  • Adjusting the gain and phase of the composite signal ultimately enables an active phase shifter based on a variable gain amplifier.
  • the implementation principle is as shown in FIG. 17.
  • the orthogonal signals I and Q are combined and amplified, and finally the outputs Vout_I of S1 and the output Vout_Q of S2 have different phases ⁇ 1 and ⁇ 2,
  • the phase shifting function is implemented.
  • the constant phase gain switching method proposed by the present application can be adopted to avoid introducing an extra phase difference and reducing the accuracy of the active phase shifter, and secondly, due to the active phase shifter.
  • the amplitude of the output signal after the road is different.
  • the final output can be adjusted through S3 after the combination.
  • S3 adopts the constant phase gain control method proposed in the present application to ensure that the adjustment gain does not introduce an additional phase difference, and the phase precision of the active phase shifter is ensured.
  • the orthogonal signals I1 and Q1 are amplified and combined to obtain an output signal OUT1 having a phase of ⁇ 1
  • the orthogonal signals I2 and Q2 are amplified and combined to obtain an output signal OUT2 having a phase of ⁇ 2.
  • the phase shifter shown in FIG. 16 the principle is similar to the above, except that the I signal and the Q signal are respectively in the form of differential signals.

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Abstract

一种放大器、放大电路及移相器，涉及通信领域，能够实现对输出相位的灵活调整，进而实现链路的相位恒定的需求。该放大器包括：第一MOS管（M1）的栅极分别耦合至信号输入端（in）以及偏置电压输入端（Vbias），第一MOS管（M1）的源极与电源（V1）相耦合，第一MOS管（M1）的漏极分别耦合至第二MOS管（M2）的源极以及第三MOS管（M3）的源极，第三MOS管（M3）的漏极耦合至地（GND），第二MOS管（M2）的漏极耦合至信号输出端（out）；第二MOS管（M2）的栅极在第一栅极控制信号的控制下使第二MOS管（M2）处于导通状态；第三MOS管（M3）的栅极在第二栅极控制信号的控制下通过改变第三MOS管（M3）的截止状态或导通状态，对第一MOS管（M1）的漏极输出的交流信号进行旁路控制；偏置电压输入端接收偏置电压以调整信号输入端的输入信号与信号输出端的输出信号之间的相位差。

Description

一种放大器、放大电路及移相器 技术领域
本申请涉及电子技术领域，尤其涉及一种放大器、放大电路及移相器。
背景技术
随着第五代移动通信技术(5G)的快速发展，相控阵天线技术已逐步成为5G收发机的重要研究方向。而为了保证收发机的动态范围，需要在接收/发射链路中加入可变增益放大器(variable gain amplifier，VGA)。以接收链路为例，当天线接收的信号较强时，则需降低接收链路的增益以避免其输出饱和，增大接收链路的非线性，增大误码率。同时，在相控阵系统中，当改变VGA的增益时，需要保证其相位恒定，以避免在切换增益时改变了天线的接收角度。因此，恒定相位可变增益放大器在5G通讯系统中变得越来越重要。
传统的可变增益放大器主要分为两种，第一种实现方式为：DSA(digital switched attenuator，数控衰减器)+固定增益放大器；其中，DSA由无源器件实现，为实现相位恒定，数控衰减器中需要设置用于补偿相位的器件，例如电感Lc，从而导致整个VGA版图面积的增加，提高了裸片die的成本，由于数控衰减器中设置的补偿相位的器件通常为硬件器件，因此对链路的相位的改变量通常固定；第二种方式是采用有源电路实现，通过切换放大器的偏置电流或负载进行增益切换，但是第二种方式并不能保证相位恒定，类似的若需要取得相位恒定的效果，也需要增加无源器件或有源电流注入进行相位补偿。总之，两种方式均需要单独设计针对链路的相位补偿方案，并且相位的改变量通常固定，并不能良好的适用于相位恒定的需求。
发明内容
本申请的实施例提供一种放大器、放大电路及移相器，能够实现对输出相位的灵活调整，进而实现链路的相位恒定的需求。
第一方面，本申请提供一种放大器，包括：第一MOS管、第二MOS管和第三MOS管；其中，第一MOS管的栅极分别耦合至信号输入端以及偏置电压输入端，第一MOS管的源极与电源相耦合，第一MOS管的漏极分别耦合至第二MOS管的源极以及第三MOS管的源极，第三MOS管的漏极耦合至地，第二MOS管的漏极耦合至信号输出端；第二MOS管的栅极用于在第一栅极控制信号的控制下，使第二MOS管处于导通状态；第三MOS管的栅极用于在第二栅极控制信号的控制下，通过改变第三MOS管的截止状态或导通状态，对第一MOS管的漏极输出的交流信号进行旁路控制；偏置电压输入端用于接收偏置电压，以调整信号输入端的输入信号与信号输出端的输出信号之间的相位差。在上述方案中，在第二MOS管处于导通状态下，可以控制第三MOS管截止；当需要改变放大器的增益时，控制第三MOS管导通，第三MOS管将部分交流信号旁路到电源的地GND中，使得放大器的增益下降进入另一种增益状态，以此来实现可变增益。另外，在增益发生改变时，向偏置电压输入端输入偏置电压，以调整信号输入端的输入信号与信号输出端的输出信号的相位差；例如，第三MOS管截止时，对于第一MOS管在偏置电压输入端输入第一偏置电压并维持恒定不变；当需要改变增益时，导通第三MOS 管的同时改变第一MOS管在偏置电压输入端的偏置电压，例如提供小于第一偏置电压的第二偏置电压，在这种状态下，第一MOS管由于偏置电压降低导致第一MOS管跨导gm降低，也可以使得放大器的增益下降，以此来实现可变增益。而在切换增益的过程中，主要第二MOS管和第三MOS管的跨导变化引入相位差。这样在切换第三MOS管的状态(由截止状态到导通状态)的同时，改变偏置电压输入端输入第一MOS管的偏置电压，会使得流过第一MOS管的电流信号发生变化，当合理地改变第一MOS管的偏置电压时，可以调整第二MOS管和第三MOS管的跨导，从而实现了能够实现对输出相位的灵活调整，此外，当第三MOS管截止状态第二MOS管的跨导等于第三MOS管导通状态第二MOS管的跨导与第三MOS管的跨导之和时，则能够实现链路的相位恒定的需求。
在一种示例性的方案中，当第三MOS管处于截止状态时，偏置电压输入端接收的偏置电压为第一偏置电压；当第三MOS管处于导通状态时，偏置电压输入端接收的偏置电压为第二偏置电压；其中，第一偏置电压大于第二偏置电压。偏置电压输入端接收第一偏置电压时，放大器处于第一增益；偏置电压输入端接收第二偏置电压时，放大器处于第二增益；第一增益大于第二增益。
在一种示例性的方案中，所述第二偏置电压是根据第一偏置电压以及公式g m2,max-(g m2+g m3)确定的；其中，g m2,max为放大器在第一增益的状态下，第二MOS管的跨导；g m2为放大器在第二增益的状态下，第二MOS管的跨导；g m3为第三MOS管在导通状态下的跨导。其中当g m2,max＝g m2+g m3时，实现链路的相位恒定的需求。
在一种示例性的方案中，还包括：偏置电路，偏置电路包括电流源和第四MOS管，所述电流源的一端耦合至地，电流源的另一端耦合至第四MOS管的漏极以及第四MOS管的栅极，第四MOS管的栅极耦合至偏置电压输入端，第四MOS管的源极耦合至电源。
在一种示例性的方案中，所述第一MOS管的栅极通过分压电阻连接偏置电压输入端。
在一种示例性的方案中，为保证放大器工作的稳定性，还包括至少一个与第一MOS管并联的第五MOS管，其中第五MOS管的栅极与第一MOS管的栅极相耦合；第五MOS管的源极与第一MOS管的源极相耦合；第五MOS管的漏极与第一MOS管的漏极相耦合。还包括至少一个与第二MOS管并联的第六MOS管，其中第六MOS管的栅极与第二MOS管的栅极相耦合；第六MOS管的源极与第二MOS管的源极相耦合；第六MOS管的漏极与第二MOS管的漏极相耦合。还包括至少一个与第三MOS管并联的第七MOS管，其中第七MOS管的栅极与第三MOS管的栅极相耦合；第七MOS管的源极与第三MOS管的源极相耦合；第七MOS管的漏极与第三MOS管的漏极相耦合。
上述第一方面及其可能的实现方式中提供了一种单端形式的放大器，当然本申请的实施例还提供一种基于上述单端形式的放大器的差分形式的放大器，该差分形式的放大器包括两个如上述的放大器，其中，第一放大器的偏置电压输入端耦合至第二放大器的偏置电压输入端。
第二方面，本申请提供一种放大电路，放大电路至少包括第一放大器和第二放大器；第一放大器和所述第二放大器之间设置有输入匹配网络和输出匹配网络，其中第一放大器的信号输出端耦合至输出匹配网络的输入端；输出匹配网络的输出端耦合至输入匹配网络的输入端；输入匹配网络的输出端耦合至第二放大器的信号输入端；其 中，输出匹配网络用于将第一放大器的信号输出端的第一电压值变换为第二电压值；输入匹配网络用于将第二电压值变换为第三电压值；第一放大器和第二放大器的至少一个为第一方面的放大器。
此外，在采用差分形式的放大器时，该放大电路包括第一差分形式的放大器和第二差分形式的放大器；其中第一差分形式的放大器和第二差分形式的放大器之间设置有输入匹配网络和输出匹配网络，其中第一差分形式的放大器的第一放大器的信号输出端耦合至输出匹配网络的第一输入端，第一差分形式的放大器的第二放大器的信号输出端耦合至输出匹配网络的第二输入端；输出匹配网络的第一输出端耦合至输入匹配网络的第一输入端，输出匹配网络的第二输出端耦合至输入匹配网络的第二输入端；输入匹配网络的第一输出端耦合至第二差分形式的放大器的第一放大器的信号输入端，输入匹配网络的第二输出端耦合至第二差分形式的放大器的第二放大器的信号输入端；其中，输出匹配网络用于将第一差分形式的放大器输出的第一差分信号变换为第二差分信号；输入匹配网络用于将第二差分信号变换为第三差分信号。第一差分形式的放大器和第二差分形式的放大器的至少一个为第一方面的放大器。
第三方面，本申请提供一种移相器，包括第一放大器、第二放大器、第三放大器以及匹配网络；其中，第一放大器的信号输出端耦合至匹配网络的第一输入端，第二放大器的信号输出端耦合至匹配网络的第二输入端；匹配网络的第一输出端耦合至第三放大器的信号输入端，匹配网络的第二输入端耦合至地；匹配网络用于将第一放大器的信号输出端与第二放大器的信号输出端的第一电压差值变换为第二电压差值，放大器包括如第一方面所述的任一放大器。第一放大器和第二放大器和第三放大器的至少一个为第一方面的放大器。
此外，在采用差分形式的放大器时，移相器包括第一差分形式的放大器、第二差分形式的放大器、第三差分形式的放大器以及匹配网络；其中，第一差分形式的放大器的第一放大器的信号输出端耦合至匹配网络的第一输入端，第一差分形式的放大器的第二放大器的信号输出端耦合至匹配网络的第二输入端；第二差分形式的放大器的第一放大器的信号输出端耦合至匹配网络的第三输入端，所述第二差分形式的放大器的第二放大器的信号输出端耦合至匹配网络的第四输入端；匹配网络的第一输出端耦合至第三差分形式的放大器的第一放大器的信号输入端，匹配网络的第二输入端耦合至第三差分形式的放大器的第二放大器的信号输入端；匹配网络用于将第一差分形式的放大器输出的第一差分信号，以及第二差分形式的放大器输出的第二差分信号合成为第三差分信号。第一差分形式的放大器和第二差分形式的放大器和第你差分形式的放大器的至少一个为第一方面的放大器。
第四方面，本申请提供一种收发机，包括如上述第一方面提供的放大器，或者包括如上述第二方面提供的放大电路、或者至第三方面提供的移相器。
第五方面，本申请提供一种发射机，包括如上述第一方面提供的放大器，或者包括如上述第二方面提供的放大电路、或者至第三方面提供的移相器。
第六方面，本申请提供一种接收机，包括如上述第一方面提供的放大器，或者包括如上述第二方面提供的放大电路、或者至第三方面提供的移相器。
第七方面，本申请提供一种通信设备，包括如第四方面提供的收发机、或者第五 方面提供的接收机、或者第六方面提供的发射机。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍。
图1为本申请的实施例提供的一种放大器的结构示意图；
图2为本申请的实施例提供的一种放大器的等效电路示意图；
图3为本申请的实施例提供的一种放大器的增益与相位差的关系示意图；
图4为本申请的另一实施例提供的一种放大器的结构示意图；
图5为本申请的实施例提供的一种放大器的电路板图；
图6为本申请的实施例提供的一种差分形式的放大器的结构示意图；
图7为本申请的实施例提供的一种放大电路的结构示意图；
图8为本申请的实施例提供的如图7所示的放大电路中的放大器的连接方式示意图；
图9为本申请的另一实施例提供的一种放大电路的结构示意图；
图10为本申请的实施例提供的如图9所示的放大电路中的差分形式的放大器的连接方式示意图；
图11为本申请的实施例提供的一种放大电路的输出信号的相位和增益的关系结构示意图；
图12为本申请的实施例提供的一种放大电路的功耗和增益的关系结构示意图；
图13为本申请的实施例提供的一种放大电路的输入线性度和增益的关系结构示意图；
图14为本申请的实施例提供的一种移相器的结构示意图；
图15为本申请的另一实施例提供的一种移相器的结构示意图；
图16为本申请的又一实施例提供的一种移相器的结构示意图；
图17为本申请的实施例提供的一种正交信号的合成示意图。
具体实施方式
下面结合附图，对本申请的实施例进行描述。
本申请的实施例应用于通信设备的射频信号收发机、接收机或发射机，其中，该通信设备为无线通信设备包括但不限于用户设备、基站等等。
通信设备可以为用户设备，用户设备可以用于一个或多个用户设备进行通信(比如D2D通信)，也可以用于与一个或多个基站进行通信。用户设备还可以称为用户终端，并且可以包括系统、用户单元、用户站、移动站、移动终端、移动设备、节点、设备、远程站、远程终端、终端、无线通信设备、无线通信装置或用户代理的功能中的一些或者所有功能。用户设备可以是蜂窝电话、无绳电话、会话发起协议(英文全称：session initiation protocol，简称：SIP)电话、智能电话、无线本地环路(英文全称：wireless local loop，简称：WLL)站、个人数字助理(英文全称：personal digital assistant，简称：PDA)、膝上型计算机、手持式通信设备、手持式计算设备、卫星无线设备、无线调制解调器卡和/或 用于在无线系统上进行通信的其它处理设备。例如该用户设备可以为能够接入3G、4G、LTE、5G等无线通信网络的移动终端，还可以是进行设备间D2D无线通信的移动终端。移动终端可以包括、RF(Radio Frequency，射频)发射机(或射频电路)、存储器、其他输入设备、显示屏、传感器、音频电路、I/O(input/output,输入/输出)子系统、处理器、充电管理芯片和电源管理芯片等部件。移动终端还可以包括摄像头、蓝牙模块、虚拟按键、实体按键等部件，在此不再赘述。本领域技术人员可以理解，上述移动终端的结构并不构成限定，可以包括更多或更少的部件，或者组合某些部件，或者拆分某些部件，或者不同的部件布置。常见的移动终端例如包括：手机、平板电脑、笔记本电脑、PDA(Personal Digital Assistant，个人数字助理)、掌上电脑、MID(Mobile Internet Device，移动互联网设备)、POS(Point of Sales，销售终端)、车载电脑、可穿戴设备(例如智能手表、智能手环、计步器)等。
通信设备也可以为基站，基站可以用于与一个或多个用户设备进行通信，也可以用于与一个或多个具有部分用户设备功能的基站进行通信(比如宏基站与微基站，如接入点，之间的通信)；基站还可以称为接入点、节点、节点B、演进节点B(eNB)或某种其它网络实体，并且可以包括以上网络实体的功能中的一些或所有功能。基站可以通过空中接口与用户设备或其他基站进行通信。该通信可以通过一个或多个扇区来进行。基站可以通过将所接收的空中接口帧转换成IP(英文全称：internet protocol，简称：IP)分组，来用作无线终端和接入网络的其余部分之间的路由器，其中所述接入网络包括IP网络。基站还可以对空中接口属性的管理进行协调，并且还可以是有线网络和无线网络之间的网关。
在本申请的实施例中使用的术语是仅仅出于描述特定实施例的目的，而非旨在限制本申请。在本申请实施例和所附权利要求书中所使用的单数形式的“一种”、“所述”和“该”也旨在包括多数形式，除非上下文清楚地表示其他含义。还应当理解，本文中使用的术语“和/或”是指并包含一个或多个相关联的列出项目的任何或所有可能组合。本文中字符“/”，一般表示前后关联对象是一种“或”的关系。此外本申请中的“第一”和“第二”等等并不表示重要性或先后顺序，仅表示一种区别。
在本申请实施例中，“示例的”一词用于表示作例子、例证或说明。本申请中被描述为“示例”的任何实施例或设计方案不应被解释为比其它实施例或设计方案更优选或更具优势。确切而言，使用示例的一词旨在以具体方式呈现概念。本申请所使用的术语“耦合”可以包含将相互耦合的两个器件进行直接连接，通过阻抗网络、容抗网络、感抗网络中的任一或其组合形式间接连接，或者其他形式的连接，对此本申请并不具体限定相互耦合的两个器件之间的具体连接形式。此外，“耦合至地”可以指直接连接地(GND)或者间接连接地。
为实现在发射链路上发送或接收链路上接收的信号的动态范围，通常在发射链路或接收链路上设置可变增益的放大器，同时为保证链路上信号的相位恒定，可变增益的放大器需要实现相位调节功能，应该理解的是，当应用于接收链路时，放大器可以为接收机中的低噪声放大器(low noise amplifier，LNA)，当应用 于发射链路时，放大器可以为发射机中的功率放大器(power amplifier，PA)；当然在采用将接收机和发射机功能集成于一体的收发机时，本申请的实施例是应用于在收发机的发射链路或接收链路上设置的放大器。
参照图1所示，本申请的实施例提供一种放大器，具体包括：
第一MOS管M1、第二MOS管M2和第三MOS管M3；其中，第一MOS管M1的栅极分别耦合至信号输入端in以及偏置电压输入端Vbias；第一MOS管M1的源极与电源V1相耦合，第一MOS管M1的漏极分别耦合至第二MOS管M2的源极以及第三MOS管M3的源极，第三MOS管M3的漏极耦合至GND，第二MOS管M2的漏极耦合至信号输出端out。
针对上述的放大器的控制方式如下：第二MOS管M2的栅极用于在第一栅极控制信号的控制下，使第二MOS管M2处于导通状态；第三MOS管M3的栅极用于在第二栅极控制信号的控制下，通过改变第三MOS管M3的截止状态或导通状态，对第一MOS管M1的漏极输出的交流信号进行旁路控制；偏置电压输入端Vbias用于接收偏置电压，以调整信号输入端in的输入信号与信号输出端out的输出信号之间的相位差。应当知道，电源V1向第一MOS管M1的源极提供的信号通常是恒流的，然而，当第一MOS管M1的栅极信号是时变信号时，在第一MOS管M1的漏极生成的信号是交流信号。
需要说明的是，当放大器处于工作状态时，第二MOS管M2栅极的第一栅极控制信号满足使得第二MOS管M2处于导通状态，第三MOS管M3状态通过栅极的第二栅极控制信号控制，其中M3有截止状态和导通状态。例如，第二MOS管M2的栅极连接一个偏置电压模块，第三MOS管M3的栅极连接一个偏置电压模块，其中，第二MOS管M2的栅极偏置电压模块可以为M2的栅极提供第一栅极控制信号以实现对M2的状态控制。第三MOS管M3的栅极偏置电压模块可以为M3的栅极提供第二栅极控制信号以实现对M3的状态控制。示例性的，如图1所示，第一MOS管M1的栅极通过电容C1连接信号输入端in，第一MOS管的栅极通过分压电阻R1连接偏置电压输入端Vbias。
基于上述图1示出的电路对其工作原理说明如下：在M2处于导通状态下，可以控制第三MOS管截止，放大器处于一种增益状态下；当需要改变放大器的增益时，导通M3，M3将部分交流信号旁路到交流地(电源的地GND)中，使得放大器的增益下降进入另一种增益状态，以此来实现可变增益。另外，在增益发生改变时，向偏置电压输入端输入偏置电压，以调整信号输入端的输入信号与信号输出端的输出信号的相位差；例如，M3截止时，另外，在一种增益状态下，M3截止，对于M1在Vbias端输入第一偏置电压并维持恒定不变；当需要改变增益时，导通M3的同时降低M1在Vbias端的偏置电压，例如提供小于第一偏置电压的第二偏置电压，在这种状态下，M1由于偏置电压降低导致M1跨导gm降低，也可以使得放大器的增益下降，以此来实现可变增益。
而在切换增益的过程中，主要第二MOS管和第三MOS管的跨导变化引入相位差。这样在切换第三MOS管的状态(由截止状态到导通状态)的同时，改变偏置电压输入端输入第一MOS管的偏置电压，会使得流过第一MOS管的电流信号发生变化，当合理地改变第一MOS管的偏置电压时，可以调整第二MOS管和第三MOS管的跨导，从而实现了能够实现对输出相位的灵活调整。具体的，当仅通过切换M3的状态进行增益切换时，由于M1的漏极节点X的寄生电容C x的存在，使得切换增益时的相位发生了变化， 其等效模型如图2所示。节点X存在对地寄生电容C x，且C x＝Cds1+Cdb1+Cgs2+Csb2+Cds3+Csb3+Cgs3，因此最终流向输出的电流即为M1分到的电流，其中Cds1为M1的源漏寄生电容，Cdb1为M1的漏极衬底寄生电容，Cgs2为M2的栅源寄生电容，Csb2为M2的源极衬底寄生电容，Cds3为M3的源漏寄生电容，Csb3为M3的源极衬底寄生电容，Cgs3为M3的栅极衬底寄生电容。信号输入端in输入的信号Vin通过M1产生的交流电流为g m1*Vin，该交流电流在节点X处发生了分流。在节点X处，根据基尔霍夫电流定律可知，g m1*Vin＝I2+I3+Ix。其中I2为流经M2的电流，I3为流经M3的电流Ix为节点X的电流，Ix为流经电容C x的电流，g m1为M1的跨导。忽略衬偏效应和沟道长度调制效应，根据导纳分流关系可得到放大器最终流向输出的电流的相位误差为：
Figure PCTCN2018086614-appb-000001
其中g m2和g m2,max分别为M2在低增益和最大增益条件下的跨导，Phase1为放大器输入信号的相位，Phase2为放大器输出信号的相位，g m3为M3导通时的跨导，C x,on和C x,off分别为M3导通和关闭时节点X的对地寄生电容。尽管M3在导通和截止状态下的寄生电容有一定变化，但其对相位的影响较小，可以近似认为C x,on≈C x,off。因此根据式(1)可以得出：切换增益时，主要由M2和M3的跨导变化引入相位差。本申请中在切换M3的状态(由截止状态到导通状态)的同时，降低Vbias端输入M1的偏置电压，会使得流过M1的直流电流ID降低。当合理地改变Vbias端的偏置电压时，即可使得：
g m2,max＝g m2+g m3   (2)
结合式(1)可知，此时放大器在切换增益时的相位误差将为0，即实现了恒定相位的增益切换。
因此，在偏置电压输入端接收第一偏置电压时，放大器处于第一增益；偏置电压输入端接收第二偏置电压时，放大器处于第二增益；并且第一增益大于第二增益。其中，第二偏置电压是根据第一偏置电压以及公式g m2,max-(g m2+g m3)确定的；g m2,max为放大器在第一增益的状态下，第二MOS管的跨导；g m2为放大器在第二增益的状态下，第二MOS管的跨导；g m3为第三MOS管在导通状态下的跨导。具体的，第二偏置电压的确定方式可以采用如下方式：在通过M3切换增益后，可以向Vbias输入初始的第二偏置电压，并测量M2和M3的跨导，若需要实现相位恒定，则需要保证，g m2,max-(g m2+g m3)＝0，因此可以根据测得的M2和M3的跨导调整第二偏置电压，直至满足g m2,max-(g m2+g m3)＝0，此时保持调整后的第二偏置电压恒定。当然根据式(1)也可以调整第二偏置电压使得g m2,max-(g m2+g m3)＝δ，实现对应固定相位差的输出，从而实现移相功能。
图3给出了本申请所提出的放大器的仿真结果，横轴为增益，纵轴为功率增益(s21)的相位。曲线一为仅切换M3进行增益切换的相位变化，可以看出，增益切换4分贝(dB)引入的相位误差为3.9度；曲线二为仅通过切换M1偏置改变增益的相位变化，可以看出切换3.2dB增益引入的相位误差约为4.6度；曲线三为采用本申请所提出的切换增益方式引入的相位误差，从图3中可以看出切换7.1dB增益引入的相位误差约1.4度。 从表1中可以看出，采用切换M3状态进行增益切换引入的相位误差斜率分别为1度每分贝(°/dB)；采用调整M1偏置方式进行增益切换引入的相位误差斜率分别为1.4°/dB，而采用本申请的实施例提供的增益控制方式，其相位误差斜率仅为0.2°/dB，远小于前两种结构，因此采用本申请所提出的切换增益方式可以实现恒定相位的增益切换。
如图4所示，还包括：偏置电路SC，偏置电路SC包括电流源Ibias和第四MOS管M4，电流源Ibias的一端耦合至地GND，电流源Ibias的另一端耦合至第四MOS管M4的漏极以及第四MOS管M4的栅极，第四MOS管M4的栅极耦合至偏置电压输入端Vbias，所述第四MOS管M4的源极耦合至电源V1。
另外，放大器还包括至少一个与第一MOS管M1并联的第五MOS管M5，其中第五MOS管M5的栅极与第一MOS管M1的栅极相耦合；第五MOS管M5的源极与第一MOS管M1的源极相耦合；第五MOS管M5的漏极与第一MOS管M1的漏极相耦合。其中需要说明的是，在工作状态，控制至少一个M5的状态与M1处于同一状态。放大器还包括至少一个与第二MOS管M2并联的第六MOS管M6，其中第六MOS管M6的栅极与第二MOS管M2的栅极相耦合；第六MOS管M6的源极与所述第二MOS管M2的源极相耦合；第六MOS管M6的漏极与第二MOS管M2的漏极相耦合。其中需要说明的是，在工作状态，控制至少一个M6的状态与M2处于同一状态。放大器还包括至少一个与第三MOS管M3并联的第七MOS管M7，其中第七MOS管M7的栅极与第三MOS管M3的栅极相耦合；第七MOS管M7的源极与所述第三MOS管M3的源极相耦合；第七MOS管M7的漏极与所述第三MOS管M3的漏极相耦合。其中需要说明的是，在工作状态，控制至少一个M7的状态与M3处于同一状态。
本申请实施提供一种放大器的电路版图如图5所示，其中包含了三个MOS管，M1(其中可以为一个或多个M1的并联，图中示出了8个M1的并联结构)，M2(其中可以为一个或多个M2的并联，图中示出了4个M2并联结构)，M3(其中可以为一个或多个M3的并联，图中示出了4个M3并联结构)。其中M2的漏极(Drain)接信号输出端，M3的漏极接地GND。在版图中M1、M2和M3的栅极(Gate,其中栅极下方为有源层，有源层可以为在聚乙烯poly生长硅化物或无机金属氧化物形成)分别连接一个偏置电压模块。
其中如图1、图4所示的放大器为单端形式的放大器，参照图6所示，本申请的实施例还提供一种差分形式的放大器，具体的包括第一放大器PA1和第二放大器PA2，其中第一放大器PA1和第二放大器PA2的形式如图1、图4示出的单端形式的放大器，此处不再赘述。第一放大器PA1的偏置电压输入端耦合至第二放大器PA2的偏置电压输入端。
上述的放大器还能够提高输入线性度，具体说明如下：
在射频收发链路中，降低增益通常是由于输入信号过大，需要降低增益以确保输入信号被线性放大，因此在降低增益时通常需要能够提高输入线性。对于放大器(VGA)来说，当仅采用M3进行增益切换时，交流电流被直接旁路到交流接地端中(电源的GND)，因此输出的线性度OP1dB会随着增益同步下降，使得输入线性IP1dB并不改变。
对于放大器来说，当其输入为频率为ω 1，幅度为A的正弦波，其输出包含了ω 1及 ω 1的各次谐波，考虑功率较大的前三次谐波，则其输出可以表示为：
y out＝g 1Acosω 1t+g 2(Acosω 1t) 2+g 3(Acosω 1t) 3   (3)
其中g 1为M1的跨导，g 2为M1的跨导一阶导数，g 3为M1的跨导二阶导数。从上式可以得出，放大器输出的基频信号的幅度和放大器电压增益为：
Figure PCTCN2018086614-appb-000002
对于典型的放大器，其g 3项为负数，因此随着输入信号幅度A的增加，基频信号的增益将逐步降低，增益降低1dB时的输入信号功率就是输入IP1dB点的定义。在最大增益条件下，若MOS管的偏置状态使得g 3为负数，同时采用本申请的实施例所提出的M3状态切换+M1偏置的方式切换增益。当M1的偏置使得g 3为正数时，则根据式(4)可以得出：放大器的增益不再压缩，即M1的跨导g m1贡献的输入IP1dB成分降低了，使得放大器的IP1dB提升。从另一个角度来说，本申请的实施例所采用的M3状态切换+M1偏置的方式，在切换增益时降低了输入直流偏置，降低了M1的过驱动电压(Vgs-Vth),因而使得放大器从A类状态逐步切换到B类状态，在实现恒定相位的同时实现了放大器的输入线性度(IP1dB)提升。
此外，本申请的实施例提供一种放大电路，放大电路至少包括第一放大器和第二放大器。
参照图7、图8所示，放大电路包括第一放大器S1和第二放大器S2，图中还示出了第三放大器S3，其中第一放大器S1和第二放大器S2之间设置有输入匹配网络P1和输出匹配网络P2，其中S1的信号输出端out耦合至输出匹配网络P2的输入端；输出匹配网络P2的输出端output耦合至输入匹配网络P1的输入端input；输入匹配网络P1的输出端耦合至S2的信号输入端in；其中，输出匹配网络P2用于将S1的信号输出端的第一电压值变换为第二电压值；输入匹配网络P1用于将第二电压值变换为第三电压值。类似的，第二放大器S2和第三放大器S3之间也设置有输入匹配网络和输出匹配网络；第一放大器S1和第二放大器S2和第三放大器S3的至少一个为上述实施例提供的放大器。示例性的输入匹配网络P1和输出匹配网络P2可以为变压器。其中，输入匹配网络P1和输出匹配网络P2主要用于实现级联的放大器之间输出信号与输出信号的转换，例如电压或电流的转换。从而使得前一级放大器的输出信号能够作为进入下一级放大器的输入信号。
以图8为例，对于每一级放大器，其输入侧设置有输入匹配网络Pin、其输出侧设置有输出匹配网络Pout。当然，每一级放大器也可以直接包含其输入侧设置的输入匹配网络Pin、以及输出侧设置的输出匹配网络Pout，这样可以直接将放大器进行级联。
在采用差分形式的放大器时，放大电路至少包括第一差分形式的放大器和第二差分形式的放大器。如图9、图10所示，放大电路包括第一差分形式的放大器S1、第二差分形式的放大器S2和第三差分形式的放大器S3，其中第一差分形式的放大器与第二差分形式的放大器S2之间设置有输入匹配网络P1和输出匹配网络P2，其中第一差 分形式的放大器S1的第一放大器的信号输出端out+耦合至输出匹配网络P2的第一输入端，第一差分形式的放大器S1的第二放大器的信号输出端out-耦合至输出匹配网络P2的第二输入端；输出匹配网络P2的第一输出端output1耦合至输入匹配网络P1的第一输入端input1，输出匹配网络P2的第二输出端output2耦合至输入匹配网络P1的第二输入端input2；输入匹配网络P1的第一输出端耦合至第二差分形式的放大器S2的第一放大器的信号输入端in+，输入匹配网络P1的第二输出端耦合至第二差分形式的放大器的第二放大器的信号输入端in-；其中，输出匹配网络P2用于将前一级差分形式的放大器输出的第一差分信号变换为第二差分信号；输入匹配网络P1用于将第二差分信号变换为第三差分信号。其中，输入匹配网络P1和输出匹配网络P2主要用于实现级联的差分形式的放大器之间输出信号与输入信号的转换，例如电压或电流的转换。从而使得前一级差分形式的放大器的输出信号能够作为进入下一级差分形式的放大器的输入信号。类似的，第二差分形式的放大器S2和第三差分形式的放大器S3之间也设置有输入匹配网络和输出匹配网络；第一差分形式的放大器S1和第二差分形式的放大器S2和第三差分形式的放大器S3的至少一个为上述实施例提供的放大器。
以图10为例，对于每一级差分形式的放大器，其输入侧设置有输入匹配网络Pin、其输出侧设置有输出匹配网络Pout。当然，每一级差分形式的放大器也可以直接包含其输入侧设置的输入匹配网络Pin、以及输出侧设置的输出匹配网络Pout，这样可以直接将差分形式的放大器进行级联。
其中需要说明的是，上述图7、图9提供的放大电路的增益控制方式为在某一级放大器(或差分形式的放大器)通过本申请所提出的方式进行增益切换；或在其中一级采用改变管M3的状态切换增益，在另外一级放大器(或差分形式的放大器)采用改变M1的偏置电压切换增益以实现恒相位增益切换。
除了IP1dB点，放大器的输入三阶交调点IIP3也决定了其线性度。针对IIP3，放大器的非线性成分主要由M1的跨导g m1的非线性产生。采用本申请所提出的改变M3的状态+改变M1的偏置电压的方式切换增益,随着偏置电压Vbias的降低，式(3)的g 3项从负数变为正数。因此两级放大器(差分形式的放大器)的M1跨导g m1的非线性项产生了抵消，降低了输出端的三阶交调项(IM3项)，而此时级联放大器(差分形式的放大器)的增益是降低的，因此此时级联放大器(差分形式的放大器)的输入线性IIP3得到了提升。
图11-图13给出了采用本申请所提出的增益切换方式时图7-10提供的放大电路对信号收发链路引入的特征点，基于前文的分析可知，本申请采用了改变M3的状态+改变M1的偏置电压的方式切换增益实现增益切换，参照图11所示，示出了增益与相位的关系，其中横轴为增益(沿横轴向右侧增益逐步增大)，纵轴为相位(沿纵轴向上相位逐步增大)，明显在切换增益(增益发生改变)时，增益(S21或电压增益)对应的相位基本保持恒定或变化很小；参照图12所示，示出了增益与功耗的关系，其中横轴为增益(沿横轴向右侧增益逐步增大)，纵轴为功耗(沿纵轴向上侧功耗逐步增大)，明显在低增益时的功耗低，高增益时功耗大；参照图13所示，示出了增益与输入线性度的关系，其中横轴为增益(沿横轴向右侧增益逐步增大)，纵轴为输入线 性度(沿纵轴向上侧线性度逐步增大)，随着增益的降低，输入线性度(IP1dB或IIP3)逐步提升。
如图14所示，本申请的实施例提供一种移相器包括第一放大器S1、第二放大器S2和第三放大器S3，以及匹配网络P1；
其中，第一放大器S1的信号输出端out耦合至匹配网络P1的第一输入端，第二放大器S2的信号输出端out耦合至匹配网络P1的第二输入端；匹配网络P1的第一输出端耦合至第三放大器的信号输入端in，匹配网络P1的第二输入端耦合至地GND；匹配网络P1用于将第一放大器S1的信号输出端与第二放大器S2的信号输出端的第一电压差值变换为第二电压差值。第一放大器S1和第二放大器S2和第三放大器S3的至少一个为上述实施例提供的放大器。
示例性的如图15所示，匹配网络P1可以为变压器，此时变压器的初级的两个输入端分别连接第一放大器S1的信号输出端out和第二放大器S2的信号输出端out。变压器的次级的两个输出端分别连接第三放大器的信号输入端in和接地GND。
如图16所示，在采用差分形式的放大器时，本申请的实施例提供一种移相器包括第一差分形式的放大器S1、第二差分形式的放大器S2、第三差分形式的放大器S3，以及匹配网络P1；其中，第一差分形式的放大器S1的第一放大器的信号输出端out+耦合至匹配网络P1的第一输入端，第一差分形式的放大器S1的第二放大器的信号输出端out-耦合至匹配网络P1的第二输入端；第二差分形式的放大器S2的第一放大器的信号输出端out+耦合至匹配网络P1的第三输入端，第二差分形式的放大器S2的第二放大器的信号输出端out-耦合至匹配网络P1的第四输入端；匹配网络P1的第一输出端耦合至第三差分形式的放大器S3的第一放大器的信号输入端in+，匹配网络P1的第二输入端耦合至第三差分形式的放大器的第二放大器的信号输入端in-；匹配网络P1用于将第一差分形式的放大器S1输出的第一差分信号，以及第二差分形式的放大器S2输出的第二差分信号合成为第三差分信号并输入第三差分形式的放大器S3。第一差分形式的放大器S1和第二差分形式的放大器S2和第三差分形式的放大器S3的至少一个为上述实施例提供的放大器。示例性的，匹配网络P1可以为合路器件，例如功率合成器件、电压合成器件或者电流合成器件等。
基于上述图14-图16提供的移相器，其可以实现正交信号(I信号,Q信号)合成时的增益调整，以图14提供的移相器进行说明，可以将I信号的电压Vin_I自S1的信号输入端输入，将Q信号的电压Vin_Q自S2的信号输入端输入，则通过S1与S2分别调整Vin_I,Vin_Q的增益和相位，从而改变Vin_I,Vin_Q的合成比例，最终通过S3可以调整合成信号的增益和相位，最终可以实现基于可变增益放大器的有源移相器。其实现原理如图17所示，通过改变S1和S2的增益使正交信号I和Q经过不同的放大后进行合路，最终S1的输出Vout_I和S2的输出Vout_Q具有不同的相位Φ1和Φ2，实现了移相功能。在调整I信号和Q信号增益时，可采用本申请所提出的恒定相位增益切换方式，以避免引入额外的相位差，降低有源移相器的精度，其次，由于有源移相器进行合路后输出信号的幅度不同，为了降低不同相位下的增益波动，可在合路后通过S3调整最终的输出。同时，S3采用本申请所提出的恒定相位增益控制方式，可确保调整增益不引入额外的相位差，保证了有源移相器的相位精度。参照图17所示， 对正交信号I1和Q1放大后合路得到相位为θ1的输出信号OUT1，对正交信号I2和Q2放大后合路得到相位为θ2的输出信号OUT2。此外，需要说明的是，在采用图16所示的移相器，其原理与上述类似，区别为I信号以及Q信号分别采用差分信号形式。
以上所述，仅为本申请的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应所述以权利要求的保护范围为准。

Claims (11)

  1. 一种放大器，其特征在于，包括：第一MOS管、第二MOS管和第三MOS管；
    所述第一MOS管的栅极分别耦合至信号输入端以及偏置电压输入端，所述第一MOS管的源极与电源相耦合，所述第一MOS管的漏极分别耦合至所述第二MOS管的源极以及所述第三MOS管的源极，所述第三MOS管的漏极耦合至地，所述第二MOS管的漏极耦合至信号输出端；
    其中，所述第二MOS管的栅极用于在第一栅极控制信号的控制下，使所述第二MOS管处于导通状态；所述第三MOS管的栅极用于在第二栅极控制信号的控制下，通过改变所述第三MOS管的截止状态或导通状态，对所述第一MOS管的漏极输出的交流信号进行旁路控制；
    所述偏置电压输入端用于接收偏置电压，以调整所述信号输入端的输入信号与所述信号输出端的输出信号之间的相位差。
  2. 根据权利要求1所述的放大器，其特征在于，
    当所述第三MOS管处于截止状态时，所述偏置电压输入端接收的所述偏置电压为第一偏置电压；当所述第三MOS管处于导通状态时，所述偏置电压输入端接收的所述偏置电压为第二偏置电压；其中，所述第一偏置电压大于所述第二偏置电压。
  3. 根据权利要求2所述的放大器，其特征在于，
    所述偏置电压输入端接收所述第一偏置电压时，所述放大器处于第一增益；所述偏置电压输入端接收所述第二偏置电压时，所述放大器处于第二增益；所述第一增益大于所述第二增益。
  4. 根据权利要求3所述的放大器，其特征在于，所述第二偏置电压是根据所述第一偏置电压以及公式g m2,max-(g m2+g m3)确定的；
    其中，g m2,max为所述放大器在所述第一增益的状态下，所述第二MOS管的跨导；所述g m2为所述放大器在所述第二增益的状态下，所述第二MOS管的跨导；所述g m3为所述第三MOS管在导通状态下的跨导。
  5. 根据权利要求1所述的放大器，其特征在于，还包括：偏置电路，所述偏置电路包括电流源和第四MOS管，所述电流源的一端耦合至地，所述电流源的另一端耦合至所述第四MOS管的漏极以及所述第四MOS管的栅极，所述第四MOS管的栅极耦合至所述偏置电压输入端，所述第四MOS管的源极耦合至所述电源。
  6. 根据权利要求1所述的放大器，其特征在于，所述第一MOS管的栅极通过分压电阻连接偏置电压输入端。
  7. 根据权利要求1所述的放大器，其特征在于，还包括至少一个与第一MOS管并联的第五MOS管，其中所述第五MOS管的栅极与第一MOS管的栅极相耦合；所述第五MOS管的源极与所述第一MOS管的源极相耦合；所述第五MOS管的漏极与所述第一MOS管的漏极相耦合。
  8. 根据权利要求1所述的放大器，其特征在于，还包括至少一个与第二MOS管并联的第六MOS管，其中所述第六MOS管的栅极与第二MOS管的栅极相耦合；所述第六MOS管的源极与所述第二MOS管的源极相耦合；所述第六MOS管的漏极与所述第二MOS管的漏极相耦合。
  9. 根据权利要求1所述的放大器，其特征在于，还包括至少一个与第三MOS管并联的第七MOS管，其中所述第七MOS管的栅极与第三MOS管的栅极相耦合；所述第七MOS管的源极与所述第三MOS管的源极相耦合；所述第七MOS管的漏极与所述第三MOS管的漏极相耦合。
  10. 一种放大电路，其特征在于，所述放大电路至少包括第一放大器和第二放大器；
    所述第一放大器和所述第二放大器之间设置有输入匹配网络和输出匹配网络，其中：
    所述第一放大器的信号输出端耦合至所述输出匹配网络的输入端；
    所述输出匹配网络的输出端耦合至所述输入匹配网络的输入端；
    所述输入匹配网络的输出端耦合至所述第二放大器的信号输入端；
    其中，所述输出匹配网络用于将所述第一放大器的信号输出端的第一电压值变换为第二电压值；
    所述输入匹配网络用于将所述第二电压值变换为第三电压值；
    所述第一放大器和所述第二放大器的至少一个为权利要求1-9任一项所述的放大器。
  11. 一种移相器，其特征在于，包括第一放大器、第二放大器、第三放大器以及匹配网络；
    其中，所述第一放大器的信号输出端耦合至所述匹配网络的第一输入端，所述第二放大器的信号输出端耦合至所述匹配网络的第二输入端；
    所述匹配网络的第一输出端耦合至所述第三放大器的信号输入端，所述匹配网络的第二输入端耦合至地；
    所述匹配网络用于将所述第一放大器的信号输出端与第二放大器的信号输出端的第一电压差值变换为第二电压差值；
    所述第一放大器和所述第二放大器和所述第三放大器的至少一个为权利要求1-9任一项所述的放大器。
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