WO2020133524A1 - 一种可变增益放大器及相控阵系统 - Google Patents

一种可变增益放大器及相控阵系统 Download PDF

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WO2020133524A1
WO2020133524A1 PCT/CN2018/125850 CN2018125850W WO2020133524A1 WO 2020133524 A1 WO2020133524 A1 WO 2020133524A1 CN 2018125850 W CN2018125850 W CN 2018125850W WO 2020133524 A1 WO2020133524 A1 WO 2020133524A1
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tube
circuit
transistor
amplifier
common
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PCT/CN2018/125850
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English (en)
French (fr)
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关允超
卢磊
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华为技术有限公司
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Priority to CN201880100545.6A priority Critical patent/CN113574798B/zh
Priority to EP18944356.7A priority patent/EP3893392A4/en
Priority to PCT/CN2018/125850 priority patent/WO2020133524A1/zh
Publication of WO2020133524A1 publication Critical patent/WO2020133524A1/zh
Priority to US17/362,885 priority patent/US12088268B2/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
    • H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
    • H03F3/193—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only with field-effect devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G3/00—Gain control in amplifiers or frequency changers
    • H03G3/20—Automatic control
    • H03G3/30—Automatic control in amplifiers having semiconductor devices
    • H03G3/3036—Automatic control in amplifiers having semiconductor devices in high-frequency amplifiers or in frequency-changers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/56—Modifications of input or output impedances, not otherwise provided for
    • H03F1/565—Modifications of input or output impedances, not otherwise provided for using inductive elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H03F3/45183—Long tailed pairs
    • H03F3/45188—Non-folded cascode stages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/68—Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/72—Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G1/00—Details of arrangements for controlling amplification
    • H03G1/0005—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal
    • H03G1/0017—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal the device being at least one of the amplifying solid state elements of the amplifier
    • H03G1/0023—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal the device being at least one of the amplifying solid state elements of the amplifier in emitter-coupled or cascode amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G1/00—Details of arrangements for controlling amplification
    • H03G1/0005—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal
    • H03G1/0017—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal the device being at least one of the amplifying solid state elements of the amplifier
    • H03G1/0029—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal the device being at least one of the amplifying solid state elements of the amplifier using FETs
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G1/00—Details of arrangements for controlling amplification
    • H03G1/0005—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal
    • H03G1/0088—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal using discontinuously variable devices, e.g. switch-operated
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G5/00—Tone control or bandwidth control in amplifiers
    • H03G5/16—Automatic control
    • H03G5/24—Automatic control in frequency-selective amplifiers
    • H03G5/28—Automatic control in frequency-selective amplifiers having semiconductor devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/111—Indexing scheme relating to amplifiers the amplifier being a dual or triple band amplifier, e.g. 900 and 1800 MHz, e.g. switched or not switched, simultaneously or not
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45481—Indexing scheme relating to differential amplifiers the CSC comprising only a direct connection to the supply voltage, no other components being present
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/72—Indexing scheme relating to gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
    • H03F2203/7236—Indexing scheme relating to gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal the gated amplifier being switched on or off by putting into parallel or not, by choosing between amplifiers by (a ) switch(es)
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G2201/00—Indexing scheme relating to subclass H03G
    • H03G2201/10—Gain control characterised by the type of controlled element
    • H03G2201/103—Gain control characterised by the type of controlled element being an amplifying element
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G2201/00—Indexing scheme relating to subclass H03G
    • H03G2201/30—Gain control characterized by the type of controlled signal
    • H03G2201/307—Gain control characterized by the type of controlled signal being radio frequency signal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/02—Transmitters
    • H04B1/04—Circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06—Receivers
    • H04B1/16—Circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
    • H04B1/40—Circuits

Definitions

  • the present application relates to the field of communication technology, and in particular to a variable gain amplifier and a phased array system with constant phase and step gain.
  • 5G Fifth generation mobile communications
  • WiGig wireless Gigabit Alliance
  • ADAS Advanced Driver Assistance Systems
  • Small cellular and broadband satellite communications such as: 5G mobile phones, wireless infrastructure, wireless Gigabit Alliance (WiGig), advanced driver assistance systems (Advanced Driver Assistance Systems, ADAS), Small cellular and broadband satellite communications.
  • MIMO multi-input multiple output
  • a phased array system needs to use a variable-gain amplifier (VGA) or attenuator in each transmit/receive channel to compensate for gain changes between array elements.
  • VGA variable-gain amplifier
  • Figure 1 shows a typical phased array transmitter. After the signals of each channel with a specific phase transmitted by the transmitter are spatially superimposed, a signal beam with enhanced signal power and directivity is formed. As shown in Figure 1, in any transmit channel, in addition to using a phase shifter for phase control, VGA is also required to provide a certain dynamic gain, and VGA is required to maintain a relatively constant phase while gain switching.
  • the VGA adopts a cascode structure, splits the cascode into multiple transistors (M3 ⁇ M8 in the figure), and controls the cascode Turn on to achieve gain switching.
  • M3 and M4 are always on; in high gain mode, M5 and M6 are on, and M7 and M8 are off, then all signal current flows through the first node (C, D port) in the figure Output matching network; turn off M5 and M6 tubes in low gain mode, and turn on M7 and M8 tubes at the same time. Since only part of the current flows to the output matching network, the gain is reduced, thereby achieving gain switching.
  • Embodiments of the present application disclose a variable gain amplifier and a phased array system with phase and step gain consistency during gain switching, to overcome the problem of performance degradation of the existing VGA during gain switching.
  • an embodiment of the present application provides a variable gain amplifier, including: a Cascode circuit, including a first amplifier tube and a second amplifier tube array, and the second amplifier tube array includes a plurality of parallel second amplifier tubes For outputting adjustable current to the output matching network, wherein the Cascode circuit is a cascode circuit, the first amplifier tube is a common source tube, and the second amplifier tube is a common grid tube, or the The Cascode circuit is a common-emitter common-base circuit, the first amplifying tube is a common-emitter amplifier, the second amplifying tube is a common-base amplifier; and a variable capacitance circuit is respectively arrayed with the second amplifying tube
  • the output matching network is coupled to a first node, and is used to adjust a parasitic capacitance of the second amplifier tube array relative to the output matching network.
  • the conduction condition of the second amplifier tube in the second amplifier tube array will change.
  • the parasitic capacitance of the Cascode circuit relative to the first node will also follow Changes, and changes in the parasitic capacitance will cause the output matching of the VGA when switching the gain to change, and thus can not guarantee the constant phase and the consistency of the gain step at different frequencies.
  • the parasitic capacitance change caused by the second amplifier tube array relative to the first node during gain switching Compensation is performed so that the parasitic capacitance seen from the first node remains approximately constant before and after gain switching, and accordingly, the matching of the final output of the VGA also remains consistent. In this way, when the gain is switched by the VGA, the consistency of the gain step and phase can be maintained in a wider frequency band.
  • variable capacitance circuit is specifically used to adjust the second amplifier tube array relative to the output matching network when the variable gain amplifier performs gain switching To compensate for changes in parasitic capacitance.
  • variable capacitance circuit includes a varactor, and one end of the varactor is coupled to the In the first node, the other end of the varactor is connected to a control voltage for adjusting the capacitance of the varactor.
  • variable capacitance circuit includes a metal oxide semiconductor (MOS) tube, and a gate of the MOS tube is coupled to In the first node, the source electrode and the drain electrode of the MOS tube are shorted together and then connected to a control voltage for adjusting the gate capacitance of the MOS tube.
  • MOS metal oxide semiconductor
  • variable capacitance circuit includes a switch and a capacitor, and one end of the switch is coupled to one end of the capacitor, The other end of the capacitor is coupled to the first node, the other end of the switch is connected to a control voltage, and the capacitance value of the variable capacitance circuit is changed by controlling the switch on or off.
  • the second amplifier tube array is used to change the number of second amplifier tubes connected between the second amplifier tube array and the output matching network , Output the adjustable current.
  • the first amplifier tube is a transistor M1
  • the second amplifier tube array includes a transistor M3 and at least one set of transistor branches
  • the transistor branch includes a transistor M5 and a transistor M7, wherein the source/emitter of the transistor M3, the transistor M5 and the transistor M7 are respectively coupled to the drain/collector of the transistor M1, the The drain/collector of the transistor M7 is connected to the power supply voltage, and the drain/collector of the transistor M3 and the transistor M5 are respectively coupled to the first node.
  • the Cascode circuit further includes an inductor, one end of the inductor is coupled to the drain/collector of the transistor M1, and the other end of the inductor is respectively connected to the transistor M3.
  • the source/emitter of the transistor M5 and the transistor M7 are coupled.
  • the Cascode circuit is a differential circuit or a single-ended circuit.
  • variable capacitance circuit is a differential circuit or a single-ended circuit.
  • an embodiment of the present application provides a phased array system, including: a plurality of channels, where any channel includes the variable gain amplifier as provided in the first aspect or any possible implementation manner of the first aspect.
  • variable gain amplifier provided in the first aspect can maintain a constant phase and gain step during gain switching, when the variable gain amplifier is applied to a phased array system, the phase control The array system has good phase consistency and gain performance when working in the millimeter wave band.
  • the phased array system may be a phased array receiver, a phased array transmitter, or a phased array transceiver.
  • the phased array system works in the 5G NR band.
  • the 5G NR frequency band includes: n257 frequency band, n258 frequency band, n260 frequency band, or n261 frequency band.
  • FIG. 1 is a schematic structural diagram of a phased array receiver in the prior art
  • FIG. 2 is a schematic structural diagram of a VGA in the prior art
  • 3a-3e are schematic structural diagrams of a VGA provided by an embodiment of the present application.
  • 4a is a schematic diagram of the step gain curve of the existing VGA shown in FIG. 2;
  • 4b is a schematic diagram of the step gain curve of the VGA shown in FIG. 3a;
  • 5a is a schematic diagram of the phase curve of the existing VGA shown in FIG. 2;
  • 5b is a schematic diagram of the phase curve of the VGA shown in FIG. 3a;
  • FIG. 6 is a schematic structural diagram of another VGA provided by an embodiment of the present application.
  • FIGS. 7a-7c are structural schematic diagrams of a single-ended structure VGA provided by embodiments of the present application.
  • At least one (item) refers to one or more
  • “multiple” refers to two or more
  • at least two (items) refers to two or three And more than three
  • "and/or” used to describe the association relationship of the associated object, indicating that there can be three kinds of relationships, for example, "A and/or B” can mean: only A, only B and A And B three cases, where A, B can be singular or plural.
  • the character “/” generally indicates that the related object is a "or” relationship.
  • “At least one of the following” or similar expressions refers to any combination of these items, including any combination of a single item or a plurality of items.
  • At least one (a) of a, b, or c can be expressed as: a, b, c, "a and b", “a and c", “b and c", or "a and b and c" ", where a, b, c can be a single or multiple.
  • an embodiment of the present application provides a variable gain amplifier (VGA) 30 with constant phase and step gain.
  • VGA variable gain amplifier
  • the VGA30 may include:
  • Cascode circuit 31 includes a cascode tube 311 (M1, M2) and a cascode tube array 312 composed of multiple cascode tubes (M3, M4, M5, M6, M7, M8) connected in parallel, wherein, the common source tube 311 is used to convert the input voltage Vin into a current, and the common gate tube array 312 is used to adjust the current output by the common source tube 311, and output an adjustable current to the output matching network 33;
  • variable capacitance circuit 32 is respectively coupled to the common node array 312 and the output matching network 33 to a first node (C, D) for adjusting the common gate array 312 relative to the output The parasitic capacitance of the matching network 33;
  • the output matching network 33 is used to convert the current output by the common grid array 312 into a voltage and output it to the outside, and adjust the impedance matching during output.
  • the output matching network 33 in the VGA 30 needs to have both load and impedance matching functions, so it can also be called a load and matching network, or a matching load.
  • the output matching network 33 may be a balun with a tuning capacitor.
  • the output matching network 33 of the present application is not limited to the specific example provided in FIG. 3b.
  • the Cascode circuit is also called a cascade amplifier, and can be implemented based on a metal oxide semiconductor (MOS) tube or a transistor. When using MOS tube, it can be called cascode circuit. When implemented with a triode, the Cascode circuit can also be called a common emitter common base circuit, and its working principle is similar to a common source common gate circuit. That is to say, in this embodiment, the Cascode circuit 31 can be regarded as including a cascaded first amplifier tube and second amplifier tube array, and the second amplifier tube array includes a plurality of parallel second amplifier tubes. The Cascode circuit is a cascode circuit, then the first amplifier tube is a common source tube, and the second amplifier tube is a common gate tube.
  • MOS metal oxide semiconductor
  • the Cascode circuit is a common emitter common base circuit
  • the first One amplifier tube is a common emitter amplifier circuit
  • the second amplifier tube is a common base amplifier circuit.
  • the MOS tube and the triode can be collectively called a transistor.
  • the following uses cascode circuit based on MOS tube as an example to further explain the working principle of VGA30.
  • the common source transistor M1 and the common gate tubes M3, M5, and M7 in parallel in the common gate tube array 312 form a first group of Cascode circuits, in which the sources of the common gate tubes M3, M5, and M7 are respectively connected to the common source tube
  • the drain of M1 is coupled to the second node (A)
  • the drain of the common-gate M7 is coupled to the power supply voltage Vcc
  • the drains of the common-gates M3 and M5 are respectively coupled to the output matching network 33 via the first node (C).
  • the common source transistor M2 and the common gate transistors M4, M6 and M8 constitute a second group of Cascode circuits, and the first group of Cascode circuits and the second group of Cascode circuits are differential circuits.
  • the sources of the cascode transistors M4, M6 and M8 are coupled to the second node (B) of the drain of the cascode transistor M2 respectively, the drain of the cascode transistor M8 is coupled to the power supply voltage Vcc, and the cascode transistors M4 and M6 The drain of the is coupled to the output matching network 33.
  • the circuits of the differential structure are usually designed symmetrically, for example: the common source tube M1 and the common source tube M2 are symmetrical, the common gate tubes M3 and M4 are symmetrical, M5 and M6 are symmetrical, M7 and M8 is also symmetrical; correspondingly, the variable capacitance circuit 32 also includes a differential variable capacitance. Therefore, for the differential structure, for convenience of expression, the subsequent embodiments and the drawings only mark and describe in detail one way in the differential structure. It should be understood that the other way not marked in the differential structure can be cross-referenced with each other and will not be described in detail .
  • the common gate transistor array 312 is input from the common source transistors M1 and M2. All the current flows to the output matching network 33; and when the VGA30 is switched to the low gain mode, by applying the conduction control signals Vcas_on to the gates of the common gates M3, M4, M7 and M8, respectively, the common gates M3, M4 are controlled. M7 and M8 are turned on, and the turn-off control signals Vcas_off are applied to the gates of the common-gate transistors M5 and M6, respectively, to control the turn-off of the common-gate transistors M5 and M6. Only part of the current will flow to the output matching network 33, and the other part of the current output by the common sources M1 and M2 is shunted by M7 and M8, so the gain is reduced.
  • the structure of the common emitter common base circuit can refer to the structure shown in FIG. 3a.
  • the common-emitter amplifier circuit M1 and the common-base amplifier circuits M3, M5, and M7 form the first group of Cascode circuits, in which the emitters of the common-base amplifier circuits M3, M5, and M7 are combined with the common-emitter amplifier circuit M1.
  • the electrodes are coupled to the second node (A)
  • the collector of the common base amplifying circuit M7 is coupled to the power supply voltage Vcc
  • the collectors of the common base amplifying circuits M3 and M5 are respectively coupled to the output matching network 33 via the first node (C) .
  • the VGA 30 When the VGA 30 performs gain switching, the turn-on condition of the common-gate transistor array 312 will change. Correspondingly, looking down from the first node (C, D), the Cascode circuit 31 is relative to the first node (C , D) the parasitic capacitance will change accordingly. Specifically, taking the high gain mode and the low gain mode as examples, in the two gain modes, the parasitic capacitances contributed by the common-gate transistors M5 and M6 to the output matching network 33 end have changed. Among them, when the VGA 30 is switched from the high gain to the low gain, the parasitic capacitance of the Cascode circuit 31 seen from the first node (C, D) is reduced. The change of the parasitic capacitance will cause the output matching of the VGA30 to change when the gain is switched, and thus the stability of the phase and the consistency of the gain step at different frequencies cannot be guaranteed.
  • variable capacitance circuit 32 is introduced in this embodiment.
  • the VGA 30 performs gain switching, by adjusting the capacitance value of the variable capacitance circuit 32, when the gain is switched, the common-gate transistor array 312 is relative to the first node ( C, D) to compensate for the parasitic capacitance change, so that the parasitic capacitance seen from the first node (C, D) remains approximately constant before and after gain switching, and accordingly, the matching of the final output of the VGA 30 also remains consistent.
  • the gain step and phase of the VGA 30 can be kept substantially constant in a wider frequency band.
  • variable capacitance circuit 32 may include a varactor 321, wherein one end of the varactor 321 is coupled to the first node (C), and the other end of the varactor 321 is connected to the control voltage Vcap
  • the capacitance of the varactor 321 can be adjusted to compensate for the parasitic capacitance change of the cascode array 312 relative to the output matching network 33 when the gain is switched, so that the first node (C, D) The parasitic capacitance seen is approximately constant.
  • variable capacitance circuit 32 may include a MOS tube 322, wherein the gate of the MOS tube 322 is coupled to the first node (C), and the source of the MOS tube 322 The pole and the drain are shorted together and then connected to the control voltage Vcap, which passes the voltage value of the control voltage Vcap.
  • the size of the gate capacitance of the MOS transistor 322 can be adjusted to compensate for the parasitic capacitance change of the common-gate array relative to the output matching network 33 when the gain is switched, so that the step gain and phase of the VGA 30 are substantially constant.
  • variable capacitance circuit 32 may include a switch 323 and a capacitor 324, where one end of the switch 323 is coupled to one end of the capacitor 324, and the other end of the capacitor 324 is coupled to In the first node (C), the other end of the switch 323 is connected to the control voltage Vcap.
  • the switch 323 By controlling whether the switch 323 is turned on or not, the capacitance value of the variable capacitor circuit 32 connected to the VGA 30 can be changed, and then the common gate transistor in the VGA 30 can be changed.
  • the array compensates for the change in the parasitic capacitance of the output matching network 33 when the gain is switched, so that the parasitic capacitance seen from the first node (C, D) is approximately stable, thereby achieving a substantially constant step gain and phase of the VGA 30.
  • the inductors L1 and L2 may also be introduced into the Cascode circuit 31, where one end of the inductor L1 is coupled to the drain of the common source tube M1 and the second node (A) , The other end of the inductor L1 is coupled to the source of each common-gate transistor (M3, M5 and M7) in the common-gate transistor array, the end of the inductor L2 and the drain of the common-source transistor M2 are coupled to the second node (B), the inductor The other end of L2 is coupled to the source of each cascode tube (M4, M6, and M8) in the cascode tube array.
  • the Cascode circuit 31 can be offset at the second node (A, B)
  • the effect of the parasitic capacitance of the variable capacitance circuit 32 can be combined with the variable capacitance circuit 32 to more accurately compensate for the change in the parasitic capacitance of the Cascode circuit 31 at the first node (C, D) when the gain is switched, further improving the step gain of the VGA 30 And phase constancy.
  • variable capacitance circuit 30 shows several alternative solutions of the variable capacitance circuit 30. Those skilled in the art should know that the variable capacitance circuit 30 can also be implemented by other circuit structures, and this application does not do this. Specific restrictions. Essentially, as long as the variable capacitance circuit 30 is connected to the first node (C, D), the parasitic capacitance of the cascode circuit 31 relative to the output matching network 33 can be adjusted.
  • Figure 4a is a schematic diagram of the step gain curve when the transceiver uses the existing VGA as shown in Figure 2.
  • the two curves of high gain and low gain respectively reflect when the VGA is in high gain and low
  • the gain step curve reflects the difference between the scattering parameters in the high gain mode and the low gain mode.
  • the S parameter value corresponding to the gain step curve is 7.113 dB
  • the S parameter value corresponding to the gain step curve is 6.152 dB
  • the gain step curve of the VGA is shown in FIG. 4b. It can be seen that in the frequency range of 24 GHz to 30 GHz, the S parameter value corresponding to the gain step curve is 6.593 dB at the frequency point of 24 GHz, and the S parameter value corresponding to the gain step curve is 6.585 dB at the frequency point of 30 GHz. At the frequency of 27GHz, the S parameter corresponding to the gain step curve is the maximum value (6.639dB). It can be seen that within the range of 24GHz to 30GHz, the error of the gain step between any two frequency points is less than 0.1dB, that is to say, the consistency of the gain step in a wide frequency range has been greatly improved.
  • the VGA's phase changes with frequency as shown in Figure 5a.
  • the VGA is in the low
  • the trend of the VGA phase with frequency is shown in FIG. 5b.
  • the embodiment of the present application further provides another VGA 40 with a constant phase and step gain.
  • the VGA 40 includes a Cascode circuit 41, an output matching network 43, and a variable capacitance circuit 42 coupled to the first node (C, D) with the Cascode circuit 41 and the output matching network 43, respectively.
  • the common grid tube array 412 is a differential structure, one of which may include a common grid tube M3 and m sets of parallel common grid tube branches, m is an integer greater than 1, and any common grid tube branch includes a common grid tube M5 And M7, the connection relationship between each common-grid tube branch and the common-grid tube M3, please refer to FIGS. 3a-3d and the foregoing embodiment regarding the connection relationship between M3, M5 and M7, which will not be repeated here.
  • variable capacitance circuit 42 may also include n parallel variable capacitance branches, and the n parallel branches are respectively connected to the common gate tube array 412 and the output matching network 43 Coupled to the first node (C, D), n is an integer greater than 1, and the structure of any variable capacitance branch can refer to the foregoing description about the variable capacitance circuit 32 in FIGS. 3a-3d, which will not be repeated.
  • the current of the output matching network 43 can be adjusted in multiple gears.
  • the common-gate transistor array 412 is relative to the output of the matching network 43
  • parasitic capacitance Therefore, by using the variable circuit circuit 42, finer compensation can be made for the parasitic capacitance change of the common-gate transistor array 412, so that the parasitic capacitance seen from the first node (C, D) is approximately stable, thereby achieving the VGA 40
  • the step gain and phase are approximately constant.
  • the number of variable capacitance branches and the number of common-gate branches may be equal or different.
  • an embodiment of the present application further provides a VGA based on a single-ended structure.
  • Figure 7a is a single-ended circuit using MOS tubes as compensation capacitors
  • Figure 7b is a single-ended circuit implementation form using varactor tubes as compensation capacitors
  • Figure 7c is a single-ended circuit implementation form using switches and capacitors as compensation capacitors. Since the differential circuit can be regarded as two symmetrically designed single-ended circuits, the VGA with a single-ended structure shown in FIGS. 7a-7c can be referred to the description of all the way in the differential circuit shown in FIGS. 3a-3d. No longer.
  • phased array system is also provided. Any channel of the phased array system includes the VGA described in the foregoing embodiment.
  • the phased array system may specifically be a phased array receiver, a phased array transmitter, or a phased array transceiver, and their structures and working principles may specifically refer to the existing technology, which will not be repeated here.
  • the phased array transceiver can work at 5G (NR) New radio (new radio frequency) frequency band
  • the 5G NR frequency band may include: n257 frequency band (26.5GHz-29.5GHz), n258 frequency band (24.25GHz-27.5GHz), n260 frequency band (37GHz-40GHz) and n261 frequency band (27.5GHz -28.35GHz) etc.

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Abstract

一种可变增益放大器以及相控阵接收机，其中，所述可变增益放大器（30，40）包括：Cascode电路（31，41），用于输出可调电流至输出匹配网络（33，43），其中，所述Cascode电路（31，41）为共源共栅电路，或者共射极共基极电路；以及可变电容电路（32，42），分别与Cascode电路（31，41）和所述输出匹配网络（33，43）耦合于第一节点，用于调整所述Cascode电路（31，41）相对于所述输出匹配网络（33，43）的寄生电容。当VGA（30，40）进行增益切换时，通过调节可变电容电路（32，42）的容值，对在增益切换时，Cascode电路（31，41）相对于第一节点引起的寄生电容变化进行补偿，从而在增益切换前后，使得从第一节点看到的寄生电容大致维持恒定，相应的，VGA（30，40）最终输出的匹配也维持一致。通过这种方式，在VGA（30，40）进行切换增益时，可以在较宽的频带内保持增益步进和相位的一致性。

Description

一种可变增益放大器及相控阵系统 技术领域
本申请涉及通信技术领域，尤其涉及一种具有恒定的相位和步进增益的可变增益放大器及相控阵系统。
背景技术
第五代移动通信(5G)是新一代无线系统和网络架构，它将在毫米波(mm Wave)频段(如28,39,60,86GHz等)中提供更快的数据速率，更低的延迟连接和更高的带宽，以支持许多高数据速率的应用，例如：5G手机，无线基础设施，无线千兆联盟(Wireless Gigabit Alliance，WiGig)，高级辅助驾驶系统(Advanced Driver Assistance Systems，ADAS)，小型蜂窝和宽带卫星通信等。
随着5G时代的到来，支持多入多出(MIMO)的相控阵技术在5G系统中的应用得到空前发展，具有波束形成功能的多通道收发机广泛被研究和应用。
相控阵系统需要在每个发射/接收通道中使用可变增益放大器(Variable-Gain Amplifier，VGA)或衰减器，以补偿阵列元件之间的增益变化。图1所示为一个典型的相控阵发射机，该发射机所发射的具有特定相位的各个通道信号在空间叠加后，形成信号功率和方向性都得到加强的信号波束。如图1所示，在任一发射通道中，除了采用移相器进行相位控制外，还需要采用VGA来提供一定的动态增益，且要求VGA在增益切换的同时能够保持相位相对恒定。
现有技术中的VGA实现方案如图2所示，该VGA采用共源共栅(cascode)结构，将共栅管拆分成多个晶体管(图中M3～M8管)，通过控制共栅管导通来实现增益切换。例如：正常工作时M3和M4始终保持导通；在高增益模式下M5和M6导通，而M7和M8关断，这时全部信号电流都经过图中第一节点(C，D端口)流向输出匹配网络；低增益模式下将M5和M6管关断，同时将M7和M8管导通，由于只有部分电流流向输出匹配网络，使得增益降低，从而实现了增益切换。
然而，上述方案在增益发生变化时，无法保持相位恒定，而且在不同频率下，增益步进也不一致，因此会恶化相控阵接收机的性能。
特别地，对于5G而言，由于5G信号的带宽较大，如何保持VGA增益步进在宽频带内的一致性也是射频前端设计的难点之一。
发明内容
本申请实施例公开了一种在增益切换时，具有相位以及步进增益一致性的可变增益放大器以及相控阵系统，以克服现有的VGA在增益切换时存在性能恶化的问题。
第一方面，本申请实施例提供了一种可变增益放大器，包括：Cascode电路，包括第一放大管和第二放大管阵列，所述第二放大管阵列包括多个并联的第二放大管，用于输出可调电流至输出匹配网络，其中，所述Cascode电路为共源共栅电路，所述第一放大管为共源管，所述第二放大管为共栅管，或者所述Cascode电路为共射极共基极电路，所述第一放大管为共射极放大器，所述第二放大管为共基极放大器；以及可变电容电路， 分别与所述第二放大管阵列和所述输出匹配网络耦合于第一节点，用于调整所述第二放大管阵列相对于所述输出匹配网络的寄生电容。当VGA进行增益切换时，第二放大管阵列中的第二放大管导通情况会发生变化，相应的，从第一节点往下看，Cascode电路相对于第一节点的寄生电容也会随之变化，而寄生电容的变化会导致VGA在切换增益时的输出匹配发生变化，进而无法保证相位的恒定和增益步进在不同频率的一致性。本实施例中通过引入了可变电容电路，当VGA进行增益切换时，通过调节可变电容电路的容值，对在增益切换时，第二放大管阵列相对于第一节点引起的寄生电容变化进行补偿，从而在增益切换前后，使得从第一节点看到的寄生电容大致维持恒定，相应的，VGA最终输出的匹配也维持一致。通过这种方式，在VGA进行切换增益时，可以在较宽的频带内保持增益步进和相位的一致性。
结合第一方面，在一种可能的实现方式中，所述可变电容电路具体用于在所述可变增益放大器进行增益切换时，对所述第二放大管阵列相对于所述输出匹配网络的寄生电容变化进行补偿。
结合第一方面或第一方面的上述任一可能的实现方式，在一种可能的实现方式中，所述可变电容电路包括变容管，其中，所述变容管的一端耦合至所述第一节点，所述变容管的另一端接用于调节所述变容管的电容值的控制电压。
结合第一方面或第一方面的上述任一可能的实现方式，在一种可能的实现方式中，所述可变电容电路包括金属氧化半导体(MOS)管，所述MOS管的栅极耦合至所述第一节点，所述MOS管的源极和漏极短接在一起后接用于调节所述MOS管的栅电容的控制电压。
结合第一方面或第一方面的上述任一可能的实现方式，在一种可能的实现方式中，所述可变电容电路包括开关和电容，所述开关的一端与所述电容的一端耦合，所述电容的另一端耦合至所述第一节点，所述开关的另一端接控制电压，通过控制所述开关的导通或关断，改变所述可变电容电路的电容值大小。
结合第一方面，在另一种可能的实现方式中，所述第二放大管阵列用于通过改变所述第二放大管阵列与所述输出匹配网络之间导通的第二放大管的数量，输出所述可调电流。
结合第一方面的前一种可能的实现方式，在一种可能的实现方式中，所述第一放大管为晶体管M1，所述第二放大管阵列包括晶体管M3和至少一组晶体管支路，所述晶体管支路包括晶体管M5和晶体管M7，其中，所述晶体管M3，所述晶体管M5和所述晶体管M7的源极/发射极分别耦合至所述晶体管M1的漏极/集电极，所述晶体管M7的漏极/集电极接电源电压，所述晶体管M3和所述晶体管M5的漏极/集电极分别耦合至所述第一节点。
在一种可能的实施方式中，所述Cascode电路还包括电感，所述电感的一端与所述晶体管M1的漏极/集电极相耦合，所述电感的另一端分别与所述晶体管M3，所述晶体管M5和所述晶体管M7的源极/发射极相耦合。
结合第一方面或第一方面的上述任一可能的实现方式，在一种可能的实现方式中，所述Cascode电路为差分电路或单端电路。
结合第一方面或第一方面的上述任一可能的实现方式，在一种可能的实现方式中，所述可变电容电路为差分电路或单端电路。
第二方面，本申请实施例提供了一种相控阵系统，包括：多个通道，其中任一通道包括如第一方面或第一方面的任一可能的实现方式提供的可变增益放大器。
本实施例中，由于第一方面提供的可变增益放大器在增益切换时，可以保持相位和增益步进的恒定，因此，当该可变增益放大器应用于相控阵系统时，可以使相控阵系统在毫米波频段工作时具有良好的相位一致性以及增益性能。
结合第二方面，在一种可能的实现方式中，所述相控阵系统可以为为相控阵接收机，相控阵发射机或相控阵收发机。
结合第二方面，在一种可能的实现方式中，所述相控阵系统工作在5G NR频段。
结合第二方面或第二方面的上述任一可能的实现方式，在一种可能的实现方式中，所述5G NR频段包括：n257频带，n258频带，n260频段或n261频段。
附图说明
图1是现有技术中的一种相控阵接收机的架构示意图；
图2是现有技术中的一种VGA的结构示意图；
图3a-图3e分别是本申请实施例提供的一种VGA的的结构示意图；
图4a是图2所示的现有VGA的步进增益曲线的示意图；
图4b是图3a所示的VGA的步进增益曲线的示意图；
图5a是图2所示的现有VGA的相位曲线的示意图；
图5b是图3a所示的VGA的相位曲线的示意图；
图6是本申请实施例提供的另一种VGA的结构示意图；
图7a-图7c分别是本申请实施例提供的一种单端结构的VGA的结构意图。
具体实施方式
下面结合本申请实施例中的附图对本申请实施例进行详细地描述。
本申请的说明书、权利要求书及附图中的术语“第一”和“第二”等是用于区别不同对象，而不是用于描述特定顺序。此外，术语“包括”和“具有”以及它们任何变形，意图在于覆盖不排他的包含。例如包含了一系列步骤或单元的过程、方法、系统、产品或设备没有限定于已列出的步骤或单元，而是可选地还包括没有列出的步骤或单元，或可选地还包括对于这些过程、方法、产品或设备固有的其它步骤或单元。
应当理解，在本申请中，“至少一个(项)”是指一个或者多个，“多个”是指两个或两个以上，“至少两个(项)”是指两个或三个及三个以上，“和/或”，用于描述关联对象的关联关系，表示可以存在三种关系，例如，“A和/或B”可以表示：只存在A，只存在B以及同时存在A和B三种情况，其中A，B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。“以下至少一项(个)”或其类似表达，是指这些 项中的任意组合，包括单项(个)或复数项(个)的任意组合。例如，a，b或c中的至少一项(个)，可以表示：a，b，c，“a和b”，“a和c”，“b和c”，或“a和b和c”，其中a，b，c可以是单个，也可以是多个。
如图3a所示，本申请实施例提供了一种具有恒定的相位和步进增益的可变增益放大器(VGA)30。
该VGA30可以包括：
共源共栅(Cascode)电路31，包括共源管311(M1，M2)和由并联的多个共栅管(M3，M4，M5，M6，M7，M8)组成的共栅管阵列312，其中，所述共源管311用于将输入电压Vin转换成电流，所述共栅管阵列312则用于对共源管311输出的电流进行调节，输出可调电流至输出匹配网络33；
可变电容电路32，分别与所述共栅管阵列312和所述输出匹配网络33耦合于第一节点(C,D)，用于调整所述所述共栅管阵列312相对于所述输出匹配网络33的寄生电容；以及
输出匹配网络33，用于将共栅管阵列312输出的电流转换成电压后对外输出，并在输出时调节阻抗匹配。
本实施例中，VGA30中的输出匹配网络33需要同时具备负载以及阻抗匹配的功能，因此又可以称为负载及匹配网络，或者匹配负载等。示例性的，如图3b所示，输出匹配网络33可以是带有调谐电容的巴伦。本领域技术人员应该知道，还可以采用其他类似结构来实现阻抗匹配的功能，例如变压器，电感等，因此，本申请的输出匹配网络33不局限于图3b提供的具体示例。
需要说明的是，本领域技术人员应当知道，Cascode电路又称为级联放大器，可以基于金属氧化物半导体(MOS)管实现，也可以基于三极管实现。当采用MOS管实现时，可以称为共源共栅电路。当采用三极管实现时，Cascode电路又可以称为共射极共基极电路，其工作原理与共源共栅电路类似。也就是说，本实施例中，Cascode电路31可以视为包括级联的第一放大管和第二放大管阵列，所述第二放大管阵列包括多个并联的第二放大管，若所述Cascode电路为共源共栅电路，则所述第一放大管为共源管，所述第二放大管为共栅管，若所述Cascode电路为共射极共基极电路，则所述第一放大管为共射极放大电路，所述第二放大管为共基极放大电路。其中，MOS管和三极管可以统称为晶体管。为了简便起见，以下以基于MOS管实现的共源共栅电路为例，对VGA30的工作原理做进一步说明。
如图3a所示，共源管M1与共栅管阵列312中并联的共栅管M3，M5和M7构成第一组Cascode电路，其中，共栅管M3，M5和M7的源极分别与共源管M1的漏极耦合于第二节点(A)，共栅管M7的漏极耦合至电源电压Vcc，共栅管M3和M5的漏极分别经第一节点(C)耦合至输出匹配网络33。而共源管M2和共栅管M4，M6和M8构成第二组Cascode电路，第一组Cascode电路和第二组Cascode电路为差分电路。类似地，共栅管M4，M6和M8的源极分别与共源管M2的漏极耦合于第二节点(B)，共栅管M8的漏极耦合至电源电压Vcc，共栅管M4和M6的漏极耦合至输出匹配网络33。
需要说明的是，通常差分结构的电路都是对称设计的，比如：共源管M1和共源管M2是对称的，共栅管M3和M4是对称的，M5和M6是对称的，M7和M8也是对称的；相应的，在可变电容电路32中，也包括差分的可变电容。因此，针对差分结构，为了表述方便，后续实施例和附图只针对差分结构中的一路进行了标示以及详细描述，应当理解，差分结构中的未标示另一路可以与之相互参考，不再赘述。
本实施例中，当VGA30正常工作时，通过在M3和M4的栅极施加导通控制信号Vcas_on，保持M3和M4导通，从而自共源管M1和M2的漏极输入的部分电流经由M3和M4输出至输出匹配网络33；当VGA30切换到高增益模式时，通过在共栅管M3，M4，M5和M6的栅极分别施加导通控制信号Vcas_on，控制共栅管M3，M4，M5和M6导通，同时在共栅管M7和M8的栅极分别施加关断控制信号Vcas_off,控制共栅管M7和M8关断，此时自共源管M1和M2输入共栅管阵列312的电流全部都流向输出匹配网络33；而当VGA30切换到低增益模式时，通过在共栅管M3，M4，M7和M8的栅极分别施加导通控制信号Vcas_on，控制共栅管M3，M4，M7和M8导通，同时在共栅管M5和M6的栅极分别施加关断控制信号Vcas_off,控制共栅管M5和M6关断，此时自共源管M1和M2输入共栅管阵列312的电流只有一部分会流向输出匹配网络33，共源管M1和M2输出的另一部分电流则被M7和M8分流，因此增益降低。
应当知道，当Cascode电路基于三极管实现时，共射极共基极电路的结构可以参考图3a所示的结构。类似的，共发射极放大电路M1与共基极放大电路M3，M5和M7构成第一组Cascode电路，其中，共基极放大电路M3，M5和M7的发射极分别与共发射极放大电路M1的集电极耦合于第二节点(A)，共基极放大电路M7的集电极耦合至电源电压Vcc，共基极放大电路M3和M5的集电极分别经第一节点(C)耦合至输出匹配网络33。关于共源共栅电路和共射极共基极电路的驱动原理，具体可以参考现有技术，这里不再详细说明。
当VGA30进行增益切换时，共栅管阵列312中的共栅管导通情况会发生变化，相应的，从第一节点(C、D)往下看，Cascode电路31相对于第一节点(C、D)的寄生电容也会随之变化。具体的，以高增益模式和低增益模式为例，在两种增益模式下，共栅管M5和M6对输出匹配网络33一端贡献的寄生电容发生了变化。其中，当VGA30从高增益切换到低增益的过程中，从第一节点(C、D)看到的Cascode电路31的寄生电容会减小。寄生电容的变化会导致VGA30在切换增益时的输出匹配发生变化，进而无法保证相位的恒定和增益步进在不同频率的一致性。
基于此，本实施例中引入了可变电容电路32，当VGA30进行增益切换时，通过调节可变电容电路32的容值，对在增益切换时，共栅管阵列312相对于第一节点(C、D)引起的寄生电容变化进行补偿，从而在增益切换前后，使得从第一节点(C、D)看到的寄生电容大致维持恒定，相应的，VGA30最终输出的匹配也维持一致。通过这种方式，在VGA30进行切换增益时，可以使VGA30在较宽的频带内增益步进和相位都大致保持恒定。
本申请中，如图3a所示，可变电容电路32可以包括变容管321，其中，变容管321的一端耦合至第一节点(C)，变容管321的另一端接控制电压Vcap，通过改变控制电压Vcap的电压值可以调节变容管321的电容值，以补偿共栅管阵列312在增益切换时相对于输出 匹配网络33的寄生电容变化，进而使从第一节点(C、D)看到的寄生电容大致恒定。
在本实施例的另一实现方式中，如图3c所示，可变电容电路32可以包括MOS管322，其中，MOS管322的栅极耦合至第一节点(C)，MOS管322的源极和漏极短接在一起后接控制电压Vcap，通过控制电压Vcap的电压值。可以通过调节MOS管322的栅电容大小，进而补偿共栅管阵列在增益切换时相对于输出匹配网络33的寄生电容变化，使得VGA30的步进增益和相位大致恒定。
在本实施例的又一实现方式中，如图3d所示，可变电容电路32可以包括开关323和电容324，其中，开关323的一端与电容324的一端耦合，电容324的另一端耦合至第一节点(C)，开关323的另一端接控制电压Vcap，通过控制开关323的导通与否，可以改变可变电容电路32连入VGA30的电容值大小，进而对VGA30中的共栅管阵列在增益切换时相对于输出匹配网络33的寄生电容变化进行补偿，使从第一节点(C、D)看到的寄生电容大致稳定，进而实现VGA30的步进增益和相位的大致恒定。
在本实施例的另一实现方式中，如图3e所示，还可以在Cascode电路31中引入电感L1和L2，其中，电感L1一端与共源管M1的漏极耦合与第二节点(A)，电感L1的另一端分别与共栅管阵列中的各个共栅管(M3，M5和M7)的源极相耦合，电感L2一端与共源管M2的漏极耦合于第二节点(B)，电感L2的另一端分别与共栅管阵列中的各个共栅管(M4，M6和M8)的源极相耦合，通过选取合适的电感值，可以抵消Cascode电路31在第二节点(A、B)处的寄生电容影响，然后结合可变电容电路32，可以对增益切换时，Cascode电路31在第一节点(C、D)处的寄生电容变化做更为精确的补偿，进一步提升VGA30的步进增益和相位的恒定性。
需要说明的是，以上只是示出了可变电容电路30的几种替代性方案，本领域技术人员应当知道，可变电容电路30还可以通过其它的电路结构来实现，本申请对此不做具体限定。本质上，只要可变电容电路30接入第一节点(C、D)后，能够调整所述共源共栅电路31相对所述输出匹配网络33的寄生电容即可。
以下结合图4a-4b对本申请提供的技术方案关于增益步进一致性的改善效果做详细说明。
图4a所示为当收发机采用如图2所示的现有的VGA时的步进增益曲线示意图，图4a中，高增益和低增益的两条曲线分别反映了当VGA在高增益和低增益两种模式下切换时散射参数(也叫S参数，S-param)随频率的变化关系，其中，增益步进曲线反映的是高增益模式和低增益模式下的散射参数的差值。可以看到在24GHz～30GHz频段范围内，在频点24GHz处，增益步进曲线对应的S参数值为7.113dB，在频点30GHz处，增益步进曲线对应的S参数值为6.152dB，也就是说，在这两个频点之间，VGA的增益步进有约1dB的误差，且随着频率的增加，增益步进的误差继续大幅恶化。
而当采用本申请实施例提供的VGA时，VGA的增益步进曲线如图4b所示。可以看到，在24GHz～30GHz频段范围内，在频点24GHz处，增益步进曲线对应的S参数值为6.593dB，在频点30GHz处，增益步进曲线对应的S参数值为6.585dB，而在频点27GHz处，增益步进曲线对应的S参数为最大值(6.639dB)。可见在24GHz～30GHz频段范围内，任意两个频 点之间的增益步进的误差小于0.1dB，也就是说，增益步进在较宽的频率范围内一致性得到了极大改善。
进一步地，以下结合图5a-5b对本申请提供的技术方案关于相位恒定性的改善效果做详细说明。
当收发机采用如图2所示的现有的VGA时，在高增益和低增益模式下，VGA的相位随频率的变化趋势如图5a所示，以频点为28GHz为例，VGA在低增益和高增益两种模式下的相位变化为-292.4°-(-306.0°)＝13.6°。而当采用本申请实施例提供的技术方案后，VGA的相位随频率的变化趋势如图5b所示，当工作频点为28GHz时，VGA在两种增益模式下的相位变化仅为-326.3°-(-328.1°)＝1.8°，由此可见，当采用本申请实施例提供的技术方案时，VGA在不同增益模式下的相位一致性也得到了大幅度改善。
如图6所示，本申请实施例还提供了另一种具有恒定的相位和步进增益的VGA40。图6中，VGA40包括Cascode电路41，输出匹配网络43，以及分别与Cascode电路41和输出匹配网络43耦合于第一节点(C、D)的可变电容电路42。其中，共栅管阵列412为差分结构，其中一路可以包括共栅管M3以及m组并联的共栅管支路，m为大于1的整数，任一共栅管支路中均包括共栅管M5和M7，各个共栅管支路与共栅管M3的连接关系，可以参考图3a-3d以及前述实施例关于M3，M5和M7的连接关系的表述，这里不再赘述。
需要说明的是，在图3a-3d所示的VGA30中，只有高增益到低增益两个档位，而如图6所示的VGA40中，由于共栅管阵列412具有m个并联共栅管支路，通过分别控制各个共栅管支路中的共栅管的导通或关断，可以对共栅管阵列412输出至输出匹配网络43的电流进行多个档位的调节，相应的，VGA40可以实现多个增益档位，以匹配不同的应用场景的需求。
进一步的，如图6所示，可变电容电路42也可以包括n个并联的可变电容支路，所述n个并联支路分别与所述共栅管阵列412和所述输出匹配网络43耦合于第一节点(C,D)，n为大于1的整数，其中任一可变电容支路的结构可以参考前述关于图3a-3d中的可变电容电路32的说明，不再赘述。
由于通过共栅管阵列412中的共栅管的导通或关断，可以对输出匹配网络43的电流进行多个档位的调节，相应的，共栅管阵列412相对于输出匹配网络43的寄生电容也存在多种变化。因此，采用可变电路电路42，可以针对共栅管阵列412的寄生电容变化做出更为精细的补偿，使从第一节点(C、D)看到的寄生电容大致稳定，进而实现VGA40的步进增益和相位的大致恒定。其中，可变电容支路的数量和共栅管支路的数量可以相等，也可以不等。
如图7a-7c所示，本申请实施例还提供了基于单端结构的VGA。其中，图7a为采用MOS管作为补偿电容的单端电路；图7b为采用变容管作为补偿电容的单端电路实现形式；图7c为采用开关和电容作为补偿电容的单端电路实现形式，由于差分电路可以看作是两个对称设计的单端电路，因此，图7a-7c所示的采用单端结构的VGA，可以参考图3a-3d所示的差分电路中的一路的描述，这里不再赘述。
本申请实施例中，还提供了一种相控阵系统，所述相控阵系统的任一通道中，包括 前述实施例所述的VGA。本实施例中，相控阵系统具体可以是相控阵接收机，相控阵发射机或者相控阵收发机，它们的结构以及工作原理具体可以参考现有技术，这里不再赘述。
进一步的，由于本申请实施例提供的VGA具有大致恒定的相位以及步进增益，可以满足5G宽频带信号对于增益步进一致性的要求，因此，该相控阵收发机可以工作在5G NR(new radio，新射频)频带，示例性，5G NR频带可以包括：n257频带(26.5GHz-29.5GHz)，n258频带(24.25GHz-27.5GHz)，n260频带(37GHz-40GHz)和n261频带(27.5GHz-28.35GHz)等。
应当理解，此处所描述的具体实施例仅为本发明的普通实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (14)

  1. 一种可变增益放大器，其特征在于，包括：
    Cascode电路，包括级联的第一放大管和第二放大管阵列，所述第二放大管阵列包括多个并联的第二放大管，用于输出可调电流至输出匹配网络，其中，所述Cascode电路为共源共栅电路，所述第一放大管为共源管，所述第二放大管为共栅管，或者所述Cascode电路为共射极共基极电路，所述第一放大管为共射极放大电路，所述第二放大管为共基极放大电路；以及
    可变电容电路，分别与所述第二放大管阵列和所述输出匹配网络耦合于第一节点。
  2. 根据权利要求1所述的可变增益放大器，其特征在于，所述可变电容电路用于在所述可变增益放大器进行增益切换时，对所述第二放大管阵列相对于所述第一节点的寄生电容变化进行补偿。
  3. 根据权利要求1或2所述的可变增益放大器，其特征在于，所述可变电容电路包括变容管，其中，所述变容管的一端耦合至所述第一节点，所述变容管的另一端接用于调节所述变容管的电容值的控制电压。
  4. 根据权利要求1或2所述的可变增益放大器，其特征在于，所述可变电容电路包括金属氧化半导体(MOS)管，所述MOS管的栅极耦合至所述第一节点，所述MOS管的源极和漏极短接在一起后接用于调节所述MOS管的栅电容的控制电压。
  5. 根据权利要求1或2所述的可变增益放大器，其特征在于，所述可变电容电路包括开关和电容，所述开关的一端与所述电容的一端耦合，所述电容的另一端耦合至所述第一节点，所述开关的另一端接控制电压，通过控制所述开关的导通或关断，改变所述可变电容电路的电容值大小。
  6. 根据权利要求1所述的可变增益放大器，其特征在于，所述第二放大管阵列用于通过改变所述第二放大管阵列与所述输出匹配网络之间导通的第二放大管的数量，输出所述可调电流。
  7. 根据权利要求6所述的可变增益放大器，其特征在于，所述第一放大管为晶体管M1，所述第二放大管阵列包括晶体管M3和至少一组晶体管支路，所述晶体管支路包括晶体管M5和晶体管M7，其中，所述晶体管M3，所述晶体管M5和所述晶体管M7的源极/发射极分别耦合至所述晶体管M1的漏极/集电极，所述晶体管M7的漏极/集电极接电 源电压，所述晶体管M3和所述晶体管M5的漏极/集电极分别耦合至所述第一节点。
  8. 根据权利要求7所述的可变增益放大器，其特征在于，所述Cascode电路还包括电感，所述电感的一端与所述晶体管M1的漏极/集电极相耦合，所述电感的另一端分别与所述晶体管M3，所述晶体管M5和所述晶体管M7的源极/发射极相耦合。
  9. 根据权利要求1-8任一所述的可变增益放大器，所述Cascode电路为差分电路或单端电路。
  10. 根据权利要求1-9任一所述的可变增益放大器，所述可变电容电路为差分电路或单端电路。
  11. 一种相控阵系统，其特征在于，包括：
    多个通道，其中任一通道包括：如权1-10任一所述的可变增益放大器。
  12. 根据权利要求11所述的相控阵系统，其特征在于，所述相控阵系统为相控阵接收机，相控阵发射机或相控阵收发机。
  13. 根据权利要求11或12所述的相控阵系统，其特征在于，所述相控阵系统工作在5G NR频段。
  14. 根据权利要求11-13任一所述的相控阵系统，其特征在于，所述5G NR频段包括：n257，n258，n260或n261中的至少一种。
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EP3893392A1 (en) 2021-10-13
CN113574798A (zh) 2021-10-29

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