WO2019213858A1 - 阵列基板及其制作方法、显示装置 - Google Patents

阵列基板及其制作方法、显示装置 Download PDF

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Publication number
WO2019213858A1
WO2019213858A1 PCT/CN2018/086124 CN2018086124W WO2019213858A1 WO 2019213858 A1 WO2019213858 A1 WO 2019213858A1 CN 2018086124 W CN2018086124 W CN 2018086124W WO 2019213858 A1 WO2019213858 A1 WO 2019213858A1
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Prior art keywords
substrate
layer
region
transistor
forming
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Ceased
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PCT/CN2018/086124
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English (en)
French (fr)
Inventor
晏国文
林致远
林俊仪
周啟华
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Shenzhen Royole Technologies Co Ltd
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Shenzhen Royole Technologies Co Ltd
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Priority to PCT/CN2018/086124 priority Critical patent/WO2019213858A1/zh
Priority to CN201880093830.XA priority patent/CN112534578A/zh
Publication of WO2019213858A1 publication Critical patent/WO2019213858A1/zh
Priority to US17/092,573 priority patent/US20210057456A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0314—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral top-gate TFTs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6731—Top-gate only TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6745—Polycrystalline or microcrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an array substrate, a method for fabricating the same, and a display device.
  • LTPO Low Temperature Polycrystalline Oxide
  • LTPS-TFT Low Temperature Poly-silicon Thin Film Transistor
  • Oxide-TFT Oxide Thin Film Transistor
  • an embodiment of the present invention discloses an array substrate, a manufacturing method thereof, and a display device.
  • An array substrate comprising a substrate, the substrate comprising at least a first region and at least a second region, the first region being provided with a low temperature polysilicon transistor, the second region being provided with an oxide transistor,
  • the oxide transistor includes an oxide semiconductor layer, a gate insulating layer, a gate electrode, and a source and a drain, the oxide semiconductor layer including a channel portion and a contact portion which are provided in connection, the channel portion and the gate insulating layer And the gates are sequentially stacked, the source and drain electrodes are in contact with the contact portion, and the channel portion is at least partially convexly disposed away from the substrate.
  • the channel portion includes a first portion and two second portions respectively disposed on opposite sides of the first portion, each second portion being deflected toward an end of the substrate by one end of the first portion.
  • first portion is parallel to the substrate, and an angle of each second portion relative to the first portion is greater than 90 degrees and less than 180 degrees.
  • the channel portion further includes two third portions, each third portion being connected between a second portion and a contact portion.
  • both of the third portions are parallel to the first portion.
  • the oxide transistor further includes a pad portion protruding from a second region of the substrate, the channel portion being at least partially located above the pad portion.
  • the pad portion includes a first pad layer and a second pad layer stacked on the first pad layer, the first pad layer being disposed adjacent to the substrate.
  • the first liner layer is formed by etching a gate insulating layer material remaining in the second region when the gate insulating layer of the low temperature polysilicon transistor is formed, and the second liner layer is engraved Etching forms a gate material of the low temperature polysilicon transistor that remains in the second region.
  • the width of the pad portion is reduced by a first end of the pad portion adjacent to the substrate toward a second end remote from the substrate.
  • an overlapping area of the orthographic projection of the contact portion on the substrate and the orthographic projection of the pad portion on the substrate is zero.
  • the oxide transistor further includes a dielectric layer covering the substrate, the dielectric layer portion forming a convex portion in a direction away from the substrate, the source drain being disposed at the The dielectric layer is disposed on the dielectric layer, and the oxide semiconductor layer covers the source drain and the dielectric layer, and the channel portion is at least partially laminated with the convex portion.
  • the width of the raised portion is reduced by a first end of the raised portion adjacent the substrate toward a second end of the raised portion away from the substrate.
  • the material of the oxide semiconductor layer includes indium gallium zinc oxide.
  • the substrate includes a substrate and a buffer layer disposed on the substrate, and the buffer layer is disposed on a side of the substrate away from the oxide semiconductor layer.
  • a display device comprising the array substrate as described above.
  • a method for fabricating an array substrate includes the following steps:
  • an oxide semiconductor layer covering a source and a drain of the oxide transistor on a second region of the substrate, the oxide semiconductor layer portion being convexly disposed away from the substrate to form a protruding structure;
  • a gate insulating layer and a gate of the oxide transistor are sequentially formed on the oxide semiconductor layer, and a gate insulating layer of the oxide transistor and a gate of the oxide transistor are stacked on the protruding portion Structurally;
  • the end portion of the oxide semiconductor layer is subjected to a conductive treatment to form a contact portion, the contact portion is in contact with a source and a drain of the oxide transistor, and a portion of the oxide semiconductor layer not subjected to a conductive treatment constitutes a channel
  • the channel portion is at least partially composed of the protruding structure.
  • the "providing a substrate, forming a low temperature polysilicon transistor on the first region of the substrate, forming a source and drain of the oxide transistor on the second region of the substrate” includes:
  • the pad portion includes a first liner layer disposed in a layered manner and a second liner layer stacked on the first liner layer, the first liner layer being disposed adjacent to the substrate, the first liner a layer formed of a material of a gate insulating layer remaining in the second region when the gate insulating layer of the low temperature polysilicon transistor is formed by etching, the second liner layer being formed by etching to form the low temperature polysilicon transistor The material of the gate remaining in the second region at the gate is formed.
  • the "providing a substrate, forming a low temperature polysilicon transistor on the first region of the substrate, forming a source and drain of the oxide transistor on the second region of the substrate” includes:
  • the structure further includes: the oxide semiconductor layer covers the convex portion and a source drain of the oxide transistor, and the protruding structure covers the convex portion.
  • An array substrate provided by the present invention, a method for fabricating the same, and a display device, wherein the channel portion is convexly disposed away from the substrate to form a curved structure, that is, without increasing the area occupied by the lateral direction of the oxide transistor
  • the overall length of the channel portion is increased.
  • the lateral length of the thin film transistor is reduced and the resolution is improved when the channel occupies the same length.
  • FIG. 1 is a schematic cross-sectional view of an array substrate according to an embodiment of the present invention.
  • FIG. 2 is a flowchart of a method for fabricating an array substrate according to an embodiment of the present invention.
  • FIG. 3 is a schematic structural view formed in step 201 of FIG. 2.
  • FIG. 4 is a schematic view showing the structure formed in step 202 of FIG. 2.
  • FIG. 5 is a schematic structural view formed in step 203 of FIG. 2.
  • FIG. 6 is a schematic flow chart of an embodiment provided in step 201 of FIG. 2 .
  • FIG. 7 is a schematic structural view formed in step 2011 of FIG. 6.
  • FIG. 8 is a schematic structural view formed in step 2012 of FIG. 6.
  • FIG. 9 is a schematic structural view formed in step 2013 of FIG. 6.
  • FIG. 10 is a schematic flow chart of another embodiment provided in step 201 of FIG. 2 .
  • FIG. 11 is a schematic diagram of a display device according to an embodiment of the present invention.
  • an embodiment of the present invention provides an array substrate 100 .
  • the array substrate 100 includes a substrate 10 including at least a first region 11 and at least a second region 13.
  • the first region 11 is provided with a low temperature polysilicon transistor 30, and the second region 13 is disposed.
  • An oxide transistor 50 includes an oxide semiconductor layer 52, a gate insulating layer 53, a gate electrode 54 and a source and drain electrode 55, and the oxide semiconductor layer 52 includes a channel portion 523 that is connected and The contact portion 525, the channel portion 523, the gate insulating layer 53, and the gate electrode 54 are sequentially stacked, the source and drain electrodes 55 are in contact with the contact portion 525, and the channel portion 523 is at least partially The protrusion is disposed in a direction away from the substrate 10.
  • the channel portion 523 is at least partially convex toward a direction away from the substrate 10, that is, the channel portion 523 is at least partially convex toward the gate electrode 54, and the channel portion 523 is curved. That is, the entire length of the channel portion 523 is increased without increasing the area occupied by the oxide transistor 50 in the lateral direction. In other words, in the case where the length of the channel portion 523 is ensured, the lateral effective area of the oxide transistor 50 is shortened, which is advantageous in improving the PPI of the display device.
  • the channel portion 523 includes a first portion 5231 and a second portion 5233 located on opposite sides of the first portion 5231, each of the second portions 5233 being deflected toward the substrate 10 by one end of the first portion 5231.
  • the first portion 5231 and the second portion 5233 together form a protrusion that protrudes from the substrate 10.
  • the channel portion 5231 further includes two third portions 5235, each of which is connected between a second portion 5233 and one of the contact portions 525.
  • the first portion 5231 is substantially parallel to the substrate 10, and the angle between each second portion 5233 relative to the first portion 5231 is greater than 90 degrees and less than 180 degrees; both of the third portions 5235 are Parallel to the first portion 5231.
  • the low temperature polysilicon transistor 30 includes a low temperature polysilicon layer 31, a gate insulating layer 32, a gate electrode 33, a dielectric layer 57, and a source and drain electrode 35.
  • the low temperature polysilicon layer 31, the gate insulating layer 32, the gate electrode 33, and the dielectric layer 57 are sequentially laminated on the substrate 10.
  • a source drain 35 is formed on the dielectric layer 57, and the source drain 35 is in contact with a non-channel region of the low temperature polysilicon layer 31.
  • the dielectric layer 57 is also used as a buffer layer of the oxide transistor 50.
  • the oxide transistor 50 further includes a pad portion 51 protruding from the second region 13 of the substrate 10, the channel portion 523 being at least partially located in the pad portion Above the 51.
  • the pad portion 51 includes a first pad layer 511 and a second pad layer 513 stacked on the first pad layer 511.
  • the first pad layer 511 is The substrate 10 is disposed adjacent to each other, and the first liner layer 511 is formed of a material of the gate insulating layer 32 remaining in the second region 13 when the gate insulating layer 32 of the low temperature polysilicon transistor 30 is formed by etching.
  • the second liner layer 513 is formed of a material of the gate electrode 33 remaining in the second region 13 when the gate 33 of the low temperature polysilicon transistor 30 is formed by etching.
  • the pad portion 51 is formed by the material of the gate insulating layer 32 and the material of the gate electrode 33 which are formed by the low temperature polysilicon transistor 30, thereby improving the performance of the array substrate 100 while saving cost.
  • the width of the pad portion 51 is from the first end of the pad portion 51 adjacent to the substrate 10 to the second portion of the pad portion 51 near the gate 54 of the oxide transistor 50 The end is reduced.
  • the cross-section of the pad portion 51 is substantially trapezoidal. It is understood that the cross-section of the pad portion 51 is not limited to a trapezoidal shape, and may be other shapes such as a square shape or a triangular shape.
  • the oxide semiconductor layer 52 may be a metal oxide semiconductor, and may include, for example, Indium Gallium Zinc Oxide (IGZO), Hafnium Indium Zinc Oxide (HIZO), Indium.
  • the oxide semiconductor is IGZO.
  • the dielectric layer 57 is formed on the substrate 10 and the pad portion 51.
  • the dielectric layer 57 forms a convex portion 573 corresponding to the pad portion 51, and the source and drain electrodes 35 are disposed at The dielectric layer 57 is disposed on the space and spaced apart from the convex portion 573.
  • the boss portion 573 covers the pad portion 51.
  • the first portion 5231 of the channel portion 523 and the boss portion 573 and the pad portion 51 are stacked.
  • the pad portion 51 is located between the boss portion 573 and the substrate 10.
  • the projected overlap area is not zero.
  • the protrusion 573 includes a top wall 5731, a first side wall 5733, a second side wall 5735, and a bottom wall 5737.
  • the top wall 5731 is opposite to the bottom wall 5737, and the top wall 5731 is connected to the Between the first side wall 5733 and the second side wall 5735, the first portion 5231 of the channel portion 523 is attached to the top wall 5731, and the two second portions 5233 are respectively attached to the first side.
  • the wall 5733 and the second side wall 5735, the two third portions 5235 are attached to the dielectric layer 57.
  • the channel portion 523 of the oxide transistor 50 spans the raised portion 573.
  • the first end of the convex portion 573 adjacent to the pad portion 51 decreases toward the second end of the convex portion 573 close to the gate 54 of the oxide transistor 50.
  • the material of the oxide semiconductor layer 52 includes indium gallium zinc oxide.
  • the overlapping area of the orthographic projection of the contact portion 525 on the substrate 10 and the orthographic projection of the convex portion 573 on the substrate 10 is zero.
  • the substrate 10 includes a substrate 13 and a buffer layer 15 disposed on the substrate 13, and the pad portion 51 is disposed adjacent to the buffer layer 15.
  • the material of the substrate 13 is made of glass. Of other embodiments, the material of the substrate 13 may be made of other materials, such as polyimide (PI).
  • the material of the buffer layer 15 includes at least one of silicon oxide and silicon nitride.
  • the pad portion 51 is not limited by the material of the gate insulating layer 32 retained by the low temperature polysilicon transistor 30 and the material of the gate electrode 33, and may be made of other materials such as silicon oxide or silicon nitride. . It can be understood that the pad portion 51 and the dielectric layer 57 may be omitted, and the channel portion 523 of the oxide semiconductor layer 52 may be at least partially convexly disposed toward the gate electrode 54 to form a curved structure. When the lateral area occupied by the oxide transistor 50 is not increased, the length of the channel portion 523 is increased.
  • the channel portion 523 In addition to the lateral direction, the channel portion 523 also extends to the vertical direction, so that the overall length of the channel portion 523 can be increased to sufficiently maintain the diffusion of carriers. Also, since the length in the lateral direction is small, the resolution of the display panel to which the thin film transistor is applied can be improved.
  • the embodiment of the present invention further provides a method for fabricating the above array substrate. Referring to FIG. 2, the method includes the following steps:
  • Step 201 referring to FIG. 3, a substrate 10 is formed on which a low temperature polysilicon transistor 30 is formed on a first region 11 of the substrate 10, and an oxide transistor 50 is formed on the second region 13 of the substrate 10. Source drain 55.
  • Step 202 referring to FIG. 4, an oxide semiconductor layer 52 covering the source and drain electrodes 55 of the oxide transistor 50 is formed on the second region 13 of the substrate 10, and the oxide semiconductor layer 52 is partially away from the oxide semiconductor layer 52.
  • the direction of the substrate 10 is convexly arranged to form a protruding structure 501.
  • Step 203 referring to FIG. 5, a gate insulating layer 53 and a gate electrode 54 of the oxide transistor 50 are sequentially formed on the oxide semiconductor layer 52.
  • the gate insulating layer 53 and the gate electrode 54 are stacked.
  • the protrusion structure 501 is disposed on the protruding structure 501.
  • Step 204 please refer to FIG. 1 , the end portion of the oxide semiconductor layer 52 is electrically conductively formed to form a contact portion 525, and the contact portion 525 is in contact with the source and drain electrodes 55 of the oxide transistor 50.
  • the portion of the oxide semiconductor layer 52 that is not subjected to the conductive treatment constitutes a channel portion 523, and the channel portion 523 is at least partially composed of the protruding structure 501, the channel portion 523, the gate insulating layer 53 and The gate electrodes 54 are stacked.
  • step 201 specifically includes the following steps:
  • an amorphous silicon (A-Si) film layer is formed, exposed, and etched on the substrate 10 to convert the patterned amorphous silicon film layer into the low temperature polysilicon layer 31.
  • Step 2012 referring to FIG. 8, a gate insulating layer 32 and a gate electrode 33 are sequentially formed on the low temperature polysilicon layer 31 of the low temperature polysilicon transistor 30, and a pad portion 51 is formed in the second region 13 of the substrate 10. Thereby forming a prefabricated structure 101.
  • the pad portion 51 is convexly disposed in a direction away from the substrate 10.
  • the pad portion 51 includes a first pad layer 511 and a second pad layer 513 stacked on the first pad layer 511, the first pad layer 511 and the lining
  • the bottom 10 is disposed adjacent to each other, and the first liner layer 511 is formed of a material of the gate insulating layer 32 remaining in the second region 13 when the gate insulating layer 32 of the low temperature polysilicon transistor 30 is formed by etching.
  • the second liner layer 513 is formed of a material of the gate electrode 33 remaining in the second region 13 when the gate 33 of the low temperature polysilicon transistor 30 is formed by etching.
  • Step 2013, referring to FIG. 9, a dielectric layer 57 is formed on the prefabricated structure 101, and the dielectric layer 57 is partially convex away from the substrate 10 to form a convex portion 573, and the convex portion 573 is covered.
  • the dielectric layer 57 located above the second region 13 is also used as a buffer layer of the oxide transistor 50.
  • Step 2014 referring again to FIG. 3, the source and drain electrodes 35 of the low temperature polysilicon transistor 30 are formed on the dielectric layer 57 of the first region 11, and on the dielectric layer 57 on the second region 13. A source and drain 55 of the oxide transistor 50 are formed. The source and drain electrodes 35 of the low temperature polysilicon transistor 30 are in contact with the non-channel region of the low temperature polysilicon layer 31.
  • Step 202 further comprising: the oxide semiconductor layer 52 covers the convex portion 573, and the protruding structure 501 covers the convex portion 573.
  • the step portion 2012 does not include forming the pad portion 51 in the second region 13 of the substrate 10.
  • step 2013 is omitted.
  • step 201 specifically includes the following steps:
  • Step 2031 forming a low temperature polysilicon layer 31 of the low temperature polysilicon transistor 30 on the first region 11 of the substrate 10.
  • step 2032 a gate insulating layer 32 and a gate electrode 33 are sequentially formed on the low temperature polysilicon layer 31 of the low temperature polysilicon transistor 30, and a pad portion 51 is formed in the second region 13 of the substrate 10.
  • step 2033 the source and drain electrodes 35 of the low temperature polysilicon transistor 30 are formed on the low temperature polysilicon layer 31, and the source and drain electrodes 55 of the oxide transistor 50 are formed on the second region 13 of the substrate 10.
  • the oxide semiconductor layer 52 covers the pad portion 51.
  • a display device 200 includes the array substrate 100 as described above.
  • the array substrate 100 provided by the present invention, the manufacturing method thereof, and the display device 200 are formed such that the channel portion 523 is convex toward the gate electrode 54 to form a curved structure, that is, without increasing the lateral direction of the oxide transistor 50.
  • the overall length of the channel portion 523 is increased.
  • the lateral occupation length of the oxide transistor 50 is lowered with the same channel length. Since the lateral effective area of the oxide transistor 50 is shortened while securing the length of the channel portion 523, it is advantageous to increase the PPI of the display device, thereby improving the display quality of the display device 200.
  • the pad portion 51 is formed using the material of the remaining gate insulating layer 32 of the low temperature polysilicon transistor 30 and the material of the gate electrode 33 such that the dielectric layer 57 is stacked in a region corresponding to the pad portion 51. Forming the boss 573 reduces the manufacturing cost.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)

Abstract

一种阵列基板、阵列基板的制作方法及显示装置，该阵列基板包括衬底（10），衬底包括至少一第一区域（11）及至少一第二区域（13），第一区域设置有低温多晶硅晶体管（30），第二区域设置有氧化物晶体管（50），氧化物晶体管包括氧化物半导体层（52）、栅极绝缘层（53）、栅极（54）、源漏极（55），氧化物半导体层包括连接设置的沟道部（523）及接触部（525），沟道部、栅极绝缘层及栅极依次层叠设置，源漏极与接触部接触，沟道部至少部分朝向远离衬底的方向凸起设置。

Description

阵列基板及其制作方法、显示装置 技术领域
本发明涉及显示技术领域，特别涉及一种阵列基板及其制作方法、显示装置。
背景技术
LTPO(Low Temperature Polycrystalline Oxide，低温多晶氧化物)技术结合了LTPS-TFT(Low Temperature Poly-silicon Thin Film Transistor，低温多晶硅薄膜晶体管)和Oxide-TFT(氧化物薄膜晶体管)这两种TFT各自的优势，具备高PPI(Pixels Per Inch，像素密度)、低功耗、高画质等方面的技术优势。一般输出管使用具有高迁移率的LTPS，以提高发光亮度；开关管使用具有低关态电流的Oxide-TFT(例如IGZO)，以降低器件功耗。但是，Oxide-TFT的导电区域会有微量(例如约1μm)的载流子扩散至半导体区域，为此，非晶氧化物的晶体管的沟道需要留足充分的长度，影响到分辨率的提升，从而影响显示品质。
发明内容
为解决上述问题，本发明实施例公开一种阵列基板及其制作方法、显示装置。
一种阵列基板，包括衬底，所述衬底包括至少一第一区域及至少一第二区域，所述第一区域设置有低温多晶硅晶体管，所述第二区域设置有氧化物晶体管，所述氧化物晶体管包括氧化物半导体层、栅极绝缘层、栅极、源漏极，所述氧化物半导体层包括连接设置的沟道部及接触部，所述沟道部、所述栅极绝缘层及所述栅极依次层叠设置，所述源漏极与所述接触部接触，所述沟道部至少部分朝向远离所述衬底的方向凸起设置。
进一步地，所述沟道部包括第一部分及二分别设置于所述第一部分相对两侧的第二部分，每个第二部分由所述第一部分的一端朝向所述衬底偏折。
进一步地，所述第一部分平行于所述衬底，每一第二部分相对所述第一部 分的夹角大于90度小于180度。
进一步地，所述沟道部还包括两个第三部分，每个第三部分连接于一个第二部分与一个接触部之间。
进一步地，两个所述第三部分均平行于所述第一部分。
进一步地，所述氧化物晶体管还包括衬垫部，所述衬垫部凸设于所述衬底的第二区域，所述沟道部至少部分位于所述衬垫部的上方。
进一步地，所述衬垫部包括第一衬垫层及叠设于所述第一衬垫层上的第二衬垫层，所述第一衬垫层与所述衬底相邻设置。
进一步地，所述第一衬垫层为刻蚀形成所述低温多晶硅晶体管的栅极绝缘层时在所述第二区域保留下来的栅极绝缘层材料形成，所述第二衬垫层为刻蚀形成所述低温多晶硅晶体管的栅极在所述第二区域保留下来的栅极材料形成。
进一步地，所述衬垫部的宽度由所述衬垫部与所述衬底相邻的第一端向远离所述衬底的第二端减小。
进一步地，所述接触部在所述衬底上的正投影与所述衬垫部在所述衬底上的正投影的交叠面积为零。
进一步地，所述氧化物晶体管还包括介质层，所述介质层覆盖所述衬底，所述介质层部分朝远离所述衬底的方向形成凸起部，所述源漏极设置在所述介质层上且间隔所述凸起部设置，所述氧化物半导体层覆盖所述源漏极及所述介质层，所述沟道部至少部分与所述凸起部层叠设置。
进一步地，所述凸起部的宽度由所述凸起部与所述衬底相邻的第一端向所述凸起部远离所述衬底的第二端减小。
进一步地，所述氧化物半导体层的材质包括铟镓锌氧化物。
进一步地，所述衬底包括基底及设于所述基底上的缓冲层，所述缓冲层设于所述衬底远离所述氧化物半导体层的一侧。
一种显示装置，包括如上所述的阵列基板。
一种阵列基板的制作方法，包括以下步骤：
提供一衬底，在所述衬底的第一区域上形成低温多晶硅晶体管，在所述衬底的第二区域上形成氧化物晶体管的源漏极；
在所述衬底的第二区域上形成覆盖所述氧化物晶体管的源漏极的氧化物半导体层，所述氧化物半导体层部分朝远离所述衬底的方向凸起设置形成凸设结构；
在所述氧化物半导体层上依次形成所述氧化物晶体管的栅极绝缘层及栅极，所述氧化物晶体管的栅极绝缘层及所述氧化物晶体管的栅极层叠设置于所述凸设结构上；及
对所述氧化物半导体层的端部进行导电化处理形成接触部，所述接触部与所述氧化物晶体管的源漏极接触，所述氧化物半导体层未进行导电化处理的部分构成沟道部，所述沟道部至少部分由所述凸设结构构成。
进一步地，所述“提供一衬底，在所述衬底的第一区域上形成低温多晶硅晶体管，在所述衬底的第二区域上形成氧化物晶体管的源漏极”，包括：
在所述衬底的第一区域上形成所述低温多晶硅晶体管的低温多晶硅层；
在所述低温多晶硅层上依次形成栅极绝缘层及栅极，及在所述衬底的第二区域形成衬垫部，从而形成预制结构；
在所述低温多晶硅层上形成所述低温多晶硅晶体管的源漏极，及所述衬底的第二区域上形成所述氧化物晶体管的源漏极。
进一步地，所述“在所述低温多晶硅层上依次形成栅极绝缘层及栅极，及在所述衬底的第二区域形成衬垫部，从而形成预制结构”与所述“在所述低温多晶硅层上形成所述低温多晶硅晶体管的源漏极，及所述衬底的第二区域上形成所述氧化物晶体管的源漏极”之间，
所述“提供一衬底，在所述衬底的第一区域上形成低温多晶硅晶体管，在所述衬底的第二区域上形成氧化物晶体管的源漏极”，还包括：在所述预制结构上形成介质层，所述介质层部分朝远离所述衬底的方向凸起形成凸起部，所述凸起部覆盖所述衬垫部，
所述“在所述低温多晶硅层上形成所述低温多晶硅晶体管的源漏极，及所述衬底的第二区域上形成所述氧化物晶体管的源漏极”，包括：在位于所述第一区域的介质层上形成所述低温多晶硅晶体管的源漏极，及在位于所述第二区域上的介质层上形成所述氧化物晶体管的源漏极。
进一步地，所述“在所述低温多晶硅层上依次形成栅极绝缘层及栅极，及在所述衬底的第二区域形成衬垫部，从而形成预制结构”，所述衬垫部包括分层设置的第一衬垫层及叠设于所述第一衬垫层上的第二衬垫层，所述第一衬垫层与所述衬底相邻设置，所述第一衬垫层由刻蚀形成所述低温多晶硅晶体管的栅极绝缘层时在所述第二区域保留下来的栅极绝缘层的材料形成，所述第二衬垫层由刻蚀形成所述低温多晶硅晶体管的栅极时在所述第二区域保留下来的栅极的材料形成。
进一步地，所述“提供一衬底，在所述衬底的第一区域上形成低温多晶硅晶体管，在所述衬底的第二区域上形成氧化物晶体管的源漏极”，包括：
在所述衬底的第一区域上形成所述低温多晶硅晶体管的低温多晶硅层；
在所述低温多晶硅晶体管的低温多晶硅层上依次形成图形化的栅极绝缘层及栅极，从而形成预制结构；
在所述预制结构上形成介质层，所述介质层部分朝远离所述衬底的方向凸起形成凸起部；
在位于所述第一区域的介质层上形成所述低温多晶硅晶体管的源漏极，及在位于所述第二区域上的介质层上形成所述氧化物晶体管的源漏极，
所述“在所述衬底的第二区域上形成覆盖所述氧化物晶体管的源漏极的氧化物半导体层，所述氧化物半导体层部分朝远离所述衬底的方向凸起设置形成凸设结构”还包括：所述氧化物半导体层覆盖所述凸起部及所述氧化物晶体管的源漏极，所述凸设结构覆盖所述凸起部。
本发明提供的阵列基板及其制作方法、显示装置，由于所述沟道部朝向远离所述衬底的方向凸起设置从而形成弯曲结构，即在不增加所述氧化物晶体管横向所占区域的情况下，增加了所述沟道部的整体长度。换而言之，通过将器件垂直设计，在沟道占相同长度的情况下，降低了薄膜晶体管横向占有长度，进而提升分辨率。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例中所需要 使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明实施方式提供的阵列基板的剖面示意图。
图2为本发明实施方式提供的阵列基板的制作方法的流程图。
图3为图2的步骤201中所形成的结构示意图。
图4为图2的步骤202中所形成的结构示意图。
图5为图2的步骤203中所形成的结构示意图。
图6为图2的步骤201中的一实施方式提供的流程示意图。
图7为图6的步骤2011中所形成的结构示意图。
图8为图6的步骤2012中所形成的结构示意图。
图9为图6的步骤2013中所形成的结构示意图。
图10为图2的步骤201中的另一实施方式提供的流程示意图。
图11为本发明实施方式提供的显示装置的示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参阅图1，本发明实施方式提供一种阵列基板100。所述阵列基板100包括衬底10，所述衬底10包括至少一第一区域11及至少一第二区域13，所述第一区域11设置有低温多晶硅晶体管30，所述第二区域13设置有氧化物晶体管50，所述氧化物晶体管50包括氧化物半导体层52、栅极绝缘层53、栅极54及源漏极55，所述氧化物半导体层52包括连接设置的沟道部523及接触部525，所述沟道部523、所述栅极绝缘层53及所述栅极54依次层叠设 置，所述源漏极55与所述接触部525接触，所述沟道部523至少部分朝向远离所述衬底10的方向凸起设置。
由于所述沟道部523至少部分朝向远离所述衬底10的方向凸起设置，即所述沟道部523至少部分朝向所述栅极54凸起设置，所述沟道部523呈弯曲状，即在不增加所述氧化物晶体管50横向所占区域的情况下，增长了所述沟道部523的整体长度。换而言之，在保证所述沟道部523的长度的情况下，缩短了所述氧化物晶体管50的横向有效面积，有利于提高显示装置的PPI。
所述沟道部523包括第一部分5231及分别位于第一部分5231相对两侧的第二部分5233，每个第二部分5233由所述第一部分5231的一端朝向所述衬底10偏折。所述第一部分5231及所述第二部分5233共同形成相对所述衬底10凸设的凸起。所述沟道部5231还包括两个第三部分5235，每个第三部分5235连接于一个第二部分5233与一个所述接触部525之间。本实施方式中，所述第一部分5231大致平行于所述衬底10，每一第二部分5233相对所述第一部分5231的夹角大于90度小于180度；两个所述第三部分5235均平行于所述第一部分5231。
在一具体实施例中，所述低温多晶硅晶体管30包括低温多晶硅层31、栅极绝缘层32、栅极33、介质层57及源漏极35。低温多晶硅层31、栅极绝缘层32、栅极33、介质层57依次层叠于所述衬底10上。源漏极35形成于所述介质层57上，所述源漏极35与所述低温多晶硅层31的非沟道区域接触。本实施方式中，介质层57亦作为所述氧化物晶体管50的缓冲层使用。
进一步地，所述氧化物晶体管50还包括衬垫部51，所述衬垫部51凸设于所述衬底10的第二区域13，所述沟道部523至少部分位于所述衬垫部51的上方。具体的，所述衬垫部51包括分层设置的第一衬垫层511及叠设于所述第一衬垫层511上的第二衬垫层513，所述第一衬垫层511与所述衬底10相邻设置，所述第一衬垫层511由刻蚀形成所述低温多晶硅晶体管30的栅极绝缘层32时在第二区域13保留下来的栅极绝缘层32的材料形成，所述第二衬垫层513由刻蚀形成所述低温多晶硅晶体管30的栅极33时在第二区域13保留下来的栅极33的材料形成。
利用制造所述低温多晶硅晶体管30保留下来的栅极绝缘层32的材料及栅极33的材料形成衬垫部51，如此在提高阵列基板100性能的同时，节约了成本。
其中，所述衬垫部51的宽度由所述衬垫部51与所述衬底10相邻的第一端向所述衬垫部51靠近所述氧化物晶体管50的栅极54的第二端减小。本实施方式中，所述衬垫部51的截面大致呈梯形，可以理解，所述衬垫部51的截面不限定为梯形，其也可以为方形、三角形等其他形状。
较佳地，所述氧化物半导体层52可以是金属氧化物半导体，例如可以包括铟镓锌氧化物(Indium Gallium Zinc Oxide，IGZO)、铪铟锌氧化物(Hafnium Indium Zinc Oxide，HIZO)、铟锌氧化物(Indium Zinc Oxide，IZO)、非晶铟锌氧化物a-InZnO、非晶氧化锌掺杂氟氧化物ZnO：F、氧化铟掺杂锡氧化物In2O3：Sn、非晶氧化铟掺杂钼氧化物In2O3：Mo、铬锡氧化物Cd2SnO4、非晶氧化锌掺杂铝氧化物ZnO：Al、非晶氧化钛掺杂铌氧化物TiO2：Nb、铬锡氧化物Cd-Sn-O或其他金属氧化物。本实施方式中，所述氧化物半导体为IGZO。
进一步地，所述介质层57形成于所述衬底10及所述衬垫部51上，所述介质层57对应所述衬垫部51形成凸起部573，所述源漏极35设置在所述介质层57上且间隔所述凸起部573设置。所述凸起部573覆盖于所述衬垫部51上。换而言之，所述沟道部523的第一部分5231、所述凸起部573及所述衬垫部51层叠设置。所述衬垫部51位于所述凸起部573与所述衬底10之间。所述沟道部523在所述衬底10上的正投影、所述凸起部573在所述衬底10上的正投影，以及所述衬垫部51在所述衬底10上的正投影交叠面积不为零。
所述凸起部573包括顶壁5731、第一侧壁5733、第二侧壁5735及底壁5737，所述顶壁5731与所述底壁5737相对设置，所述顶壁5731连接于所述第一侧壁5733与所述第二侧壁5735之间，所述沟道部523的第一部分5231贴设于所述顶壁5731，两个第二部分5233分别贴设于所述第一侧壁5733及所述第二侧壁5735，两个第三部分5235贴合于介质层57上。所述氧化物晶体管50的沟道部523横跨所述凸起部573。
进一步地，所述凸起部573与所述衬垫部51相邻的第一端向所述凸起部573靠近所述氧化物晶体管50的栅极54的第二端减小。
进一步地，所述氧化物半导体层52的材质包括铟镓锌氧化物。
进一步地，所述接触部525在衬底10的正投影与所述凸起部573在衬底10的正投影的交叠面积为零。
进一步地，所述衬底10包括基底13及设于所述基底13上的缓冲层15，所述衬垫部51与所述缓冲层15相邻设置。所述基底13的材质选用玻璃，当然在其他实施例中，所述基底13的材质可以选用其它材质，例如聚酰亚胺(Polyimide，PI)等。所述缓冲层15的材质包括氧化硅、氮化硅中的至少一种。
可以理解，不限定衬垫部51由所述低温多晶硅晶体管30保留下来的栅极绝缘层32的材料及栅极33的材料形成，其可以为其它材料制成，例如氧化硅或氮化硅等。可以理解，所述衬垫部51、所述介质层57可以省略，所述氧化物半导体层52的沟道部523至少部分朝向所述栅极54凸起设置形成弯曲结构即可，如此，在不增加所述氧化物晶体管50所占横向区域的情况下，增加了所述沟道部523的长度。
除了横向方向外，沟道部523也延伸至竖向方向，因而可增加沟道部523的整体长度，给载流子的扩散留足充分的长度。并且，由于横向方向的长度较小，因而可提升应用薄膜晶体管的显示面板的分辨率。
本发明实施例还提供一种上述阵列基板的制作方法，请参阅图2，具体包括以下步骤：
步骤201，请参阅图3，提供一衬底10，在所述衬底10的第一区域11上形成低温多晶硅晶体管30，在所述衬底10的第二区域13上形成氧化物晶体管50的源漏极55。
步骤202，请参阅图4，在所述衬底10的第二区域13上形成覆盖所述氧化物晶体管50的源漏极55的氧化物半导体层52，所述氧化物半导体层52部分朝远离所述衬底10的方向凸起设置形成凸设结构501。
步骤203，请参阅图5，在所述氧化物半导体层52上依次形成所述氧化物晶体管50的栅极绝缘层53及栅极54，所述栅极绝缘层53及所述栅极54层叠设置于所述凸设结构501上。
步骤204，请接合参阅图1，对所述氧化物半导体层52的端部进行导电化处理形成接触部525，所述接触部525与所述氧化物晶体管50的源漏极55接触，所述氧化物半导体层52未进行导电化处理的部分构成沟道部523，所述沟道部523至少部分由所述凸设结构501构成，所述沟道部523、所述栅极绝缘层53及所述栅极54层叠设置。
请参阅图6，步骤201中具体包括以下步骤：
步骤2011，请参阅图7，在所述衬底10的第一区域11上形成所述低温多晶硅晶体管30的低温多晶硅层31。
具体地，在衬底10进行非晶硅(A-Si)膜层成膜、曝光、刻蚀，将图形化的非晶硅膜层转化为低温多晶硅层31。
步骤2012，请参阅图8，在所述低温多晶硅晶体管30的低温多晶硅层31上依次形成栅极绝缘层32及栅极33，及在所述衬底10的第二区域13形成衬垫部51，从而形成预制结构101。所述衬垫部51朝远离所述衬底10的方向凸起设置。
所述衬垫部51包括分层设置的第一衬垫层511及叠设于所述第一衬垫层511上的第二衬垫层513，所述第一衬垫层511与所述衬底10相邻设置，所述第一衬垫层511由刻蚀形成所述低温多晶硅晶体管30的栅极绝缘层32时在第二区域13保留下来的栅极绝缘层32的材料形成，所述第二衬垫层513由刻蚀形成所述低温多晶硅晶体管30的栅极33时在第二区域13保留下来的栅极33的材料形成。
步骤2013，请参阅图9，在所述预制结构101上形成介质层57，所述介质层57部分朝远离所述衬底10的方向凸起形成凸起部573，所述凸起部573覆盖所述衬垫部51。本实施方式中，位于所述第二区域13上方的介质层57亦作为氧化物晶体管50的缓冲层使用。
步骤2014，请再次参阅图3，在位于所述第一区域11的介质层57上形成所述低温多晶硅晶体管30的源漏极35，及在位于所述第二区域13上的介质层57上形成所述氧化物晶体管50的源漏极55。所述低温多晶硅晶体管30的源漏极35与所述低温多晶硅层31的非沟道区域接触。
步骤202，还包括：所述氧化物半导体层52覆盖所述凸起部573，所述凸设结构501覆盖所述凸起部573。
可以理解，在一实施例中，步骤2012中不包括在所述衬底10的第二区域13形成衬垫部51。
可以理解，在一实施例中，步骤2013省略，请参阅图10，步骤201具体包括以下步骤：
步骤2031，在所述衬底10的第一区域11上形成所述低温多晶硅晶体管30的低温多晶硅层31。
步骤2032，在所述低温多晶硅晶体管30的低温多晶硅层31上依次形成栅极绝缘层32及栅极33，及在所述衬底10的第二区域13形成衬垫部51。
步骤2033，在所述低温多晶硅层31上形成所述低温多晶硅晶体管30的源漏极35，及所述衬底10的第二区域13上形成所述氧化物晶体管50的源漏极55。
其中，在步骤202中，所述氧化物半导体层52覆盖所述衬垫部51。
请参阅图11，一种显示装置200，包括如上所述的阵列基板100。
本发明提供的阵列基板100及其制作方法、显示装置200，由于所述沟道部523朝向所述栅极54凸起设置，从而形成弯曲结构，即在不增加所述氧化物晶体管50横向所占区域的情况下，增长了所述沟道部523的整体长度。换而言之，通过将器件垂直设计，在沟道长度相同的情况下，降低氧化物晶体管50的横向占有长度。由于在保证所述沟道部523的长度的情况下，缩短了所述氧化物晶体管50的横向有效面积，有利于提高显示装置的PPI，从而提高显示装置200的显示品质。此外，利用制造所述低温多晶硅晶体管30的保留下来的栅极绝缘层32的材料及栅极33的材料形成衬垫部51，使得所述介质层57在对应所述衬垫部51的区域堆叠形成凸起部573，降低了制造成本。
以上所述是本发明的优选实施例，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也视为本发明的保护范围。

Claims (21)

  1. 一种阵列基板，其特征在于，包括衬底，所述衬底包括至少一第一区域及至少一第二区域，所述第一区域设置有低温多晶硅晶体管，所述第二区域设置有氧化物晶体管，所述氧化物晶体管包括氧化物半导体层、栅极绝缘层、栅极、源漏极，所述氧化物半导体层包括连接设置的沟道部及接触部，所述沟道部、所述栅极绝缘层及所述栅极依次层叠设置，所述源漏极与所述接触部接触，所述沟道部至少部分朝向远离所述衬底的方向凸起设置。
  2. 如权利要求1所述的阵列基板，其特征在于，所述沟道部包括第一部分及二分别设置于所述第一部分相对两侧的第二部分，每个第二部分由所述第一部分的一端朝向所述衬底偏折。
  3. 如权利要求2所述的阵列基板，其特征在于，所述第一部分平行于所述衬底，每一第二部分相对所述第一部分的夹角大于90度小于180度。
  4. 如权利要求3所述的阵列基板，其特征在于，所述沟道部还包括两个第三部分，每个第三部分连接于一个第二部分与一个接触部之间。
  5. 如权利要求4所述的阵列基板，其特征在于，两个所述第三部分均平行于所述第一部分。
  6. 如权利要求1所述的阵列基板，其特征在于，所述氧化物晶体管还包括衬垫部，所述衬垫部凸设于所述衬底的第二区域，所述沟道部至少部分位于所述衬垫部的上方。
  7. 如权利要求6所述的阵列基板，其特征在于，所述衬垫部包括第一衬垫层及叠设于所述第一衬垫层上的第二衬垫层，所述第一衬垫层与所述衬底相邻设置。
  8. 如权利要求7所述的阵列基板，其特征在于，所述第一衬垫层为刻蚀形成所述低温多晶硅晶体管的栅极绝缘层时在所述第二区域保留下来的栅极绝缘层材料形成，所述第二衬垫层为刻蚀形成所述低温多晶硅晶体管的栅极在所述第二区域保留下来的栅极材料形成。
  9. 如权利要求7所述的阵列基板，其特征在于，所述衬垫部的宽度由所述衬垫部与所述衬底相邻的第一端向远离所述衬底的第二端减小。
  10. 如权利要求6所述的阵列基板，其特征在于，所述接触部在所述衬底上的正投影与所述衬垫部在所述衬底上的正投影的交叠面积为零。
  11. 如权利要求1所述的阵列基板，其特征在于，所述氧化物晶体管还包括介质层，所述介质层覆盖所述衬底，所述介质层部分朝远离所述衬底的方向形成凸起部，所述源漏极设置在所述介质层上且间隔所述凸起部设置，所述氧化物半导体层覆盖所述源漏极及所述介质层，所述沟道部至少部分与所述凸起部层叠设置。
  12. 如权利要求11所述的阵列基板，其特征在于，所述凸起部的宽度由所述凸起部与所述衬底相邻的第一端向远离所述衬底的第二端减小。
  13. 如权利要求1所述的阵列基板，其特征在于，所述氧化物半导体层的材质包括铟镓锌氧化物。
  14. 如权利要求1所述的阵列基板，其特征在于，所述衬底包括基底及设于所述基底上的缓冲层，所述缓冲层设于所述衬底远离所述氧化物半导体层的一侧。
  15. 如权利要求14所述的阵列基板，其特征在于，所述缓冲层的材质包括氧化硅、氮化硅中的至少一种。
  16. 一种显示装置，其特征在于，包括如权利要求1-15项中任意一项所述的阵列基板。
  17. 一种阵列基板的制作方法，其特征在于，包括以下步骤：
    提供一衬底，在所述衬底的第一区域上形成低温多晶硅晶体管，在所述衬底的第二区域上形成氧化物晶体管的源漏极；
    在所述衬底的第二区域上形成覆盖所述氧化物晶体管的源漏极的氧化物半导体层，所述氧化物半导体层部分朝远离所述衬底的方向凸起设置形成凸设结构；
    在所述氧化物半导体层上依次形成所述氧化物晶体管的栅极绝缘层及栅极，所述氧化物晶体管的栅极绝缘层及所述氧化物晶体管的栅极层叠设置于所述凸设结构上；及
    对所述氧化物半导体层的端部进行导电化处理形成接触部，所述接触部与所述氧化物晶体管的源漏极接触，所述氧化物半导体层未进行导电化处理的部分构成沟道部，所述沟道部至少部分由所述凸设结构构成。
  18. 如权利要求17所述的制作方法，其特征在于，所述“提供一衬底，在所述衬底的第一区域上形成低温多晶硅晶体管，在所述衬底的第二区域上形成氧化物晶体管的源漏极”，包括：
    在所述衬底的第一区域上形成所述低温多晶硅晶体管的低温多晶硅层；
    在所述低温多晶硅层上依次形成栅极绝缘层及栅极，及在所述衬底的第二区域形成衬垫部，从而形成预制结构；
    在所述低温多晶硅层上形成所述低温多晶硅晶体管的源漏极，及所述衬底的第二区域上形成所述氧化物晶体管的源漏极。
  19. 如权利要求18所述的制作方法，其特征在于，所述“在所述低温多晶硅层上依次形成栅极绝缘层及栅极，及在所述衬底的第二区域形成衬垫部，从而形成预制结构”与所述“在所述低温多晶硅层上形成所述低温多晶硅晶体管的源漏极，及所述衬底的第二区域上形成所述氧化物晶体管的源漏极”之间，
    所述“提供一衬底，在所述衬底的第一区域上形成低温多晶硅晶体管，在所述衬底的第二区域上形成氧化物晶体管的源漏极”，还包括：在所述预制结构上形成介质层，所述介质层部分朝远离所述衬底的方向凸起形成凸起部，所述凸起部覆盖所述衬垫部，
    所述“在所述低温多晶硅层上形成所述低温多晶硅晶体管的源漏极，及所述衬底的第二区域上形成所述氧化物晶体管的源漏极”，包括：在位于所述第一区域的介质层上形成所述低温多晶硅晶体管的源漏极，及在位于所述第二区域上的介质层上形成所述氧化物晶体管的源漏极。
  20. 如权利要求19所述的制作方法，其特征在于，所述衬垫部包括分层设置的第一衬垫层及叠设于所述第一衬垫层上的第二衬垫层，所述第一衬垫层与所述衬底相邻设置，所述第一衬垫层由刻蚀形成所述低温多晶硅晶体管的栅极绝缘层时在所述第二区域保留下来的栅极绝缘层的材料形成，所述第二衬垫层由刻蚀形成所述低温多晶硅晶体管的栅极时在所述第二区域保留下来的栅极的材料形成。
  21. 如权利要求17所述的制作方法，其特征在于，所述“提供一衬底，在所述衬底的第一区域上形成低温多晶硅晶体管，在所述衬底的第二区域上形成氧化物晶体管的源漏极”，包括：
    在所述衬底的第一区域上形成所述低温多晶硅晶体管的低温多晶硅层；
    在所述低温多晶硅晶体管的低温多晶硅层上依次形成栅极绝缘层及栅极，从而形成预制结构；
    在所述预制结构上形成介质层，所述介质层部分朝远离所述衬底的方向凸起形成凸起部；
    在位于所述第一区域的介质层上形成所述低温多晶硅晶体管的源漏极，及在位于所述第二区域上的介质层上形成所述氧化物晶体管的源漏极，
    所述“在所述衬底的第二区域上形成覆盖所述氧化物晶体管的源漏极的氧化物半导体层，所述氧化物半导体层部分朝远离所述衬底的方向凸起设置形成凸设结构”还包括：所述氧化物半导体层覆盖所述凸起部及所述氧化物晶体管的源漏极，所述凸设结构覆盖所述凸起部。
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