WO2019205341A1 - 阵列基板及显示面板 - Google Patents

阵列基板及显示面板 Download PDF

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Publication number
WO2019205341A1
WO2019205341A1 PCT/CN2018/099112 CN2018099112W WO2019205341A1 WO 2019205341 A1 WO2019205341 A1 WO 2019205341A1 CN 2018099112 W CN2018099112 W CN 2018099112W WO 2019205341 A1 WO2019205341 A1 WO 2019205341A1
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WO
WIPO (PCT)
Prior art keywords
metal pattern
layer
array substrate
area
boundary
Prior art date
Application number
PCT/CN2018/099112
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English (en)
French (fr)
Inventor
曹志浩
Original Assignee
武汉华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 武汉华星光电技术有限公司 filed Critical 武汉华星光电技术有限公司
Priority to US16/306,589 priority Critical patent/US11205666B2/en
Publication of WO2019205341A1 publication Critical patent/WO2019205341A1/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509—Filters, e.g. light shielding masks
    • G02F1/133514—Colour filters
    • G02F1/133516—Methods for their manufacture, e.g. printing, electro-deposition or photolithography
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate

Definitions

  • the present invention relates to the field of flat panel displays, and in particular to an array substrate and a display panel.
  • LCD Liquid crystal displays
  • LCD display device includes TFT (Thin Film Transistor, thin film transistor device, and TFT-LCD, thin film field effect transistor liquid crystal display, each liquid crystal pixel on such display is driven by a thin film transistor integrated behind it, thus having high reaction speed and high Brightness, high contrast, small size, low power consumption, no radiation, etc., occupy a dominant position in the current display market.
  • TFT Thin Film Transistor, thin film transistor device, and TFT-LCD, thin film field effect transistor liquid crystal display
  • the processed array substrate and the color film substrate need to be cut to form a plurality of display panels of equal size.
  • the display panel includes an array substrate cutting line and a color film substrate cutting line. The distance between the color film substrate cutting line and the display area is smaller than the distance between the tangent line of the array substrate and the display area. Therefore, the color film substrate substrate cutting line is located at the periphery of the array substrate. Above the line.
  • the force generated during cutting deforms the film structure on the corresponding array substrate, and the metal trace on the film structure is irreversibly broken due to deformation, so that the display The panel produces anomalies that reduce the yield of the product.
  • the invention provides an array substrate and a display panel to solve the technical problem that the existing color film substrate is broken when the product is cut.
  • the invention provides an array substrate comprising:
  • the first area corresponding to a display area of the display panel
  • the second area disposed outside the first area, the second area corresponding to the non-display area of the display panel,
  • the second region includes a substrate, at least one inorganic layer formed on the substrate, and a wire formed on the inorganic layer,
  • the second region further includes at least one metal pattern formed between the substrate and the wire, and the metal pattern or a portion of the metal pattern is blocked by the wire.
  • the array substrate further includes a first cutting boundary and a second cutting boundary, the first cutting boundary and the wire crossing;
  • the first cutting boundary and the second cutting boundary are parallel to a first boundary of the first region, and a distance between the first cutting boundary and the first boundary is smaller than the second cutting boundary and the The spacing of the first boundary.
  • the metal pattern is formed below the intersection of the first cutting boundary and the wire.
  • the inorganic layer includes a buffer layer, a dielectric layer, and a flat layer formed on the substrate, and the substrate includes at least one between the inorganic layer or the adjacent inorganic layers.
  • Metal pattern is a preferred embodiment of the present invention.
  • the metal pattern comprises a combination of one or more of a first metal pattern, a second metal pattern or a third metal pattern;
  • the first metal pattern corresponds to a light shielding layer in the first region, the second metal pattern and a gate layer in the first region, the third metal pattern and the first The source and drain in the area correspond.
  • the first metal pattern is formed on the substrate, between the substrate and the buffer layer;
  • the second metal pattern is formed on the buffer layer between the buffer layer and the dielectric layer;
  • the third metal pattern is formed on the dielectric layer between the dielectric layer and the planar layer.
  • the first metal pattern and the light shielding layer are formed by a first patterning process
  • the second metal pattern and the gate electrode are formed by a second patterning process
  • the source drain is formed by a third patterning process.
  • the array substrate further includes a first insulating layer and a second insulating layer;
  • the first insulating layer is formed on the inorganic layer, the wire is formed on the first insulating layer, and the second insulating layer is formed on the wire.
  • the invention also proposes an array substrate comprising:
  • the first area corresponding to a display area of the display panel
  • the second area disposed outside the first area, the second area corresponding to the non-display area of the display panel,
  • the second region includes a substrate, at least one inorganic layer formed on the substrate, and a wire formed on the inorganic layer,
  • the second region further includes at least one metal pattern formed between the substrate and the wire.
  • the array substrate further includes a first cutting boundary and a second cutting boundary, the first cutting boundary and the wire crossing;
  • the first cutting boundary and the second cutting boundary are parallel to a first boundary of the first region, and a distance between the first cutting boundary and the first boundary is smaller than the second cutting boundary and the The spacing of the first boundary.
  • the metal pattern is formed below the intersection of the first cutting boundary and the wire.
  • the inorganic layer includes a buffer layer, a dielectric layer, and a flat layer formed on the substrate, and the substrate includes at least one between the inorganic layer or the adjacent inorganic layers.
  • Metal pattern is a preferred embodiment of the present invention.
  • the metal pattern comprises a combination of one or more of a first metal pattern, a second metal pattern or a third metal pattern;
  • the first metal pattern corresponds to a light shielding layer in the first region, the second metal pattern and a gate layer in the first region, the third metal pattern and the first The source and drain in the area correspond.
  • the first metal pattern is formed on the substrate, between the substrate and the buffer layer;
  • the second metal pattern is formed on the buffer layer between the buffer layer and the dielectric layer;
  • the third metal pattern is formed on the dielectric layer between the dielectric layer and the planar layer.
  • the first metal pattern and the light shielding layer are formed by a first patterning process
  • the second metal pattern and the gate electrode are formed by a second patterning process
  • the source drain is formed by a third patterning process.
  • the array substrate further includes a first insulating layer and a second insulating layer;
  • the first insulating layer is formed on the inorganic layer, the wire is formed on the first insulating layer, and the second insulating layer is formed on the wire.
  • the present invention also proposes a display panel comprising the above array substrate.
  • the invention improves the hardness of the film layer structure in the region by providing at least one metal pattern between the substrate and the wire in the second region, and reduces deformation caused by the array substrate when cutting the lobes, thereby preventing The breakage of the wire increases the yield of the product.
  • FIG. 1 is a top plan view of an array substrate according to a preferred embodiment of the present invention.
  • FIG. 2 is a structural view of a film layer of the array substrate corresponding to the first cutting boundary AB of FIG. 1.
  • FIG. 1 is a top view of an array substrate according to a preferred embodiment of the present invention, wherein the array substrate includes a first area and a second area, the area corresponding to the first area is the area MNFE;
  • the first area corresponds to the display area of the display panel
  • the second area corresponds to the non-display area of the display panel, and is disposed outside the first area, that is, the area GHDC of the area MNFE is removed;
  • the array substrate further includes a first cutting boundary AB and a second cutting boundary CD, the first cutting boundary AB and the second cutting boundary CD being located in the second region, the first cutting boundary AB and the The second cutting boundary CD is only a reference line for cutting, and has no other meaning;
  • the first cutting boundary AB is a color film substrate cutting line
  • the second cutting boundary CD is an array substrate cutting line; since the area of the color film substrate is smaller than the area of the array substrate, the color film substrate is required.
  • the area ABHG in FIG. 1 is a color film substrate, and the area GHCD is an array substrate, that is, the color film substrate corresponding to the array substrate is cut according to the first cutting boundary AB, and the area ABDC is removed, and the second cutting boundary is
  • the CD is a cutting reference line of the array substrate.
  • first cutting boundary AB and the second cutting boundary CD are parallel to the first boundary EF of the first region, and the spacing between the first cutting boundary AB and the first boundary EF Less than the distance between the second cutting boundary CD and the first boundary EF.
  • FIG. 2 is a structural view of a film layer of the array substrate corresponding to the first cutting boundary AB of FIG. 1, the second region including a substrate 101, at least one inorganic layer formed on the substrate 101, and formed in the On the inorganic layer, the wire 102,
  • the second region further includes at least one metal pattern formed between the substrate 101 and the wire 102.
  • the metal pattern is formed under the wire 102, that is, the metal pattern or part of the metal pattern is blocked by the pattern of the wire 102; preferably, in order to save raw materials or ensure array substrate light
  • the transmittance of the metal pattern may also exist only below the first cutting boundary AB, that is, below the intersection of the first cutting boundary AB and the wire 102.
  • the inorganic layer includes a buffer layer 103, a dielectric layer 104, and a planarization layer 105 formed on the substrate 101, and the substrate 101 and the inorganic layer or adjacent inorganic layers are included At least one metal pattern including a combination of one or more of the first metal pattern 106, the second metal pattern 107, or the third metal pattern 108;
  • the second region includes a three-layer metal pattern, that is, a first metal pattern 106, a first metal pattern 107, or a first metal pattern 108; wherein the first metal pattern 106 Formed on the substrate 101 between the substrate 101 and the buffer layer 103; the second metal pattern 107 is formed on the buffer layer 103 at the buffer layer 103 and the dielectric layer 104.
  • the third metal pattern 108 is formed on the dielectric layer 104 between the dielectric layer 104 and the flat layer 105;
  • the first region that is, the display region includes a light shielding layer, a gate, and a source and a drain;
  • the first metal pattern corresponds to a light shielding layer in the first region, and the second metal a pattern and a gate layer in the first region, the third metal pattern corresponding to a source and a drain in the first region;
  • the first metal pattern 106 and the light shielding layer are the same film layer structure of the array substrate
  • the second metal pattern 107 and the gate electrode are the same film layer structure of the array substrate
  • the third The metal pattern 108 and the source and drain electrodes are the same film layer structure of the array substrate; that is, the first metal pattern 106 and the light shielding layer are formed by a first patterning process, the second metal pattern 107 and the gated layer
  • the pole is formed by a second patterning process
  • the third metal pattern 108 and the source drain are formed by a third patterning process; that is, the added metal pattern of the invention can improve the product without adding other mask processes. Yield.
  • the array substrate located in the second region further includes a first insulating layer 109 and a second insulating layer 110; the first insulating layer 109 is formed on the inorganic layer, and the wire 102 Formed on the first insulating layer 109, the second insulating layer 110 is formed on the wire 102.
  • the metal has a relatively high hardness, so the region Compared with the maximum stress that can be withstood by the prior art film structure, when the same cutting force is applied, the deformation of the film structure in the region becomes small, preventing the breakage of the wire and improving the product.
  • the metal patterns are disposed under the wires and covered by the wires.
  • the present invention also proposes a display panel comprising the above array substrate.
  • the present invention provides an array substrate and a display panel, the array substrate including a first area and a second area, the first area corresponding to a display area of the display panel; the second area and the non-display panel Corresponding to the display area, disposed on the outer side of the first area;
  • the array substrate located in the second area includes a substrate, at least one inorganic layer formed on the substrate, and a wire formed on the inorganic layer;
  • the second region further includes at least one metal pattern formed between the substrate and the wire; the present invention provides at least between the substrate and the wire in the second region A metal pattern enhances the hardness of the film structure in the region, reduces the deformation of the array substrate when cutting the lobes, prevents breakage of the wires, and improves the yield of the product.

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  • Engineering & Computer Science (AREA)
  • Nonlinear Science (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Chemical & Material Sciences (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

一种阵列基板及显示面板，阵列基板包括第一区域和第二区域，第一区域与显示面板的显示区域对应；第二区域与显示面板的非显示区域对应；第二区域包括基板（101）及形成于基板（101）上的导线（102）；其中，第二区域还包括至少一金属图案，金属图案形成于基板（101）与导线（102）之间。

Description

阵列基板及显示面板 技术领域
本发明涉及平板显示器领域，特别涉及一种阵列基板及显示面板。
 背景技术
LCD（Liquid crystal displays，液晶显示器）是一种被广泛应用的平板显示器，主要是通过液晶开关调制背光源光场强度来实现画面显示。LCD显示装置中包括TFT（Thin Film Transistor，薄膜晶体管）器件，而TFT-LCD即薄膜场效应晶体管液晶显示器，此类显示器上的每一液晶象素点都是由集成在其后的薄膜晶体管来驱动，因而具有高反应速度、高亮度、高对比度、体积小、功耗低、无辐射等特点，在当前的显示器市场中占据主导地位。
现有技术中，基于成本的考虑，加工形成的阵列基板与彩膜基板贴合后需要被切割形成若干块大小相等的显示面板。其中，显示面板包括阵列基板切割线和彩膜基板切割线，彩膜基板切割线与显示区域的间距小于阵列基板切线与显示区域的间距；因此，彩膜基板基板切割线位于所述阵列基板外围走线的上方。
对所述彩膜基板进行切割时，切割时所产生的力对与之对应阵列基板上的膜层结构产生形变，而膜层结构上的金属走线因形变而出现不可恢复的断裂，使得显示面板产生异常，降低产品的良率。
 技术问题
本发明提供一种阵列基板及显示面板，以解决现有彩膜基板进行产品切割时出现断线的技术问题。
 技术解决方案
本发明提供一种阵列基板，其包括：
第一区域，所述第一区域与显示面板的显示区域对应；
第二区域，设置于所述第一区域的外侧，所述第二区域与所述显示面板的非显示区域对应，
所述第二区域包括基板、形成于所述基板之上的至少一无机层以及形成于所述无机层上导线，
其中，所述第二区域还包括至少一金属图案，所述金属图案形成于所述基板与所述导线之间，所述金属图案或部分所述金属图案被所述导线遮挡。
根据本发明一优选实施例，所述阵列基板还包括第一切割边界和第二切割边界，所述第一切割边界和所述导线交叉；
所述第一切割边界和所述第二切割边界与所述第一区域的第一边界互相平行，所述第一切割边界与所述第一边界的间距小于所述第二切割边界与所述第一边界的间距。
根据本发明一优选实施例，所述金属图案形成于所述第一切割边界与所述导线交叉点的下方。
根据本发明一优选实施例，所述无机层包括形成于所述基板上的缓冲层、介质层以及平坦层，所述基板与所述无机层或相邻两所述无机层之间包括至少一金属图案。
根据本发明一优选实施例，所述金属图案包括第一金属图案、第二金属图案或第三金属图案中一种或多种的组合；
其中，所述第一金属图案与所述第一区域中的遮光层对应，所述第二金属图案与所述第一区域中的栅极层应，所述第三金属图案与所述第一区域中的源漏极对应。
根据本发明一优选实施例，所述第一金属图案形成所述基板之上，位于所述基板与所述缓冲层之间；
所述第二金属图案形成于所述缓冲层上，位于所述缓冲层与所述介质层之间；
所述第三金属图案形成于所述介质层上，位于所述介质层与所述平坦层之间。
根据本发明一优选实施例，所述第一金属图案和所述遮光层通过第一构图工艺形成，所述第二金属图案和所述栅极通过第二构图工艺形成，所述第三金属图案和所述源漏极通过第三构图工艺形成。
根据本发明一优选实施例，所述阵列基板还包括第一绝缘层和第二绝缘层；
所述第一绝缘层形成于所述无机层上，所述导线形成于所述第一绝缘层上，所述第二绝缘层形成于所述导线上。
本发明还提出了一种阵列基板，其包括：
第一区域，所述第一区域与显示面板的显示区域对应；
第二区域，设置于所述第一区域的外侧，所述第二区域与所述显示面板的非显示区域对应，
所述第二区域包括基板、形成于所述基板之上的至少一无机层以及形成于所述无机层上导线，
其中，所述第二区域还包括至少一金属图案，所述金属图案形成于所述基板与所述导线之间。
根据本发明一优选实施例，所述阵列基板还包括第一切割边界和第二切割边界，所述第一切割边界和所述导线交叉；
所述第一切割边界和所述第二切割边界与所述第一区域的第一边界互相平行，所述第一切割边界与所述第一边界的间距小于所述第二切割边界与所述第一边界的间距。
根据本发明一优选实施例，所述金属图案形成于所述第一切割边界与所述导线交叉点的下方。
根据本发明一优选实施例，所述无机层包括形成于所述基板上的缓冲层、介质层以及平坦层，所述基板与所述无机层或相邻两所述无机层之间包括至少一金属图案。
根据本发明一优选实施例，所述金属图案包括第一金属图案、第二金属图案或第三金属图案中一种或多种的组合；
其中，所述第一金属图案与所述第一区域中的遮光层对应，所述第二金属图案与所述第一区域中的栅极层应，所述第三金属图案与所述第一区域中的源漏极对应。
根据本发明一优选实施例，所述第一金属图案形成所述基板之上，位于所述基板与所述缓冲层之间；
所述第二金属图案形成于所述缓冲层上，位于所述缓冲层与所述介质层之间；
所述第三金属图案形成于所述介质层上，位于所述介质层与所述平坦层之间。
根据本发明一优选实施例，所述第一金属图案和所述遮光层通过第一构图工艺形成，所述第二金属图案和所述栅极通过第二构图工艺形成，所述第三金属图案和所述源漏极通过第三构图工艺形成。
根据本发明一优选实施例，所述阵列基板还包括第一绝缘层和第二绝缘层；
所述第一绝缘层形成于所述无机层上，所述导线形成于所述第一绝缘层上，所述第二绝缘层形成于所述导线上。
本发明还提出了一种显示面板，所述显示面板包括上述阵列基板。
 有益效果
本发明通过在第二区域中的所述基板与所述导线之间设置至少一金属图案，提升了该区域膜层结构的硬度，减小了阵列基板在切割裂片时所产生的形变，防止了导线的断裂，提高了产品的良率。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明优选实施例一种阵列基板的俯视图；
图2为图1第一切割边界AB所对应的阵列基板的膜层结构图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图示，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是用以相同标号表示。
图1所示为本发明优选实施例一种阵列基板的俯视图，其中，所述阵列基板包括第一区域和第二区域，所述第一区域所对应的面积为区域MNFE；
本实施例中，所述第一区域与显示面板的显示区域对应，所述第二区域与显示面板的非显示区域对应，设置于所述第一区域的外侧，即除去区域MNFE的区域GHDC；
所述阵列基板还包括第一切割边界AB和第二切割边界CD，所述第一切割边界AB和所述第二切割边界CD位于所述第二区域，所述第一切割边界AB和所述第二切割边界CD仅仅为切割的参考线，不具有其他意义；
本实施例中，所述第一切割边界AB为彩膜基板切割线，所述第二切割边界CD为阵列基板切割线；由于彩膜基板的面积小于阵列基板的面积，因此需要对彩膜基板进行切割；
其中，图1中的区域ABHG为彩膜基板，区域GHCD为阵列基板，即根据第一切割边界AB对所述阵列基板所对应的彩膜基板进行切割，去除区域ABDC，所述第二切割边界CD为阵列基板的切割参考线。
本实施例中，所述第一切割边界AB和所述第二切割边界CD与所述第一区域的第一边界EF互相平行，所述第一切割边界AB与所述第一边界EF的间距小于所述第二切割边界CD与所述第一边界EF的间距。
图2所示为图1中第一切割边界AB所对应的阵列基板的膜层结构图，所述第二区域包括基板101、形成于所述基板101之上的至少一无机层以及形成于所述无机层上导线102，
其中，所述第二区域还包括至少一金属图案，所述金属图案形成于所述基板101与所述导线102之间。
本实施例中，所述金属图案形成于所述导线102的下方，即所述金属图案或部分所述金属图案被所述导线102的图案所遮挡；优选的，为了节约原材料或保证阵列基板光的透过率，所述金属图案还可以仅存在于所述第一切割边界AB下方，即所述第一切割边界AB和所述导线102交叉点的下方。
本实施例中，所述无机层包括形成于所述基板101上的缓冲层103、介质层104以及平坦层105，所述基板101与所述无机层或相邻两所述无机层之间包括至少一金属图案，所述金属图案包括第一金属图案106、第二金属图案107或第三金属图案108中一种或多种的组合；
如图2所示，本实施例中，所述第二区域包括三层金属图案，即第一金属图案106、第一金属图案107或第一金属图案108；其中，所述第一金属图案106形成所述基板101之上，位于所述基板101与所述缓冲层103之间；所述第二金属图案107形成于所述缓冲层103上，位于所述缓冲层103与所述介质层104之间；所述第三金属图案108形成于所述介质层104上，位于所述介质层104与所述平坦层105之间；
另外，所述第一区域，即显示区域包括遮光层、栅极以及源漏极；本实施例中，所述第一金属图案与所述第一区域中的遮光层对应，所述第二金属图案与所述第一区域中的栅极层应，所述第三金属图案与所述第一区域中的源漏极对应；
即所述第一金属图案106和所述遮光层为所述阵列基板的同一膜层结构，所述第二金属图案107和所述栅极为所述阵列基板的同一膜层结构，所述第三金属图案108和所述源漏极为所述阵列基板的同一膜层结构；即，所述第一金属图案106和所述遮光层通过第一构图工艺形成，所述第二金属图案107和所栅极通过第二构图工艺形成，所述第三金属图案108和所述源漏极通过第三构图工艺形成；即本发明所增加的金属图案不需要增加其他的光罩工艺，即可提高产品的良率。
如图2所示，位于所述第二区域的所述阵列基板还包括第一绝缘层109和第二绝缘层110；所述第一绝缘层109形成于所述无机层上，所述导线102形成于所述第一绝缘层109上，所述第二绝缘层110形成于所述导线102上。
当所述彩膜基板按照第一切割边界进行切割时，由于所述第一切割边界所对应的阵列基板相比现有技术增加了至少一金属图案，由于金属具有比较高的硬度，因此该区域相比现有技术膜层结构所能承受的最大应力变大，使得受到同等切割力的作用时，该区域的膜层结构所发生的形变量变小，防止了导线的断裂，提高了产品的良率；另外，为了保证阵列基板光的透过率，所述金属图案均设置在导线的下方，被导线被覆盖。
本发明还提出了一种显示面板，所述显示面板包括上述阵列基板。
本发明提出了一种阵列基板及显示面板，所述阵列基板包括第一区域和第二区域，所述第一区域与显示面板的显示区域对应；所述第二区域与所述显示面板的非显示区域对应，设置于所述第一区域的外侧；位于所述第二区域的所述阵列基板包括基板、形成于所述基板之上的至少一无机层以及形成于所述无机层上导线；另外，所述第二区域还包括至少一金属图案，所述金属图案形成于所述基板与所述导线之间；本发明通过在第二区域中的所述基板与所述导线之间设置至少一金属图案，提升了该区域膜层结构的硬度，减小了阵列基板在切割裂片时所产生的形变，防止了导线的断裂，提高了产品的良率。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (17)

  1. 一种阵列基板，其中，所述阵列基板包括：
    第一区域，所述第一区域与显示面板的显示区域对应；
    第二区域，设置于所述第一区域的外侧，所述第二区域与所述显示面板的非显示区域对应，
    所述第二区域包括基板、形成于所述基板之上的至少一无机层以及形成于所述无机层上导线，
    其中，所述第二区域还包括至少一金属图案，所述金属图案形成于所述基板与所述导线之间，所述金属图案或部分所述金属图案被所述导线遮挡。
  2. 根据权利要求1所述阵列基板，其中，所述阵列基板还包括第一切割边界和第二切割边界，所述第一切割边界和所述导线交叉；
    所述第一切割边界和所述第二切割边界与所述第一区域的第一边界互相平行，所述第一切割边界与所述第一边界的间距小于所述第二切割边界与所述第一边界的间距。
  3. 根据权利要求2所述阵列基板，其中，所述金属图案形成于所述第一切割边界与所述导线交叉点的下方。
  4. 根据权利要求1所述阵列基板，其中，所述无机层包括形成于所述基板上的缓冲层、介质层以及平坦层，所述基板与所述无机层或相邻两所述无机层之间包括至少一金属图案。
  5. 根据权利要求4所述阵列基板，其中，所述金属图案包括第一金属图案、第二金属图案或第三金属图案中一种或多种的组合；
    其中，所述第一金属图案与所述第一区域中的遮光层对应，所述第二金属图案与所述第一区域中的栅极层应，所述第三金属图案与所述第一区域中的源漏极对应。
  6. 根据权利要求5所述阵列基板，其中，所述第一金属图案形成所述基板之上，位于所述基板与所述缓冲层之间；
    所述第二金属图案形成于所述缓冲层上，位于所述缓冲层与所述介质层之间；
    所述第三金属图案形成于所述介质层上，位于所述介质层与所述平坦层之间。
  7. 根据权利要求5所述阵列基板，其中，所述第一金属图案和所述遮光层通过第一构图工艺形成，所述第二金属图案和所述栅极通过第二构图工艺形成，所述第三金属图案和所述源漏极通过第三构图工艺形成。
  8. 根据权利要求1所述阵列基板，其中，所述阵列基板还包括第一绝缘层和第二绝缘层；
    所述第一绝缘层形成于所述无机层上，所述导线形成于所述第一绝缘层上，所述第二绝缘层形成于所述导线上。
  9. 一种阵列基板，其中，所述阵列基板包括：
    第一区域，所述第一区域与显示面板的显示区域对应；
    第二区域，设置于所述第一区域的外侧，所述第二区域与所述显示面板的非显示区域对应，
    所述第二区域包括基板、形成于所述基板之上的至少一无机层以及形成于所述无机层上导线，
    其中，所述第二区域还包括至少一金属图案，所述金属图案形成于所述基板与所述导线之间。
  10. 根据权利要求9所述阵列基板，其中，所述阵列基板还包括第一切割边界和第二切割边界，所述第一切割边界和所述导线交叉；
    所述第一切割边界和所述第二切割边界与所述第一区域的第一边界互相平行，所述第一切割边界与所述第一边界的间距小于所述第二切割边界与所述第一边界的间距。
  11. 根据权利要求10所述阵列基板，其中，所述金属图案形成于所述第一切割边界与所述导线交叉点的下方。
  12. 根据权利要求9所述阵列基板，其中，所述无机层包括形成于所述基板上的缓冲层、介质层以及平坦层，所述基板与所述无机层或相邻两所述无机层之间包括至少一金属图案。
  13. 根据权利要求12所述阵列基板，其中，所述金属图案包括第一金属图案、第二金属图案或第三金属图案中一种或多种的组合；
    其中，所述第一金属图案与所述第一区域中的遮光层对应，所述第二金属图案与所述第一区域中的栅极层应，所述第三金属图案与所述第一区域中的源漏极对应。
  14. 根据权利要求13所述阵列基板，其中，所述第一金属图案形成所述基板之上，位于所述基板与所述缓冲层之间；
    所述第二金属图案形成于所述缓冲层上，位于所述缓冲层与所述介质层之间；
    所述第三金属图案形成于所述介质层上，位于所述介质层与所述平坦层之间。
  15. 根据权利要求13所述阵列基板，其中，所述第一金属图案和所述遮光层通过第一构图工艺形成，所述第二金属图案和所述栅极通过第二构图工艺形成，所述第三金属图案和所述源漏极通过第三构图工艺形成。
  16. 根据权利要求9所述阵列基板，其中，所述阵列基板还包括第一绝缘层和第二绝缘层；
    所述第一绝缘层形成于所述无机层上，所述导线形成于所述第一绝缘层上，所述第二绝缘层形成于所述导线上。
  17. 一种显示面板，其中，所述显示面板包括权利要求1所述的阵列基板。
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