Classifications

• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/06—Auxiliary circuits, e.g. for writing into memory
  • G11C16/32—Timing circuits
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/06—Auxiliary circuits, e.g. for writing into memory
  • G11C16/08—Address circuits; Decoders; Word-line control circuits
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/06—Auxiliary circuits, e.g. for writing into memory
  • G11C16/24—Bit-line control circuits
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
  • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
  • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
  • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
  • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/68—Floating-gate IGFETs
  • H10D30/681—Floating-gate IGFETs having only two programming levels
  • H10D30/684—Floating-gate IGFETs having only two programming levels programmed by hot carrier injection
  • H10D30/685—Floating-gate IGFETs having only two programming levels programmed by hot carrier injection from the channel
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/68—Floating-gate IGFETs
  • H10D30/6891—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode
  • H10D30/6892—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode having at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C16/00—Erasable programmable read-only memories
  • G11C16/02—Erasable programmable read-only memories electrically programmable
  • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
  • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
  • G11C16/0425—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a merged floating gate and select transistor
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C8/00—Arrangements for selecting an address in a digital store
  • G11C8/10—Decoders
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C8/00—Arrangements for selecting an address in a digital store
  • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection

Definitions

• the present invention relates to non-volatile memory arrays.
• Non-volatile memory devices are well known in the art.
• a split-gate memory cell is disclosed in U.S. Patent 5,029,130.
• This memory cell has a floating gate and a control gate disposed over and controlling the conductivity of a channel region of the substrate extending between source and drain regions.
• Various combinations of voltages are applied to the control gate, source and drain to program the memory cell (by injecting electrons onto the floating gate), to erase the memory cell (by removing electrons from the floating gate), and to read the memory cell (by measuring or detecting the conductivity of the channel region to determine the programming state of the floating gate).
• U.S. Patent 7,315,056 discloses a memory cell that additionally includes a program/erase gate over the source region.
• U.S. Patent 7,868,375 discloses a memory cell that additionally includes an erase gate over the source region and a coupling gate over the floating gate.
• Fig. 1 illustrates a split gate memory cell 10 with spaced apart source and drain regions 14/16 formed in a silicon semiconductor substrate 12.
• a channel region 18 of the substrate is defined between the source/drain regions 14/16.
• a floating gate 20 is disposed over and insulated from a first portion of the channel region 18 (and partially over and insulated from the source region 14).
• a control gate (also referred to as a word line gate or select gate) 22 has a lower portion disposed over and insulated from a second portion of the channel region 18, and an upper portion that extends up and over the floating gate 20 (i.e., the control gate 22 wraps around an upper edge of the floating gate 20).
• Memory cell 10 can be erased by placing a high positive voltage on the control gate 22, and a reference potential on the source and drain regions 14/16. The high voltage drop between the floating gate 20 and control gate 22 will cause electrons on the floating gate 20 to tunnel from the floating gate 20, through the intervening insulation, to the control gate 22 by the well-known Fowler-Nordheim tunneling mechanism (leaving the floating gate 20 positively charged or more positively charged - the erased state). Memory cell 10 can be programmed by applying a ground potential to drain region 16, a positive voltage on source region 14, and a positive voltage on the control gate 22.
• Electrons will then flow from the drain region 16 toward the source region 14, with some electrons becoming accelerated and heated whereby they are injected (by hot electron injection) onto the floating gate 20 (leaving the floating gate negatively charged or more negatively charged - the programmed state).
• Memory cell 10 can be read by placing ground potential on the drain region 16, a positive voltage on the source region 14 and a positive voltage on the control gate 22 (turning on the channel region portion under the control gate 22). If the floating gate is positively charged (erased), electrical current will flow from source region 14 to drain region 16 (i.e. the memory cell 10 is sensed to be in its erased“1” state based on sensed current flow).
• the channel region under the floating gate is weakly turned on or turned off, thereby reducing or preventing any current flow (i.e., the memory cell 10 is sensed to be in its programmed“0” state based on sensed low or no current flow).
• FIG. 2 illustrates an alternate split gate memory cell 24 with same elements as memory cell 10, but additionally with a program/erase (PE) gate 26 disposed over and insulated from the source region 14 (i.e. this is a three gate design).
• PE program/erase
• Memory cell 24 can be erased by placing a high voltage on the PE gate 26 to induce tunneling of electrons from the floating gate 20 to the PE gate 26.
• Memory cell 24 can be programmed by placing positive voltages on the control gate 22, PE gate 26 and source region 14, and a current on drain region 16, to inject electrons from the current flowing through the channel region 18 onto floating gate 20.
• Memory cell 24 can be read by placing positive voltages on the control gate 22 and drain region 16, and sensing current flow.
• FIG. 3 illustrates an alternate split gate memory cell 28 with same elements as memory cell 10, but additionally with an erase gate 30 disposed over and insulated from the source region 14, and a coupling gate 32 over and insulated from the floating gate 20.
• Memory cell 28 can be erased by placing a high voltage on the erase gate 30 and optionally a negative voltage on the coupling gate 32 to induce tunneling of electrons from the floating gate 20 to the erase gate 30.
• Memory cell 28 can be programmed by placing positive voltages on the control gate 22, erase gate 30, coupling gate 32 and source region 14, and a current on drain region 16, to inject electrons from the current flowing through the channel region 18 onto floating gate 20.
• Memory cell 28 can be read by placing positive voltages on the control gate 22 and drain region 16 (and optionally on the erase gate 30 and/or the coupling gate 32), and sensing current flow.
• each memory cell can only store one bit of data (i.e., the cell has only two possible programming states), which are read by placing the memory cell above its read threshold whereby it will conduct the read current if not programmed with electrons, and it will not conduct (or conduct very little) if programmed with electrons.
• each memory cell can be programmed to one of many programming states, which is determined by reading the memory cell using a subthreshold read operation.
• each memory cell can be gradually programmed with electrons until a desired programming state is achieved.
• the memory cell read voltage(s) are selected to place the memory cell in a sub-threshold state (i.e., the read voltage(s) are insufficient to turn the memory cell on no matter its programmed state), so that any current through the channel region of the memory cell represents sub-threshold leakage current.
• subthreshold leakage current will be proportional to the programming state of the memory cell, and therefore indicative of the programming state of the memory cell. Therefore, in this manner, the memory cells can be used in an analog manner whereby they are programmed to an analog programming state and produce an analog read current that is proportional to the analog programming state.
• Analog operation is ideal for applications such as neural nets, where the memory cells are used to store individual weight values, and the array is used to perform vector/matrix multiplication (i.e., the neuron layer inputs are placed on the word lines, and are effectively multiplied by the weights stored in the individual memory cells to produce the outputs on the bit lines).
• vector/matrix multiplication i.e., the neuron layer inputs are placed on the word lines, and are effectively multiplied by the weights stored in the individual memory cells to produce the outputs on the bit lines.
• Sources of the current demand include large word line drivers, bit-line pre-charging, differential op-amps for differential current sensing, and activation. In all cases, voltage and current supplies need to handle the peak voltage and current requirements for operating the memory array, making these devices larger and consume more power.
• a memory device that includes a plurality of memory cells arranged in rows and columns, a plurality of word lines each connected to a row of the memory cells, a plurality of bit lines each connected to a column of the memory cells, a word line driver connected to the word lines, a bit line driver connected to the bit lines, a plurality of word line switches each disposed on one of the word lines for selectively connecting and disconnecting one of the rows of memory cells to and from the word line driver, a plurality of bit line switches each disposed on one of the bit lines for selectively connecting and disconnecting one of the columns of memory cells to and from the bit line driver, and a controller configured to control the plurality of word line switches to connect some but not all of the rows of memory cells to the word line driver at a first point in time, and control the plurality of bit line switches to connect some but not all of the columns of memory cells to the bit line driver at a second point in time.
• a memory device includes a plurality of memory cells arranged in rows and columns, a plurality of word lines each connected to a row of the memory cells, a plurality of bit lines each connected to a column of the memory cells, a word line driver connected to the word lines, a bit line driver connected to the bit lines, a plurality of word line switches each disposed on one of the word lines for selectively connecting and disconnecting one of the rows of memory cells to and from the word line driver, and a controller configured to control the plurality of word line switches to connect some but not all of the rows of memory cells to the word line driver at a first point in time.
• a memory device includes a plurality of memory cells arranged in rows and columns, a plurality of word lines each connected to a row of the memory cells, a plurality of bit lines each connected to a column of the memory cells, a word line driver connected to the word lines, a bit line driver connected to the bit lines, a plurality of bit line switches each disposed on one of the bit lines for selectively connecting and disconnecting one of the columns of memory cells to and from the bit line driver, and a controller configured to control the plurality of bit line switches to connect some but not all of the columns of memory cells to the bit line driver at a first point in time.
• a method of operating a memory device where the memory device includes a plurality of memory cells arranged in rows and columns, a plurality of word lines each connected to a row of the memory cells, a plurality of bit lines each connected to a column of the memory cells, a word line driver connected to the word lines, a bit line driver connected to the bit lines, a plurality of word line switches each disposed on one of the word lines for selectively connecting and disconnecting one of the rows of memory cells to and from the word line driver, and a plurality of bit line switches each disposed on one of the bit lines for selectively connecting and disconnecting one of the columns of memory cells to and from the bit line driver.
• the method includes operating the plurality of word line switches to connect some but not all of the rows of memory cells to the word line driver at a first point in time, and operating the plurality of bit line switches to connect some but not all of the columns of memory cells to the bit line driver at a second point in time.
• Fig. 1 is a side cross sectional view of a conventional split gate memory cell having two conductive gates.
• Fig. 2 is a side cross sectional view of a conventional split gate memory cell having three conductive gates.
• Fig. 3 is a side cross sectional view of a conventional split gate memory cell having four conductive gates.
• Fig. 4 is a schematic view of the memory array configuration of the present invention.
• Fig. 5 is a plan view showing the architecture of an exemplary memory device of the present invention.
• Electrical power and current demands for operating the memory array can be reduced by selectively grouping certain components that are operated together at certain points in time, and operating that group of components together to the exclusion of others during certain operations. In doing so, the components that supply electrical current and voltage can be reduced in size and complexity, and will consume less power.
• FIG. 4 illustrates the memory array configuration of the present invention, and is applicable to any of the previously described memory cell configurations.
• a memory array 38 includes memory cells 40 arranged in rows and columns.
• Word lines WL0, WL1, ... WLn-l, and WLn extend in the row direction and are driven by word line driver 42.
• Bit lines BL0, BL1, ... BLp-l, and BLp extend in the column direction, and are driven by bit line driver 44.
• the bit line driver 44 not only includes circuitry for driving voltages/currents onto the bit lines, but also sense amplifier circuitry for sensing the voltages/currents on the bit lines.
• Each memory cell 40 is located at an intersection of one of the word lines WL and one of the bit lines BL.
• Each of the word lines WLO-WLn is connected to and/or forms the control gates (also called the word line gates or the select gates) for an entire row of the memory cells 40.
• Each of the bit lines BLO-BLp is connected to the drain regions for an entire column of the memory cells 40.
• Each word line WL includes a switch (WL switch 46) that selectively passes or blocks incoming signals on the word line WL from the word line driver 42. Specifically, each switch has a closed or connected state where it will conduct or pass signals there through, and an open or disconnected state where it will not conduct or pass signals there through.
• the word line switches 46 can be clustered in groups 48i, 48 2 , ...48 m ), where all of the word line switches 46 in each group are operated together. The word line switches 46 are opened (to block signals) and closed (to pass signals) in response to control signals on one or more WL switch control lines 50.
• Each bit line BL includes a switch (BL switch 52) that selectively passes or blocks signals on the bit line to/from the bit line driver 44. Specifically, each switch has a closed or connected state where it will conduct or pass signals there through, and an open or disconnected state where it will not conduct or pass signals there through.
• the bit line switches 52 can be clustered in groups 54i, 54 3 ⁇ 4 ...54 k ), where all of the bit line switches 52 in each group are operated together. The bit line switches 52 are opened (to block signals) and closed (to pass signals) in response to control signals on one or more BL switch control lines 56.
• the present invention manages and controls peak current/power demand by selectively controlling the WL switches 46 on the word lines WL, and the BL switches 52 on the bit lines BL. Specifically, only some of the WL switches 46 are activated (closed) at a point in time to pass voltages/currents from the word line driver 42 to just some of the word lines WL. Similarly, only some of the BL switches 52 are activated (closed) at a point in time to pass voltages/currents between the bit line driver 44 and just some of the bit lines BL. By having some but not all of the WL switches 46 and/or some but not all of the BL switches 52 closed at one time, the peak current demand by the memory array is reduced.
• This reduction in peak current demand can be achieved by activating one or more, but not all, of the groups 48 of WL switches 46 at one time. Similarly, this reduction in peak current demand can be achieved by activating one or more, but not all, of the groups 54 of BL switches 52 at one time.
• bit lines For example, certain operations call for the bit lines to be pre-charged to a specific voltage.
• one or more but not all of the groups 54 of the BL switches 52 can be activated (closed) so that only some of the bit lines are pre-charged at one time (i.e. a first point in time) by the bit line driver 44.
• the other bit lines can be pre charged at later time(s) (i.e., at one or more other points in time different from the first point in time).
• the sense amplifier circuitry can include differential sense amplifiers each of which detects the difference in voltage between two of the bit lines.
• the BL switches 52 can be used to sequentially activate different groups 54 of bit lines connected to different differential sense amplifiers in the bit line driver 44 at different times.
• the word lines and bit lines are discharged of voltage (i.e., by coupling to ground) during certain operations.
• the WL switches 46 and/or BL switches 52 can be successively closed at different times during this operation, so that only some of the lines are discharged at one time (which reduces ground noise). This can be done individually (switch by switch) or by groups (group by group, groups by groups, etc.).
• the response from an operation involving one group of switches can be an input trigger to another group of switches.
• each switch group 46/54 can vary depending on the peak current demands of the device. Alternately, the switches can be operated individually without being operated in groups.
• the above described WL switches 46 and BL switches 52 allow for simplification of the design and operation of the word line driver 42 and the bit line driver 44.
• the architecture of an exemplary memory device is illustrated in Fig. 5.
• the memory device includes an array 60 of non-volatile memory cells, which can be segregated into two separate planes (Plane A 62a and Plane B 62b).
• the memory cells can be of the type shown in Figures 1-3, formed on a single chip, arranged in a plurality of rows and columns in the semiconductor substrate 12. Adjacent to the array of non-volatile memory cells are address decoders (e.g.
• XDEC 64 (a row decoder that preferably includes the word line driver 42), SLDRV 66 (a source line driver for driving the source lines), YMUX 68 (a column decoder that preferably includes the bit line driver 44), HVDEC 70 (a high voltage decoder) and a bit line controller (BLINHCTL 72), which are used to decode addresses and supply the various voltages to the various memory cell gates and regions during read, program, and erase operations for selected memory cells.
• Controller 76 (containing control circuitry) controls the various device elements to implement each operation (program, erase, read) on target memory cells.
• Charge pump CHRGPMP 74 provides the various voltages used to read, program and erase the memory cells under the control of the controller 76.
• the control signals on the WL switch control line(s) 50 and the BL switch control line(s) 56 are preferably provided by controller 76.
• references to the present invention herein are not intended to limit the scope of any claim or claim term, but instead merely make reference to one or more features that may be covered by one or more claims.
• Materials, processes and numerical examples described above are exemplary only, and should not be deemed to limit the claims. Single layers of material could be formed as multiple layers of such or similar materials, and vice versa.
• the term“adjacent” includes“directly adjacent” (no intermediate materials, elements or space disposed therebetween) and“indirectly adjacent” (intermediate materials, elements or space disposed there between),“mounted to” includes“directly mounted to” (no intermediate materials, elements or space disposed there between) and“indirectly mounted to” (intermediate materials, elements or spaced disposed there between), and“electrically coupled” includes“directly electrically coupled to” (no intermediate materials or elements there between that electrically connect the elements together) and“indirectly electrically coupled to” (intermediate materials or elements there between that electrically connect the elements together).
• forming an element“over a substrate” can include forming the element directly on the substrate with no intermediate materials/elements therebetween, as well as forming the element indirectly on the substrate with one or more intermediate materials/elements there between.

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• 2018
  • 2018-06-21 US US16/015,020 patent/US10580491B2/en active Active
• 2019
  • 2019-01-28 JP JP2020550668A patent/JP7093419B2/ja active Active
  • 2019-01-28 KR KR1020207023530A patent/KR102282580B1/ko active Active
  • 2019-01-28 EP EP19771178.1A patent/EP3769307B1/en active Active
  • 2019-01-28 CN CN201980021261.2A patent/CN111919255A/zh active Pending
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