KR102282580B1 - 비휘발성 메모리 어레이에서 피크 전력 요구 및 잡음을 관리하기 위한 시스템 및 방법 - Google Patents
비휘발성 메모리 어레이에서 피크 전력 요구 및 잡음을 관리하기 위한 시스템 및 방법 Download PDFInfo
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- KR102282580B1 KR102282580B1 KR1020207023530A KR20207023530A KR102282580B1 KR 102282580 B1 KR102282580 B1 KR 102282580B1 KR 1020207023530 A KR1020207023530 A KR 1020207023530A KR 20207023530 A KR20207023530 A KR 20207023530A KR 102282580 B1 KR102282580 B1 KR 102282580B1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
- G11C16/0425—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a merged floating gate and select transistor
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/24—Bit-line control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/32—Timing circuits
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- H01L27/11524—
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- H01L27/11526—
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/68—Floating-gate IGFETs
- H10D30/681—Floating-gate IGFETs having only two programming levels
- H10D30/684—Floating-gate IGFETs having only two programming levels programmed by hot carrier injection
- H10D30/685—Floating-gate IGFETs having only two programming levels programmed by hot carrier injection from the channel
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/68—Floating-gate IGFETs
- H10D30/6891—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode
- H10D30/6892—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode having at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/10—Decoders
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Read Only Memory (AREA)
- Dram (AREA)
- Static Random-Access Memory (AREA)
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201862647573P | 2018-03-23 | 2018-03-23 | |
| US62/647,573 | 2018-03-23 | ||
| US16/015,020 US10580491B2 (en) | 2018-03-23 | 2018-06-21 | System and method for managing peak power demand and noise in non-volatile memory array |
| US16/015,020 | 2018-06-21 | ||
| PCT/US2019/015369 WO2019182684A2 (en) | 2018-03-23 | 2019-01-28 | System and method for managing peak power demand and noise in non-volatile memory array |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20200102520A KR20200102520A (ko) | 2020-08-31 |
| KR102282580B1 true KR102282580B1 (ko) | 2021-07-28 |
Family
ID=67985589
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020207023530A Active KR102282580B1 (ko) | 2018-03-23 | 2019-01-28 | 비휘발성 메모리 어레이에서 피크 전력 요구 및 잡음을 관리하기 위한 시스템 및 방법 |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US10580491B2 (https=) |
| EP (1) | EP3769307B1 (https=) |
| JP (1) | JP7093419B2 (https=) |
| KR (1) | KR102282580B1 (https=) |
| CN (1) | CN111919255A (https=) |
| TW (1) | TWI685848B (https=) |
| WO (1) | WO2019182684A2 (https=) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2021150497A (ja) * | 2020-03-19 | 2021-09-27 | キオクシア株式会社 | 記憶装置 |
| US11943922B1 (en) * | 2023-11-11 | 2024-03-26 | Western Digital Technologies, Inc. | Non-volatile memory with three dimensional stacked word line switches |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050269622A1 (en) | 2004-06-07 | 2005-12-08 | Pavel Klinger | Semiconductor memory array of floating gate memory cells with program/erase and select gates, and methods of making and operating same |
Family Cites Families (22)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5029130A (en) | 1990-01-22 | 1991-07-02 | Silicon Storage Technology, Inc. | Single transistor non-valatile electrically alterable semiconductor memory device |
| JP3337564B2 (ja) | 1994-09-16 | 2002-10-21 | 松下電器産業株式会社 | 半導体記憶装置 |
| US6404670B2 (en) | 1996-05-24 | 2002-06-11 | Uniram Technology, Inc. | Multiple ports memory-cell structure |
| US6256224B1 (en) * | 2000-05-03 | 2001-07-03 | Hewlett-Packard Co | Write circuit for large MRAM arrays |
| JP2006004514A (ja) | 2004-06-17 | 2006-01-05 | Matsushita Electric Ind Co Ltd | 半導体記憶装置 |
| US20090039410A1 (en) | 2007-08-06 | 2009-02-12 | Xian Liu | Split Gate Non-Volatile Flash Memory Cell Having A Floating Gate, Control Gate, Select Gate And An Erase Gate With An Overhang Over The Floating Gate, Array And Method Of Manufacturing |
| KR20100120517A (ko) | 2009-05-06 | 2010-11-16 | 삼성전자주식회사 | 불휘발성 메모리 장치 및 그것의 워드 라인 또는 비트 라인의 제어방법 |
| US7868657B1 (en) * | 2009-07-22 | 2011-01-11 | Qualcomm, Incorporated | High voltage logic circuits |
| CN102859603A (zh) * | 2010-04-27 | 2013-01-02 | 莫塞德技术公司 | 具有交替选择的相变存储阵列块 |
| US8305808B2 (en) | 2010-08-12 | 2012-11-06 | Yield Microelectronics Corp. | Low-voltage EEPROM array |
| JP2012069203A (ja) | 2010-09-22 | 2012-04-05 | Toshiba Corp | 不揮発性半導体記憶装置及び不揮発性半導体記憶装置の駆動方法 |
| US8400864B1 (en) | 2011-11-01 | 2013-03-19 | Apple Inc. | Mechanism for peak power management in a memory |
| US10541029B2 (en) * | 2012-08-01 | 2020-01-21 | Micron Technology, Inc. | Partial block memory operations |
| WO2014129172A1 (ja) * | 2013-02-19 | 2014-08-28 | パナソニック株式会社 | 不揮発性半導体記憶装置 |
| JP2014170599A (ja) * | 2013-03-01 | 2014-09-18 | Toshiba Corp | 半導体記憶装置 |
| US20150155039A1 (en) * | 2013-12-02 | 2015-06-04 | Silicon Storage Technology, Inc. | Three-Dimensional Flash NOR Memory System With Configurable Pins |
| JP6151203B2 (ja) | 2014-03-04 | 2017-06-21 | 株式会社東芝 | 演算制御装置、それを備えたメモリシステム、および、情報処理装置 |
| JP6271460B2 (ja) | 2015-03-02 | 2018-01-31 | 東芝メモリ株式会社 | 半導体記憶装置 |
| US9672930B2 (en) * | 2015-05-29 | 2017-06-06 | Silicon Storage Technology, Inc. | Low power operation for flash memory system |
| KR102469172B1 (ko) * | 2016-03-14 | 2022-11-22 | 에스케이하이닉스 주식회사 | 비휘발성 메모리 장치 및 이의 검증 라이트 방법 |
| US11308383B2 (en) | 2016-05-17 | 2022-04-19 | Silicon Storage Technology, Inc. | Deep learning neural network classifier using non-volatile memory array |
| KR102493814B1 (ko) * | 2016-06-29 | 2023-02-02 | 에스케이하이닉스 주식회사 | 메모리 장치 |
-
2018
- 2018-06-21 US US16/015,020 patent/US10580491B2/en active Active
-
2019
- 2019-01-28 JP JP2020550668A patent/JP7093419B2/ja active Active
- 2019-01-28 KR KR1020207023530A patent/KR102282580B1/ko active Active
- 2019-01-28 EP EP19771178.1A patent/EP3769307B1/en active Active
- 2019-01-28 CN CN201980021261.2A patent/CN111919255A/zh active Pending
- 2019-01-28 WO PCT/US2019/015369 patent/WO2019182684A2/en not_active Ceased
- 2019-03-07 TW TW108107677A patent/TWI685848B/zh active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050269622A1 (en) | 2004-06-07 | 2005-12-08 | Pavel Klinger | Semiconductor memory array of floating gate memory cells with program/erase and select gates, and methods of making and operating same |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111919255A (zh) | 2020-11-10 |
| TWI685848B (zh) | 2020-02-21 |
| WO2019182684A3 (en) | 2020-05-14 |
| EP3769307A2 (en) | 2021-01-27 |
| KR20200102520A (ko) | 2020-08-31 |
| EP3769307B1 (en) | 2023-11-08 |
| WO2019182684A2 (en) | 2019-09-26 |
| US10580491B2 (en) | 2020-03-03 |
| EP3769307A4 (en) | 2021-11-03 |
| JP2021518627A (ja) | 2021-08-02 |
| TW201941210A (zh) | 2019-10-16 |
| US20190295647A1 (en) | 2019-09-26 |
| JP7093419B2 (ja) | 2022-06-29 |
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