WO2019174032A1 - Procédé de fabrication de memristor, memristor et mémoire résistive non volatile (rram) - Google Patents

Procédé de fabrication de memristor, memristor et mémoire résistive non volatile (rram) Download PDF

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Publication number
WO2019174032A1
WO2019174032A1 PCT/CN2018/079279 CN2018079279W WO2019174032A1 WO 2019174032 A1 WO2019174032 A1 WO 2019174032A1 CN 2018079279 W CN2018079279 W CN 2018079279W WO 2019174032 A1 WO2019174032 A1 WO 2019174032A1
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Prior art keywords
memristor
dielectric layer
lower electrode
electrode
conductive path
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PCT/CN2018/079279
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English (en)
Chinese (zh)
Inventor
姚国峰
沈健
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深圳市汇顶科技股份有限公司
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Priority to CN201880000463.4A priority Critical patent/CN110546778A/zh
Priority to PCT/CN2018/079279 priority patent/WO2019174032A1/fr
Publication of WO2019174032A1 publication Critical patent/WO2019174032A1/fr

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching

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  • Embodiments of the present application relate to the field of memory manufacturing, and more particularly, to a method of fabricating a memristor, a memristor, and a resistive random access memory (RRAM).
  • RRAM resistive random access memory
  • Resistive Random Access Memory is a non-volatile memory that uses materials with variable resistance characteristics to store information. It has low power consumption, high density, and read and write. Fast speed, good durability and so on.
  • the basic memory cell of RRAM is a memristor.
  • the memristor is mainly composed of a lower electrode, a resistive layer and an upper electrode.
  • the working principle of the memristor is: when a positive voltage is applied between the two electrodes, a resistive layer is formed.
  • the conductive filament (Filament) exhibits a low resistance state; and when a RESET current is generated between the two electrodes, the conductive filament in the resistance layer breaks to exhibit a high resistance state, and the variable The resistance characteristic achieves the switching of RRAM '0' and '1' in effect.
  • the magnitude of the resulting reverse current peak is related to the area of the lower electrode of the memristor.
  • the area of the lower electrode is generally determined by the minimum size allowed by the process platform. Due to the limitation of the minimum size of the existing process platform, the electrode area of the memristor cannot be made smaller, and the memristor of the smaller electrode area is prepared. The process can only increase the process cost by means of a more advanced process platform. Therefore, a memristor manufacturing method is needed, which can produce a memristor with a smaller electrode area without increasing the process cost.
  • the embodiment of the present application provides a method for manufacturing a memristor, a memristor and a resistive random access memory (RRAM), which can fabricate a memristor having a smaller electrode area without increasing the process cost.
  • RRAM resistive random access memory
  • a method of fabricating a memristor comprising:
  • An upper electrode of the memristor is fabricated on the resistive layer of the memristor.
  • the method further includes:
  • a second conductive path electrically connected to the upper electrode of the memristor is prepared.
  • the depositing the lower electrode of the memristor comprises:
  • a lower electrode of the memristor is deposited over the via.
  • the preparing a resistive layer of the memristor in a section along a deposition direction of a lower electrode of the memristor comprises:
  • a resistive layer of the memristor is deposited on an upper surface of the second dielectric layer and an inner surface of the blind via.
  • the preparing an upper electrode of the memristor on the resistive layer of the memristor comprises:
  • An upper electrode material of the memristor is deposited on a surface of the resistive layer of the memristor to inject the upper electrode material into the blind via.
  • the method further includes:
  • a second conductive path is formed on an inner surface of the trench, the second conductive path electrically connecting an upper electrode of the memristor.
  • the depositing the lower electrode of the memristor comprises:
  • the third dielectric layer is subjected to a thinning treatment to expose the cross section of the lower electrode of the memristor located on the side surface of the second dielectric layer.
  • the preparing a resistive layer of the memristor in a section along a deposition direction of a lower electrode of the memristor comprises:
  • a resistive layer of the memristor is deposited over the cross section of the lower electrode of the memristor.
  • the preparing an upper electrode of the memristor on the resistive layer of the memristor comprises:
  • An upper surface of the memristor of the memristor is deposited on the upper surface of the resistive layer.
  • the method further includes:
  • a second conductive via is formed over the second via.
  • a ratio of an etch rate of the second dielectric layer to an etch rate of the first dielectric layer is greater than a specific threshold.
  • a memristor produced according to the method of fabricating a memristor according to the first aspect and any one of the possible implementations of the first aspect.
  • a memristor comprising an upper electrode, a resistive layer and a lower electrode;
  • the lower electrode is electrically connected to the first conductive path
  • the upper electrode is electrically connected to the second conductive path
  • the first conductive path is used to implement electricity of the lower electrode and the outside Connected
  • the second conductive path is used to achieve electrical connection between the upper electrode and the outside.
  • a resistive random access memory comprising:
  • a resistive random access memory comprising:
  • FIG. 1 is a schematic view of a typical structure of a memristor.
  • FIG. 2 is a schematic view of a three-dimensional structure of a memristor.
  • FIG. 3 is a schematic flow chart of a method of fabricating a memristor according to an embodiment of the present application.
  • FIG. 4 is a schematic diagram of preparing a first conductive via in accordance with an embodiment of the present application.
  • FIG. 5 is a schematic diagram of preparing a via hole according to an embodiment of the present application.
  • FIG. 6 is a schematic diagram of a lower electrode for preparing a memristor according to an embodiment of the present application.
  • FIG. 7 is a schematic illustration of the preparation of a blind via in accordance with an embodiment of the present application.
  • FIG. 8 is a schematic diagram of preparing a resistive layer in accordance with an embodiment of the present application.
  • FIG. 9 is a schematic diagram of the preparation of an upper electrode in accordance with an embodiment of the present application.
  • FIG. 10 is a schematic diagram of preparing a second conductive via in accordance with an embodiment of the present application.
  • FIG. 11 is a schematic diagram of preparing a dielectric layer in accordance with another embodiment of the present application.
  • Figure 12 is a schematic illustration of forming a support structure in accordance with another embodiment of the present application.
  • Figure 13 is a schematic illustration of the preparation of a lower electrode in accordance with another embodiment of the present application.
  • FIG. 14 is a schematic diagram of the preparation of a dielectric layer in accordance with another embodiment of the present application.
  • FIG. 15 is a schematic view of forming a cross section of a lower electrode in accordance with another embodiment of the present application.
  • FIG. 16 is a schematic view showing formation of a resistive layer and an upper electrode according to another embodiment of the present application.
  • 17 is a schematic diagram of preparing a dielectric layer in accordance with another embodiment of the present application.
  • FIG. 18 is a schematic diagram of preparing a first conductive via in accordance with another embodiment of the present application.
  • 19 is a schematic diagram of preparing a second conductive via in accordance with another embodiment of the present application.
  • 20 is a schematic structural view of a memristor according to an embodiment of the present application.
  • FIG. 21 is a schematic structural diagram of an RRAM according to an embodiment of the present application.
  • the memristor may include a lower electrode 106, a resistive layer 108, and an upper electrode 110.
  • the lower electrode 106 may be connected to the first conductive via 103.
  • the electrode 110 is connected to the second conductive path 111, so that the memristor 11 and the memristor 12 can form a crossbar structure through the first conductive path 103 and the second conductive path 111, as shown in FIG.
  • the resistor is addressed.
  • FIG. 3 is a schematic flow chart of a method 400 of fabricating a memristor according to an embodiment of the present application
  • FIG. 3 shows the main steps or operations of the manufacturing method of the microlens of the embodiment of the present application, but the steps or operations are merely examples, and other operations of the present application or various operations of FIG. 3 may be performed.
  • the various steps in method 400 may also be performed in a different order than described in the method embodiments, and it is possible that not all operations in the method embodiments are performed.
  • the method 400 can include:
  • the lower electrode material of the memristor may be deposited by a deposition process.
  • the deposition process may be a physical Vapor Deposition (PVD) Atomic layer deposition (ALD) process.
  • the deposition process of the metal-organic chemical vapor deposition (MOCVD) is not limited in the embodiment of the present application.
  • the deposited lower electrode material may be further processed.
  • the deposited lower electrode material may be processed by a photolithography process and an etching process to obtain a desired shape of the lower electrode.
  • the lower electrode material of the memristor may be a material having strong reactivity.
  • the lower electrode material may be at least one of the following materials: titanium (Ti), copper. (Cu), tungsten (W), hafnium (Hf), and chromium (Cr), or other reactive materials, which are not limited in the examples of the present application.
  • a resistive layer of the memristor is prepared in a section along a deposition direction of a lower electrode of the memristor
  • the resistive layer of the memristor can be prepared along the cross section of the lower electrode of the memristor, so that the lower electrode of the memristor is in contact with the resistive layer of the memristor.
  • the region is the cross section along the deposition direction of the lower electrode of the memristor. Since the thickness of the cross section is determined by the deposition process and is not limited by the minimum size of the process platform, it is only necessary to control the memristor by the deposition process.
  • the thickness of the lower electrode of the device can achieve the purpose of reducing the area of the lower electrode of the memristor.
  • the electrode area of the memristor prepared according to the method for fabricating the memristor according to the embodiment of the present application is not affected by the process platform.
  • the minimum size limit enables memristors with smaller electrode areas to be produced without increasing process cost, thereby reducing memory power consumption.
  • the lower electrode of the memristor gradually thickens on the first surface during deposition of the lower electrode material, here, the lower electrode
  • the direction in which the material gradually becomes thicker ie, the direction of the thickness of the lower electrode of the memristor
  • the direction can be understood as the deposition direction of the lower electrode of the memristor.
  • the cross section of the resistive layer of the memristor and the lower electrode of the memristor may be parallel to the deposition direction of the lower electrode of the memristor, or approximately parallel.
  • the cross section may have an angle with a deposition direction of the lower electrode that is less than a certain threshold.
  • the deposition direction of the lower electrode of the memristor can be considered to be perpendicular to the first surface, and correspondingly, the cross section along the deposition direction
  • the embodiment of the present application is not limited to the first surface, or is approximately perpendicular to the first surface.
  • the material of the resistive layer of the memristor may be a transition metal oxide.
  • the material of the resistive layer may be at least one of the following materials: titanium oxide. (TiO x), tantalum oxide (TaO x), niobium oxide (NbO x), zirconium oxide (ZrO x), zinc oxide (ZnO x), scandium oxide (ScO x), oxygen Chinese yttrium (YO x), nickel oxide (NiO x ), tungsten oxide (WO x ), vanadium pentoxide (VO x ), or other transition metal oxides, which are not limited in the examples of the present application.
  • the resistive layer material of the memristor may be deposited on the cross section of the lower electrode of the memristor by a deposition process (eg, PVD, ALD or MOCVD, etc.), optionally Further, the resistive layer material of the deposited memristor may be further processed.
  • the deposited resistive layer material may be processed by a photolithography process and an etching process to obtain a desired resistive layer of the memristor. shape.
  • an upper electrode of the memristor is prepared on the resistive layer of the memristor.
  • a deposition process for example, PVD, ALD or MOCVD, etc.
  • the upper electrode material of the memristor may be processed by a photolithography process and an etching process to obtain the shape of the upper electrode of the desired memristor.
  • the material of the upper electrode may be a simple metal element having a work function of about 5 eV, or may be a chemically stable metal compound.
  • the optional metal elemental material includes, but is not limited to, palladium (Pd), iridium (Ir), gold (Au), nickel (Ni), ruthenium (Ru), or, if a metal compound is selected, Selected metal compounds include, but are not limited to, tantalum nitride (TaN), titanium nitride (TiN), tantalum carbide (TaC), tungsten carbide (WC).
  • the resistive layer of the memristor can be prepared along the cross section of the lower electrode in the deposition direction of the memristor, and further, the resistive layer can be prepared on the resistive layer of the memristor.
  • the upper electrode of the resistor that is, the resistance layer of the memristor and the upper electrode of the memristor are sequentially prepared on the basis of the cross section of the deposition direction of the lower electrode of the memristor, thereby controlling the lower electrode of the deposited memristor
  • the thickness along the deposition direction can achieve the purpose of controlling the area of the lower electrode of the memristor, and the thickness of the lower electrode of the memristor is determined by the deposition process, and is not limited by the minimum size of the process platform. Therefore, the process is not increased. In the case of cost, a memristor having a smaller electrode area can be fabricated, and the effect of reducing the power consumption of the memory can be achieved.
  • the method 400 may further include:
  • a second conductive path electrically connected to the upper electrode of the memristor is prepared.
  • the memristor can be connected to an external circuit, such as a transistor circuit, through the first conductive path and the second conductive path, thereby enabling operations such as reading, writing, and erasing of the control memory.
  • the lower electrode and the upper electrode of the memristor can form a crossbar structure through the first conductive path and the second conductive path, respectively, and the crossbar structure can be used for addressing the memristor.
  • FIG. 4 to FIG. 19 are exemplified by manufacturing two memristors.
  • a single memristor, or more memristors, or a memories may be obtained according to the steps shown in FIGS. 4 to 19.
  • the embodiment of the present application does not limit this.
  • Embodiment 1 the manufacturing steps shown in FIGS. 4 to 10 are referred to as Embodiment 1
  • Embodiment 2 the manufacturing steps shown in FIGS. 11 to 19 are referred to as Embodiment 2.
  • Embodiment 1 and Embodiment 2 will be described below with reference to the drawings.
  • the manufacturing method can include the following:
  • step 1a is performed to prepare a first conductive via 202 on the upper surface of a complementary metal oxide semiconductor (CMOS) substrate 20, as shown in FIG. 4;
  • CMOS complementary metal oxide semiconductor
  • the material of the first conductive via 202 may be deposited on the upper surface of the CMOS substrate 20 by a deposition process (eg, PVD).
  • the material of the deposited first conductive via 202 may be further
  • the material of the first conductive via 202 can be processed by a photolithography process and an etching process to obtain a pattern of the desired first conductive via 202.
  • the photoresist may be first spin-coated on the surface of the material of the deposited first conductive via 202, and then the photoresist is exposed and developed to obtain a pattern of the desired first conductive via 202, and then the first conductive via 202 is The material is etched to obtain a first conductive via 202 of a certain thickness (eg, 250 nanometers).
  • the material of the first conductive path 202 may be a conductive material, such as aluminum, or copper, or may be other conductive materials. If the material of the first conductive path 202 is copper, The first conductive path 202 is prepared by the damascene process, which is not limited in this embodiment of the present application.
  • the first conductive via 202 and the CMOS substrate 20 may be connected by a conductive via, which is not shown in any of FIGS. 4 to 19.
  • step 1b is performed to deposit a first dielectric layer 201 on the upper surface of the CMOS substrate 20, as shown in FIG. 5;
  • the deposition process used to deposit the first dielectric layer 201 is CVD, and details are not described herein.
  • the deposited first dielectric layer 201 covers the first conductive via 202, that is, the first conductive via 202 is in the first dielectric layer 201. Due to the presence of the first conductive via 202, the surface of the first dielectric layer 201 may be uneven, further The upper surface of the first dielectric layer 201 may be planarized. For example, the upper surface of the first dielectric layer 201 may be planarized by a chemical-mechanical planarization (CMP) process, and planarized. The thickness of the first dielectric layer 201 is reduced. In one possible embodiment, the original thickness of the first dielectric layer 201 may be 1000 nm, and the thickness of the planarized first dielectric layer 201 may be 350 nm.
  • CMP chemical-mechanical planarization
  • the material of the first dielectric layer 201 may be an oxide of silicon, or a nitride of silicon, or a compound of other silicon, which is not limited in the embodiment of the present application.
  • step 1c is performed to process the upper surface of the first dielectric layer 201 to form a via 203 that reaches the first conductive via 202, as shown in FIG.
  • the upper surface of the first dielectric layer 201 may be processed by a photolithography process and an etching process to form a via 203 that reaches the first conductive via 202, that is, the bottom of the via 203 reaches the first conductive
  • the via 202, or the bottom of the via 203, is connected to the first conductive via 202.
  • step 1d is performed to fill the through hole 203 with a conductive material as shown in FIG.
  • a conductive material may be deposited on the upper surface of the first dielectric layer 201 to inject the conductive material into the via hole 203, and then remove other regions on the upper surface of the first dielectric layer 201 except the via hole 203.
  • the conductive material on the conductive material that is, only the conductive material at the location where the via 203 is located, the conductive material in the via can be used to achieve electrical connection between the first conductive via and the lower electrode.
  • step 1e is performed to deposit a lower electrode 206 of the memristor on the upper surface of the first dielectric layer 201, as shown in FIG. 6;
  • the electrical connection of the lower electrode 206 and the first conductive via 202 can be achieved through the via 203.
  • the material of the lower electrode 206 may be the material exemplified in the foregoing embodiment, and details are not described herein again.
  • the deposition direction of the lower electrode 206 of the memristor may be the deposition direction 216 shown in FIG. 6, and the deposition direction 216 may be considered to be perpendicular or approximately perpendicular to the upper surface of the first dielectric layer 201.
  • the cross section of the lower electrode in the deposition direction of the resistor may also be perpendicular or approximately perpendicular to the upper surface of the first dielectric layer 201.
  • step 1f is performed to deposit a second dielectric layer 205 on the upper surface of the first dielectric layer 201, as shown in FIG. 6;
  • the material of the second dielectric layer 205 may be an oxide of silicon, or a nitride of silicon, or may be a compound of other silicon, which is not limited in the embodiment of the present application.
  • the material of the second dielectric layer 205 and the first dielectric layer 201 may be the same or different, which is not limited in the embodiment of the present application.
  • the upper surface of the second dielectric layer 205 may be planarized.
  • the upper surface of the second dielectric layer 205 may be planarized by a CMP process, or may be incorrect.
  • the second dielectric layer 205 is subjected to a planarization process and is directly subjected to subsequent processing, which is not limited in the embodiment of the present application.
  • step 1g is performed to form a blind via 207 in the deposition direction of the lower electrode 206 on the upper surface of the second dielectric layer 205, as shown in FIG.
  • the blind via 207 may be controlled to penetrate a portion of the lower electrode material, and the bottom of the blind via 207 abuts the first dielectric layer 201.
  • the section 266 through which the blind via 207 penetrates the lower electrode 206 can be considered as a section of the lower electrode 206 in the deposition direction, that is, a section in which the lower electrode 206 is in effective contact with the resistive layer.
  • the bottom of the blind hole 207 may be located below the contact surface of the first dielectric layer 201 and the second dielectric layer 205.
  • the bottom of the blind hole 207 may be located below the upper surface of the first dielectric layer 201.
  • the etching depth of the blind via 207 can be controlled by a reactive ion etch (RIE) process.
  • the etching depth can be determined according to the etching depth of the blind via 207, and the etching rate corresponding to the dielectric layer material can be determined.
  • the duration is such that the etching is stopped when the time required for the etching is reached; or, if the materials of the first dielectric layer 201 and the second dielectric layer 205 are different, in this case, the etching can be controlled by the stop point detection system of the etching apparatus.
  • the termination time that is, the etching can be stopped when the desired etching depth is reached.
  • step 1h is performed to deposit a resistive layer 208 on the upper surface of the second dielectric layer 205 to inject the material of the resistive layer into the blind via 207, thereby achieving the cross section of the resistive layer 208 and the lower electrode 206 along the deposition direction.
  • the contact is shown in Figure 8.
  • the deposition process and materials used for preparing the resistive layer may refer to related descriptions in the foregoing embodiments, and details are not described herein again.
  • step 1i is performed to deposit the upper electrode 210 of the memristor on the upper surface of the second dielectric layer 205 to inject the material of the upper electrode into the blind via 207, thereby achieving contact between the resistive layer 208 and the upper electrode 210, as shown in the figure. 9 is shown.
  • the deposition process and materials used for preparing the upper electrode may refer to the related descriptions in the foregoing embodiments.
  • the precious metal material may be further processed by a stripping process. Since the stripping process is a process known in the industry, no longer here. Narration.
  • step 1j is performed to deposit a third dielectric layer 211 on the upper surface of the second dielectric layer 205 and the upper surface of the upper electrode 210, as shown in FIG.
  • the third dielectric layer 211 may be planarized, or the third dielectric layer may not be planarized, and the subsequent processing may be directly performed.
  • step 1k is performed to etch the upper surface of the third dielectric layer 211 to obtain a trench 213 that reaches the upper electrode of the memristor, that is, the bottom of the formed trench 213 is in contact with the upper electrode.
  • step 11 may be performed to prepare a second conductive path 212 on the inner surface of the trench 213 and the upper surface of the third dielectric layer 211.
  • the preparation method and material of the second conductive path 212 can refer to the preparation method and material of the first conductive path 202, and details are not described herein again.
  • the memristor unit 21 and the memristor unit 22 can be obtained.
  • the memristor unit 21 and the memrist unit 22 are a lateral structure memristor, a memrist unit 21 and a memristor.
  • the resistor unit 22 can be connected to the corresponding transistor circuit on the CMOS substrate 20 through the first conductive path 202 and the second conductive path 212, so that operations such as reading and writing and erasing of the memory can be realized.
  • the manufacturing method may include the following contents:
  • step 2a depositing a first dielectric layer 301 on the upper surface of the CMOS substrate 30, as shown in FIG.
  • the deposition process used to deposit the first dielectric layer 301 may also be the deposition process described above, and details are not described herein again.
  • the material of the first dielectric layer 301 may be an oxide of silicon, or a nitride of silicon, or may be a compound of other silicon, which is not limited by the embodiment of the present application.
  • the material of the first dielectric layer 301 may be a nitride of silicon and may have a thickness of 100 nm.
  • step 2b is performed to deposit a second dielectric layer 302 on the upper surface of the first dielectric layer 301, as shown in FIG.
  • the deposition process used to deposit the second dielectric layer 302 may also be the deposition process described above, and details are not described herein again.
  • the material of the second dielectric layer 302 may be an oxide of silicon, or a nitride of silicon, or may be a compound of other silicon, which is not limited by the embodiment of the present application.
  • the material of the second dielectric layer 302 may be an oxide of silicon and may have a thickness of 400 nm.
  • the second dielectric layer 302 may also be processed by a photolithography process and an etching process to form the second dielectric layer 302 into a support structure, that is, the second dielectric layer 302 is on the upper surface of the first dielectric layer 301.
  • the projected area is smaller than the area of the upper surface of the first dielectric layer 301.
  • the cross section of the support structure may be rectangular or trapezoidal, as shown in FIG.
  • the ratio of the etch rate of the second dielectric layer 302 to the etch rate of the first dielectric layer 301 is greater than a specific threshold.
  • the specific threshold may be 3, or may be 5, the present application.
  • the first dielectric layer 301 can serve as an etch stop layer for the second dielectric layer 302, thereby making the etching process for the second dielectric 302 more controllable.
  • step 2c is performed to deposit the lower electrode 303 of the memristor on the surfaces of the first dielectric layer 301 and the second dielectric layer 302, as shown in FIG.
  • the lower electrode material of the memristor covers the upper surface of the first dielectric layer 301, the upper surface of the second dielectric layer 302, and the side surface.
  • the implementation of the lower electrode 303 for depositing the memristor can be referred to the related description in the foregoing embodiment, and details are not described herein again.
  • the deposition direction of the lower electrode 303 of the memristor may include the deposition direction 313 and the deposition direction 323 shown in FIG. 13, wherein the deposition direction 313 is perpendicular or approximately perpendicular to the upper surface of the support structure formed by the second dielectric layer 302.
  • the deposition direction 323 is perpendicular or approximately perpendicular to the side surface of the support structure formed by the second dielectric layer 302.
  • step 2d is performed to deposit a third dielectric layer 304 on the surface of the lower electrode 303 of the memristor, as shown in FIG. 14;
  • the material of the third dielectric layer 304 may be an oxide of silicon, or a nitride of silicon, or a compound of other silicon, which is not limited in the embodiment of the present application.
  • the material of the third dielectric layer 304 and the material of the second dielectric layer 302 may be the same, or may be different, which is not limited by the embodiment of the present application.
  • a tetraethylsiloxane (TEOS) thermal decomposition process may be employed to reduce plasma density and bombardment energy during deposition.
  • TEOS tetraethylsiloxane
  • step 2e may be performed to perform planarization processing and thinning treatment on the upper surface of the third dielectric layer 304 to expose the section 333 of the lower electrode of the memristor located on the side surface of the second dielectric layer 302,
  • the section 333 is a section along the deposition direction 323, and the section 333 is a surface in effective contact with the resistance layer as shown in FIG.
  • the third dielectric layer 304 may be planarized and thinned by a CMP process, wherein the slurry used in the CMP process grinds the material of the third dielectric layer and the lower electrode material.
  • the rates are the same or similar to facilitate control of the CMP process.
  • step 2f is performed to deposit the resistive layer 305 of the memristor over the section 333 of the lower electrode 303 of the memristor, as shown in FIG.
  • the deposition process used to deposit the resistive layer 305, and the resistive layer material used in the resistive layer 305 can be referred to the related description of the foregoing embodiment, and details are not described herein again.
  • step 2g is performed to deposit the upper electrode 307 of the memristor on the upper surface of the resistor 305 of the memristor, as shown in FIG.
  • the deposition process for depositing the upper electrode 307 and the upper electrode material used for the upper electrode can be referred to the related description of the foregoing embodiment, and details are not described herein again.
  • the upper electrode 307 and the resistance layer 305 may be patterned by a photolithography process and an etching process to form the memristor unit 31 and the memristor unit 32.
  • the first conductive path corresponding to the lower electrode may be prepared first, and then the second conductive path corresponding to the upper electrode may be prepared, or the second conductive path corresponding to the upper electrode may be prepared first, and then the lower electrode is prepared.
  • the embodiment of the present application does not limit the preparation sequence of the first conductive path and the second conductive path.
  • the first conductive path corresponding to the lower electrode is prepared as an example.
  • step 2h may also be performed to deposit a fourth dielectric layer 308 on the upper surface of the upper electrode 307 of the memristor, as shown in FIG. 17;
  • the material and deposition process of the fourth dielectric layer may refer to materials and deposition processes of other dielectric layers, and details are not described herein again.
  • step 2i may be performed to etch the fourth dielectric layer 308 to form a first via 309 that reaches the lower electrode 303 of the memristor, that is, the bottom of the first via 309 reaches the memristor.
  • Lower electrode 303 as shown in FIG. 18;
  • step 2j is performed to deposit a conductive material on the upper surface of the fourth dielectric layer 308 to fill the first via hole 309 with a conductive material, and further, remove the first via hole on the upper surface of the fourth dielectric layer 308.
  • the conductive material at the position of 309 that is, the conductive material is only retained at the position of the first through hole 309, and the electrical connection between the lower electrode 303 of the memristor and the first conductive path can be realized by filling the conductive material in the first through hole 309. As shown in Figure 18.
  • the conductive material may be tungsten or other conductive materials, which is not limited in the embodiment of the present application.
  • step 2k is performed to prepare a first conductive via 310 above the first via 309;
  • the first conductive via 310 may be formed over the first via 309 by a sputter deposition, a photolithography process, and an etch process.
  • the first conductive via 310 is electrically connected to the first via 309, so that the lower electrode 303 can be realized. Electrical connection to the first conductive path 310.
  • materials and preparation processes for selecting the first conductive path may refer to related descriptions in the foregoing embodiments, and details are not described herein again.
  • step 21 is performed, a fifth dielectric layer 312 is deposited on the upper surface of the fourth dielectric layer 308, and the fifth dielectric layer 312 covers the first conductive via 310, as shown in FIG.
  • the material and deposition process of the fifth dielectric layer 312 may refer to materials and deposition processes of other dielectric layers, and details are not described herein again.
  • the fifth dielectric layer 312 may be planarized.
  • the fifth dielectric layer 312 may be planarized by a CMP process.
  • step 2m is performed to etch the fifth dielectric layer 312 to form a second via 311 that reaches the upper electrode of the memristor, as shown in FIG. 19;
  • the fifth dielectric layer 312 can be processed by a photolithography process and an etching process to form a second via 311 that reaches the upper electrode 307 of the memristor, that is, the bottom of the second via 311 and the memristor.
  • the upper electrodes 307 are connected.
  • step 2n may be performed to fill the second via hole 311 with a conductive material
  • a conductive material is deposited on the upper surface of the fifth dielectric layer 312 to fill the second via hole 311 with a conductive material. Further, the second via hole 311 may be removed from the upper surface of the fifth dielectric layer 312. The conductive material at the position, that is, the conductive material is only retained at the position of the second through hole 311, and the electrical connection between the upper electrode 307 and the second conductive path 314 of the memristor can be realized by filling the conductive material in the second through hole 311, such as Figure 19 shows.
  • step 2k is performed to prepare a second conductive via 314 over the second via 311.
  • a second conductive via 314 can be formed over the second via 311 by a sputter deposition, a photolithography process, and an etch process, and the second conductive via 314 is electrically connected to the second via 311, thereby enabling Electrical connection of the upper electrode 307 and the second conductive path 314 is achieved.
  • the memristor unit 31 and the memristor unit 32, and the first conductive path 310 and the second conductive path 314 can be obtained, so that the memristor unit 31 and the memristor unit 32 can pass through the first conductive path 310 and the first
  • the two conductive paths 314 are connected to corresponding transistor circuits on the CMOS substrate 30, so that operations such as reading and writing and erasing of the memory can be realized.
  • Embodiment 1 and Embodiment 2 are possible implementation manners of the method 400 for fabricating a memristor according to an embodiment of the present application, or a preferred implementation manner, the memristor according to the embodiment of the present application.
  • Other implementations resulting from the manufacturing method 400 also fall within the scope of protection of the embodiments of the present application.
  • the method for manufacturing the memristor of the embodiment of the present application may also be other alternative or equivalent modifications of the various operations in the above steps.
  • the embodiment of the present application does not limit the operation process or operation mode adopted in each step. .
  • the embodiments of the above-described method of manufacturing the memristor may be performed by a robot or a numerically controlled machining method, and the device software or process for executing the manufacturing method of the memristor may be stored in the memory by execution.
  • the computer program code executes the above-described method of manufacturing the memristor.
  • the embodiment of the present application further provides a memristor.
  • the memristor 500 can include a lower electrode 510, a resistance layer 520, and an upper electrode 530.
  • a section 511 along the deposition direction 512 of the lower electrode 510 is in surface contact with the resistance layer 520, that is, a section 511 is a region where the lower electrode 510 and the resistance layer 520 are in effective contact, the resistance layer 520 and the upper electrode 530 face contact.
  • the section 511 may be parallel or approximately parallel to the deposition direction 512, ie, the section 511 may have an angle to the deposition direction 512.
  • the lower electrode 510 is electrically connected to the first conductive path
  • the upper electrode is electrically connected to the second conductive path
  • the first conductive path is used to implement the lower electrode and the outside Electrical connection
  • the second conductive path is used to achieve electrical connection between the upper electrode and the outside.
  • the memristor 500 is a memristor or memristor array prepared according to the method of fabricating the memristor described above.
  • the embodiment of the present application further provides an RRAM.
  • the RRAM 600 may include a memristor 601, which may be a memristor prepared according to the manufacturing method of the memristor described above. Or a memristor array, or a memristor 500.
  • the size of the sequence numbers of the foregoing processes does not mean the order of execution sequence, and the order of execution of each process should be determined by its function and internal logic, and should not be applied to the embodiment of the present application.
  • the implementation process constitutes any limitation.
  • the various embodiments of the above-described manufacturing methods may be performed by a robot or a numerically controlled machining method, and the device software or process for executing the manufacturing method may execute the above-described manufacturing method by executing computer program code stored in a memory. .
  • the disclosed systems, devices, and methods may be implemented in other manners.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division.
  • there may be another division manner for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored or not executed.
  • the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be in an electrical, mechanical or other form.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

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Abstract

Des modes de réalisation de la présente invention concernent un procédé de fabrication de memristor, un memristor et une mémoire résistive non volatile (RRAM), le procédé de fabrication de memristor comprenant : le dépôt d'une électrode inférieure d'un memristor ; la préparation d'une couche de résistance du memristor le long d'une section transversale de la direction de dépôt de l'électrode inférieure du memristor ; la préparation d'une électrode supérieure du memristor sur la couche de résistance du memristor.
PCT/CN2018/079279 2018-03-16 2018-03-16 Procédé de fabrication de memristor, memristor et mémoire résistive non volatile (rram) WO2019174032A1 (fr)

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PCT/CN2018/079279 WO2019174032A1 (fr) 2018-03-16 2018-03-16 Procédé de fabrication de memristor, memristor et mémoire résistive non volatile (rram)

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