WO2019169607A1 - 抑制电流失配的电荷泵电路及其控制方法、锁相环电路 - Google Patents

抑制电流失配的电荷泵电路及其控制方法、锁相环电路 Download PDF

Info

Publication number
WO2019169607A1
WO2019169607A1 PCT/CN2018/078432 CN2018078432W WO2019169607A1 WO 2019169607 A1 WO2019169607 A1 WO 2019169607A1 CN 2018078432 W CN2018078432 W CN 2018078432W WO 2019169607 A1 WO2019169607 A1 WO 2019169607A1
Authority
WO
WIPO (PCT)
Prior art keywords
node
control
current
feedback
coupled
Prior art date
Application number
PCT/CN2018/078432
Other languages
English (en)
French (fr)
Inventor
王伟威
卢磊
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to PCT/CN2018/078432 priority Critical patent/WO2019169607A1/zh
Priority to CN201880090848.4A priority patent/CN111819777B/zh
Publication of WO2019169607A1 publication Critical patent/WO2019169607A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop

Definitions

  • the present application relates to the field of communications technologies, and in particular, to a charge pump circuit for suppressing current mismatch, a control method thereof, and a phase locked loop circuit.
  • the phase-locked loop generally includes a Phase/Frequency Detector (PFD), a Charge Pump (CP), a Loop Filter (LPF), a Voltage Controlled Oscillator (VCO), and a Voltage Controlled Oscillator (VCO). Divider.
  • the charge pump is an important component of the phase-locked loop, which can convert the signal output from the phase-detection discriminator into a voltage signal through a loop filter, and control the oscillation frequency of the voltage-controlled oscillator through the voltage signal.
  • the charge pump circuit generally includes two identically sized currents Iup and Idn generated by the same bias current mirror circuit, two circuit branches coupled between the input node of the current Iup and the input node of the current Idn. And a feedback loop composed of an operational amplifier connected between the two circuit branches, the feedback loop is used to ensure the stability of the charge pump output voltage when the current Iup and the current Idn are equal in magnitude.
  • the current Iup and the current Idn may not be equal, resulting in current mismatch between the two, affecting the stability of the charge pump output voltage.
  • the present application provides a charge pump circuit for suppressing current mismatch, a control method thereof, and a phase locked loop circuit, which can improve the stability of the charge pump output voltage.
  • the technical solution is as follows:
  • an embodiment of the present application provides a charge pump circuit for suppressing current mismatch, comprising: a first control circuit, a second control circuit, and a first feedback circuit; the first control circuit and the first current input respectively a node, a first control node, a second control node, a first feedback node, and a second feedback node, the first control circuit configured to use a potential of the first control signal from the first control node as an effective potential And when a potential of the second control signal from the second control node is an effective potential, inputting a first current from the first current input node to the second feedback node; the first feedback circuit respectively The first feedback node, the second feedback node, and the filter node are coupled, and the first feedback circuit is configured to control input of the second feedback under control of the first feedback node and the filter node The value of the current of the node is equal to the value of the first current; the second control circuit and the second current input node, the third control node, the fourth control node, and the output
  • the charge pump circuit for suppressing current mismatch includes a first control circuit, a second control circuit and a first feedback circuit, and the first feedback circuit is capable of controlling a value of a current input to the second feedback node to be equal to the first
  • the value of the current is such that the value of the charging current and the value of the discharging current are equal, and the current mismatch of the charging current and the discharging current can be suppressed, and the stability of the output voltage of the charge pump is ensured compared to the related art.
  • the charge pump circuit further includes: a third control circuit and a second feedback circuit; the third control circuit and the first current input node, the second current input node, and the first control a node, the third control node, and a third feedback node are coupled, the third control circuit is configured to input the second current into the third feedback when a potential of the first control signal is an effective potential Node, or, when the potential of the third control signal is an effective potential, input the first current into the third feedback node; the second feedback circuit and the third feedback node and the filtering respectively The nodes are coupled, and the second feedback circuit is configured to control the potential of the third feedback node under the control of the third feedback node and the filter node.
  • the setting of the third control circuit and the second feedback circuit is such that the charge pump circuit provided by the embodiment of the present application is in the third control signal whether the potentials of the first control signal and the second control signal are both active potentials
  • the potential of the fourth control signal is an effective potential, no charge sharing occurs between the second current input node and the output node, between the second feedback node and the output node, and the stability of the output voltage can be ensured.
  • the charge pump circuit further includes: the charge pump circuit further comprising: a first current source and a second current source; the first current source is coupled to the first current input node, the first current a source for inputting the first current to the first current input node; the second current source coupled to the second current input node, the second current source for inputting the second current The second current input node.
  • the first current source and the second current source may be implemented by the same type of device, for example, the circuit for providing the first current and the circuit for providing the second current may be composed of P-type transistors or both of N-type transistors. Therefore, the matching characteristic of the first current input to the first current input node and the second current input to the second current input node is better, the current mismatch of the charging current and the discharging current can be better suppressed, and the charge pump is further improved. The stability of the output voltage.
  • the charge pump circuit is applied in a phase locked loop circuit
  • the phase locked loop circuit comprises: a phase discriminator, wherein the phase discriminator is configured to output a first phase error signal according to the input clock signal. And a second phase error signal; the first phase error signal is used as the first control signal; an inverted signal of the second phase error signal is used as the second control signal; the first phase error signal The inverted signal is used as the third control signal; the second phase error signal is used as the fourth control signal.
  • the first phase error signal and the second phase error signal are signals obtained according to a comparison result between the clock signal outputted by the voltage controlled oscillator and the reference clock signal in the phase locked loop circuit, the first phase error signal and the first The pulse width of the pulse signal of the two phase error signals is different, but the pulse amplitude of the pulse signal is the same, and the control effect of the first phase error signal and the second phase error signal on the charge pump circuit can be understood as a voltage controlled oscillator.
  • the phase difference between the output and the divided clock signal and the reference clock signal is converted into a time difference between the charging and discharging process, and the charging and discharging process is controlled by the time difference, that is, when according to the first phase error signal and
  • the second phase error signal controls the first control circuit and the second control circuit, the charging time period for charging the charge pump output node and the discharging time period for discharging the charge pump output node can be adjusted.
  • the charge pump circuit is applied in a phase locked loop circuit
  • the phase locked loop circuit includes: a sampling phase detector; the first current source is coupled to a first output end of the sampling phase detector a first sampling signal outputted by the first output terminal for adjusting a value of the first current; a second current source coupled to a second output end of the sampling phase detector, the second output The second sampled signal outputted by the terminal is used to adjust the value of the second current.
  • phase-locked loop circuit further includes: a pulse generator for generating a pulse signal; the pulse signal being used as the first control signal and the fourth control signal; An inverted signal is used as the second control signal and the third control signal.
  • the first sampling signal and the second sampling signal are voltage signals obtained by sampling the clock signal output by the voltage controlled oscillator according to the reference clock signal, the voltage amplitudes of the first sampling signal and the second sampling signal are different.
  • the adjustment of the first current by the first sampling signal and the adjustment of the second current by the second sampling signal can be understood as converting the phase difference between the clock signal outputted by the voltage controlled oscillator and the reference clock signal into a pair a current source and a second current source perform a controlled voltage difference, and since the voltage value exhibits a positive correlation with the adjusted current value, the voltage difference can be converted into a adjusted current difference between the first current and the second current .
  • the charge pump circuit can realize charging and discharging under the control of the first control signal, the second control signal, the third control signal and the fourth control signal. Process control.
  • the first feedback circuit includes: a first clamping module and a first current source module; a first input end of the first clamping module is coupled to the first feedback node, the first clamping a second input of the module is coupled to the filter node, an output of the first clamp module is coupled to a control end of the first current source module, the first clamp module is configured to The potential of the output end of the first clamp module is stabilized under the control of the first feedback node and the filter node; the input end of the first current source module is coupled to the second feedback node, the first An output end of the current source module is grounded, and the first current source module is configured to control a value of a current input to the second feedback node and the first current under control of a control end of the first current source module The values are equal.
  • the first clamping module includes: a first operational amplifier; a non-inverting input of the first operational amplifier is coupled to the first feedback node, and an inverting input of the first operational amplifier is The filter node is coupled, and an output of the first operational amplifier is coupled to a control terminal of the first current source module.
  • the voltages of the first feedback node and the filter node are equal, and the value of the current input to the second feedback node is equal to the value of the first current, that is, the charging current is realized. And the suppression function of the current mismatch of the discharge current.
  • the first current source module includes: a first transistor; a gate of the first transistor is coupled to an output end of the first clamping module, and a first pole of the first transistor The second feedback node is coupled, and the second pole of the first transistor is grounded.
  • the first control circuit includes: a second transistor and a third transistor; a gate of the second transistor is coupled to the first control node, and a first pole of the second transistor is a first current input node coupled, a second pole of the second transistor coupled to the first feedback node; a gate of the third transistor coupled to the second control node, the third transistor A first pole is coupled to the first feedback node, and a second pole of the third transistor is coupled to the second feedback node.
  • the second transistor may be a P-type transistor
  • the third transistor may be an N-type transistor.
  • the first transistor and the third transistor are combined.
  • the voltage of the first current input node, the voltage of the second feedback node, and the voltage of the first feedback node may be more accurately held equal.
  • the second control circuit includes: a fourth transistor and a fifth transistor; a gate of the fourth transistor is coupled to the third control node, and a first pole of the fourth transistor is a second current input node coupled, a second pole of the fourth transistor coupled to the output node; a gate of the fifth transistor coupled to the fourth control node, the fifth transistor A pole is coupled to the output node, and a second pole of the fifth transistor is coupled to the second feedback node.
  • the fourth transistor may be a P-type transistor
  • the fifth transistor may be an N-type transistor.
  • the voltage and the voltage of the output node can be kept relatively equal, that is, there is no charge sharing between the second current input node and the output node, and between the second feedback node and the output node, thus reducing and outputting
  • the output voltage at the output of the node-coupled charge pump has a chance of glitch, which in turn ensures the stability of the output voltage.
  • the third control circuit includes: a sixth transistor and a seventh transistor; a gate of the sixth transistor is coupled to the first control node, and a first pole of the sixth transistor is a second current input node coupled, a second pole of the sixth transistor coupled to the third feedback node; a gate of the seventh transistor coupled to the third control node, the seventh transistor A first pole is coupled to the first current input node, and a second pole of the seventh transistor is coupled to the third feedback node.
  • the second feedback circuit includes: a second clamping module and a second current source module; a first input end of the second clamping module is coupled to the third feedback node, and the second clamping a second input of the module is coupled to the filter node, an output of the second clamp module is coupled to a control end of the second current source module, and the second clamp module is configured to The potential of the output end of the second clamp module is stabilized under the control of the third feedback node and the filter node; the input end of the second current source module is coupled to the third feedback node, and the second The output of the current source module is grounded, and the second current source module is configured to control the potential of the third feedback node under the control of the control end of the second current source module.
  • the second clamping module includes: a second operational amplifier; a non-inverting input of the second operational amplifier is coupled to the third feedback node, and an inverting input of the second operational amplifier is The filter node is coupled, and an output of the second operational amplifier is coupled to a control terminal of the second current source module.
  • the voltages of the third feedback node and the filter node are equal, which provides a basis for ensuring that the voltage of the second current input node and the voltage of the output node are equal.
  • the second current source module includes: an eighth transistor; a gate of the eighth transistor is coupled to an output end of the second clamping module, and a first pole of the eighth transistor The third feedback node is coupled, and the second pole of the eighth transistor is grounded.
  • circuits for generating the current supplied by the first current source and the current supplied by the second current source are composed of P-type transistors or both are N-type transistors, the matching characteristics of the charging current and the discharging current will be Better, it can further improve the stability of the charge pump output voltage.
  • the embodiment of the present application provides a control method of a charge pump circuit for suppressing current mismatch, the method for controlling a charge pump circuit according to any one of the first aspects, the charge pump circuit comprising: a first control circuit, a second control circuit, and a first feedback circuit, the method comprising: applying a first control signal at an active potential to the first control node, and applying a second control signal at an active potential to the second control node Causing the first control circuit to input a first current from the first current input node to the second feedback node under control of the first control signal and the second control signal; applying to the third control node a third control signal of an effective potential, and applying a fourth control signal at an effective potential to the fourth control node, such that the second control circuit, under the control of the third control signal and the fourth control signal, a second current input and output node from the second current input node, and causing the first feedback circuit to be under the control of the first feedback node and the filter node Equal to the current value of the second
  • the charge pump circuit includes a first control circuit, a second control circuit and a first feedback circuit, wherein the first feedback circuit can control the input second feedback node
  • the value of the current is equal to the value of the first current, so that the value of the charging current and the value of the discharging current are equal, and the current mismatch of the charging current and the discharging current can be suppressed, and the stability of the output voltage of the charge pump is ensured compared with the related art.
  • the charge pump circuit further includes: a third control circuit and a second feedback circuit, the method further comprising: applying a first control signal at an effective potential to the first control node, further causing the The third control circuit inputs the second current into the third feedback node, so that the second feedback circuit controls the potential of the third feedback node under the control of the third feedback node and the filter node;
  • the third control node applies a third control signal at an effective potential, and further causes the third control circuit to input the first current into the third feedback node, such that the second feedback circuit is in the third feedback
  • the potential of the third feedback node is controlled under the control of the node and the filter node.
  • the setting of the third control circuit and the second feedback circuit is such that the charge pump circuit provided by the embodiment of the present application is in the third control signal and whether the potentials of the first control signal and the second control signal are both active potentials
  • the potential of the fourth control signal is an effective potential, no charge sharing occurs between the second current input node and the output node, and between the second feedback node and the output node, and the stability of the output voltage can be ensured.
  • the matching characteristics of the first current and the second current are better, and the current mismatch of the charging current and the discharging current can be better suppressed, further Improve the stability of the charge pump output voltage.
  • an embodiment of the present application provides a phase locked loop circuit, where the phase locked loop circuit includes: a phase discriminating frequency discriminator, a loop filter, a voltage controlled oscillator, a frequency divider, and the first aspect.
  • a charge pump circuit configured to output a first phase error signal and a second phase error signal according to the input clock signal; the charge pump circuit is configured to be based on the first phase error signal And the second phase error signal outputting a current to the loop filter; the loop filter for generating a control voltage signal according to a current output by the charge pump; the voltage controlled oscillator for using the control The voltage signal outputs a target clock signal; the frequency divider is configured to divide the target clock signal, and input the divided target clock signal to the phase discriminator.
  • an embodiment of the present application provides a phase-locked loop circuit, where the phase-locked loop circuit includes: a sampling phase detector, a pulse generator, a loop filter, a voltage controlled oscillator, and the first aspect.
  • a charge pump circuit configured to output a first sampling signal and a second sampling signal according to an input clock signal
  • the pulse generator is configured to generate a pulse signal, wherein the pulse signal is used to control a The time at which the charge pump outputs a current
  • the charge pump circuit is configured to output the current to the loop filter according to the pulse signal, the first sampling signal, and the second sampling signal; And generating a control voltage signal according to the current output by the charge pump
  • the voltage controlled oscillator is configured to output a target clock signal according to the control voltage signal, and input the target clock signal to the sampling type phase detector.
  • the embodiment of the present application provides a storage medium, where the computer program is stored in the storage medium, and the computer program is executed by the processor to implement a charge pump circuit for suppressing current mismatch provided by the embodiment of the present application. Control method.
  • an embodiment of the present application provides a chip, where the chip includes a programmable logic circuit and/or a program instruction, and is used to implement a charge inhibiting current mismatch provided by an embodiment of the present application.
  • the control method of the pump circuit is not limited to a programmable logic circuit and/or a program instruction.
  • the charge pump circuit for suppressing current mismatch and the control method thereof and the phase locked loop circuit provided by the embodiment of the present application, includes a first control circuit, a second control circuit and a first feedback circuit, wherein the first feedback circuit can The value of the current input to the second feedback node is controlled to be equal to the value of the first current, so that the value of the charging current and the value of the discharging current are equal, and the current mismatch of the charging current and the discharging current can be suppressed, and the electric charge is ensured compared with the related art.
  • the stability of the pump output voltage can be controlled to be equal to the value of the first current, so that the value of the charging current and the value of the discharging current are equal, and the current mismatch of the charging current and the discharging current can be suppressed, and the electric charge is ensured compared with the related art.
  • FIG. 1 is a schematic structural diagram of a charge pump circuit according to an exemplary embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of another charge pump circuit according to an exemplary embodiment of the present application.
  • FIG. 3 is a circuit schematic diagram of a charge pump circuit provided by an exemplary embodiment of the present application.
  • FIG. 4 is a circuit schematic diagram of another charge pump circuit provided by an exemplary embodiment of the present application.
  • FIG. 5 is a flowchart of a method for controlling a charge pump circuit according to an exemplary embodiment of the present application
  • FIG. 6 is a schematic structural diagram of a phase locked loop circuit according to an exemplary embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of another phase-locked loop circuit provided by an exemplary embodiment of the present application.
  • the transistors used in all embodiments of the present application may be thin film transistors or field effect transistors or other devices having the same characteristics, and the transistors employed in the embodiments of the present application are mainly switching transistors according to their roles in the circuit. Since the source and drain of the switching transistor used here are symmetrical, the source and the drain are interchangeable. In the embodiment of the present application, the source is referred to as a first stage, and the drain is referred to as a second stage. According to the form in the drawing, the middle end of the transistor is the gate, the signal input end is the source, and the signal output end is the drain.
  • the switching transistor used in the embodiment of the present application may include a P-type switching transistor and an N-type switching transistor, wherein the P-type switching transistor is turned on when the gate is at a low potential, and is turned off when the gate is at a high potential, and the N-type switching transistor is Turns on when the gate is high, and turns off when the gate is low.
  • the multiple signals in the various embodiments of the present application correspond to a high potential and a low potential, and the effective potential of the signal is a potential for turning on the switching transistor.
  • the low potential is an effective potential
  • the N-type The switching transistor has a high potential as an effective potential.
  • the embodiment of the present application proposes a charge pump circuit for suppressing current mismatch.
  • the charge pump circuit may include: a first control circuit 10, a second control circuit 20, and a first feedback circuit 30.
  • the first control circuit 10 is coupled to the first current input node D1, the first control node K1, the second control node K2, the first feedback node E1 and the second feedback node E2, respectively.
  • the potential of the first control signal from the first control node K1 is an effective potential
  • the potential of the second control signal from the second control node K2 is an effective potential
  • the first current input from the first current input node D1 is input.
  • the coupling in the embodiment of the present application may include an implementation manner such as a direct connection and an indirect connection, which is not specifically limited in the embodiment of the present application.
  • the first feedback circuit 30 is coupled to the first feedback node E1, the second feedback node E2, and the filter node Vx, respectively.
  • the first feedback circuit 30 is configured to control the input under the control of the first feedback node E1 and the filter node Vx.
  • the value of the current of the second feedback node E2 is equal to the value of the first current (refers to being equal within the error tolerance).
  • the controlling action of the first feedback circuit 30 on the value of the current input to the second feedback node E2 may be referred to as the clamping action of the first feedback circuit 30.
  • the second control circuit 20 is coupled to the second current input node D2, the third control node K3, the fourth control node K4, the output node Vout, and the second feedback node E2, respectively.
  • the potential of the third control signal of the three control node K3 is an effective potential
  • the potential of the fourth control signal from the fourth control node K4 is an effective potential
  • the second current input and output node Vout from the second current input node D2 And, a current equal to the value of the first current is input to the second feedback node E2.
  • the second current input to the second current input node D2 can be regarded as a charging current for charging the output node Vout
  • the first current input to the first current input node D1 can be regarded as discharging the output node Vout.
  • the discharge current, the first feedback circuit 30 controls the value of the current input to the second feedback node E2 to be equal to the value of the first current such that the value of the charging current and the value of the discharge current remain equal throughout the charge pump circuit at steady state.
  • the current mismatch of the charging current and the discharging current can be suppressed, that is, the current mismatch due to factors such as process, voltage, and temperature deviation can be overcome, and the stability of the charge pump output voltage is effectively ensured.
  • a filter resistor R1 is connected between the filter node Vx and the output node Vout, and the filter node Vx is grounded through the first capacitor C1, and the first capacitor C1 is used to stabilize the voltage of the filter node Vx.
  • the output node Vout is grounded through a second capacitor C2 for stabilizing the voltage of the output node Vout.
  • the filter resistor R1 may be a resistor in a loop filter in a phase locked loop circuit
  • the first capacitor C1 and the second capacitor C2 may filter the loop Capacitor in the device.
  • the charge pump circuit may further include: a first current source I1 and a second current source I2.
  • the first current source I1 is coupled to the first current input node D1, and the first current source I1 is configured to input the first current from the first current source I1 into the first current input node D1; the second current source I2
  • the second current source I2 is coupled to the second current input node D2 for inputting the second current from the second current source I2 to the second current input node D2.
  • the first current source I1 and the second current source I2 are also respectively connected to a power source Vdd for supplying power to the first current source I1 and the second current source I2.
  • the charge pump circuit can be applied in a phase locked loop circuit and a clock data recovery circuit, wherein the phase locked loop circuit can include: a phase discriminator for using an input clock signal according to the input Outputting a first phase error signal and a second phase error signal, the first phase error signal may be used as a first control signal; the inverted signal of the second phase error signal may be used as a second control signal; the first phase error The inverted signal of the signal can be used as the third control signal; the second phase error signal can be used as the fourth control signal. That is, the first phase error signal can be used to control a charging process that charges the charge pump output node Vout, which can be used to control the discharging process that discharges the charge pump output node Vout.
  • the phase locked loop circuit can include: a phase discriminator for using an input clock signal according to the input Outputting a first phase error signal and a second phase error signal, the first phase error signal may be used as a first control signal; the inverted signal of the second phase error signal may be used as
  • the first phase error signal and the second phase error signal are signals obtained according to a comparison result between the clock signal outputted by the voltage controlled oscillator and the reference clock signal in the phase locked loop circuit, the first phase error signal and the first The pulse width of the pulse signal of the two phase error signals is different, but the pulse amplitude of the pulse signal is the same, and the control effect of the first phase error signal and the second phase error signal on the charge pump circuit can be understood as a voltage controlled oscillator.
  • the phase difference between the output and the divided clock signal and the reference clock signal is converted into a time difference between the charging and discharging process, and the charging and discharging process is controlled by the time difference, that is, when according to the first phase error signal and
  • the second phase error signal controls the first control circuit 10 and the second control circuit 20
  • the charging time period for charging the charge pump output node Vout and the discharging time period for discharging the charge pump output node Vout can be adjusted.
  • the phase locked loop circuit may include: a sampling phase detector and a pulse generator, the first current source I1 is coupled to the first output end of the sampling phase detector, and the first sampling signal outputted by the first output end is used for Adjusting a value of the first current; the second current source I2 is coupled to the second output of the sampling phase detector, and the second sampling signal outputted by the second output is used to adjust a value of the second current; the pulse generator is configured to generate a pulse signal, which can be used as a first control signal and a fourth control signal, the inverted signal of which can be used as a second control signal and a third control signal, that is, the pulse signal is used to adjust to The charge duration of the charge pump output node Vout charging and the discharge duration of discharging the charge pump output node Vout.
  • the first sampling signal and the second sampling signal are voltage signals obtained by sampling the clock signal output by the voltage controlled oscillator according to the reference clock signal, the voltage amplitudes of the first sampling signal and the second sampling signal are different.
  • the adjustment of the first current by the first sampling signal and the adjustment of the second current by the second sampling signal can be understood as converting the phase difference between the clock signal outputted by the voltage controlled oscillator and the reference clock signal into a pair a current source and a second current source perform a controlled voltage difference, and since the voltage value exhibits a positive correlation with the adjusted current value, the voltage difference can be converted into a adjusted current difference between the first current and the second current .
  • the charge pump circuit can realize charging and discharging under the control of the first control signal, the second control signal, the third control signal and the fourth control signal. Process control.
  • first current source I1 and the second current source I2 may be implemented by the same type of device.
  • the circuit for providing the first current and the circuit for providing the second current may both be composed of P-type transistors or both of them are N-type.
  • the transistor is configured such that the matching characteristic of the first current input to the first current input node D1 and the second current input to the second current input node D2 is better, and the current mismatch of the charging current and the discharging current can be better suppressed, further Improve the stability of the charge pump output voltage.
  • the first feedback circuit 30 may include a first clamping module 301 and a first current source module 302 .
  • the first input end of the first clamping module 301 is coupled to the first feedback node E1, and the second input end of the first clamping module 301 is coupled to the filter node Vx, and the output end of the first clamping module 301
  • the first clamping module 301 is configured to stabilize the potential of the output end of the first clamping module 301 under the control of the first feedback node E1 and the filtering node Vx.
  • the input end of the first current source module 302 is coupled to the second feedback node E2.
  • the output end of the first current source module 302 is grounded.
  • the first current source module 302 is used at the control end of the first current source module 302. Under control, the value of the current input to the second feedback node E2 is controlled to be equal to the value of the first current.
  • the function of the first current source module 302 is equivalent to generating a current source similar to the first current source I1 at the second feedback node E2 under the control of its control terminal. Therefore, it is named as the first current. Source module.
  • the first clamping module 301 can include: a first operational amplifier OP1.
  • the non-inverting input terminal of the first operational amplifier OP1 is coupled to the first feedback node E1, and the inverting input terminal of the first operational amplifier OP1 is coupled to the filter node Vx, and the output terminal of the first operational amplifier OP1 is connected to the first current
  • the control terminals of source module 302 are coupled.
  • the voltages of the first feedback node E1 and the filter node Vx are equal, and the value of the current input to the second feedback node E2 is equal to the value of the first current, that is, A suppression function for the current mismatch of the charging current and the discharging current.
  • the principle of “virtual short” of an operational amplifier means that under ideal conditions, the potentials of the two inputs of the non-inverting input and the inverting input of the operational amplifier are equal; the principle of “virtual-off” of the operational amplifier refers to the ideal situation.
  • the current flowing into the two inputs of the op amp is zero.
  • the first current source module 302 can be implemented in various manners. The embodiment of the present application is described by taking a transistor implementation as an example. Referring to FIG. 3, the first current source module 302 may include: The first transistor M1. The gate of the first transistor M1 is coupled to the output of the first clamping module 301. The first pole of the first transistor M1 is coupled to the second feedback node E2, and the second pole of the first transistor M1 is grounded. Alternatively, the first transistor M1 may be an N-type transistor.
  • the first control circuit 10 can include a first control module 101 and a second control module 102.
  • the first control module 101 is coupled to the first control node K1, the first current input node D1, and the first feedback node E1, and the first control module 101 is configured to: when the potential of the first control signal is an effective potential, The first current is input to the first feedback node E1.
  • the second control module 102 is coupled to the second control node K2, the first feedback node E1, and the second feedback node E2, respectively.
  • the second control module 102 is configured to: when the potential of the second control signal is an effective potential, The signal of the first feedback node E1 (that is, the first current) is input to the second feedback node E2.
  • the first control module 101 may include: a second transistor M2 having a gate coupled to the first control node K1, and a first pole of the second transistor M2 The first current input node D1 is coupled, and the second pole of the second transistor M2 is coupled to the first feedback node E1.
  • the second control module 102 can include a third transistor M3 having a gate coupled to a second control node K2, a first pole of the third transistor M3 and a first feedback.
  • the node E1 is coupled, and the second pole of the third transistor M3 is coupled to the second feedback node E2.
  • the second transistor M2 may be a P-type transistor
  • the third transistor M3 may be an N-type transistor.
  • the first transistor M1 and the third transistor are turned on.
  • the voltage of the first current input node D1, the voltage of the second feedback node E2, and the voltage of the first feedback node E1 can be kept relatively equal.
  • the second control circuit 20 may include a third control module 201 and a fourth control module 202.
  • the third control module 201 is coupled to the third control node K3, the second current input node D2, and the output node Vout, and the third control module 201 is configured to: when the potential of the third control signal is an effective potential, the second Current input and output node Vout.
  • the fourth control module 202 is coupled to the fourth control node K4, the output node Vout, and the second feedback node E2, respectively.
  • the fourth control module 202 is configured to receive the output node when the potential of the fourth control signal is an effective potential.
  • the signal of Vout ie, the second current
  • the signal of Vout is input to the second feedback node E2.
  • the third control module 201 may include: a fourth transistor M4, the gate of the fourth transistor M4 is coupled to the third control node K3, and the first pole of the fourth transistor M4 is The second current input node D2 is coupled, and the second pole of the fourth transistor M4 is coupled to the output node Vout.
  • the fourth control module 202 can include a fifth transistor M5 having a gate coupled to a fourth control node K4, a first pole and an output node Vout of the fifth transistor M5. Phase coupled, the second pole of the fifth transistor M5 is coupled to the second feedback node E2.
  • the fourth transistor M4 may be a P-type transistor
  • the fifth transistor M5 may be an N-type transistor.
  • the voltage of the second current input node D2 the voltage of the two feedback nodes E2 and the voltage of the output node Vout can be kept relatively equal, that is, neither between the second current input node D2 and the output node Vout, between the second feedback node E2 and the output node Vout Charge sharing occurs, which reduces the probability of glitch on the output voltage of the output of the charge pump connected to the output node Vout, thereby ensuring the stability of the output voltage.
  • the charge pump circuit may further include: a third control circuit 40 and a second feedback circuit 50.
  • the third control circuit 40 is coupled to the first current input node D1, the second current input node D2, the first control node K1, the third control node K3, and the third feedback node E3, respectively.
  • the potential of the first control signal is an effective potential
  • the second current is input to the third feedback node E3, or when the potential of the third control signal is the effective potential, the first current is input to the third feedback node E3.
  • the second feedback circuit 50 is coupled to the third feedback node E3 and the filter node Vx, respectively.
  • the second feedback circuit 50 is configured to control the potential of the third feedback node E3 under the control of the third feedback node E3 and the filter node Vx. .
  • the third control circuit 40 and the second feedback circuit 50 form a feedback loop between the second current input node D2 and the filter node Vx such that the second current input node D2
  • the voltage, the voltage of the third feedback node E3 and the voltage of the filter node Vx can be kept equal, and at the same time, since there is no voltage drop across the filter resistor R1 when the entire charge pump circuit is in a steady state, the voltage of the filter node Vx is equal to the output node Vout.
  • the voltage is such that the voltages of the output node Vout, the second current input node D2, and the second feedback node E2 are equal, that is, between the second current input node D2 and the output node Vout, the second feedback node E2, and the output node Vout No charge sharing occurs between them, which reduces the probability of glitch at the output voltage of the output of the charge pump connected to the output node Vout, thereby ensuring the stability of the output voltage.
  • the third control circuit 40 and the second feedback circuit 50 constitute a feedback loop between the first current input node D1 and the filter node Vx, such that the first current input node D1
  • the voltage, the voltage of the third feedback node E3 and the voltage of the filter node Vx can be kept equal.
  • the voltage of the second current input node D2, the voltage of the second feedback node E2, and the voltage of the output node Vout can be kept relatively equal, so that the second current No charge sharing occurs between the input node D2 and the output node Vout, between the second feedback node E2 and the output node Vout, which reduces the probability of glitch at the output voltage of the output of the charge pump connected to the output node Vout, and further The stability of the output voltage is guaranteed.
  • the charge pump circuit provided by the embodiment of the present application is effective when the potentials of the first control signal and the second control signal are both active potentials and the potentials of the third control signal and the fourth control signal are valid. At the potential, no charge sharing occurs between the second current input node D2 and the output node Vout, between the second feedback node E2 and the output node Vout, and the stability of the output voltage can be ensured.
  • the third control circuit 40 may include a sixth transistor M6 and a seventh transistor M7.
  • the gate of the sixth transistor M6 is coupled to the first control node K1, the first pole of the sixth transistor M6 is coupled to the second current input node D2, and the second pole and the third feedback node of the sixth transistor M6 E3 is coupled.
  • the gate of the seventh transistor M7 is coupled to the third control node K3, the first pole of the seventh transistor M7 is coupled to the first current input node D1, and the second pole and the third feedback node of the seventh transistor M7 E3 is coupled.
  • the second feedback circuit 50 may include a second clamping module 501 and a second current source module 502.
  • the first input end of the second clamping module 501 is coupled to the third feedback node E3, the second input end of the second clamping module 501 is coupled to the filter node Vx, and the output end of the second clamping module 501
  • the second clamping module 501 is configured to stabilize the potential of the output of the second clamping module 501 under the control of the third feedback node E3 and the filtering node Vx.
  • the input end of the second current source module 502 is coupled to the third feedback node E3, the output end of the second current source module 502 is grounded, and the second current source module 502 is used at the control end of the second current source module 502. Under control, the potential of the third feedback node E3 is controlled. At this time, the function of the second current source module 502 is equivalent to generating a current source at the third feedback node E3 under the control of its control terminal. Therefore, it is named as the second current source module.
  • the second clamping module 501 can include a second operational amplifier OP2.
  • the non-inverting input of the second operational amplifier OP2 is coupled to the third feedback node E3, the inverting input of the second operational amplifier OP2 is coupled to the filter node Vx, and the output of the second operational amplifier OP2 is coupled to the second current source module.
  • the control terminals of 502 are coupled. According to the principle of the "virtual short-break" of the second operational amplifier OP2, the voltages of the third feedback node E3 and the filter node Vx are equal, which provides a basis for ensuring that the voltage of the second current input node D2 and the voltage of the output node Vout are equal.
  • the second current source module 502 can be implemented in various embodiments.
  • the embodiment of the present application is described by taking a transistor implementation as an example.
  • the second current source module 502 may include: An eighth transistor M8 having a gate coupled to an output of the second clamping module 501, a first pole of the eighth transistor M8 coupled to a third feedback node E3, the eighth transistor M8 The two poles are grounded.
  • the eighth transistor M8 may be an N-type transistor.
  • the circuits for generating the current provided by the first current source I1 and generating the current provided by the second current source I2 are composed of the same type of devices, for example, they are all composed of P-type transistors or both are N.
  • the transistor is composed, the matching characteristics of the charging current and the discharging current are better, and the stability of the charge pump output voltage can be further improved.
  • the charge pump circuit for suppressing current mismatch includes a first control circuit, a second control circuit, and a first feedback circuit, and the first feedback circuit can control the current input to the second feedback node.
  • the value of the first current is equal to the value of the first current, so that the value of the charging current and the value of the discharging current are equal, and the current mismatch of the charging current and the discharging current can be suppressed, and the stability of the charge pump output voltage is ensured compared to the related art.
  • the matching characteristics of the first current and the second current are better, and the current mismatch of the charging current and the discharging current can be better suppressed, further Improve the stability of the charge pump output voltage.
  • the embodiment of the present application provides a control method for a charge pump circuit for suppressing current mismatch.
  • the method is used to control a charge pump circuit provided by an embodiment of the present application.
  • the charge pump circuit includes: a first control circuit 10 and a second control.
  • Step 801 applying a first control signal at an effective potential to the first control node, and applying a second control signal at an effective potential to the second control node, so that the first control circuit is at the first control signal and the second control signal Controlling, inputting a first current from the first current input node to the second feedback node; and causing the third control circuit to input the second current into the third feedback node, such that the second feedback circuit is at the third feedback node and the filter node Under the control, the potential of the third feedback node is controlled.
  • Step 802 applying a third control signal at an effective potential to the third control node, and applying a fourth control signal at an effective potential to the fourth control node, so that the second control circuit is at the third control signal and the fourth control signal.
  • Controlling inputting a second current from the second current input node to the output node, and causing the first feedback circuit to control the value of the current input to the second feedback node and the first under the control of the first feedback node and the filter node
  • the values of the currents are equal, and the third control circuit inputs the first current to the third feedback node such that the second feedback circuit controls the potential of the third feedback node under the control of the third feedback node and the filter node.
  • the charge pump circuit shown in FIG. 4, the second transistor M2, the fourth transistor M4, the sixth transistor M6, and the seventh transistor M7 are P-type transistors, and the third transistor M3 and the fifth transistor M5 may be N.
  • the transistor is taken as an example to explain its working principle in detail:
  • step 801 when the first control signal is an effective potential, and the second control signal is an effective potential, the second transistor M2 is turned on by the first control signal, and the first current source I1 passes through the second transistor M2.
  • the third transistor M3 Inputting a first power signal to the first feedback node E1
  • the third transistor M3 is turned on by the second control signal, and the first feedback node E1 inputs the first power signal to the second feedback node E2 through the third transistor M3, and
  • the voltages of the first feedback node E1 and the filter node Vx are equal, such that the value of the current input to the second feedback node E2 is equal to the value of the first current.
  • the value of the charging current and the value of the discharging current are equal, and the suppression of the current mismatch of the charging current and the discharging current is achieved.
  • the voltage of the first current input node D1 and the voltage of the second feedback node E2 are both equal to the voltage of the first feedback node E1.
  • the voltages of the first feedback node E1 and the filter node Vx are equal.
  • the sixth transistor M6 is turned on by the first control signal, and the second power input node inputs the second power signal to the third feedback node E3 through the sixth transistor M6, and the voltage of the second power input node is equal to the third Feedback the voltage of node E3.
  • the voltages of the third feedback node E3 and the filter node Vx are equal.
  • the voltage of the filter node Vx is equal to the voltage of the output node Vout when the entire charge pump circuit is in a steady state, it can be seen that the voltages of the output node Vout, the second current input node D2, and the second feedback node E2 are equal, that is, No charge sharing occurs between the second current input node D2 and the output node Vout, between the second feedback node E2 and the output node Vout, which reduces the occurrence of glitch on the output voltage of the output of the charge pump connected to the output node Vout.
  • the probability of ensuring the stability of the output voltage is
  • step 802 when the third control signal is an effective potential, and the fourth control signal is an effective potential, the fourth transistor M4 is turned on by the third control signal, and the second current source I2 is passed through the fourth transistor M4.
  • the second power signal input and output node Vout, the fifth transistor M5 is turned on by the fourth control signal, and the output node Vout inputs the second power signal to the second feedback node E2 through the fifth transistor M5.
  • the clamping action of an operational amplifier OP1 the output voltage of the first operational controller remains as the output voltage value in step 801, and the value of the current input to the second feedback node E2 is still equal to the value of the first current, such that The suppression of the current mismatch of the charging current and the discharging current is achieved.
  • the matching characteristics of the first current and the second current are better, and under the action of the third control circuit 40 and the second feedback circuit 50, The voltage of the first current input node D1 and the voltage of the second current input node D2 are equal, which can better suppress the current mismatch of the charging current and the discharging current, and further improve the stability of the charge pump output voltage.
  • the voltage of the second current input node D2 and the voltage of the second feedback node E2 are both equal to the voltage of the output node Vout.
  • the voltages of the first feedback node E1 and the filter node Vx are equal.
  • the seventh transistor M7 is turned on by the third control signal, and the first power input node inputs the first power signal to the third feedback node E3 through the seventh transistor M7, and the voltage of the first power input node is equal to the third Feedback the voltage of node E3.
  • the voltages of the third feedback node E3 and the filter node Vx are equal.
  • the voltage of the filter node Vx is equal to the voltage of the output node Vout when the entire charge pump circuit is in a steady state, it can be seen that the voltages of the output node Vout, the second current input node D2, and the second feedback node E2 are equal, that is, No charge sharing occurs between the second current input node D2 and the output node Vout, between the second feedback node E2 and the output node Vout.
  • the potentials of the third control signal and the fourth control signal are both at the potential of the first control signal and the second control signal, and at the potential of the third control signal and the fourth control signal.
  • both are active potentials, no charge sharing occurs between the second current input node D2 and the output node Vout, between the second feedback node E2 and the output node Vout, and the stability of the output voltage can be ensured.
  • control method of the charge pump circuit for suppressing current mismatch includes a first control circuit, a second control circuit, and a first feedback circuit, wherein the first feedback circuit can control
  • the value of the current input to the second feedback node is equal to the value of the first current, so that the value of the charging current and the value of the discharging current are equal, and the current mismatch of the charging current and the discharging current can be suppressed, and the charge pump is ensured compared to the related art.
  • the stability of the output voltage is provided by the embodiment of the present application.
  • the matching characteristics of the first current and the second current are better, and the current mismatch of the charging current and the discharging current can be better suppressed, further Improve the stability of the charge pump output voltage.
  • the embodiment of the present application further provides a phase-locked loop circuit, and the phase-locked loop circuit includes any one of the charge pump circuits provided by the embodiments of the present application.
  • the phase locked loop circuit can be used to generate a clock signal.
  • FIG. 6 is a schematic diagram of a Phase Locked Loop (PLL) circuit according to an embodiment of the present application.
  • the phase locked loop includes: a phase detector (Phase/Frequency Detector), and a charge.
  • a charge pump a charge pump, a loop filter, a voltage controlled oscillator (VCO), and a frequency divider (Divider), wherein the charge pump includes the current suppression provided by the embodiment of the present application. Equipped with a charge pump circuit.
  • the phase discriminator can compare the frequency-divided clock signal with the input reference clock signal Ref and output Comparing the phase error signal
  • the phase error signal includes: a first phase error signal up and a second phase error signal dn
  • the charge pump is configured to perform a loop according to the first phase error signal up and the second phase error signal dn a filter output current
  • the loop filter is configured to generate a control voltage signal according to the current output by the charge pump, and under the control of the control voltage signal, the frequency of the clock signal output by the voltage controlled oscillator can be adjusted to the frequency of the reference clock signal N times.
  • phase-locked loop includes: a sampling phase detector (Sampling PD), a charge pump, and a pulse generator (Pulser). ), loop filter and voltage controlled oscillator.
  • the pulse signal generated by the pulse generator is used to control the time of the charge pump output current, and the charge pump includes the charge pump circuit for suppressing current mismatch provided by the embodiment of the present application.
  • the pulse generator is configured to generate two pulse signals (pulse signal P1 and pulse signal P2) which are mutually inverted signals, and the pulse signal is used to adjust the charging duration for charging the charge pump output node Vout and The length of discharge that is discharged for the charge pump output node Vout, that is, the pulse signal is used to control the time at which the charge pump outputs current.
  • the clock signal outputted by the voltage controlled oscillator can be sampled according to the input reference clock signal Ref, and after sampling, the first sampling signal SP1 and the second sampling signal SP2 are output, and the charge pump is used for And outputting a current to the loop filter according to the pulse signal, the first sampling signal SP1 and the second sampling signal SP2, wherein the loop filter is configured to generate a control voltage signal according to the current output by the charge pump, and under the action of the control voltage signal, press
  • the frequency of the clock signal that the controlled oscillator can output can be adjusted to N times the frequency of the reference clock signal.
  • the embodiment of the present application further provides a storage medium in which a computer program is stored, and when the computer program is executed by the processor, the control method of the charge pump circuit for suppressing current mismatch provided by the embodiment of the present application is implemented.
  • the embodiment of the present application provides a chip, which includes a programmable logic circuit and/or program instructions, and is used to implement a control method of a charge pump circuit for suppressing current mismatch as provided by the embodiment of the present application.
  • a person skilled in the art may understand that all or part of the steps of implementing the above embodiments may be completed by hardware, or may be instructed by a program to execute related hardware, and the program may be stored in a computer readable storage medium.
  • the storage medium mentioned may be a read only memory, a magnetic disk or an optical disk or the like.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

一种抑制电流失配的电荷泵电路及其控制方法、锁相环电路，涉及通信技术领域，包括：第一控制电路（10）、第二控制电路（20）和第一反馈电路（30）；第一控制电路用于将来自第一电流输入节点（D1）的第一电流输入第二反馈节点（E2）；第一反馈电路用于在第一反馈节点（E1）和滤波节点（Vx）的控制下，控制输入第二反馈节点的电流的值与第一电流的值相等；第二控制电路用于在来自第三控制节点（K3）的第三控制信号的电位为有效电位，且来自第四控制节点（K4）的第四控制信号的电位为有效电位时，将来自第二电流输入节点（D2）的第二电流输入输出节点（V out），以及，将与第一电流的值相等的电流输入第二反馈节点。该电荷泵电路能够抑制充电电流和放电电流的电流失配，保证了电荷泵输出电压的稳定性。

Description

抑制电流失配的电荷泵电路及其控制方法、锁相环电路 技术领域
本申请涉及通信技术领域，特别涉及一种抑制电流失配的电荷泵电路及其控制方法、锁相环电路。
背景技术
锁相环一般包括鉴相鉴频器(Phase/Frequency Detector，PFD)、电荷泵(Charge Pump，CP)、环路滤波器(Loop Filter，LPF)、压控振荡器(Voltage ControlledOscillator，VCO)和分频器(Divider)。其中，电荷泵是锁相环的重要组成部分，其能将鉴相鉴频器输出的信号通过环路滤波器转化为电压信号，并通过该电压信号控制压控振荡器的振荡频率。
相关技术中，电荷泵电路一般包括由相同偏置电流镜像电路产生的两个大小相同的电流Iup和电流Idn、耦合在该电流Iup的输入节点和电流Idn的输入节点之间的两条电路支路，以及跨接在该两条电路支路之间由运算放大器组成的反馈回路，该反馈回路用于在电流Iup和电流Idn大小相等时，保证电荷泵输出电压的稳定性。
但是，实际实现时，由于工艺、电压和温度偏差等因素，电流Iup和电流Idn可能不相等，导致两者电流失配，影响电荷泵输出电压的稳定性。
发明内容
本申请提供了一种抑制电流失配的电荷泵电路及其控制方法、锁相环电路，可以提高电荷泵输出电压的稳定性。所述技术方案如下：
第一方面，本申请实施例提供了一种抑制电流失配的电荷泵电路，包括：第一控制电路、第二控制电路和第一反馈电路；所述第一控制电路分别与第一电流输入节点、第一控制节点、第二控制节点、第一反馈节点和第二反馈节点相耦合，所述第一控制电路用于在来自所述第一控制节点的第一控制信号的电位为有效电位，且来自所述第二控制节点的第二控制信号的电位为有效电位时，将来自所述第一电流输入节点的第一电流输入所述第二反馈节点；所述第一反馈电路分别与所述第一反馈节点、所述第二反馈节点和滤波节点相耦合，所述第一反馈电路用于在所述第一反馈节点和所述滤波节点的控制下，控制输入所述第二反馈节点的电流的值与所述第一电流的值相等；所述第二控制电路分别与第二电流输入节点、第三控制节点、第四控制节点、输出节点和所述第二反馈节点相耦合，所述第二控制电路用于在来自所述第三控制节点的第三控制信号的电位为有效电位，且来自所述第四控制节点的第四控制信号的电位为有效电位时，将来自所述第二电流输入节点的第二电流输入所述输出节点，以及，将与所述第一电流的值相等的电流输入所述第二反馈节点。
本申请实施例提供的抑制电流失配的电荷泵电路，包括第一控制电路、第二控制电路和第一反馈电路，该第一反馈电路能够控制输入第二反馈节点的电流的值等于第一电流的值，使得充电电流的值和放电电流的值相等，能够抑制充电电流和放电电流的电流失配，相较于相关技术，保证了电荷泵输出电压的稳定性。
进一步地，所述电荷泵电路还包括：第三控制电路和第二反馈电路；所述第三控制电路分别与所述第一电流输入节点、所述第二电流输入节点、所述第一控制节点、所述第三控制节点和第三反馈节点相耦合，所述第三控制电路用于在所述第一控制信号的电位为有效电位时，将所述第二电流输入所述第三反馈节点，或者，在所述第三控制信号的电位为有效电位时，将所述第一电流输入所述第三反馈节点；所述第二反馈电路分别与所述第三反馈节点和所述滤波节点相耦合，所述第二反馈电路用于在所述第三反馈节点和所述滤波节点的控制下，控制所述第三反馈节点的电位。
该第三控制电路和第二反馈电路的设置，使得本申请实施例提供的电荷泵电路，无论是在第一控制信号和第二控制信号的电位均为有效电位时，还是在第三控制信号和第四控制信号的电位均为有效电位时，第二电流输入节点和输出节点之间、第二反馈节点和输出节点之间均不会出现电荷分享，均能够保证输出电压的稳定性。
并且，所述电荷泵电路还包括：所述电荷泵电路还包括：第一电流源和第二电流源；所述第一电流源与所述第一电流输入节点相耦合，所述第一电流源用于将所述第一电流输入所述第一电流输入节点；所述第二电流源与所述第二电流输入节点相耦合，所述第二电流源用于将所述第二电流输入所述第二电流输入节点。
进一步地，该第一电流源和该第二电流源可以采用同类型器件实现，例如：提供第一电流的电路和提供第二电流的电路可以均由P型晶体管组成或均由N型晶体管组成，使得输入第一电流输入节点的第一电流和输入第二电流输入节点的第二电流的匹配特性会更好，可以更好地抑制充电电流和放电电流的电流失配，进一步地提高电荷泵输出电压的稳定性。
可选地，所述电荷泵电路应用在锁相环电路中，所述锁相环电路包括：鉴相鉴频器，所述鉴相鉴频器用于根据输入的时钟信号输出第一相位误差信号和第二相位误差信号；所述第一相位误差信号用作所述第一控制信号；所述第二相位误差信号的反相信号用作所述第二控制信号；所述第一相位误差信号的反相信号用作所述第三控制信号；所述第二相位误差信号用作所述第四控制信号。
此时，由于第一相位误差信号和第二相位误差信号是根据锁相环电路中压控振荡器输出的时钟信号与参考时钟信号的比较结果得到的信号，该第一相位误差信号和该第二相位误差信号的脉冲信号的脉冲宽度不同，但脉冲信号的脉冲幅值相同，该第一相位误差信号和该第二相位误差信号对电荷泵电路的控制作用，可以理解为将压控振荡器输出的且经分频后的时钟信号与参考时钟信号的相位差转换为充放电过程的时间差，并通过该时间差实现对充放电过程的控制，也即是，当根据该第一相位误差信号和该第二相位误差信号控制第一控制电路和第二控制电路时，能够调节为电荷泵输出节点充电的充电时长和为电荷泵输出节点放电的放电时长。
可选地，所述电荷泵电路应用在锁相环电路中，所述锁相环电路包括：采样鉴相器；所述第一电流源与所述采样鉴相器的第一输出端相耦合，所述第一输出端输出的第一采样信号用于调节所述第一电流的值；所述第二电流源与所述采样鉴相器的第二输出端相耦合，所述第二输出端输出的第二采样信号用于调节所述第二电流的值。
并且，所述锁相环电路还包括：脉冲发生器，所述脉冲发生器用于生成脉冲信号；所述脉冲信号用作所述第一控制信号和所述第四控制信号；所述脉冲信号的反相信号用作所 述第二控制信号和所述第三控制信号。
此时，由于第一采样信号和第二采样信号是根据参考时钟信号对压控振荡器输出的时钟信号进行采样后得到的电压信号，该第一采样信号和第二采样信号的电压幅值不同。通过第一采样信号对第一电流进行调节和通过第二采样信号对第二电流进行调节的调节作用，可理解为将压控振荡器输出的时钟信号与参考时钟信号的相位差转换成对第一电流源和第二电流源进行控制的电压差，且由于电压值与调节后的电流值表现为正相关的关系，该电压差可转换为调节后的第一电流和第二电流的电流差。将该调节后的第一电流和第二电流输入电荷泵电路后，电荷泵电路在第一控制信号、第二控制信号、第三控制信号和第四控制信号的控制下，可实现对充放电过程的控制。
并且，通过第一采样信号和第二采样信号对第一电流和第二电流进行调节，可实现对第一电流和第二电流的单独控制，相对于相关技术，提高了电荷泵电路的适用范围和电荷泵电路使用的灵活性。
其中，所述第一反馈电路包括：第一钳位模块和第一电流源模块；所述第一钳位模块的第一输入端与所述第一反馈节点相耦合，所述第一钳位模块的第二输入端与所述滤波节点相耦合，所述第一钳位模块的输出端与所述第一电流源模块的控制端相耦合，所述第一钳位模块用于在所述第一反馈节点和所述滤波节点的控制下，稳定所述第一钳位模块的输出端的电位；所述第一电流源模块的输入端与所述第二反馈节点相耦合，所述第一电流源模块的输出端接地，所述第一电流源模块用于在所述第一电流源模块的控制端的控制下，控制输入所述第二反馈节点的电流的值与所述第一电流的值相等。
可选地，所述第一钳位模块包括：第一运算放大器；所述第一运算放大器的同相输入端与所述第一反馈节点相耦合，所述第一运算放大器的反相输入端与所述滤波节点相耦合，所述第一运算放大器的输出端与所述第一电流源模块的控制端相耦合。
根据该第一运算放大器“虚短虚断”的原理，第一反馈节点和滤波节点的电压相等，且输入至第二反馈节点的电流的值等于第一电流的值，即实现了对充电电流和放电电流的电流失配的抑制功能。
可选地，所述第一电流源模块包括：第一晶体管；所述第一晶体管的栅极与所述第一钳位模块的输出端相耦合，所述第一晶体管的第一极与所述第二反馈节点相耦合，所述第一晶体管的第二极接地。
可选地，所述第一控制电路包括：第二晶体管和第三晶体管；所述第二晶体管的栅极与所述第一控制节点相耦合，所述第二晶体管的第一极与所述第一电流输入节点相耦合，所述第二晶体管的第二极与所述第一反馈节点相耦合；所述第三晶体管的栅极与所述第二控制节点相耦合，所述第三晶体管的第一极与所述第一反馈节点相耦合，所述第三晶体管的第二极与所述第二反馈节点相耦合。
需要说明的是，第二晶体管可以为P型晶体管，第三晶体管可以为N型晶体管，此时，在第二晶体管和第三晶体管开启时，在该第一晶体管和第三晶体管的共同作用下，第一电流输入节点的电压、第二反馈节点的电压和第一反馈节点的电压可较准确地保持为相等。
可选地，所述第二控制电路包括：第四晶体管和第五晶体管；所述第四晶体管的栅极与所述第三控制节点相耦合，所述第四晶体管的第一极与所述第二电流输入节点相耦合，所述第四晶体管的第二极与所述输出节点相耦合；所述第五晶体管的栅极与所述第四控制 节点相耦合，所述第五晶体管的第一极与所述输出节点相耦合，所述第五晶体管的第二极与所述第二反馈节点相耦合。
需要说明的是，第四晶体管可以为P型晶体管，第五晶体管可以为N型晶体管，此时，在第四晶体管和第五晶体管开启时，第二电流输入节点的电压、第二反馈节点的电压和输出节点的电压可较准确地保持为相等，也即是，第二电流输入节点和输出节点之间、第二反馈节点和输出节点之间均不会出现电荷分享，这样降低了与输出节点相耦合的电荷泵的输出端的输出电压出现毛刺的几率，进而保证了输出电压的稳定性。
可选地，所述第三控制电路包括：第六晶体管和第七晶体管；所述第六晶体管的栅极与所述第一控制节点相耦合，所述第六晶体管的第一极与所述第二电流输入节点相耦合，所述第六晶体管的第二极与所述第三反馈节点相耦合；所述第七晶体管的栅极与所述第三控制节点相耦合，所述第七晶体管的第一极与所述第一电流输入节点相耦合，所述第七晶体管的第二极与所述第三反馈节点相耦合。
其中，所述第二反馈电路包括：第二钳位模块和第二电流源模块；所述第二钳位模块的第一输入端与所述第三反馈节点相耦合，所述第二钳位模块的第二输入端与所述滤波节点相耦合，所述第二钳位模块的输出端与所述第二电流源模块的控制端相耦合，所述第二钳位模块用于在所述第三反馈节点和所述滤波节点的控制下，稳定所述第二钳位模块的输出端的电位；所述第二电流源模块的输入端与所述第三反馈节点相耦合，所述第二电流源模块的输出端接地，所述第二电流源模块用于在所述第二电流源模块的控制端的控制下，控制所述第三反馈节点的电位。
可选地，所述第二钳位模块包括：第二运算放大器；所述第二运算放大器的同相输入端与所述第三反馈节点相耦合，所述第二运算放大器的反相输入端与所述滤波节点相耦合，所述第二运算放大器的输出端与所述第二电流源模块的控制端相耦合。
根据该第二运算放大器“虚短虚断”的原理，第三反馈节点和滤波节点的电压相等，为保证第二电流输入节点的电压和输出节点的电压相等提供了依据。
可选地，所述第二电流源模块包括：第八晶体管；所述第八晶体管的栅极与所述第二钳位模块的输出端相耦合，所述第八晶体管的第一极与所述第三反馈节点相耦合，所述第八晶体管的第二极接地。
需要说明的是，当产生第一电流源所提供的电流和第二电流源所提供的电流的电路均由P型晶体管组成或均由N型晶体管组成时，充电电流和放电电流的匹配特性会更好，能够进一步提高电荷泵输出电压的稳定性。
第二方面，本申请实施例提供了一种抑制电流失配的电荷泵电路的控制方法，所述方法用于控制如第一方面任一所述的电荷泵电路，所述电荷泵电路包括：第一控制电路、第二控制电路和第一反馈电路，所述方法包括：向第一控制节点施加处于有效电位的第一控制信号，且向第二控制节点施加处于有效电位的第二控制信号，使得所述第一控制电路在所述第一控制信号和所述第二控制信号的控制下，将来自第一电流输入节点的第一电流输入第二反馈节点；向第三控制节点施加处于有效电位的第三控制信号，且向第四控制节点施加处于有效电位的第四控制信号，使得所述第二控制电路在所述第三控制信号和所述第四控制信号的控制下，将来自第二电流输入节点的第二电流输入输出节点，以及，使得所述第一反馈电路在第一反馈节点和滤波节点的控制下，控制输入所述第二反馈节点的电流 的值与所述第一电流的值相等。
本申请实施例提供的抑制电流失配的电荷泵电路的控制方法，该电荷泵电路包括第一控制电路、第二控制电路和第一反馈电路，该第一反馈电路能够控制输入第二反馈节点的电流的值等于第一电流的值，使得充电电流的值和放电电流的值相等，能够抑制充电电流和放电电流的电流失配，相较于相关技术，保证了电荷泵输出电压的稳定性。
可选地，所述电荷泵电路还包括：第三控制电路和第二反馈电路，所述方法还包括：向所述第一控制节点施加处于有效电位的第一控制信号，还使得所述第三控制电路将所述第二电流输入第三反馈节点，使得所述第二反馈电路在所述第三反馈节点和所述滤波节点的控制下，控制所述第三反馈节点的电位；向所述第三控制节点施加处于有效电位的第三控制信号，还使得所述第三控制电路将所述第一电流输入所述第三反馈节点，使得所述第二反馈电路在所述第三反馈节点和所述滤波节点的控制下，控制所述第三反馈节点的电位。
该第三控制电路和第二反馈电路的设置，使得本申请实施例提供的电荷泵电路，无论在第一控制信号和第二控制信号的电位均为有效电位时，还是在第三控制信号和第四控制信号的电位均为有效电位时，第二电流输入节点和输出节点之间、第二反馈节点和输出节点之间均不会出现电荷分享，均能够保证输出电压的稳定性。
并且，当第一电流源和第二电流源采用同类型器件实现时，第一电流和第二电流的匹配特性会更好，可以更好地抑制充电电流和放电电流的电流失配，进一步地提高电荷泵输出电压的稳定性。
第三方面，本申请实施例提供了一种锁相环电路，所述锁相环电路包括：鉴相鉴频器、环路滤波器、压控振荡器、分频器以及如第一方面任一所述的电荷泵电路；所述鉴相鉴频器用于根据输入的时钟信号，输出第一相位误差信号和第二相位误差信号；所述电荷泵电路用于根据所述第一相位误差信号和所述第二相位误差信号将所述环路滤波器输出电流；所述环路滤波器用于根据所述电荷泵输出的电流生成控制电压信号；所述压控振荡器用于根据所述控制电压信号输出目标时钟信号；所述分频器用于对所述目标时钟信号进行分频，并将分频后的目标时钟信号输入所述鉴相鉴频器。
第四方面，本申请实施例提供了一种锁相环电路，所述锁相环电路包括：采样型鉴相器、脉冲发生器、环路滤波器、压控振荡器以及如第一方面任一所述的电荷泵电路；所述采样型鉴相器用于根据输入的时钟信号输出第一采样信号和第二采样信号；所述脉冲发生器用于生成脉冲信号，所述脉冲信号用于控制所述电荷泵输出电流的时间；所述电荷泵电路用于根据所述脉冲信号、所述第一采样信号和所述第二采样信号将所述环路滤波器输出电流；所述环路滤波器用于根据所述电荷泵输出的电流生成控制电压信号；所述压控振荡器用于根据所述控制电压信号输出目标时钟信号，并将所述目标时钟信号输入所述采样型鉴相器。
第五方面，本申请实施例提供了一种存储介质，所述存储介质内存储有计算机程序，所述计算机程序被处理器执行时实现如本申请实施例提供的抑制电流失配的电荷泵电路的控制方法。
第六方面，本申请实施例提供了一种芯片，所述芯片包括可编程逻辑电路和/或程序指令，当所述芯片运行时用于实现如本申请实施例提供的抑制电流失配的电荷泵电路的控制方法。
本申请实施例提供的抑制电流失配的电荷泵电路及其控制方法、锁相环电路，该电荷泵电路包括第一控制电路、第二控制电路和第一反馈电路，该第一反馈电路能够控制输入第二反馈节点的电流的值等于第一电流的值，使得充电电流的值和放电电流的值相等，能够抑制充电电流和放电电流的电流失配，相较于相关技术，保证了电荷泵输出电压的稳定性。
附图说明
图1是本申请示例性实施例提供的一种电荷泵电路的结构示意图；
图2是本申请示例性实施例提供的另一种电荷泵电路的结构示意图；
图3是本申请示例性实施例提供的一种电荷泵电路的电路示意图；
图4是本申请示例性实施例提供的另一种电荷泵电路的电路示意图；
图5是本申请示例性实施例提供的一种电荷泵电路的控制方法的流程图；
图6是本申请示例性实施例提供的一种锁相环电路的结构示意图；
图7是本申请示例性实施例提供的另一种锁相环电路的结构示意图。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请实施方式作进一步地详细描述。
本申请所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件，根据在电路中的作用本申请的实施例所采用的晶体管主要为开关晶体管。由于这里采用的开关晶体管的源极、漏极是对称的，所以其源极、漏极是可以互换的。在本申请实施例中，将其中源极称为第一级，漏极称为第二级。按附图中的形态规定晶体管的中间端为栅极、信号输入端为源极、信号输出端为漏极。此外，本申请实施例所采用的开关晶体管可以包括P型开关晶体管和N型开关晶体管，其中，P型开关晶体管在栅极为低电位时开启，在栅极为高电位时截止，N型开关晶体管在栅极为高电位时开启，在栅极为低电位时截止。此外，本申请各个实施例中的多个信号都对应有高电位和低电位，信号的有效电位为使开关晶体管打开的电位，例如：对于P型开关晶体管，低电位为有效电位，对于N型开关晶体管，高电位为有效电位。
本申请实施例提出了一种抑制电流失配的电荷泵电路，请参考图1，该电荷泵电路可以包括：第一控制电路10、第二控制电路20和第一反馈电路30。
该第一控制电路10分别与第一电流输入节点D1、第一控制节点K1、第二控制节点K2、第一反馈节点E1和第二反馈节点E2相耦合，该第一控制电路10用于在来自第一控制节点K1的第一控制信号的电位为有效电位，且来自第二控制节点K2的第二控制信号的电位为有效电位时，将来自第一电流输入节点D1的第一电流输入第二反馈节点E2。其中，本申请实施例所说的耦合可以包括直接连接和间接连接等实现方式，本申请实施例对其不做具体限定。
该第一反馈电路30分别与第一反馈节点E1、第二反馈节点E2和滤波节点Vx相耦合，该第一反馈电路30用于在第一反馈节点E1和滤波节点Vx的控制下，控制输入第二反馈节 点E2的电流的值与第一电流的值相等(指在误差允许范围内相等)。其中，该第一反馈电路30对输入第二反馈节点E2的电流的值的控制作用可称为第一反馈电路30的钳位作用。
该第二控制电路20分别与第二电流输入节点D2、第三控制节点K3、第四控制节点K4、输出节点Vout和第二反馈节点E2相耦合，该第二控制电路20用于在来自第三控制节点K3的第三控制信号的电位为有效电位，且来自第四控制节点K4的第四控制信号的电位为有效电位时，将来自第二电流输入节点D2的第二电流输入输出节点Vout，以及，将与第一电流的值相等的电流输入第二反馈节点E2。
需要说明的是，输入该第二电流输入节点D2的第二电流可视为为输出节点Vout充电的充电电流，输入该第一电流输入节点D1的第一电流可视为为输出节点Vout放电的放电电流，该第一反馈电路30通过控制输入第二反馈节点E2的电流的值与第一电流的值相等，使得充电电流的值和放电电流的值在整个电荷泵电路处于稳态时保持相等，相对于相关技术，能够抑制充电电流和放电电流的电流失配，即能够克服由于工艺、电压和温度偏差等因素引起的电流失配，有效地保证了电荷泵输出电压的稳定性。
实际应用中，如图1所示，滤波节点Vx与输出节点Vout之间连接有滤波电阻R1，且滤波节点Vx通过第一电容器C1接地，该第一电容器C1用于稳定该滤波节点Vx的电压，输出节点Vout通过第二电容器C2接地，该第二电容器C2用于稳定该输出节点Vout的电压。示例地，当该电荷泵电路应用在锁相环电路中时，该滤波电阻R1可以为锁相环电路中环路滤波器中的电阻，第一电容器C1和第二电容器C2可以为该环路滤波器中的电容器。
请继续参考图2，该电荷泵电路还可以包括：第一电流源I1和第二电流源I2。其中，第一电流源I1与第一电流输入节点D1相耦合，该第一电流源I1用于将来自该第一电流源I1的第一电流输入第一电流输入节点D1；第二电流源I2与第二电流输入节点D2相耦合，该第二电流源I2用于将来自该第二电流源I2的第二电流输入第二电流输入节点D2。并且，该第一电流源I1和该第二电流源I2还分别与电源Vdd连接，该电源Vdd用于为第一电流源I1和第二电流源I2提供电源。
实际应用中，该电荷泵电路可应用在锁相环电路和时钟数据恢复电路中，其中，该锁相环电路可以包括：鉴相鉴频器，该鉴相鉴频器用于根据输入的时钟信号输出第一相位误差信号和第二相位误差信号，该第一相位误差信号可以用作第一控制信号；该第二相位误差信号的反相信号可以用作第二控制信号；该第一相位误差信号的反相信号可以用作第三控制信号；该第二相位误差信号可以用作第四控制信号。也即是，该第一相位误差信号可以用于控制为电荷泵输出节点Vout充电的充电过程，该第二相位误差信号可以用于控制为电荷泵输出节点Vout放电的放电过程。
此时，由于第一相位误差信号和第二相位误差信号是根据锁相环电路中压控振荡器输出的时钟信号与参考时钟信号的比较结果得到的信号，该第一相位误差信号和该第二相位误差信号的脉冲信号的脉冲宽度不同，但脉冲信号的脉冲幅值相同，该第一相位误差信号和该第二相位误差信号对电荷泵电路的控制作用，可以理解为将压控振荡器输出的且经分频后的时钟信号与参考时钟信号的相位差转换为充放电过程的时间差，并通过该时间差实现对充放电过程的控制，也即是，当根据该第一相位误差信号和该第二相位误差信号控制第一控制电路10和第二控制电路20时，能够调节为电荷泵输出节点Vout充电的充电时长和为电荷泵输出节点Vout放电的放电时长。
或者，该锁相环电路可以包括：采样鉴相器和脉冲发生器，第一电流源I1与该采样鉴相器的第一输出端相耦合，第一输出端输出的第一采样信号用于调节第一电流的值；第二电流源I2与采样鉴相器的第二输出端相耦合，第二输出端输出的第二采样信号用于调节第二电流的值；该脉冲发生器用于生成脉冲信号，该脉冲信号可以用作第一控制信号和第四控制信号，该脉冲信号的反相信号可以用作第二控制信号和第三控制信号，也即是，该脉冲信号用于调节为电荷泵输出节点Vout充电的充电时长和为电荷泵输出节点Vout放电的放电时长。
此时，由于第一采样信号和第二采样信号是根据参考时钟信号对压控振荡器输出的时钟信号进行采样后得到的电压信号，该第一采样信号和第二采样信号的电压幅值不同。通过第一采样信号对第一电流进行调节和通过第二采样信号对第二电流进行调节的调节作用，可理解为将压控振荡器输出的时钟信号与参考时钟信号的相位差转换成对第一电流源和第二电流源进行控制的电压差，且由于电压值与调节后的电流值表现为正相关的关系，该电压差可转换为调节后的第一电流和第二电流的电流差。将该调节后的第一电流和第二电流输入电荷泵电路后，电荷泵电路在第一控制信号、第二控制信号、第三控制信号和第四控制信号的控制下，可实现对充放电过程的控制。
并且，通过第一采样信号和第二采样信号对第一电流和第二电流进行调节，可实现对第一电流和第二电流的单独控制，相对于相关技术，提高了电荷泵电路的适用范围和电荷泵电路使用的灵活性。
进一步地，该第一电流源I1和该第二电流源I2可以采用同类型器件实现，例如：提供第一电流的电路和提供第二电流的电路可以均由P型晶体管组成或均由N型晶体管组成，使得输入第一电流输入节点D1的第一电流和输入第二电流输入节点D2的第二电流的匹配特性会更好，可以更好地抑制充电电流和放电电流的电流失配，进一步地提高电荷泵输出电压的稳定性。
请参考图2，第一反馈电路30可以包括：第一钳位模块301和第一电流源模块302。
该第一钳位模块301的第一输入端与第一反馈节点E1相耦合，该第一钳位模块301的第二输入端与滤波节点Vx相耦合，该第一钳位模块301的输出端与第一电流源模块302的控制端相耦合，该第一钳位模块301用于在第一反馈节点E1和滤波节点Vx的控制下，稳定第一钳位模块301的输出端的电位。
该第一电流源模块302的输入端与第二反馈节点E2相耦合，该第一电流源模块302的输出端接地，该第一电流源模块302用于在第一电流源模块302的控制端的控制下，控制输入第二反馈节点E2的电流的值与第一电流的值相等。此时，该第一电流源模块302的作用相当于在其控制端的控制下，在第二反馈节点E2处产生一个类似于第一电流源I1的电流源，因此，将其命名为第一电流源模块。
进一步地，请参考图3，该第一钳位模块301可以包括：第一运算放大器OP1。该第一运算放大器OP1的同相输入端与第一反馈节点E1相耦合，该第一运算放大器OP1的反相输入端与滤波节点Vx相耦合，该第一运算放大器OP1的输出端与第一电流源模块302的控制端相耦合。根据该第一运算放大器OP1“虚短虚断”的原理，第一反馈节点E1和滤波节点Vx的电压相等，且输入至第二反馈节点E2的电流的值等于第一电流的值，即实现了对充电电流和放电电流的电流失配的抑制功能。其中，运算放大器的“虚短”的原理是指 在理想情况下，运算放大器的同相输入端和反相输入端两个输入端的电位相等；运算放大器的“虚断”的原理是指在理想情况下，流入运算放大器两个输入端的电流为零。
实际应用中，该第一电流源模块302可以有多种可实现方式，本申请实施例以通过晶体管实现为例对其进行说明，请继续参考图3，该第一电流源模块302可以包括：第一晶体管M1。该第一晶体管M1的栅极与第一钳位模块301的输出端相耦合，该第一晶体管M1的第一极与第二反馈节点E2相耦合，第一晶体管M1的第二极接地。可选地，该第一晶体管M1可以为N型晶体管。
请继续参考图2，第一控制电路10可以包括：第一控制模块101和第二控制模块102。
该第一控制模块101分别与第一控制节点K1、第一电流输入节点D1和第一反馈节点E1相耦合，该第一控制模块101用于在第一控制信号的电位为有效电位时，将第一电流输入第一反馈节点E1。
该第二控制模块102分别与第二控制节点K2、第一反馈节点E1和第二反馈节点E2相耦合，该第二控制模块102用于在第二控制信号的电位为有效电位时，将来自第一反馈节点E1的信号(也即是第一电流)输入第二反馈节点E2。
进一步地，请继续参考图3，该第一控制模块101可以包括：第二晶体管M2，该第二晶体管M2的栅极与第一控制节点K1相耦合，该第二晶体管M2的第一极与第一电流输入节点D1相耦合，该第二晶体管M2的第二极与第一反馈节点E1相耦合。
请继续参考图3，该第二控制模块102可以包括：第三晶体管M3，该第三晶体管M3的栅极与第二控制节点K2相耦合，该第三晶体管M3的第一极与第一反馈节点E1相耦合，该第三晶体管M3的第二极与第二反馈节点E2相耦合。
可选地，第二晶体管M2可以为P型晶体管，第三晶体管M3可以为N型晶体管，此时，在第二晶体管M2和第三晶体管M3开启时，在该第一晶体管M1和第三晶体管M3的共同作用下，第一电流输入节点D1的电压、第二反馈节点E2的电压和第一反馈节点E1的电压可较准确地保持为相等。
请继续参考图2，第二控制电路20可以包括：第三控制模块201和第四控制模块202。
该第三控制模块201分别与第三控制节点K3、第二电流输入节点D2和输出节点Vout相耦合，该第三控制模块201用于在第三控制信号的电位为有效电位时，将第二电流输入输出节点Vout。
该第四控制模块202分别与第四控制节点K4、输出节点Vout和第二反馈节点E2相耦合，该第四控制模块202用于在第四控制信号的电位为有效电位时，将来自输出节点Vout的信号(也即是第二电流)输入第二反馈节点E2。
进一步地，请继续参考图3，该第三控制模块201可以包括：第四晶体管M4，该第四晶体管M4的栅极与第三控制节点K3相耦合，该第四晶体管M4的第一极与第二电流输入节点D2相耦合，该第四晶体管M4的第二极与输出节点Vout相耦合。
请继续参考图3，该第四控制模块202可以包括：第五晶体管M5，该第五晶体管M5的栅极与第四控制节点K4相耦合，该第五晶体管M5的第一极与输出节点Vout相耦合，该第五晶体管M5的第二极与第二反馈节点E2相耦合。
可选地，第四晶体管M4可以为P型晶体管，第五晶体管M5可以为N型晶体管，此时，在第四晶体管M4和第五晶体管M5开启时，第二电流输入节点D2的电压、第二反馈 节点E2的电压和输出节点Vout的电压可较准确地保持为相等，也即是，第二电流输入节点D2和输出节点Vout之间、第二反馈节点E2和输出节点Vout之间均不会出现电荷分享，这样降低了与输出节点Vout连接的电荷泵的输出端的输出电压出现毛刺的几率，进而保证了输出电压的稳定性。
可选地，请参考图2，该电荷泵电路还可以包括：第三控制电路40和第二反馈电路50。
该第三控制电路40分别与第一电流输入节点D1、第二电流输入节点D2、第一控制节点K1、第三控制节点K3和第三反馈节点E3相耦合，该第三控制电路40用于在第一控制信号的电位为有效电位时，将第二电流输入第三反馈节点E3，或者，在第三控制信号的电位为有效电位时，将第一电流输入第三反馈节点E3。
该第二反馈电路50分别与第三反馈节点E3和滤波节点Vx相耦合，该第二反馈电路50用于在第三反馈节点E3和滤波节点Vx的控制下，控制第三反馈节点E3的电位。
在第一控制信号的电位为有效电位时，该第三控制电路40和第二反馈电路50构成了第二电流输入节点D2和滤波节点Vx之间的反馈回路，使得第二电流输入节点D2的电压、第三反馈节点E3的电压和滤波节点Vx的电压能够保持相等，同时，由于在整个电荷泵电路处于稳态时，滤波电阻R1上没有电压降，滤波节点Vx的电压等于输出节点Vout的电压，使得输出节点Vout、第二电流输入节点D2和第二反馈节点E2的电压相等，也即是，第二电流输入节点D2和输出节点Vout之间、第二反馈节点E2和输出节点Vout之间均不会出现电荷分享，这样降低了与输出节点Vout连接的电荷泵的输出端的输出电压出现毛刺的几率，进而保证了输出电压的稳定性。
在第三控制信号的电位为有效电位时，该第三控制电路40和第二反馈电路50构成了第一电流输入节点D1和滤波节点Vx之间的反馈回路，使得第一电流输入节点D1的电压、第三反馈节点E3的电压和滤波节点Vx的电压能够保持相等。并且，在第四晶体管M4和第五晶体管M5的作用下，第二电流输入节点D2的电压、第二反馈节点E2的电压和输出节点Vout的电压可较准确地保持为相等，使得第二电流输入节点D2和输出节点Vout之间、第二反馈节点E2和输出节点Vout之间均不会出现电荷分享，这样降低了与输出节点Vout连接的电荷泵的输出端的输出电压出现毛刺的几率，进而保证了输出电压的稳定性。
由上可知，本申请实施例提供的电荷泵电路，无论是在第一控制信号和第二控制信号的电位均为有效电位时，还是在第三控制信号和第四控制信号的电位均为有效电位时，第二电流输入节点D2和输出节点Vout之间、第二反馈节点E2和输出节点Vout之间均不会出现电荷分享，均能够保证输出电压的稳定性。
进一步地，请参考图4，第三控制电路40可以包括：第六晶体管M6和第七晶体管M7。
该第六晶体管M6的栅极与第一控制节点K1相耦合，该第六晶体管M6的第一极与第二电流输入节点D2相耦合，该第六晶体管M6的第二极与第三反馈节点E3相耦合。
该第七晶体管M7的栅极与第三控制节点K3相耦合，该第七晶体管M7的第一极与第一电流输入节点D1相耦合，该第七晶体管M7的第二极与第三反馈节点E3相耦合。
进一步地，请继续参考图2，第二反馈电路50可以包括：第二钳位模块501和第二电流源模块502。
该第二钳位模块501的第一输入端与第三反馈节点E3相耦合，该第二钳位模块501的第二输入端与滤波节点Vx相耦合，该第二钳位模块501的输出端与第二电流源模块502的 控制端相耦合，该第二钳位模块501用于在第三反馈节点E3和滤波节点Vx的控制下，稳定第二钳位模块501的输出端的电位。
该第二电流源模块502的输入端与第三反馈节点E3相耦合，该第二电流源模块502的输出端接地，该第二电流源模块502用于在第二电流源模块502的控制端的控制下，控制第三反馈节点E3的电位。此时，该第二电流源模块502的作用相当于在其控制端的控制下，在第三反馈节点E3处产生一个电流源，因此，将其命名为第二电流源模块。
进一步地，请参考图4，该第二钳位模块501可以包括：第二运算放大器OP2。该第二运算放大器OP2的同相输入端与第三反馈节点E3相耦合，第二运算放大器OP2的反相输入端与滤波节点Vx相耦合，第二运算放大器OP2的输出端与第二电流源模块502的控制端相耦合。根据该第二运算放大器OP2“虚短虚断”的原理，第三反馈节点E3和滤波节点Vx的电压相等，为保证第二电流输入节点D2的电压和输出节点Vout的电压相等提供了依据。
实际应用中，该第二电流源模块502可以有多种可实现方式，本申请实施例以通过晶体管实现为例对其进行说明，请继续参考图4，第二电流源模块502可以包括：第八晶体管M8，该第八晶体管M8的栅极与第二钳位模块501的输出端相耦合，该第八晶体管M8的第一极与第三反馈节点E3相耦合，该第八晶体管M8的第二极接地。可选地，该第八晶体管M8可以为N型晶体管。
需要说明的是，当产生第一电流源I1所提供的电流和产生第二电流源I2所提供的电流的电路均由同类型的器件组成时，例如：均由P型晶体管组成或均由N型晶体管组成时，充电电流和放电电流的匹配特性会更好，能够进一步提高电荷泵输出电压的稳定性。
综上所述，本申请实施例提供的抑制电流失配的电荷泵电路，包括第一控制电路、第二控制电路和第一反馈电路，该第一反馈电路能够控制输入第二反馈节点的电流的值等于第一电流的值，使得充电电流的值和放电电流的值相等，能够抑制充电电流和放电电流的电流失配，相较于相关技术，保证了电荷泵输出电压的稳定性。并且，当第一电流源和第二电流源采用同类型器件实现时，第一电流和第二电流的匹配特性会更好，可以更好地抑制充电电流和放电电流的电流失配，进一步地提高电荷泵输出电压的稳定性。
本申请实施例提供了一种抑制电流失配的电荷泵电路的控制方法，该方法用于控制本申请实施例提供的电荷泵电路，该电荷泵电路包括：第一控制电路10、第二控制电路20、第一反馈电路30、第三控制电路40和第二反馈电路50，请参考图5，方法包括：
步骤801、向第一控制节点施加处于有效电位的第一控制信号，且向第二控制节点施加处于有效电位的第二控制信号，使得第一控制电路在第一控制信号和第二控制信号的控制下，将来自第一电流输入节点的第一电流输入第二反馈节点；以及，使得第三控制电路将第二电流输入第三反馈节点，使得第二反馈电路在第三反馈节点和滤波节点的控制下，控制第三反馈节点的电位。
步骤802、向第三控制节点施加处于有效电位的第三控制信号，且向第四控制节点施加处于有效电位的第四控制信号，使得第二控制电路在第三控制信号和第四控制信号的控制下，将来自第二电流输入节点的第二电流输入输出节点，以及，使得第一反馈电路在第一反馈节点和滤波节点的控制下，控制输入第二反馈节点的电流的值与第一电流的值相等， 以及，使得第三控制电路将第一电流输入第三反馈节点，使得第二反馈电路在第三反馈节点和滤波节点的控制下，控制第三反馈节点的电位。
本申请实施例以图4所示的电荷泵电路，第二晶体管M2、第四晶体管M4、第六晶体管M6和第七晶体管M7为P型晶体管，第三晶体管M3和第五晶体管M5可以为N型晶体管为例，详细介绍其工作原理：
在步骤801中，第一控制信号为有效电位，且第二控制信号为有效电位时，第二晶体管M2在该第一控制信号的作用下开启，第一电流源I1通过该第二晶体管M2将输入第一电源信号第一反馈节点E1，第三晶体管M3在该第二控制信号的作用下开启，第一反馈节点E1通过该第三晶体管M3将第一电源信号输入第二反馈节点E2，以及，根据第一运算放大器OP1“虚短虚断”的原理，第一反馈节点E1和滤波节点Vx的电压相等，使得输入至第二反馈节点E2的电流的值等于第一电流的值。此时，充电电流的值和放电电流的值相等，实现了对充电电流和放电电流的电流失配的抑制作用。
并且，由于该第二晶体管M2和第三晶体管M3均开启，第一电流输入节点D1的电压和第二反馈节点E2的电压均等于第一反馈节点E1的电压。以及，根据第一运算放大器OP1“虚短虚断”的原理，第一反馈节点E1和滤波节点Vx的电压相等。同时，第六晶体管M6在第一控制信号的作用下开启，第二电源输入节点通过该第六晶体管M6将第二电源信号输入第三反馈节点E3，且第二电源输入节点的电压等于第三反馈节点E3的电压。以及，根据第二运算放大器OP2“虚短虚断”的原理，第三反馈节点E3和滤波节点Vx的电压相等。且由于在整个电荷泵电路处于稳态时，滤波节点Vx的电压等于输出节点Vout的电压，因此，可知输出节点Vout、第二电流输入节点D2和第二反馈节点E2的电压相等，也即是，第二电流输入节点D2和输出节点Vout之间、第二反馈节点E2和输出节点Vout之间均不会出现电荷分享，这样降低了与输出节点Vout连接的电荷泵的输出端的输出电压出现毛刺的几率，进而保证了输出电压的稳定性。
在步骤802中，第三控制信号为有效电位，且第四控制信号为有效电位时，第四晶体管M4在该第三控制信号的作用下开启，第二电流源I2通过该第四晶体管M4将第二电源信号输入输出节点Vout，第五晶体管M5在该第四控制信号的作用下开启，输出节点Vout通过该第五晶体管M5将第二电源信号输入第二反馈节点E2，此时，根据第一运算放大器OP1的钳位作用，第一运算控制器的输出电压仍保持为在步骤801中的输出电压值，且输入至第二反馈节点E2的电流的值仍等于第一电流的值，这样实现了对充电电流和放电电流的电流失配的抑制作用。且当第一电流源和第二电流源采用同类型器件实现时，第一电流和第二电流的匹配特性会更好，并且，在第三控制电路40和第二反馈电路50的作用下，第一电流输入节点D1的电压和第二电流输入节点D2的电压相等，可以更好地抑制充电电流和放电电流的电流失配，进一步地提高电荷泵输出电压的稳定性。
并且，由于该第四晶体管M4和第五晶体管M5均开启，第二电流输入节点D2的电压和第二反馈节点E2的电压均等于输出节点Vout的电压。以及，根据第一运算放大器OP1“虚短虚断”的原理，第一反馈节点E1和滤波节点Vx的电压相等。同时，第七晶体管M7在第三控制信号的作用下开启，第一电源输入节点通过该第七晶体管M7将第一电源信号输入第三反馈节点E3，且第一电源输入节点的电压等于第三反馈节点E3的电压。以及，根据第二运算放大器OP2“虚短虚断”的原理，第三反馈节点E3和滤波节点Vx的电压相 等。且由于在整个电荷泵电路处于稳态时，滤波节点Vx的电压等于输出节点Vout的电压，因此，可知输出节点Vout、第二电流输入节点D2和第二反馈节点E2的电压相等，也即是，第二电流输入节点D2和输出节点Vout之间、第二反馈节点E2和输出节点Vout之间均不会出现电荷分享。
从电荷泵电路在步骤801和步骤802中的工作过程可以看出，无论在第一控制信号和第二控制信号的电位均为有效电位时，还是在第三控制信号和第四控制信号的电位均为有效电位时，第二电流输入节点D2和输出节点Vout之间、第二反馈节点E2和输出节点Vout之间均不会出现电荷分享，均能够保证输出电压的稳定性。
综上所述，本申请实施例提供的抑制电流失配的电荷泵电路的控制方法，该电荷泵电路包括第一控制电路、第二控制电路和第一反馈电路，该第一反馈电路能够控制输入第二反馈节点的电流的值等于第一电流的值，使得充电电流的值和放电电流的值相等，能够抑制充电电流和放电电流的电流失配，相较于相关技术，保证了电荷泵输出电压的稳定性。并且，当第一电流源和第二电流源采用同类型器件实现时，第一电流和第二电流的匹配特性会更好，可以更好地抑制充电电流和放电电流的电流失配，进一步地提高电荷泵输出电压的稳定性。
本申请实施例还提供了一种锁相环电路，该锁相环电路包括：如本申请实施例提供的任一电荷泵电路。其中，该锁相环电路可用于产生时钟信号。
图6是根据本申请实施例提供的一种锁相环(Phase Locked Loop，PLL)电路的示意图，如图6所示，该锁相环包括：鉴相鉴频器(Phase/FrequencyDetector)、电荷泵(Charge Pump)、环路滤波器(Loop Filter)、压控振荡器(Voltage Controlled Oscillator，VCO)和分频器(Divider)，其中，该电荷泵包括本申请实施例所提供的抑制电流失配的电荷泵电路。
在该锁相环电路中，压控振荡器输出的时钟信号被分频器分频后,鉴相鉴频器可将分频后的时钟信号与输入的参考时钟信号Ref进行相位比较，并输出比较后的相位误差信号，该相位误差信号包括：第一相位误差信号up和第二相位误差信号dn，电荷泵用于根据该第一相位误差信号up和该第二相位误差信号dn向环路滤波器输出电流，环路滤波器用于根据该电荷泵输出的电流生成控制电压信号，在该控制电压信号的控制下，压控振荡器输出的时钟信号的频率可调整为参考时钟信号的频率的N倍。
图7是根据本申请实施例提供的另一种锁相环电路的示意图，如图7所示，该锁相环包括：采样型鉴相器(Sampling PD)、电荷泵、脉冲发生器(Pulser)、环路滤波器和压控振荡器。其中，脉冲发生器产生的脉冲信号用于控制电荷泵输出电流的时间，其中，该电荷泵包括本申请实施例所提供的抑制电流失配的电荷泵电路。
在该锁相环电路中，脉冲发生器用于产生互为反相信号的两个脉冲信号(脉冲信号P1和脉冲信号P2)，该脉冲信号用于调节为电荷泵输出节点Vout充电的充电时长和为电荷泵输出节点Vout放电的放电时长，也即是，该脉冲信号用于控制所述电荷泵输出电流的时间。压控振荡器输出的时钟信号在输入采样型鉴相器后，可根据输入的参考时钟信号Ref被采样，并在采样后输出第一采样信号SP1和第二采样信号SP2，该电荷泵用于根据脉冲信号、第一采样信号SP1和第二采样信号SP2向环路滤波器输出电流，该环路滤波器用于根据电荷泵输出的电流生成控制电压信号，在该控制电压信号的作用下，压控振荡器可输出的时 钟信号的频率可调整为参考时钟信号的频率的N倍。
本申请实施例还提供了一种存储介质，该存储介质内存储有计算机程序，计算机程序被处理器执行时实现本申请实施例提供的抑制电流失配的电荷泵电路的控制方法。
本申请实施例提供了一种芯片，该芯片包括可编程逻辑电路和/或程序指令，当该芯片运行时用于实现如本申请实施例提供的抑制电流失配的电荷泵电路的控制方法。
本领域普通技术人员可以理解实现上述实施例的全部或部分步骤可以通过硬件来完成，也可以通过程序来指令相关的硬件完成，所述的程序可以存储于一种计算机可读存储介质中，上述提到的存储介质可以是只读存储器，磁盘或光盘等。
以上所述仅为本发明的较佳实施例，并不用以限制本发明，凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (19)

  1. 一种抑制电流失配的电荷泵电路，其特征在于，包括：第一控制电路、第二控制电路和第一反馈电路；
    所述第一控制电路分别与第一电流输入节点、第一控制节点、第二控制节点、第一反馈节点和第二反馈节点相耦合，所述第一控制电路用于在来自所述第一控制节点的第一控制信号的电位为有效电位，且来自所述第二控制节点的第二控制信号的电位为有效电位时，将来自所述第一电流输入节点的第一电流输入所述第二反馈节点；
    所述第一反馈电路分别与所述第一反馈节点、所述第二反馈节点和滤波节点相耦合，所述第一反馈电路用于在所述第一反馈节点和所述滤波节点的控制下，控制输入所述第二反馈节点的电流的值与所述第一电流的值相等；
    所述第二控制电路分别与第二电流输入节点、第三控制节点、第四控制节点、输出节点和所述第二反馈节点相耦合，所述第二控制电路用于在来自所述第三控制节点的第三控制信号的电位为有效电位，且来自所述第四控制节点的第四控制信号的电位为有效电位时，将来自所述第二电流输入节点的第二电流输入所述输出节点，以及，将与所述第一电流的值相等的电流输入所述第二反馈节点。
  2. 根据权利要求1所述的电荷泵电路，其特征在于，所述电荷泵电路还包括：第三控制电路和第二反馈电路；
    所述第三控制电路分别与所述第一电流输入节点、所述第二电流输入节点、所述第一控制节点、所述第三控制节点和第三反馈节点相耦合，所述第三控制电路用于在所述第一控制信号的电位为有效电位时，将所述第二电流输入所述第三反馈节点，或者，在所述第三控制信号的电位为有效电位时，将所述第一电流输入所述第三反馈节点；
    所述第二反馈电路分别与所述第三反馈节点和所述滤波节点相耦合，所述第二反馈电路用于在所述第三反馈节点和所述滤波节点的控制下，控制所述第三反馈节点的电位。
  3. 根据权利要求1或2所述的电荷泵电路，其特征在于，所述电荷泵电路还包括：第一电流源和第二电流源；
    所述第一电流源与所述第一电流输入节点相耦合，所述第一电流源用于将所述第一电流输入所述第一电流输入节点；
    所述第二电流源与所述第二电流输入节点相耦合，所述第二电流源用于将所述第二电流输入所述第二电流输入节点。
  4. 根据权利要求1至3任一所述的电荷泵电路，其特征在于，所述电荷泵电路应用在锁相环电路中，所述锁相环电路包括：鉴相鉴频器，所述鉴相鉴频器用于根据输入的时钟信号输出第一相位误差信号和第二相位误差信号；
    所述第一相位误差信号用作所述第一控制信号；
    所述第二相位误差信号的反相信号用作所述第二控制信号；
    所述第一相位误差信号的反相信号用作所述第三控制信号；
    所述第二相位误差信号用作所述第四控制信号。
  5. 根据权利要求1至3任一所述的电荷泵电路，其特征在于，所述电荷泵电路应用在锁相环电路中，所述锁相环电路包括：采样鉴相器；
    所述第一电流源与所述采样鉴相器的第一输出端相耦合，所述第一输出端输出的第一采样信号用于调节所述第一电流的值；
    所述第二电流源与所述采样鉴相器的第二输出端相耦合，所述第二输出端输出的第二采样信号用于调节所述第二电流的值。
  6. 根据权利要求5所述的电荷泵电路，其特征在于，所述锁相环电路还包括：脉冲发生器，所述脉冲发生器用于生成脉冲信号；
    所述脉冲信号用作所述第一控制信号和所述第四控制信号；
    所述脉冲信号的反相信号用作所述第二控制信号和所述第三控制信号。
  7. 根据权利要求1至6任一所述的电荷泵电路，其特征在于，所述第一反馈电路包括：第一钳位模块和第一电流源模块；
    所述第一钳位模块的第一输入端与所述第一反馈节点相耦合，所述第一钳位模块的第二输入端与所述滤波节点相耦合，所述第一钳位模块的输出端与所述第一电流源模块的控制端相耦合，所述第一钳位模块用于在所述第一反馈节点和所述滤波节点的控制下，稳定所述第一钳位模块的输出端的电位；
    所述第一电流源模块的输入端与所述第二反馈节点相耦合，所述第一电流源模块的输出端接地，所述第一电流源模块用于在所述第一电流源模块的控制端的控制下，控制输入所述第二反馈节点的电流的值与所述第一电流的值相等。
  8. 根据权利要求7所述的电荷泵电路，其特征在于，所述第一钳位模块包括：第一运算放大器；
    所述第一运算放大器的同相输入端与所述第一反馈节点相耦合，所述第一运算放大器的反相输入端与所述滤波节点相耦合，所述第一运算放大器的输出端与所述第一电流源模块的控制端相耦合。
  9. 根据权利要求7或8所述的电荷泵电路，其特征在于，所述第一电流源模块包括：第一晶体管；
    所述第一晶体管的栅极与所述第一钳位模块的输出端相耦合，所述第一晶体管的第一极与所述第二反馈节点相耦合，所述第一晶体管的第二极接地。
  10. 根据权利要求1至9任一所述的电荷泵电路，其特征在于，所述第一控制电路包括：第二晶体管和第三晶体管；
    所述第二晶体管的栅极与所述第一控制节点相耦合，所述第二晶体管的第一极与所述第一电流输入节点相耦合，所述第二晶体管的第二极与所述第一反馈节点相耦合；
    所述第三晶体管的栅极与所述第二控制节点相耦合，所述第三晶体管的第一极与所述第一反馈节点相耦合，所述第三晶体管的第二极与所述第二反馈节点相耦合。
  11. 根据权利要求1至10任一所述的电荷泵电路，其特征在于，所述第二控制电路包括：第四晶体管和第五晶体管；
    所述第四晶体管的栅极与所述第三控制节点相耦合，所述第四晶体管的第一极与所述第二电流输入节点相耦合，所述第四晶体管的第二极与所述输出节点相耦合；
    所述第五晶体管的栅极与所述第四控制节点相耦合，所述第五晶体管的第一极与所述输出节点相耦合，所述第五晶体管的第二极与所述第二反馈节点相耦合。
  12. 根据权利要求2至11任一所述的电荷泵电路，其特征在于，所述第三控制电路包括：第六晶体管和第七晶体管；
    所述第六晶体管的栅极与所述第一控制节点相耦合，所述第六晶体管的第一极与所述第二电流输入节点相耦合，所述第六晶体管的第二极与所述第三反馈节点相耦合；
    所述第七晶体管的栅极与所述第三控制节点相耦合，所述第七晶体管的第一极与所述第一电流输入节点相耦合，所述第七晶体管的第二极与所述第三反馈节点相耦合。
  13. 根据权利要求2至12任一所述的电荷泵电路，其特征在于，所述第二反馈电路包括：第二钳位模块和第二电流源模块；
    所述第二钳位模块的第一输入端与所述第三反馈节点相耦合，所述第二钳位模块的第二输入端与所述滤波节点相耦合，所述第二钳位模块的输出端与所述第二电流源模块的控制端相耦合，所述第二钳位模块用于在所述第三反馈节点和所述滤波节点的控制下，稳定所述第二钳位模块的输出端的电位；
    所述第二电流源模块的输入端与所述第三反馈节点相耦合，所述第二电流源模块的输出端接地，所述第二电流源模块用于在所述第二电流源模块的控制端的控制下，控制所述第三反馈节点的电位。
  14. 根据权利要求13所述的电荷泵电路，其特征在于，所述第二钳位模块包括：第二运算放大器；
    所述第二运算放大器的同相输入端与所述第三反馈节点相耦合，所述第二运算放大器的反相输入端与所述滤波节点相耦合，所述第二运算放大器的输出端与所述第二电流源模块的控制端相耦合。
  15. 根据权利要求13或14所述的电荷泵电路，其特征在于，所述第二电流源模块包括：第八晶体管；
    所述第八晶体管的栅极与所述第二钳位模块的输出端相耦合，所述第八晶体管的第一极与所述第三反馈节点相耦合，所述第八晶体管的第二极接地。
  16. 一种抑制电流失配的电荷泵电路的控制方法，其特征在于，所述方法用于控制如权 利要求1至15任一所述的电荷泵电路，所述电荷泵电路包括：第一控制电路、第二控制电路和第一反馈电路，所述方法包括：
    向第一控制节点施加处于有效电位的第一控制信号，且向第二控制节点施加处于有效电位的第二控制信号，使得所述第一控制电路在所述第一控制信号和所述第二控制信号的控制下，将来自第一电流输入节点的第一电流输入第二反馈节点；
    向第三控制节点施加处于有效电位的第三控制信号，且向第四控制节点施加处于有效电位的第四控制信号，使得所述第二控制电路在所述第三控制信号和所述第四控制信号的控制下，将来自第二电流输入节点的第二电流输入输出节点，以及，使得所述第一反馈电路在第一反馈节点和滤波节点的控制下，控制输入所述第二反馈节点的电流的值与所述第一电流的值相等。
  17. 根据权利要求16所述的方法，其特征在于，所述电荷泵电路还包括：第三控制电路和第二反馈电路，所述方法还包括：
    向所述第一控制节点施加处于有效电位的第一控制信号，还使得所述第三控制电路将所述第二电流输入第三反馈节点，使得所述第二反馈电路在所述第三反馈节点和所述滤波节点的控制下，控制所述第三反馈节点的电位；
    向所述第三控制节点施加处于有效电位的第三控制信号，还使得所述第三控制电路将所述第一电流输入所述第三反馈节点，使得所述第二反馈电路在所述第三反馈节点和所述滤波节点的控制下，控制所述第三反馈节点的电位。
  18. 一种锁相环电路，其特征在于，所述锁相环电路包括：鉴相鉴频器、环路滤波器、压控振荡器、分频器以及如权利要求1至15任一所述的电荷泵电路；
    所述鉴相鉴频器用于根据输入的时钟信号，输出第一相位误差信号和第二相位误差信号；
    所述电荷泵电路用于根据所述第一相位误差信号和所述第二相位误差信号向所述环路滤波器输出电流；
    所述环路滤波器用于根据所述电荷泵电路输出的电流生成控制电压信号；
    所述压控振荡器用于根据所述控制电压信号输出目标时钟信号；
    所述分频器用于对所述目标时钟信号进行分频，并将分频后的目标时钟信号输入所述鉴相鉴频器。
  19. 一种锁相环电路，其特征在于，所述锁相环电路包括：采样型鉴相器、脉冲发生器、环路滤波器、压控振荡器以及如权利要求1至15任一所述的电荷泵电路；
    所述采样型鉴相器用于根据输入的时钟信号输出第一采样信号和第二采样信号；
    所述脉冲发生器用于生成脉冲信号，所述脉冲信号用于控制所述电荷泵电路输出电流的时间；
    所述电荷泵电路用于根据所述脉冲信号、所述第一采样信号和所述第二采样信号向所述环路滤波器输出电流；
    所述环路滤波器用于根据所述电荷泵电路输出的电流生成控制电压信号；
    所述压控振荡器用于根据所述控制电压信号输出目标时钟信号，并将所述目标时钟信号 输入所述采样型鉴相器。
PCT/CN2018/078432 2018-03-08 2018-03-08 抑制电流失配的电荷泵电路及其控制方法、锁相环电路 WO2019169607A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/CN2018/078432 WO2019169607A1 (zh) 2018-03-08 2018-03-08 抑制电流失配的电荷泵电路及其控制方法、锁相环电路
CN201880090848.4A CN111819777B (zh) 2018-03-08 2018-03-08 抑制电流失配的电荷泵电路及其控制方法、锁相环电路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2018/078432 WO2019169607A1 (zh) 2018-03-08 2018-03-08 抑制电流失配的电荷泵电路及其控制方法、锁相环电路

Publications (1)

Publication Number Publication Date
WO2019169607A1 true WO2019169607A1 (zh) 2019-09-12

Family

ID=67846854

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2018/078432 WO2019169607A1 (zh) 2018-03-08 2018-03-08 抑制电流失配的电荷泵电路及其控制方法、锁相环电路

Country Status (2)

Country Link
CN (1) CN111819777B (zh)
WO (1) WO2019169607A1 (zh)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113890538A (zh) * 2021-09-25 2022-01-04 北京知存科技有限公司 采样电路、采样阵列、存算一体芯片以及电子设备
CN115379619A (zh) * 2022-10-13 2022-11-22 合肥灿芯科技有限公司 一种led共阴驱动芯片
WO2024088137A1 (zh) * 2022-10-25 2024-05-02 加特兰微电子科技(上海)有限公司 电荷泵、锁相环、雷达传感器及电子设备

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114362748B (zh) * 2022-03-18 2022-05-27 深圳通锐微电子技术有限公司 电荷泵的电流调整方法、电流调整电路和锁相环电路

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040257162A1 (en) * 2003-06-23 2004-12-23 Mokeddem Hadj L. Charge pump for eliminating dc mismatches at common drian nodes
US7161401B2 (en) * 2004-02-27 2007-01-09 Broadcom Corporation Wide output-range charge pump with active biasing current
US7184510B2 (en) * 2003-09-26 2007-02-27 Quicklogic Corporation Differential charge pump
CN101414784A (zh) * 2007-10-16 2009-04-22 瑞昱半导体股份有限公司 电荷泵
US7701271B1 (en) * 2007-09-24 2010-04-20 Ozmo, Inc. High linearity charge pump method and apparatus
CN102097933A (zh) * 2009-12-14 2011-06-15 瑞昱半导体股份有限公司 一种电荷泵浦装置及其方法
CN104935163A (zh) * 2015-06-03 2015-09-23 西安电子科技大学 一种低电荷泄露的四支路电荷泵

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6181210B1 (en) * 1998-09-21 2001-01-30 Broadcom Corporation Low offset and low glitch energy charge pump for PLL-based timing recovery systems
US7053684B1 (en) * 2004-04-28 2006-05-30 Cirrus Logic, Inc. Reduced jitter charge pumps and circuits and systems utilizing the same
US7385429B1 (en) * 2005-05-31 2008-06-10 Altera Corporation Charge pump with reduced current mismatch
US7492197B2 (en) * 2005-11-17 2009-02-17 Realtek Semiconductor Corp. Charge pump circuit with regulated current output
US7365593B1 (en) * 2006-01-11 2008-04-29 Xilinx, Inc. Output equalized charge pump
CN101409554B (zh) * 2007-10-11 2012-05-16 北京朗波芯微技术有限公司 用于电荷泵锁相环的环路滤波电路
US7868669B2 (en) * 2008-03-26 2011-01-11 Infineon Technologies Ag Self-regulated charge pump with loop filter
CN101515709B (zh) * 2009-03-27 2010-09-15 东南大学 超低失配锁相环电路的电荷泵
WO2012101467A1 (en) * 2011-01-24 2012-08-02 Tredefin S.A. Efficient low noise differential amplifier, reutilizing the bias current
CN103036422A (zh) * 2012-12-12 2013-04-10 电子科技大学 一种用于电荷泵锁相环的电荷泵电路
US20150200588A1 (en) * 2014-01-16 2015-07-16 Qualcomm Incorporated Low-power, self-biasing-capable charge pump with current matching capabilities
US10151644B2 (en) * 2015-03-13 2018-12-11 Taiwan Semiconductor Manufacturing Company Limited Combination current generator configured to selectively generate one of a PTAT and a CTAT current

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040257162A1 (en) * 2003-06-23 2004-12-23 Mokeddem Hadj L. Charge pump for eliminating dc mismatches at common drian nodes
US7184510B2 (en) * 2003-09-26 2007-02-27 Quicklogic Corporation Differential charge pump
US7161401B2 (en) * 2004-02-27 2007-01-09 Broadcom Corporation Wide output-range charge pump with active biasing current
US7701271B1 (en) * 2007-09-24 2010-04-20 Ozmo, Inc. High linearity charge pump method and apparatus
CN101414784A (zh) * 2007-10-16 2009-04-22 瑞昱半导体股份有限公司 电荷泵
CN102097933A (zh) * 2009-12-14 2011-06-15 瑞昱半导体股份有限公司 一种电荷泵浦装置及其方法
CN104935163A (zh) * 2015-06-03 2015-09-23 西安电子科技大学 一种低电荷泄露的四支路电荷泵

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113890538A (zh) * 2021-09-25 2022-01-04 北京知存科技有限公司 采样电路、采样阵列、存算一体芯片以及电子设备
CN115379619A (zh) * 2022-10-13 2022-11-22 合肥灿芯科技有限公司 一种led共阴驱动芯片
WO2024088137A1 (zh) * 2022-10-25 2024-05-02 加特兰微电子科技(上海)有限公司 电荷泵、锁相环、雷达传感器及电子设备

Also Published As

Publication number Publication date
CN111819777A (zh) 2020-10-23
CN111819777B (zh) 2022-04-05

Similar Documents

Publication Publication Date Title
WO2019169607A1 (zh) 抑制电流失配的电荷泵电路及其控制方法、锁相环电路
JP4608153B2 (ja) チャージポンプ電流補正回路
US9419631B2 (en) Charge pump circuit used for charge pump phase-locked loop
US7330059B2 (en) In-loop duty corrector delay-locked loop for multiphase clock generation
US7271619B2 (en) Charge pump circuit reducing noise and charge error and PLL circuit using the same
US8228130B1 (en) Circuitry and method for precision amplitude control in quartz and MEMS oscillators
JPH11163696A (ja) 周波数比較器及びこれを用いたクロック再生回路
US20070109031A1 (en) Charge pump circuit with regulated current output
WO2018145612A1 (zh) 电荷泵电路和锁相环
US9419632B1 (en) Charge pump for use in phase-locked loop
TWI684329B (zh) 用於迴路電路之基於電壓調節器的迴路濾波器以及迴路濾波方法
US8786334B2 (en) Lock detection circuit and phase-locked loop circuit including the same
US9473022B2 (en) Self-biased charge pump
US8723566B1 (en) Correcting for offset-errors in a PLL/DLL
US20060170468A1 (en) PLL circuit and program for same
US6894569B2 (en) High-performance charge pump for self-biased phase-locked loop
US20230163769A1 (en) Low noise phase lock loop (pll) circuit
US9252791B1 (en) Phase locked loop and method for generating an oscillator signal
US8248123B2 (en) Loop filter
WO2015143980A1 (zh) 电荷泵的实现电路
CN110061739B (zh) 一种对工艺引起mos电容栅极漏电不敏感的pll电路
WO2018177195A1 (zh) 一种电荷泵、基于电荷泵的处理方法及锁相环电路、存储介质
TWI653820B (zh) 壓控振盪器與鎖相迴路
Zhang et al. A low mismatch symmetric charge pump for the application in PLLs
JP2001326574A (ja) 位相同期回路およびクロック発生回路

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18908731

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 18908731

Country of ref document: EP

Kind code of ref document: A1