WO2018145612A1 - 电荷泵电路和锁相环 - Google Patents

电荷泵电路和锁相环 Download PDF

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Publication number
WO2018145612A1
WO2018145612A1 PCT/CN2018/075271 CN2018075271W WO2018145612A1 WO 2018145612 A1 WO2018145612 A1 WO 2018145612A1 CN 2018075271 W CN2018075271 W CN 2018075271W WO 2018145612 A1 WO2018145612 A1 WO 2018145612A1
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WIPO (PCT)
Prior art keywords
transistor
gate
module
drain
source
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PCT/CN2018/075271
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English (en)
French (fr)
Inventor
丁庆
周海峰
吴光胜
李晓丛
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深圳市华讯方舟微电子科技有限公司
华讯方舟科技有限公司
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Application filed by 深圳市华讯方舟微电子科技有限公司, 华讯方舟科技有限公司 filed Critical 深圳市华讯方舟微电子科技有限公司
Priority to US16/476,391 priority Critical patent/US11218152B2/en
Publication of WO2018145612A1 publication Critical patent/WO2018145612A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
    • H03L7/0895—Details of the current generators
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/36—Means for starting or stopping converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
    • H03L7/0895—Details of the current generators
    • H03L7/0896—Details of the current generators the current generators being controlled by differential up-down pulses

Definitions

  • the present invention relates to the field of integrated circuit technology, and more particularly to a charge pump circuit and a phase locked loop having a low voltage and wide output range.
  • Phase Locked Loop can perform signal modulation and demodulation, clock recovery, and carrier for mixers and wireless receivers. Resume the generation of the local oscillator signal.
  • the Charge Pump Phase-locked Loop (CP-PLL) is the most common phase-locked loop circuit available today because of its high speed and low noise.
  • the Charge Pump (CP) circuit plays a very important role in the charge pump phase-locked loop. Its main function is to pass the UP and DN pulse digital signals from the Phase Frequency Detector (PFD).
  • a low-pass filter (LPF) is converted into an analog voltage signal that controls the oscillation frequency of a Voltage Control Oscillator (VCO). Therefore, the charge pump circuit has a very important influence on the characteristics of the entire phase-locked loop.
  • an operational amplifier circuit is used to clamp the voltage between different nodes, which not only increases the complexity of the circuit, but also brings stability to the overall stability of the circuit. Hidden dangers.
  • the structure of the operational amplifier also needs to achieve rail-to-rail input and output characteristics, further increasing the design difficulty of the operational amplifier.
  • the operating frequency range is often low and cannot be applied to the high-frequency domain.
  • a charge pump circuit includes a start module, a bias module, a current mirror module, a charge and discharge feedback control module, and a charge and discharge matching module electrically connected in sequence;
  • the startup module is configured to start the bias module
  • the biasing module is configured to generate a constant bias current and output to the current mirror module
  • the current mirror module is configured to receive the bias current, and amplify the bias current into two outputs;
  • the charge and discharge feedback control module is configured to detect an output voltage of the charge pump, and control a charging current or a discharge current in the charge and discharge matching module according to the output voltage feedback to suppress a mismatch between the charging current and the discharging current ;
  • the charge and discharge matching module is configured to receive an external charge control signal or a discharge control signal to charge or discharge an output load of the charge pump.
  • the startup module includes transistors M1, M2, and M3;
  • the transistor M1 and the transistor M3 constitute an inverter, the source of the transistor M1 and the transistor M2 is connected to the power supply terminal, the drain of the transistor M1 is connected to the gate of the transistor M2, and is connected to the drain of the transistor M3; the gate of the transistor M1 is The gate of the transistor M3 is connected, the source of the transistor M3 is grounded, and the gate of the transistor M1 and the drain of the transistor M2 are respectively connected to the bias module.
  • the biasing module includes transistors M4, M5, M6, M7, M8, M9, and M10;
  • the source of the transistor M4, the source of the transistor M5, and the source of the transistor M10 are all connected to the power supply terminal; the gate of the transistor M4 is connected to the gate of the transistor M5; the drain of the transistor M4 is respectively connected to the gate of the transistor M4.
  • the start module, the drain of the transistor M6, the gate of the transistor M10 are connected; the drain of the transistor M5 is connected to the drain of the transistor M7 and the gate of the transistor M7, respectively; the gate of the transistor M6 is connected to the gate of the transistor M7; The source of the transistor M6 is connected to the drain of the transistor M8; the source of the transistor M7 is connected to the drain of the transistor M9, the gate of the transistor M9, and the startup module, respectively; the source of the transistor M8 and the source of the transistor M9 are respectively Ground; the drain of transistor M10 is connected to a current mirror circuit.
  • the biasing module further includes resistors R1, R2, and R3, wherein the source of the transistor M8 is grounded via a resistor R1; the resistors R2, R3 are grounded in parallel and are both pseudo-resistors of the resistor R1.
  • the current mirror module includes transistors M11, M12, M13, M14, M15, M16, M17, M18, M19; wherein the source of the transistor M11, the source of the transistor M12, and the source of the transistor M15 The source of the transistor M16 and the source of the transistor M17 are both grounded; the source of the transistor M13, the source of the transistor M14, the source of the transistor M18, and the source of the transistor M19 are all connected to the power supply terminal;
  • the drain of the transistor M11 is connected to the gate of the transistor M11 and the bias module, respectively; the gate of the transistor M11 is connected to the gate of the transistor M12; the drain of the transistor M12 is connected to the drain of the transistor M13 and the gate of the transistor M13, respectively.
  • the gate of the transistor M13 is connected to the gate of the transistor M14; the drain of the transistor M14 is connected to the drain of the transistor M15, the gate of the transistor M15, and the gate of the transistor M17, respectively; the gate of the transistor M15 and the transistor M16
  • the gate of the transistor M16 is connected to the drain of the transistor M18 and the gate of the transistor M18; the gate of the transistor M18 is connected to the gate of the transistor M18; the drain of the transistor M17 and the drain of the transistor M19 are respectively Connected to the charge and discharge matching module.
  • the charge and discharge matching module includes a charging unit and a discharge unit; wherein
  • the charging circuit receives an offset module of one output of the current mirror module, and outputs a charging current according to the charging control signal to charge an output load of the charge pump; the discharging circuit receives another path of the current mirror module The output biasing module outputs a discharge current according to the discharge control signal to discharge the output load of the charge pump.
  • the charging unit includes transistors M20, M21, M22, M23, and M24;
  • the source of the transistor M20, the drain and the source of the transistor M21, and the source of the transistor M22 are all connected to the power supply terminal; the gate of the transistor M20 is grounded, the drain of the transistor M20 is respectively connected to the source of the transistor M23, and the charge and discharge feedback control The module is connected; the gate of the transistor M21 is respectively connected to the gate of the transistor M23 and the gate of the transistor M24; the gate of the transistor M22 receives the charge control signal connection, and the drain of the transistor M22 is connected to the source of the transistor M24; The drain of M23 is connected to the gate of transistor M23 and the current mirror module, respectively; the drain of transistor M24 is connected to the output load of the charge pump.
  • the discharge unit includes transistors M25, M26, M27, M28, and M29;
  • the drain of the transistor M25 is respectively connected to the gate of the transistor M25 and the current mirror module; the gate of the transistor M25 is respectively connected to the drain of the transistor M25, the gate of the transistor M26, and the gate of the transistor M28; the source of the transistor M25
  • the poles are respectively connected to the drain of the transistor M27 and the charge and discharge feedback control module; the drain of the transistor M26 is connected to the output load of the charge pump, the source of the transistor M26 is connected to the drain of the transistor M29; the gate of the transistor M27 is The power supply terminal is connected, the source of the transistor M27, the source and the drain of the transistor M28, and the source of the transistor M29 are both grounded; the gate of the transistor M29 receives the discharge control signal.
  • the charge and discharge feedback control module includes a charge feedback unit and a discharge feedback unit
  • the charging feedback unit is respectively connected to the charging unit and the output load of the charge pump; the charging feedback unit is configured to detect an output voltage of the charge pump, and control a discharge current output by the discharging unit according to the output voltage feedback, Suppressing a mismatch between the charging current and the discharging current;
  • the discharge feedback unit is respectively connected to the output load of the discharge unit and the charge pump; the discharge feedback unit is configured to detect an output voltage of the charge pump, and control the charging current output by the charging unit according to the output voltage feedback, The mismatch of the charging current and the discharging current is suppressed.
  • the charge feedback unit includes a transistor M30, and the discharge feedback unit includes a transistor M31;
  • the source of the transistor M30 is connected to the power supply terminal, the drain of the transistor M30 is connected to the charging unit, and the gate of the transistor M30 is connected to the output load of the charge pump;
  • the source of the transistor M31 is grounded, the drain of the transistor M31 is connected to the discharge electric unit, and the gate of the transistor M31 is connected to the output load of the charge pump.
  • the charge pump circuit includes a start module, a bias module, a current mirror module, a charge and discharge feedback control module, and a charge and discharge matching module electrically connected in sequence.
  • the charging feedback circuit can control the charging current or the discharging current in the charging/discharging matching module according to the detected output voltage of the charge pump, and suppress the mismatch between the charging current and the discharging current, thereby maintaining the electric charge in a wide output voltage range. Matching of pump charge current and discharge current.
  • the charge pump circuit in the embodiment of the invention has a simple structure and is suitable for a low voltage working environment.
  • phase locked loop including the above described charge pump circuit.
  • FIG. 1 is a block diagram showing the structure of a charge pump circuit in an embodiment
  • FIG. 2 is a circuit schematic diagram of a charge pump circuit in one embodiment
  • FIG. 3 is a simulation diagram of matching of a charging current and a discharging current of a charge pump in one embodiment
  • FIG. 4 is a transient simulation diagram of charging of a charge pump at 100 MHz in one embodiment
  • Figure 5 is a transient simulation of the discharge of a charge pump at 100 MHz in one embodiment.
  • FIG. 1 is a block diagram showing the structure of a circuit pump circuit in one embodiment.
  • a charge pump circuit includes a start module 10, a bias module 20, a current mirror module 30, a charge and discharge feedback control module 40, and a charge and discharge matching module 50 that are electrically connected in sequence.
  • the start module 10 is configured to start the bias module 20; the bias module 20 is configured to generate a constant bias current and output to the current mirror module 30; the current mirror module 30 is configured to receive And the bias current is amplified and divided into two outputs; the charge and discharge feedback control module 40 is configured to detect an output voltage of the charge pump, and control the charge and discharge according to the output voltage feedback Matching the charging current or the discharging current in the module 50 to suppress the mismatch of the charging current and the discharging current; the charging and discharging matching module 50 is configured to receive an external charging control signal or a discharging control signal to charge the output load of the charge pump or Discharge.
  • the charge pump circuit includes a startup module 10 electrically connected in sequence, a bias module 20, a current mirror module 30, a charge and discharge feedback control module 40, and a charge and discharge matching module 50.
  • the charging feedback circuit can control the charging current or the discharging current in the charging/discharging matching module 50 according to the detected output voltage of the charge pump, and suppress the mismatch between the charging current and the discharging current, thereby maintaining the charge pump in a wide output voltage range. Matching of charging current and discharging current.
  • the charge pump circuit in the embodiment of the invention has a simple structure and is suitable for a low voltage working environment.
  • the startup module 10 includes transistors M1, M2, and M3.
  • the transistor is a MOS transistor
  • the transistor M1 and the transistor M2 are p-channel MOS transistors (PMOS)
  • the transistor M3 is an n-channel MOS transistor (NMOS).
  • the transistor M1 and the transistor M3 constitute an inverter.
  • the source of the transistor M1 and the transistor M2 is connected to the power supply terminal, and the drain of the transistor M1 is connected to the gate of the transistor M2 and then connected to the drain of the transistor M3.
  • the gate of the transistor M1 is connected to the gate of the transistor M3, and the source of the transistor M3 is grounded.
  • the gate of the transistor M1 and the drain of the transistor M2 are respectively connected to the bias module 20.
  • the biasing module 20 employs a non-linear reference biasing module 20 structure that includes transistors M4, M5, M6, M7, M8, M9, and M10.
  • the transistor is a MOS transistor, the transistor M4, the transistor M5, and the transistor M10 are p-channel MOS transistors (PMOS); the transistor M6, the transistor M7, the transistor M8, and the transistor M9 are n-channel MOS transistors (NMOS).
  • the source of the transistor M4, the source of the transistor M5, and the source of the transistor M10 are all connected to the power supply terminal.
  • the gate of the transistor M4 is connected to the gate of the transistor M5.
  • the drain of the transistor M4 is connected to the gate of the transistor M4, the start-up module 10, the drain of the transistor M6, and the gate of the transistor M10, respectively.
  • the drain of the transistor M5 is connected to the drain of the transistor M7 and the gate of the transistor M7, respectively.
  • the gate of the transistor M6 is connected to the gate of the transistor M7; the source of the transistor M6 is connected to the drain of the transistor M8.
  • the source of the transistor M7 is connected to the drain of the transistor M9, the gate of the transistor M9, and the startup module 10, respectively.
  • the source of the transistor M8 and the source of the transistor M9 are both grounded.
  • the drain of transistor M10 is coupled to a current mirror circuit.
  • a stable bias voltage is generated by the biasing module 20, thereby controlling the transistor MOS transistor in the biasing module 20 to generate a constant bias current, wherein the biasing module 20 produces a constant bias current of about 10 uA.
  • the biasing module 20 further includes a resistor R1, a resistor R2, and a resistor R3.
  • the source of the transistor M8 is grounded via a resistor R1.
  • the resistor R2 and the resistor R3 are connected in parallel and are the pseudo resistors of the resistor R1.
  • the resistor R2 and the resistor R3 are placed on both sides of the resistor R1, so that the physical environment around the resistor R1 is relatively uniform, and the resistance value of the resistor R1 is reduced by the process fluctuation.
  • current mirror module 30 includes transistors M11, M12, M13, M14, M15, M16, M17, M18, M19.
  • the transistor is a MOS transistor, the transistor M13, the transistor M14, the transistor M18, and the transistor M19 are p-channel MOS transistors (PMOS); the transistor M11, the transistor M12, the transistor M15, the transistor M16, and the transistor M17 are n-channel MOS transistors. (NMOS).
  • the transistor M11 and the transistor M12 form a first current mirror pair, the transistor M13 and the transistor M14 form a second current mirror pair; the transistor M15, the transistor M16 and the transistor M17 form a third current mirror pair; the transistor M18 and the transistor M19 form a fourth current. Mirror pair.
  • the source of the transistor M11, the source of the transistor M12, the source of the transistor M15, the source of the transistor M16, and the source of the transistor M17 are all grounded.
  • the source of the transistor M13, the source of the transistor M14, the source of the transistor M18, and the source of the transistor M19 are all connected to the power supply terminal.
  • the drain of the transistor M11 is connected to the gate of the transistor M11 and the drain of the transistor M10, respectively; the gate of the transistor M11 is connected to the gate of the transistor M12.
  • the drain of the transistor M12 is connected to the drain of the transistor M13 and the gate of the transistor M13, respectively.
  • the gate of the transistor M13 is connected to the gate of the transistor M14.
  • the drain of the transistor M14 is connected to the drain of the transistor M15, the gate of the transistor M15, and the gate of the transistor M17, respectively.
  • the gate of the transistor M15 is connected to the gate of the transistor M16.
  • the drain of the transistor M16 is connected to the drain of the transistor M18 and the gate of the transistor M18, respectively.
  • the gate of transistor M18 is coupled to the gate of transistor M18.
  • the drain of the transistor M17 and the drain of the transistor M19 are connected to the charge and discharge matching module 50, respectively.
  • transistor M16 is a mirror image of transistor M15
  • transistor M17 is another mirror image of transistor M15.
  • the biasing module 20 is divided into two paths by the third current mirror, and the transistor is amplified by the transistor M16 and the fourth current mirror.
  • the constant current of the transistor 1 is output to the charge and discharge matching module 50; the other path is amplified by the transistor M17 to a constant current of the transistor MA, and then output to the charge and discharge matching module 50.
  • the constant current generated by the biasing module 20 is about 10uA, and after passing through four pairs of current mirrors, the transistor M11/transistor M12, the transistor M13/the transistor M14, the transistor M15/the transistor M16/the transistor M17, the transistor M18/the transistor M19, can be 10uA
  • the constant current is amplified to about 500uA, which realizes the amplification of the current.
  • the charge and discharge matching module 50 includes a charging unit 510 and a discharging unit 520; wherein the charging circuit receives the biasing module 20 of one output of the current mirror module 30, and outputs according to the charging control signal.
  • the charging current charges the output load of the charge pump.
  • the discharge circuit receives the bias module 20 of the other output of the current mirror module 30, and outputs a discharge current according to the discharge control signal to discharge the output load of the charge pump.
  • charging unit 510 includes transistors M20, M21, M22, M23, and M24.
  • the discharge unit 520 includes transistors M25, M26, M27, M28, and M29.
  • the transistor is a MOS transistor, and the transistor M20, the transistor M21, the transistor M22, the transistor M23, and the transistor M24 are p-channel MOS transistors (PMOS); the transistor M25, the transistor M26, the transistor M27, the transistor M28, and the transistor M29 are n-channels.
  • MOS transistor NMOS
  • the source of the transistor M20, the drain and the source of the transistor M21, and the source of the transistor M22 are all connected to the power supply terminal; the gate of the transistor M20 is grounded, the drain of the transistor M20 is respectively connected to the source of the transistor M23, and the charge and discharge feedback control Module 40 is connected.
  • the gate of the transistor M21 is connected to the gate of the transistor M23 and the gate of the transistor M24, respectively.
  • the gate of the transistor M22 receives the charge control signal (UP), and the drain of the transistor M22 is connected to the source of the transistor M24.
  • the drain of the transistor M23 is connected to the gate of the transistor M23 and the drain of the transistor M17, respectively.
  • the drain of transistor M24 is coupled to the output load of the charge pump.
  • the drain of the transistor M25 is connected to the gate of the transistor M25 and the drain of the transistor M19, respectively; the gate of the transistor M25 is connected to the drain of the transistor M25, the gate of the transistor M26, and the gate of the transistor M28, respectively; the source of the transistor M25
  • the poles are respectively connected to the drain of the transistor M27 and the charge and discharge feedback control module 40.
  • the drain of the transistor M26 is connected to the output load of the charge pump, and the source of the transistor M26 is connected to the drain of the transistor M29.
  • the gate of the transistor M27 is connected to the power supply terminal, and the source of the transistor M27, the source and the drain of the transistor M28, and the source of the transistor M29 are both grounded.
  • the gate of transistor M29 receives the discharge control signal (DN).
  • the charge and discharge feedback control module 40 includes a charge feedback unit 410 and a discharge feedback unit 420.
  • the charging feedback unit 410 is respectively connected to the charging unit 510 and the output load of the charge pump; the charging feedback unit 410 is configured to detect an output voltage of the charge pump, and control the output of the discharging unit 520 according to the output voltage feedback.
  • the discharge current suppresses mismatch between the charging current and the discharging current.
  • the discharge feedback unit 420 is respectively connected to the discharge unit 520 and the output load of the charge pump; the discharge feedback unit 420 is configured to detect an output voltage of the charge pump, and control the output of the charging unit 510 according to the output voltage feedback.
  • the charging current suppresses the mismatch between the charging current and the discharging current.
  • the charge feedback unit 410 includes a transistor M30, which is a p-channel MOS transistor (PMOS), the discharge feedback unit 420 includes a transistor M31, and the transistor M31 is an n-channel MOS transistor (NMOS).
  • the source of the transistor M30 is connected to the power supply terminal, the drain of the transistor M30 is connected to the drain of the transistor M20 and the source of the transistor M23, and the gate of the transistor M30 is connected to the output load of the charge pump.
  • the source of the transistor M31 is grounded, the drain of the transistor M31 is connected to the source of the transistor M25 and the drain of the transistor M27, and the gate of the transistor M31 is connected to the output load of the charge pump.
  • the charge control signal UP controls the switch MOS transistor M22 in the charge unit 510
  • the discharge control signal DN controls the switch MOS transistor M26 in the discharge unit 520.
  • the charging unit 510 and the discharge unit 520 constitute a loop.
  • the charge and discharge feedback control module 40 detects the output voltage OUT of the charge pump, and feeds back the detected output voltage to the charge feedback unit 410 transistor M30 or the discharge feedback unit 420 transistor M31, thereby controlling the charge and discharge matching module 50 to be in a wider output range. Achieve matching.
  • the transistor M30 of the charge feedback unit 410 enters the deep three-stage tube region, and the equivalent on-resistance decreases, reducing the image output to the output branch of the discharge unit 520 (transistor M26, transistor M29) The current, therefore, reduces the mismatch between the charging current and the discharging current.
  • the output voltage OUT voltage drops, its discharge feedback unit 420 transistor M31 enters the deep triode region, and the equivalent on-resistance decreases, reducing the current mirrored to the output branch (transistor M22, transistor M24) in the charging unit 510, thus This also reduces the mismatch between the charging current and the discharging current.
  • the charge pump circuit in the embodiment of the invention has a simple structure and is suitable for a low voltage working environment.
  • Figure 3 shows the matching simulation diagram of the charge current and discharge current of the charge pump.
  • the black solid line represents the change of the charge current with the output voltage
  • the black dotted line represents the relationship of the discharge current with the output voltage.
  • the gray solid line represents It is the difference between the charging current and the discharging current over the entire output swing range.
  • Fig. 4 is a transient simulation diagram of the charge pump charging at 100 MHz
  • Fig. 5 is a transient simulation diagram of the charge pump discharging at 100 MHz.
  • phase locked loop (not shown) is provided, including the charge pump circuit of any of the above embodiments. Since the charge pump circuit of any of the above embodiments is built in the phase locked loop, the matching of the charge pump charging current and the discharging current can be maintained over a wide range of output voltages.
  • the charge pump circuit has a simple circuit structure and is suitable for use in a low voltage, low power phase locked loop system.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
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Abstract

一种电荷泵电路和锁相环，该电路包括依次电连接的启动模块（10）、偏置模块（20）、电流镜模块（30）、充放电反馈控制模块（40）和充放电匹配模块（50）。启动模块（10）用于启动偏置模块（20）。偏置模块（20）用于产生恒定的偏置电流并输出至电流镜模块（30）。电流镜模块（30）用于接收偏置电流，并对偏置电流进行放大分两路输出。充放电反馈控制模块（40），用于检测电荷泵的输出电压并根据输出电压反馈控制充放电匹配模块（50）中的充电电流或放电电流，抑制充电电流与放电电流的失配。充放电匹配模块（50）用于接收外部充电控制信号或放电控制信号，对电荷泵的输出负载充电或放电。上述电荷泵电路无需运算放大器，就能在较宽输出电压范围内保持充电电流和放电电流的匹配，电路结构简单且能工作在较高的频率。

Description

电荷泵电路和锁相环 技术领域
本发明涉及集成电路技术领域，特别是涉及低压宽输出范围的电荷泵电路和锁相环。
背景技术
作为现代无线通信系统应用中最流行的一种频率合成器结构，锁相环(Phase Locked Loop，PLL)可以完成信号的调制和解调，时钟恢复，以及为混频器和无线接收器的载波恢复产生本振信号。而电荷泵锁相环(Charge Pump Phase-locked Loop，CP-PLL)更是因为其高速度、低噪声等特点，成为现今最普遍的一种锁相环电路。电荷泵(Charge Pump，CP)电路在电荷泵锁相环中起着非常重要的作用，其主要功能是把来自鉴频鉴相器(Phase Frequency Detector，PFD)的UP和DN脉冲数字信号，通过低通滤波器(Loop Filter，LPF)转换为模拟的电压信号，该信号控制压控振荡器(Voltage Control Oscillator，VCO)的振荡频率。因此，电荷泵电路对整个锁相环环路的特性有着非常重要的影响。
传统的实现电荷泵电路充电电流和放电电流匹配的电路结构中，采用运算放大器电路来钳制不同结点间的电压，这不但增加了电路的复杂度，还给电路整体的稳定性带来了一定的隐患。同时若要实现较大的输出电压摆幅，运算放大器的结构还需要实现轨到轨的输入输出特性，进一步增加了运算放大器的设计难度。而且，对于低压工作的运算放大器，其工作频率范围往往较低，不能适用于高频领域。
发明内容
基于此，有必要提供一种无需提供额外的运算放大器，就能实现在较宽输出电压范围内电荷泵充电电流和放电电流的匹配，且电路结构简单的电荷泵电路和锁相环。
一种电荷泵电路，包括依次电连接的启动模块、偏置模块、电流镜模块、充放电反馈控制模块和充放电匹配模块；其中，
所述启动模块用于启动所述偏置模块；
所述偏置模块用于产生恒定的偏置电流并输出至所述电流镜模块；
所述电流镜模块用于接收所述偏置电流，并对所述偏置电流进行放大分两路输出；
所述充放电反馈控制模块，用于检测电荷泵的输出电压，并根据所述输出电压反馈控制所述充放电匹配模块中的充电电流或放电电流，抑制所述充电电流与放电电流的失配；
所述充放电匹配模块用于接收外部充电控制信号或放电控制信号，对电荷泵的输出负载充电或放电。
在其中一个实施例中，所述启动模块包括晶体管M1、M2和M3；其中，
晶体管M1和晶体管M3构成反相器，晶体管M1、晶体管M2的源极与电源端连接，晶体管M1的漏极与晶体管M2的栅极连接后与晶体管M3的漏极连接；晶体管M1的栅极与晶体管M3的栅极连接，晶体管M3的源极接地；晶体管M1的栅极、晶体管M2的漏极分别与所述偏置模块连接。
在其中一个实施例中，所述偏置模块包括晶体管M4、M5、M6、M7、M8、M9和M10；其中，
晶体管M4的源极、晶体管M5的源极、晶体管M10的源极均与电源端连接；晶体管M4的栅极与晶体管M5的栅极连接；晶体管M4的漏极分别与晶体管M4的栅极、所述启动模块、晶体管M6的漏极、晶体管M10的栅极连接；晶体管M5的漏极分别与晶体管M7的漏极、晶体管M7的栅极连接；晶体管M6的栅极与晶体管M7的栅极连接；晶体管M6的源极与晶体管M8的漏极连接；晶体管M7的源极分别与晶体管M9的漏极、晶体管M9的栅极、所述启动模块连接；晶体管M8的源极、晶体管M9的源极均接地；晶体管M10的漏极与电流镜像电路连接。
在其中一个实施例中，所述偏置模块还包括电阻R1、R2和R3，其中，晶体管M8的源极经电阻R1接地；电阻R2、R3并联接地且均为电阻R1的伪电 阻。
在其中一个实施例中，所述电流镜模块包括晶体管M11、M12、M13、M14、M15、M16、M17、M18、M19；其中，晶体管M11的源极、晶体管M12的源极、晶体管M15的源极、晶体管M16的源极、晶体管M17的源极均接地；晶体管M13的源极、晶体管M14的源极、晶体管M18的源极、晶体管M19的源极均与电源端连接；
晶体管M11的漏极分别与晶体管M11的栅极、所述偏置模块连接；晶体管M11的栅极与晶体管M12的栅极连接；晶体管M12的漏极分别与晶体管M13的漏极、晶体管M13的栅极连接；晶体管M13的栅极与晶体管M14的栅极连接；晶体管M14的漏极分别与晶体管M15的漏极、晶体管M15的栅极、晶体管M17的栅极连接；晶体管M15的栅极与晶体管M16的栅极连接；晶体管M16的漏极分别与晶体管M18的漏极、晶体管M18的栅极连接；晶体管M18的栅极与晶体管M18的栅极连接；晶体管M17的漏极、晶体管M19的漏极分别与充放电匹配模块连接。
在其中一个实施例中，所述充放电匹配模块包括充电单元和放电单元；其中，
所述充电电路接收所述电流镜模块的一路输出的偏置模块，并根据所述充电控制信号输出充电电流，对电荷泵的输出负载充电；所述放电电路接收所述电流镜模块的另一路输出的偏置模块，并根据所述放电控制信号输出放电电流，对电荷泵的输出负载放电。
在其中一个实施例中，所述充电单元包括晶体管M20、M21、M22、M23和M24；其中，
晶体管M20的源极、晶体管M21的漏极和源极、晶体管M22的源极均与电源端连接；晶体管M20的栅极接地，晶体管M20的漏极分别与晶体管M23的源极、充放电反馈控制模块连接；晶体管M21的栅极分别与晶体管M23的栅极、晶体管M24的栅极连接；晶体管M22的栅极接收所述充电控制信号连接，晶体管M22的漏极与晶体管M24的源极连接；晶体管M23的漏极分别与晶体管M23的栅极、所述电流镜模块连接；晶体管M24的漏极与电荷泵的输出负载 连接。
所述放电单元包括晶体管M25、M26、M27、M28和M29；其中，
晶体管M25的漏极分别与晶体管M25的栅极、所述电流镜模块连接；晶体管M25的栅极分别与晶体管M25的漏极、晶体管M26的栅极、晶体管M28的栅极连接；晶体管M25的源极分别与晶体管M27的漏极、所述充放电反馈控制模块连接；晶体管M26的漏极与电荷泵的输出负载连接，晶体管M26的源极与晶体管M29的漏极连接；晶体管M27的栅极与电源端连接，晶体管M27的源极、晶体管M28的源极、漏极、晶体管M29的源极均接地；晶体管M29的栅极接收所述放电控制信号。
在其中一个实施例中，所述充放电反馈控制模块包括充电反馈单元和放电反馈单元；
所述充电反馈单元分别与所述充电单元、电荷泵的输出负载连接；所述充电反馈单元用于检测电荷泵的输出电压，并根据所述输出电压反馈控制所述放电单元输出的放电电流，抑制所述充电电流与放电电流的失配；
所述放电反馈单元分别与所述放电单元、电荷泵的输出负载连接；所述放电反馈单元用于检测电荷泵的输出电压，并根据所述输出电压反馈控制所述充电单元输出的充电电流，抑制所述充电电流与放电电流的失配。
在其中一个实施例中，所述充电反馈单元包括晶体管M30，所述放电反馈单元包括晶体管M31；其中，
晶体管M30的源极与电源端连接，晶体管M30的漏极与所述充电单元连接，晶体管M30的栅极与电荷泵的输出负载连接；
晶体管M31的源极接地，晶体管M31的漏极与所述放电电单元连接，晶体管M31的栅极与电荷泵的输出负载连接。
上述电荷泵电路，包括依次电连接的启动模块、偏置模块、电流镜模块、充放电反馈控制模块和充放电匹配模块。通过充电反馈电路根据检测的电荷泵的输出电压，能够控制充放电匹配模块中的充电电流或放电电流，抑制充电电流与放电电流的失配，就能实现在较宽输出电压范围内，保持电荷泵充电电流和放电电流的匹配。同时，本发明实施例中的电荷泵电路结构简单，适用于低 压工作环境。
此外，还提供一种锁相环，包括上述电荷泵电路。
附图说明
图1为一个实施例中电荷泵电路的结构框图；
图2为一个实施例中电荷泵电路的电路原理图；
图3为一个实施例中电荷泵的充电电流和放电电流的匹配仿真图；
图4为一个实施例中电荷泵在100MHz时充电的瞬态仿真图；
图5为一个实施例中电荷泵在100MHz时放电的瞬态仿真图。
具体实施方式
为了便于理解本发明，下面将参照相关附图对本发明进行更全面的描述。附图中给出了本发明的较佳实施例。但是，本发明可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本发明的公开内容的理解更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本发明的技术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在限制本发明。本文所使用的术语“和/或”包括一个或多个相关的所列项目的任意的和所有的组合。
如图1所示的为一个实施例中电路泵电路的结构框图。一种电荷泵电路，包括依次电连接的启动模块10、偏置模块20、电流镜模块30、充放电反馈控制模块40和充放电匹配模块50。
其中，所述启动模块10用于启动所述偏置模块20；所述偏置模块20用于产生恒定的偏置电流并输出至所述电流镜模块30；所述电流镜模块30用于接收所述偏置电流，并对所述偏置电流进行放大分两路输出；所述充放电反馈控制模块40，用于检测电荷泵的输出电压，并根据所述输出电压反馈控制所述充放电匹配模块50中的充电电流或放电电流，抑制所述充电电流与放电电流的失配；所述充放电匹配模块50用于接收外部充电控制信号或放电控制信号，对电荷泵 的输出负载充电或放电。
上述电荷泵电路，包括依次电连接的启动模块10、偏置模块20、电流镜模块30、充放电反馈控制模块40和充放电匹配模块50。通过充电反馈电路根据检测的电荷泵的输出电压，能够控制充放电匹配模块50中的充电电流或放电电流，抑制充电电流与放电电流的失配，就能在较宽输出电压范围内保持电荷泵充电电流和放电电流的匹配。同时，本发明实施例中的电荷泵电路结构简单，适用于低压工作环境。
在一个实施例中，参考图2，启动模块10包括晶体管M1、M2和M3。其中，晶体管采用的是MOS管，晶体管M1、晶体管M2为p沟道MOS管(PMOS)；晶体管M3为n沟道MOS管(NMOS)。晶体管M1和晶体管M3构成反相器，晶体管M1、晶体管M2的源极与电源端连接，晶体管M1的漏极与晶体管M2的栅极连接后与晶体管M3的漏极连接。晶体管M1的栅极与晶体管M3的栅极连接，晶体管M3的源极接地。晶体管M1的栅极、晶体管M2的漏极分别与所述偏置模块20连接。
当电源上电时，所有晶体管均处于关闭状态，节点A为高电平，节点C为低电平。增加启动模块10后，晶体管M1和晶体管M2构成反相器，节点B则为低电平，晶体管MOS管晶体管M2导通，给节点C充电，节点C电平上升，偏置模块20开始偏离零点。当偏置模块20到达稳定状态时，节点A为低电平，节点B为高电平，晶体管MOS管晶体管M2关闭，启动模块10不再影响偏置模块20。
在一个实施例中，偏置模块20采用了非线性基准偏置模块20结构，偏置模块20包括晶体管M4、M5、M6、M7、M8、M9和M10。其中，晶体管采用的是MOS管，晶体管M4、晶体管M5、晶体管M10为p沟道MOS管(PMOS)；晶体管M6、晶体管M7、晶体管M8、晶体管M9为n沟道MOS管(NMOS)。
晶体管M4的源极、晶体管M5的源极、晶体管M10的源极均与电源端连接。晶体管M4的栅极与晶体管M5的栅极连接。晶体管M4的漏极分别与晶体管M4的栅极、所述启动模块10、晶体管M6的漏极、晶体管M10的栅极连接。晶体管M5的漏极分别与晶体管M7的漏极、晶体管M7的栅极连接。晶体管 M6的栅极与晶体管M7的栅极连接；晶体管M6的源极与晶体管M8的漏极连接。晶体管M7的源极分别与晶体管M9的漏极、晶体管M9的栅极、所述启动模块10连接。晶体管M8的源极、晶体管M9的源极均接地。晶体管M10的漏极与电流镜像电路连接。通过偏置模块20生稳定的偏置电压，进而控制偏置模块20中的晶体管MOS管产生恒定的偏置电流，其中，偏置模块20产生的恒定偏置电流在10uA左右。
在一个实施例中，偏置模块20还包括电阻R1、电阻R2和电阻R3，其中，晶体管M8的源极经电阻R1接地；电阻R2、电阻R3并联且均为电阻R1的伪电阻。版图实现时，电阻R2、电阻R3放置在电阻R1两边，使得电阻R1周围的物理环境比较均一，减小电阻R1的电阻值受工艺波动的影响。
在一个实施例中，电流镜模块30包括晶体管M11、M12、M13、M14、M15、M16、M17、M18、M19。其中，晶体管采用的是MOS管，晶体管M13、晶体管M14、晶体管M18、晶体管M19为p沟道MOS管(PMOS)；晶体管M11、晶体管M12、晶体管M15、晶体管M16、晶体管M17为n沟道MOS管(NMOS)。其中，晶体管M11、晶体管M12构成第一电流镜对，晶体管M13、晶体管M14构成第二电流镜对；晶体管M15、晶体管M16、晶体管M17构成第三电流镜对；晶体管M18、晶体管M19构成第四电流镜对。
晶体管M11的源极、晶体管M12的源极、晶体管M15的源极、晶体管M16的源极、晶体管M17的源极均接地。晶体管M13的源极、晶体管M14的源极、晶体管M18的源极、晶体管M19的源极均与电源端连接。晶体管M11的漏极分别与晶体管M11的栅极、晶体管M10的漏极连接；晶体管M11的栅极与晶体管M12的栅极连接。晶体管M12的漏极分别与晶体管M13的漏极、晶体管M13的栅极连接。晶体管M13的栅极与晶体管M14的栅极连接。晶体管M14的漏极分别与晶体管M15的漏极、晶体管M15的栅极、晶体管M17的栅极连接。晶体管M15的栅极与晶体管M16的栅极连接。晶体管M16的漏极分别与晶体管M18的漏极、晶体管M18的栅极连接。晶体管M18的栅极与晶体管M18的栅极连接。晶体管M17的漏极、晶体管M19的漏极分别与充放电匹配模块50连接。
在第三电流镜对中，晶体管M16为晶体管M15的镜像，晶体管M17为晶体管M15的另一镜像。偏置模块20输出的偏置电流10uA经第一电流镜对、第二电流镜对后，由第三电流镜将偏置模块20分为两路，一路经晶体管M16、第四电流镜对放大成1晶体管MA的恒定电流后输出至充放电匹配模块50；另一路经晶体管M17放大成1晶体管MA的恒定电流后输出至充放电匹配模块50。偏置模块20产生的恒定电流在10uA左右，通过四对电流镜对晶体管M11/晶体管M12，晶体管M13/晶体管M14，晶体管M15/晶体管M16/晶体管M17，晶体管M18/晶体管M19后，可以将10uA的恒定电流放大到500uA左右，实现了对电流的放大。
在一个实施例中，充放电匹配模块50包括充电单元510和放电单元520；其中，所述充电电路接收所述电流镜模块30的一路输出的偏置模块20，并根据所述充电控制信号输出充电电流，对电荷泵的输出负载充电。所述放电电路接收所述电流镜模块30的另一路输出的偏置模块20，并根据所述放电控制信号输出放电电流，对电荷泵的输出负载放电。
在一个实施例中，充电单元510包括晶体管M20、M21、M22、M23和M24。放电单元520包括晶体管M25、M26、M27、M28和M29。其中，晶体管采用的是MOS管，晶体管M20、晶体管M21、晶体管M22、晶体管M23、晶体管M24为p沟道MOS管(PMOS)；晶体管M25、晶体管M26、晶体管M27、晶体管M28、晶体管M29为n沟道MOS管(NMOS)。
晶体管M20的源极、晶体管M21的漏极和源极、晶体管M22的源极均与电源端连接；晶体管M20的栅极接地，晶体管M20的漏极分别与晶体管M23的源极、充放电反馈控制模块40连接。
晶体管M21的栅极分别与晶体管M23的栅极、晶体管M24的栅极连接。晶体管M22的栅极接收所述充电控制信号(UP)，晶体管M22的漏极与晶体管M24的源极连接。晶体管M23的漏极分别与晶体管M23的栅极、晶体管M17的漏极连接。晶体管M24的漏极与电荷泵的输出负载连接。晶体管M25的漏极分别与晶体管M25的栅极、晶体管M19的漏极连接；晶体管M25的栅极分别与晶体管M25的漏极、晶体管M26的栅极、晶体管M28的栅极连接；晶体管 M25的源极分别与晶体管M27的漏极、所述充放电反馈控制模块40连接。晶体管M26的漏极与电荷泵的输出负载连接，晶体管M26的源极与晶体管M29的漏极连接。晶体管M27的栅极与电源端连接，晶体管M27的源极、晶体管M28的源极、漏极、晶体管M29的源极均接地。晶体管M29的栅极接收所述放电控制信号(DN)。
在一个实施例中，所述充放电反馈控制模块40包括充电反馈单元410和放电反馈单元420。所述充电反馈单元410分别与所述充电单元510、电荷泵的输出负载连接；所述充电反馈单元410用于检测电荷泵的输出电压，并根据所述输出电压反馈控制所述放电单元520输出的放电电流，抑制所述充电电流与放电电流的失配。所述放电反馈单元420分别与所述放电单元520、电荷泵的输出负载连接；所述放电反馈单元420用于检测电荷泵的输出电压，并根据所述输出电压反馈控制所述充电单元510输出的充电电流，抑制所述充电电流与放电电流的失配。
在一个实施例中，所述充电反馈单元410包括晶体管M30，晶体管M30为p沟道MOS管(PMOS)，所述放电反馈单元420包括晶体管M31，晶体管M31为n沟道MOS管(NMOS)。其中，晶体管M30的源极与电源端连接，晶体管M30的漏极分别与晶体管M20的漏极、晶体管M23的源极连接，晶体管M30的栅极与电荷泵的输出负载连接。晶体管M31的源极接地，晶体管M31的漏极分别晶体管M25的源极、晶体管M27的漏极连接，晶体管M31的栅极与电荷泵的输出负载连接。
具体地，充电控制信号UP控制充电单元510中的开关MOS管M22，放电控制信号DN控制放电单元520中的开关MOS管M26。当充电控制信号UP、放电控制信号DN均为高电平时，充电单元510、放电单元520构成回路。充放电反馈控制模块40检测电荷泵的输出电压OUT，并将检测的输出电压反馈至充电反馈单元410晶体管M30或放电反馈单元420晶体管M31，进而控制充放电匹配模块50在在较宽输出范围内实现匹配。
进一步地，当输出电压OUT电压上升时，其充电反馈单元410晶体管M30进入深三级管区，等效的导通电阻降低，减少了镜像到放电单元520中输出支 路(晶体管M26，晶体管M29)的电流，因此也就减小了充电电流和放电电流的失配。当输出电压OUT电压下降时，其放电反馈单元420晶体管M31进入深三极管区，等效的导通电阻降低，减少了镜像到充电单元510中输出支路(晶体管M22，晶体管M24)的电流，因此也就减小了充电电流和放电电流的失配。通过上述电荷泵电路，就能实现在较宽输出电压范围内电荷泵充电电流和放电电流的匹配。同时，本发明实施例中的电荷泵电路结构简单，适用于低压工作环境。
如图3所示的为电荷泵的充电电流和放电电流的匹配仿真图，黑实线代表充电电流随输出电压的变化关系，黑色虚线代表放电电流随输出电压的变化关系，灰色实线代表的是充电电流和放电电流在整个输出摆幅范围内的差值。由图3可知，当电源电压为1V时，输出电压摆幅从113mV到870mV，充电电流和放电电流的误差小于4％。图4电荷泵在100MHz时充电的瞬态仿真图，图5电荷泵在100MHz时放电时的瞬态仿真图。由图4和图5可以看出，当充电控制信号或放电控制信号在100MHz时，该电荷泵充电和放电的瞬态仿真没有毛刺现象。传统的采用运算放大器扩展电荷泵充电电流和放电电流匹配的电路结构复杂，其工作频率范围受到运算放大器带宽的影响，不能工作在较高的频率。而本发明实施例中，该电荷泵电路能在较高的频率范围内工作。即便是没有采用运算放大器，在较宽输出电压范围内也能保持电荷泵充电电流和放电电流的匹配。
此外，还提供一种锁相环(图中未示)，包括上述任一实施例中的电荷泵电路。由于锁相环中内置有上述任一实施例中的电荷泵电路，可以在较宽输出电压范围内保持电荷泵充电电流和放电电流的匹配。在一个实施例中，由于电荷泵电路的电路结构简单，适用于低压低功耗锁相环系统中。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细， 但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (10)

  1. 一种电荷泵电路，其特征在于，包括依次电连接的启动模块、偏置模块、电流镜模块、充放电反馈控制模块和充放电匹配模块；其中，
    所述启动模块用于启动所述偏置模块；
    所述偏置模块用于产生恒定的偏置电流并输出至所述电流镜模块；
    所述电流镜模块用于接收所述偏置电流，并对所述偏置电流进行放大分两路输出；
    所述充放电反馈控制模块，用于检测电荷泵的输出电压，并根据所述输出电压反馈控制所述充放电匹配模块中的充电电流或放电电流，抑制所述充电电流与放电电流的失配；
    所述充放电匹配模块用于接收外部充电控制信号或放电控制信号，对电荷泵的输出负载充电或放电。
  2. 根据权利要求1所述的电荷泵电路，其特征在于，所述启动模块包括晶体管M1、M2和M3；其中，
    晶体管M1和晶体管M3构成反相器，晶体管M1、晶体管M2的源极与电源端连接，晶体管M1的漏极与晶体管M2的栅极连接后与晶体管M3的漏极连接；晶体管M1的栅极与晶体管M3的栅极连接，晶体管M3的源极接地；晶体管M1的栅极、晶体管M2的漏极分别与所述偏置模块连接。
  3. 根据权利要求1所述的电荷泵电路，其特征在于，所述偏置模块包括晶体管M4、M5、M6、M7、M8、M9和M10；其中，
    晶体管M4的源极、晶体管M5的源极、晶体管M10的源极均与电源端连接；晶体管M4的栅极与晶体管M5的栅极连接；晶体管M4的漏极分别与晶体管M4的栅极、所述启动模块、晶体管M6的漏极、晶体管M10的栅极连接；晶体管M5的漏极分别与晶体管M7的漏极、晶体管M7的栅极连接；晶体管M6的栅极与晶体管M7的栅极连接；晶体管M6的源极与晶体管M8的漏极连接；晶体管M7的源极分别与晶体管M9的漏极、晶体管M9的栅极、所述启动模块连接；晶体管M8的源极、晶体管M9的源极均接地；晶体管M10的漏极与电流镜像电路连接。
  4. 根据权利要求3所述的电荷泵电路，其特征在于，所述偏置模块还包括电阻R1、R2和R3，其中，晶体管M8的源极经电阻R1接地；电阻R2、R3并联接地且均为电阻R1的伪电阻。
  5. 根据权利要求1所述的电荷泵电路，其特征在于，所述电流镜模块包括晶体管M11、M12、M13、M14、M15、M16、M17、M18、M19；其中，晶体管M11的源极、晶体管M12的源极、晶体管M15的源极、晶体管M16的源极、晶体管M17的源极均接地；晶体管M13的源极、晶体管M14的源极、晶体管M18的源极、晶体管M19的源极均与电源端连接；
    晶体管M11的漏极分别与晶体管M11的栅极、所述偏置模块连接；晶体管M11的栅极与晶体管M12的栅极连接；晶体管M12的漏极分别与晶体管M13的漏极、晶体管M13的栅极连接；晶体管M13的栅极与晶体管M14的栅极连接；晶体管M14的漏极分别与晶体管M15的漏极、晶体管M15的栅极、晶体管M17的栅极连接；晶体管M15的栅极与晶体管M16的栅极连接；晶体管M16的漏极分别与晶体管M18的漏极、晶体管M18的栅极连接；晶体管M18的栅极与晶体管M18的栅极连接；晶体管M17的漏极、晶体管M19的漏极分别与充放电匹配模块连接。
  6. 根据权利要求1所述的电荷泵电路，其特征在于，所述充放电匹配模块包括充电单元和放电单元；其中，
    所述充电电路接收所述电流镜模块的一路输出的偏置模块，并根据所述充电控制信号输出充电电流，对电荷泵的输出负载充电；所述放电电路接收所述电流镜模块的另一路输出的偏置模块，并根据所述放电控制信号输出放电电流，对电荷泵的输出负载放电。
  7. 根据权利要求6所述的电荷泵电路，其特征在于，所述充电单元包括晶体管M20、M21、M22、M23和M24；其中，
    晶体管M20的源极、晶体管M21的漏极和源极、晶体管M22的源极均与电源端连接；晶体管M20的栅极接地，晶体管M20的漏极分别与晶体管M23的源极、充放电反馈控制模块连接；晶体管M21的栅极分别与晶体管M23的栅极、晶体管M24的栅极连接；晶体管M22的栅极接收所述充电控制信号连接， 晶体管M22的漏极与晶体管M24的源极连接；晶体管M23的漏极分别与晶体管M23的栅极、所述电流镜模块连接；晶体管M24的漏极与电荷泵的输出负载连接；
    所述放电单元包括晶体管M25、M26、M27、M28和M29；其中，
    晶体管M25的漏极分别与晶体管M25的栅极、所述电流镜模块连接；晶体管M25的栅极分别与晶体管M25的漏极、晶体管M26的栅极、晶体管M28的栅极连接；晶体管M25的源极分别与晶体管M27的漏极、所述充放电反馈控制模块连接；晶体管M26的漏极与电荷泵的输出负载连接，晶体管M26的源极与晶体管M29的漏极连接；晶体管M27的栅极与电源端连接，晶体管M27的源极、晶体管M28的源极、漏极、晶体管M29的源极均接地；晶体管M29的栅极接收所述放电控制信号。
  8. 根据权利要求6所述的电荷泵电路，其特征在于，所述充放电反馈控制模块包括充电反馈单元和放电反馈单元；
    所述充电反馈单元分别与所述充电单元、电荷泵的输出负载连接；所述充电反馈单元用于检测电荷泵的输出电压，并根据所述输出电压反馈控制所述放电单元输出的放电电流，抑制所述充电电流与放电电流的失配；
    所述放电反馈单元分别与所述放电单元、电荷泵的输出负载连接；所述放电反馈单元用于检测电荷泵的输出电压，并根据所述输出电压反馈控制所述充电单元输出的充电电流，抑制所述充电电流与放电电流的失配。
  9. 根据权利要求8所述的电荷泵电路，其特征在于，所述充电反馈单元包括晶体管M30，所述放电反馈单元包括晶体管M31；其中，
    晶体管M30的源极与电源端连接，晶体管M30的漏极与所述充电单元连接，晶体管M30的栅极与电荷泵的输出负载连接；
    晶体管M31的源极接地，晶体管M31的漏极与所述放电电单元连接，晶体管M31的栅极与电荷泵的输出负载连接。
  10. 一种锁相环，其特征在于，包括如权利要求1～9任一项所述的电荷泵电路。
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