WO2019169565A1 - 直流失调消除电路以及直流失调消除方法 - Google Patents

直流失调消除电路以及直流失调消除方法 Download PDF

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Publication number
WO2019169565A1
WO2019169565A1 PCT/CN2018/078202 CN2018078202W WO2019169565A1 WO 2019169565 A1 WO2019169565 A1 WO 2019169565A1 CN 2018078202 W CN2018078202 W CN 2018078202W WO 2019169565 A1 WO2019169565 A1 WO 2019169565A1
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Prior art keywords
output
nmos transistor
signal
resistor
input
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PCT/CN2018/078202
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English (en)
French (fr)
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章可循
葛军华
周杰
潘剑华
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厦门优迅高速芯片有限公司
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Priority to PCT/CN2018/078202 priority Critical patent/WO2019169565A1/zh
Priority to US16/969,988 priority patent/US11264956B2/en
Publication of WO2019169565A1 publication Critical patent/WO2019169565A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/04—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only
    • H03F3/16—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only with field-effect devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45475—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using IC blocks as the active amplifying circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H03F3/45183—Long tailed pairs
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
    • H03F3/45632—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit
    • H03F3/45744—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit by offset reduction
    • H03F3/45748—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit by offset reduction by using a feedback circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
    • H03F3/45928—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection using IC blocks as the active amplifying circuit
    • H03F3/45968—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection using IC blocks as the active amplifying circuit by offset reduction
    • H03F3/45973—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection using IC blocks as the active amplifying circuit by offset reduction by using a feedback circuit
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
    • H04B10/60—Receivers
    • H04B10/66—Non-coherent receivers, e.g. using direct detection
    • H04B10/69—Electrical arrangements in the receiver
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/171—A filter circuit coupled to the output of an amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/321—Use of a microprocessor in an amplifier circuit or its control circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/375—Circuitry to compensate the offset being present in an amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/408—Indexing scheme relating to amplifiers the output amplifying stage of an amplifier comprising three power stages
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude

Definitions

  • the present invention relates to the field of electronic circuits, and more particularly to a DC offset cancellation circuit and a DC offset cancellation method.
  • the high-speed signal amplifier is an important part of the optical receiver.
  • the main function is to amplify the voltage signal provided by the pre-semiconductor amplifier for use in the latter stage.
  • the existing high-speed Signal amplifiers are typically a combination of a limiting amplifier and a differential amplifier.
  • a DC offset cancellation circuit is needed to eliminate the offset of the DC level of the output due to process distortion or DC level offset at the input. Otherwise, the DC level of the output will be seriously degraded, which will affect the normal operation of the amplifier and eventually cause The circuit is out of balance.
  • FIG. 1 is a schematic diagram showing the structure of a conventional DC offset cancellation circuit, which includes a high speed amplifier, a low pass filter, and a differential amplifier.
  • the high speed amplifier includes an input stage having an dc offset cancellation function, an amplification stage, and an output buffer stage; the input stage has a first signal input terminal Inp, a second signal input terminal Inn, a first signal output terminal Outp, and a second signal The output terminal Outn and the first DC compensation terminal DCinp and the second DC compensation terminal DCinn; the first signal input terminal Inp and the second signal input terminal Inn are respectively used for inputting input signals inp and inn; the DC compensation terminal DCinp And DCinn for inputting the compensation signals dcinp and dcinn, respectively, the first signal output terminal Outp and the second signal output terminal Outn are respectively for outputting the first output signals outp1 and outn1; the first output signals outp1 and outn1 are input The stages are processed by processing the input signals inp and inn and the compensation signals dcinp and dcinn; the non-inverting input end and the inverting input end of the amplification stage are respectively connected to the first signal output end
  • the non-inverting input of the differential amplifier is connected to the non-inverting output of the output buffer stage through a low-pass filter; the inverting input of the differential amplifier is connected to the non-inverting input of the output buffer stage through a low-pass filter;
  • the low pass filter is configured to filter the output signals outp and outn of the output buffer stage respectively to extract a pair of common mode output signals G1 and G2 in the output signals outp and outn;
  • the differential amplifier is used to output the common mode signal G1 and G2 are differentially amplified to generate compensation signals dcinp and dcinn for the input stage to eliminate dc offset.
  • the existing dc offset cancellation circuit actually uses a closed loop control method to generate the compensation signals dcinp and dcinn for the input stage to eliminate the dc offset; however, the existing dc offset cancellation circuit can only be applied to the input signals inp and inn.
  • a high-speed amplifier in a stable and continuous application environment such as a continuous mode receiving amplifier circuit in an optical communication system
  • an application environment such as light
  • the burst mode receiving amplifier circuit In the high-speed signal amplifier of the communication system, the burst mode receiving amplifier circuit, this is because the compensation signals dcinp and dcinn generated by the existing DC offset cancellation circuit can be explained not only according to the DC offset caused by the process problem, but also according to Due to the offset of the input signals inp and inn itself, in the application environment where the input signals inp and inn are stable and continuous, the compensation signals dcinp and dcinn can generate corresponding changes in time according to the DC offset of the input signals inp and inn to eliminate Input DC offset of signals inp and inn; but input signal in application environment When the amplitudes of inp and inn vary greatly and the variation is discontinuous, the existing DC offset cancellation circuit cannot cancel the compensation signals dcinp and dcinn if the changes of the compensation signals dcinp and dcinn cannot keep up with the changes of the input signals inp and inn. Instead, it is possible to generate an inverse effect that causes the
  • the solution of the present invention is:
  • a dc offset cancellation circuit includes a high speed amplifier, a voltage comparator, a microprocessor, and a digital to analog converter;
  • the high speed amplifier includes an input stage having an dc offset cancellation function, an amplification stage, and an output buffer stage;
  • the first signal input The terminal Inp and the second signal input terminal Inn are respectively used for inputting the input signals inp and inn;
  • the DC compensation terminals DCinp and DCinn are respectively used for inputting the compensation signals dcinp and dcinn, the first signal output terminal Outp and the second signal output
  • the ends Outn are respectively used for outputting the first output signals outp1 and outn1;
  • the first output signals outp1 and outn1 are generated by the input stage processing the input signals inp and inn and the compensation signals
  • the digital-to-analog converter is configured to receive the digital control signal DCS and generate a pair of compensation signals dcinp and dcinn according to the digital control signal DCS and output to the first DC compensation terminal DCinp and the second DC compensation terminal DCinn of the input stage, respectively.
  • the digital signal input terminal Din of the digital-to-analog converter has n, n is a positive integer greater than or equal to 2; n digital signal input terminals Din are the first digital signal input terminal Din (1) to the nth digital signal input a terminal Din(n); the digital signal input terminal Din of the digital-to-analog converter is connected to the microprocessor through a digital bus; the digital-to-analog converter includes a first conversion resistor R01, a second conversion resistor R02, and n conversion circuits The n conversion circuits are sequentially the first conversion circuit to the nth conversion circuit; one end of the first conversion resistor R01 and one end of the second conversion resistor R02 are grounded; the first conversion circuit includes a first inverter F1 and a first current source I1, a first positive phase controllable switch S1 and a first inverting controllable switch K1, an input end of the first current source i1 is connected to the working power supply VDD, and an output end of the first current source i1 is connected
  • the input stage includes a first resistor R1, a second resistor R2, a first NMOS transistor Q1, a second NMOS transistor Q2, a third NMOS transistor Q3, a fourth NMOS transistor Q4, a first constant current source I0, and a first voltage control a current source I1 and a second voltage-controlled current source I2; one end of the first resistor R1 is connected to the working power supply VDD, and the other end of the first resistor R1 is connected to the drain of the first NMOS transistor Q1 and the drain of the third NMOS transistor Q3; One end of the second resistor R2 is connected to the working power supply VDD, and the other end of the second resistor R2 is connected to the drain of the second NMOS transistor Q2 and the drain of the fourth NMOS transistor Q4; the input end of the first constant current source I0 is connected The source of the first NMOS transistor Q1 and the source of the second NMOS transistor Q2, the output end of the first constant current source I0 is grounded; the input end
  • the input stage includes a third resistor R3, a fourth resistor R4, a fifth NMOS transistor Q5, a sixth NMOS transistor Q6, a seventh NMOS transistor Q7, an eighth NMOS transistor Q8, a second constant current source I3, and a third constant current.
  • the first resistor R3 is connected to the working power supply VDD, the other end of the third resistor R3 is connected to the drain of the fifth NMOS transistor Q5 and the drain of the seventh NMOS transistor Q7; the fourth resistor R4 is connected at one end.
  • the power supply VDD, the other end of the fourth resistor R4 is connected to the drain of the sixth NMOS transistor Q6 and the drain of the eighth NMOS transistor Q8; the input end of the second constant current source I3 is connected to the source of the fifth NMOS transistor Q5 and a source of the sixth NMOS transistor Q6, an output end of the second constant current source I3 is grounded; an input end of the third constant current source I4 is connected to a source of the seventh NMOS transistor Q7 and a source of the eighth NMOS transistor Q8, The output end of the third constant current source I4 is grounded; the gate of the seventh NMOS transistor Q7 and the gate of the eighth NMOS transistor Q8 are respectively the second DC compensation terminal DCinn and the first DC compensation terminal of the input stage a common end of the seventh NMOS transistor Q7 and the fifth NMOS transistor Q5 and the third resistor R3 is a second signal output terminal Outn of the input stage; the eighth NMOS The common terminal of Q8 and the sixth NMOS transistor Q6
  • the input stage includes a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a capacitor C1, a ninth NMOS transistor Q9, a tenth NMOS transistor Q10, and a fourth constant current source I5;
  • One end of the fifth resistor R5 is connected to the working power supply VDD, and the other end of the fifth resistor R5 is connected to the drain of the ninth NMOS transistor Q9;
  • the common end of the fifth resistor R5 and the ninth NMOS transistor Q9 is the second signal of the input stage The output end Outn;
  • the sixth resistor R6 is connected to the working power supply VDD at one end, the other end of the sixth resistor R6 is connected to the tenth NMOS transistor Q10;
  • the common end of the sixth resistor R6 and the tenth NMOS transistor Q10 is the input stage a first signal output terminal Outp;
  • one end of the seventh resistor R7 is connected to the gate of the ninth NMOS
  • the gate of the ten NMOS transistor Q10, and the other end of the eighth resistor R8 is connected to the other end of the capacitor C1;
  • the common end of the resistor R8 and the tenth NMOS transistor Q10 is the second signal input terminal Inn of the input stage;
  • the common end of the eighth resistor R8 and the capacitor C1 is the first DC compensation terminal DCinp of the input stage;
  • the input end of the fourth constant current source I5 is connected to the source of the ninth NMOS transistor Q9 and the source of the tenth NMOS transistor Q10, and the output end of the fourth constant current source I5 is grounded.
  • a DC offset cancellation method the cancellation method is based on the DC offset cancellation circuit described above; the cancellation method is applied to the first signal input terminal Inp and the second signal input terminal Inn of the input stage without input signals inn and inp input
  • the DC offset cancellation method includes:
  • Step 1 The microprocessor presets a decimal initial value and assigns the initial value to the digital control signal DCS; then the digital-to-analog converter receives the digital control signal DCS and generates corresponding compensation signals dcinp and dcinn according to the digital control signal DCS. The output is compensated to the output stage;
  • Step 2 using a low-pass filter to propose common-mode output signals G1 and G2 in the output signals outp and outn of the output stage; then the voltage comparator compares the common-mode output signals G1 and G2 to output a digital logic signal DLS; When the common mode output signal G1 is greater than the common mode output signal G2, the digital logic signal DLS output by the voltage comparator is high level; when the common mode output signal G1 is smaller than the common mode output signal G2, the digital logic signal DLS output by the voltage comparator Low level;
  • Step 3 The microprocessor reads the digital logic signal DLS generated by the voltage comparator and judges the digital logic signal DLS. If the digital logic signal DLS is high, it proceeds to step 4; if the digital logic signal DLS is low , then go to step five;
  • Step 4 The microprocessor adds one to the initial value and assigns the processed initial value to the digital control signal DCS, and the digital-to-analog converter generates corresponding compensation signals dcinp and dcinn according to the digital control signal DCS to output The output stage is compensated, and then step two is repeated. Then the microprocessor reads the digital logic signal DLS of the voltage comparator again and judges. If the digital logic signal DLS is low, the microprocessor maintains the digital control signal DCS. The assignment is unchanged, otherwise repeat step four;
  • Step 5 The microprocessor decrements the initial value and assigns the processed initial value to the digital control signal DCS, and the digital-to-analog converter generates corresponding compensation signals dcinp and dcinn according to the digital control signal DCS to output The output stage is compensated, and then step two is repeated. Then the microprocessor reads the digital logic signal DLS of the voltage comparator again and judges. If the digital logic signal DLS is high, the microprocessor maintains the digital control signal DCS. The assignment is unchanged, otherwise repeat step 5.
  • the DC offset cancellation circuit of the present invention provides a compensation signal dcinp and dcinn to the input stage to perform DC offset cancellation on the high speed amplifier by a digital analog hybrid control method, and the DC offset cancellation circuit has a microprocessor Therefore, the compensation signals dcinp and dcinn can be locked by the microprocessor to ensure stable elimination of the DC offset caused by the process problem, so that even if the input signals inp and inn are subsequently input, the locked compensation signals dcinp and dcinn are still locked, and will not be Under the influence of the input signals inp and inn, the DC offset cancellation circuit can eliminate only the DC offset caused by the process problem, and can avoid the prior art that the compensation signal is not timely according to the changes of the input signals inp and inn. The corresponding change is such that the high speed amplifier does not work properly, so the dc offset cancellation circuit can operate when the amplitudes of the input signals inp and inn vary greatly and the variations are discontinuous.
  • the dc offset cancellation circuit can be used to generate the compensation signals dcinp and dcinn when the input stage of the high speed amplifier has no input signals inp and inn to eliminate the high speed amplifier due to process problems.
  • the DC offset, and the compensation signals dcinp and dcinn can be locked by the microprocessor to ensure stable elimination of the DC offset caused by the process problem, so that the input signals inp and inn of the subsequent input change greatly and the change is discontinuous, and the lock can be ensured.
  • the compensation signals dcinp and dcinn are still in a locked state, and are not affected by the input signals inp and inn, and can avoid the corresponding changes in the prior art by the compensation signal not according to the changes of the input signals inp and inn so that the high speed amplifier cannot be normal.
  • 1 is a schematic structural view of a conventional DC offset cancellation circuit
  • FIG. 2 is a schematic structural view of a DC offset cancellation circuit of the present invention
  • FIG. 3 is a schematic structural view of a digital-to-analog converter of the present invention.
  • FIG. 4 is a first schematic structural view of an input stage of the present invention.
  • Figure 5 is a second schematic structural view of an input stage of the present invention.
  • Figure 6 is a third schematic structural view of the input stage of the present invention.
  • FIG. 7 is a flow chart of a DC offset cancellation method of the present invention.
  • the present invention discloses a DC offset cancellation circuit including a high speed amplifier, a voltage comparator, a microprocessor, and a digital to analog converter; the high speed amplifier includes an input having a DC offset cancellation function. a stage, an amplification stage, and an output buffer stage; the input stage has a first signal input terminal Inp, a second signal input terminal Inn, a first signal output terminal Outp, a second signal output terminal Outn, and a first DC compensation terminal DCinp and a second DC compensation terminal DCinn; the first signal input terminal Inp and the second signal input terminal Inn are respectively used for inputting input signals inp and inn; and the DC compensation terminals DCinp and DCinn are respectively used for inputting compensation signals dcinp and dcinn, The first signal output terminal Outp and the second signal output terminal Outn are respectively used to output first output signals outp1 and outn1; the first output signals outp1 and outn1 are input signals inp and in and the compensation signal
  • the second DC compensation terminal DCinn is connected, and the digital-to-analog converter is configured to receive the digital control signal DCS and generate a pair of compensation signals dcinp and dcinn according to the digital control signal DCS and output to the first DC compensation terminal DCinp and the first input stage respectively Two DC compensation terminals DCinn.
  • the DC offset cancellation circuit of the present invention provides a compensation signal dcinp and dcinn to an input stage for DC offset cancellation of a high speed amplifier by a digital analog hybrid control method, the DC offset cancellation circuit having a microprocessor, and thus by microprocessing
  • the compensation signals dcinp and dcinn can be locked to ensure stable cancellation of DC offset caused by process problems, so that even after inputting input signals inp and inn, the locked compensation signals dcinp and dcinn are still locked, and are not affected by input signal inp and The influence of inn, the DC offset cancellation circuit can only eliminate the DC offset caused by the process problem, and can avoid the prior art that the compensation signal does not change according to the changes of the input signals inp and inn in time to make corresponding changes.
  • the high-speed amplifier does not work properly, so the dc offset cancellation circuit can operate when the amplitudes of the input signals inp and inn vary greatly and the variation is discontinuous.
  • the circuit structure of the digital-to-analog converter and the input stage is specifically described below; and the amplification stage may be a combination of a differential amplifier and a limiting amplifier in the prior art; the output buffer stage may be The output buffer; the low pass filter and the voltage comparator are all common techniques in the art and are not described.
  • the digital signal input terminal Din of the digital-to-analog converter has n, n is a positive integer greater than or equal to 2; n digital signal input terminals Din are sequentially the first digital signal input terminal Din (1) To the nth digital signal input terminal Din(n); the digital signal input terminal Din of the digital to analog converter is connected to the microprocessor through a digital bus; the digital to analog converter includes a first conversion resistor R01 and a second conversion resistor R02 and n conversion circuits, wherein the n conversion circuits are a first conversion circuit to an nth conversion circuit; one end of the first conversion resistor R01 and one end of the second conversion resistor R02 are grounded; and the first conversion circuit includes a first inverter F1, the first current source i1, the first positive phase controllable switch S1 and the first inverting controllable switch K1, the input end of the first current source i1 is connected to the working power supply VDD, and the output end of the first current source i1 is connected to the first An
  • the present invention provides a structure of three input stages.
  • the input stage may include a first resistor R1, a second resistor R2, a first NMOS transistor Q1, a second NMOS transistor Q2, and a third NMOS transistor.
  • a fourth NMOS transistor Q4 a first constant current source I0, a first voltage-controlled current source I1, and a second voltage-controlled current source I2; one end of the first resistor R1 is connected to the working power supply VDD, and the other end of the first resistor R1 Connecting the drain of the first NMOS transistor Q1 and the drain of the third NMOS transistor Q3; one end of the second resistor R2 is connected to the working power supply VDD, and the other end of the second resistor R2 is connected to the drain of the second NMOS transistor Q2 and the fourth a drain of the NMOS transistor Q4; an input end of the first constant current source I0 is connected to a source of the first NMOS transistor Q1 and a source of the second NMOS transistor Q2, and an output end of the first constant current source I0 is grounded; The input end of the first voltage-controlled current source I1 is connected to the source of the third NMOS transistor Q3, the output end of the first voltage-controlled current source I1 is grounded; the
  • the output end of the second voltage-controlled current source I2 is grounded; the control end of the first voltage-controlled current source I1 and the second voltage-controlled current source I2
  • the terminal is respectively a second DC compensation terminal DCinn of the input stage and a first DC compensation terminal DCinp; a gate of the third NMOS transistor Q3 and a gate of the fourth NMOS transistor Q4 are connected to a bias power source Vref;
  • the common end of the third NMOS transistor Q3 and the first NMOS transistor Q1 and the first resistor R1 is the second signal output terminal Outn of the input stage; the fourth NMOS transistor Q4 and the second NMOS transistor Q2 and the second resistor
  • the common end of R2 is the first signal output terminal Outp of the input stage; the gate of the first NMOS transistor Q1 and the gate of the second NMOS transistor Q2 are respectively the first signal input end Inp of the input stage and The second signal input terminal Inn.
  • the input stage may also include a third resistor R3, a fourth resistor R4, a fifth NMOS transistor Q5, a sixth NMOS transistor Q6, a seventh NMOS transistor Q7, an eighth NMOS transistor Q8, and a second a constant current source I3 and a third constant current source I4; one end of the third resistor R3 is connected to the working power supply VDD, and the other end of the third resistor R3 is connected to the drain of the fifth NMOS transistor Q5 and the drain of the seventh NMOS transistor Q7; One end of the fourth resistor R4 is connected to the working power supply VDD, and the other end of the fourth resistor R4 is connected to the drain of the sixth NMOS transistor Q6 and the drain of the eighth NMOS transistor Q8; the input end of the second constant current source I3 is connected a source of the fifth NMOS transistor Q5 and a source of the sixth NMOS transistor Q6, and an output end of the second constant current source I3 is grounded; an input end of the third resistor R3
  • the input stage may further include a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a capacitor C1, a ninth NMOS transistor Q9, a tenth NMOS transistor Q10, and a first a fourth constant current source I5; one end of the fifth resistor R5 is connected to the working power supply VDD, and the other end of the fifth resistor R5 is connected to the drain of the ninth NMOS transistor Q9; the common end of the fifth resistor R5 and the ninth NMOS transistor Q9 a second signal output terminal Outn of the input stage; one end of the sixth resistor R6 is connected to the working power supply VDD, and the other end of the sixth resistor R6 is connected to the tenth NMOS transistor Q10; the sixth resistor R6 and the tenth NMOS transistor The common end of the Q10 is the first signal output terminal Outp of the input stage; the seventh resistor R7 is connected to the gate of the ninth NMOS transistor Q
  • the other end of the first resistor R8 and the tenth NMOS transistor Q10 is the second signal input terminal Inn of the input stage; the common end of the eighth resistor R8 and the capacitor C1 is the input stage The first DC compensating end DCinp; the input end of the fourth constant current source I5 is connected to the source of the ninth NMOS transistor Q9 and the source of the tenth NMOS transistor Q10, and the output end of the fourth constant current source I5 is grounded.
  • the present invention also provides a DC offset cancellation method, which is based on the DC offset cancellation circuit described above; the cancellation method is applied to the first signal input terminal Inp and the second signal input terminal Inn of the input stage without input
  • the DC offset cancellation method includes:
  • Step 1 S1 The microprocessor presets a decimal initial value and assigns the initial value to the digital control signal DCS; then the digital-to-analog converter receives the digital control signal DCS and generates corresponding compensation signals dcinp and dcinn according to the digital control signal DCS. Output to the output stage for compensation;
  • Step 2 S2: using a low-pass filter to propose common-mode output signals G1 and G2 in the output signals outp and outn of the output stage; then the voltage comparator compares the common-mode output signals G1 and G2 to output a digital logic signal DLS; When the common mode output signal G1 is greater than the common mode output signal G2, the digital logic signal DLS output by the voltage comparator is at a high level; when the common mode output signal G1 is smaller than the common mode output signal G2, the digital logic signal output by the voltage comparator DLS is low;
  • Step 3 S3 The microprocessor reads the digital logic signal DLS generated by the voltage comparator and judges the digital logic signal DLS. If the digital logic signal DLS is high, it proceeds to step 4; if the digital logic signal DLS is low Ping, go to step five;
  • Step 4 S4: The microprocessor adds one to the initial value and assigns the processed initial value to the digital control signal DCS, and the digital-to-analog converter generates corresponding compensation signals dcinp and dcinn according to the digital control signal DCS. The output is compensated to the output stage, and then step 2 is repeated. Then the microprocessor reads the digital logic signal DLS of the voltage comparator again and judges. If the digital logic signal DLS is low, the microprocessor maintains the digital control signal DCS. The assignment is unchanged, otherwise step 4 is repeated; the compensation signals dcinp and dcinn are locked to ensure stable elimination of DC offset caused by process problems;
  • Step 5 S5: The microprocessor decrements the value of the initial value and assigns the processed initial value to the digital control signal DCS, and the digital-to-analog converter generates corresponding compensation signals dcinp and dcinn according to the digital control signal DCS. The output is compensated to the output stage, and then step two is repeated. Then the microprocessor reads the digital logic signal DLS of the voltage comparator again and judges. If the digital logic signal DLS is high, the microprocessor maintains the digital control signal DCS. The assignment is unchanged, otherwise repeat step five.
  • the microprocessor keeps the value of the digital control signal DCS unchanged, it is determined that the digital-to-analog converter generates the compensation signals dcinp and dcinn through the digital control signal DCS at this time, which has eliminated the DC offset cancellation caused by the process problem, and the microprocessor Keeping the digital control signal DCS unchanged, the corresponding compensation signals dcinp and dcinn are also unchanged, that is, the compensation signals dcinp and dcinn are locked. Therefore, by the DC offset cancellation method, the DC offset cancellation circuit can be used to generate the compensation signals dcinp and dcinn when the input stage of the high speed amplifier has no input signals inp and inn to eliminate the DC offset caused by the high speed amplifier due to process problems.
  • the compensation signals dcinp and dcinn can be locked by the microprocessor to ensure stable elimination of the DC offset caused by the process problem, so that the microprocessor can guarantee the amplitude of the input signals inp and inn of the subsequent input is large and the variation is discontinuous.
  • the locked compensation signals dcinp and dcinn are still in a locked state and are not affected by the input signals inp and inn. Therefore, the DC offset cancellation circuit only eliminates the DC offset caused by the process problem, and can avoid the prior art compensation signal. A corresponding change is made in time according to changes in the input signals inp and inn so that the high speed amplifier does not operate normally.

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Abstract

一种直流失调消除电路和直流失调消除方法，该直流失调消除电路包括高速放大器、电压比较器、微处理器以及数模转换器；所述高速放大器包括具有直流失调消除功能的输入级、放大级以及输出缓冲级；所述电压比较器与输出缓冲级相连；所述微处理器与电压比较器相连；所述数模转化器与微处理器相连，所述数模转换器与输出级。所述直流失调消除电路是通过数字模拟混合控制方法来提供补偿信号给输入级以对高速放大器进行直流失调消除，能通过微处理器锁定补偿信以保证稳定消除工艺问题造成的直流失调消除，能避免由补偿信号没有根据输入信号的变化而及时进行相应的变化以使得高速放大器不能正常工作的问题。

Description

直流失调消除电路以及直流失调消除方法 技术领域
本发明涉及电子电路领域，特别是指一种直流失调消除电路以及直流失调消除方法。
背景技术
现今光通信已经成为通信行业发展的主流，高速信号放大器作为光接收机内的重要组成部分，主要功能是将前级跨阻放大器提供的电压信号进行放大以供后级电路使用，现有的高速信号放大器一般为限幅放大器与差分放大器的组合。在高速信号放大器中，需要直流失调消除电路以消除由于工艺失真或者输入端直流电平失调引起的输出端直流电平的失调，否则输出端直流电平的失调严重时会影响到放大器的正常工作，最终引起电路失衡。
图1是现有的直流失调消除电路的结构示意图示意图，其包括高速放大器、低通滤波器和差分放大器。
所述高速放大器包括具有直流失调消除功能的输入级、放大级以及输出缓冲级；所述输入级具有第一信号输入端Inp、第二信号输入端Inn、第一信号输出端Outp、第二信号输出端Outn以及第一直流补偿端DCinp和第二直流补偿端DCinn；所述第一信号输入端Inp和第二信号输入端Inn分别用于输入输入信号inp和inn；所述直流补偿端DCinp和DCinn分别用于输入补偿信号dcinp和dcinn，所述第一信号输出端Outp和第二信号输出端Outn分别用于输出第一输出信号outp1和outn1；所述第一输出信号outp1和outn1由输入级将输入信号inp和inn和补偿信号dcinp和dcinn进行处理后产生；所述放大级的同相输入端和反相输入端分别与第一信号输出端Outp和第二信号输出端Outn相连，所述放大级用于对第一输出信号outp1和outn1对进行放大以产生第二输出信号outp2和outn2；所述输出缓冲级的同相输入端和反相输入端与放大级的同相输出端和反相输出端相连，所述输出缓冲级用于缓冲第二输出信号outp2和outn2以产生输出信号outp和outn。
所述差分放大器的同相输入端通过低通滤波器与输出缓冲级的同相输出端相连；所述差分放大器的反相输入端通过低通滤波器与输出缓冲级的同相输入端相连；两个所述低通滤波器用于对输出缓冲级的输出信号outp和outn分别进行滤波以提取输出信号outp和outn中的一对共模输出信号G1和G2；所述差分放大器用于对该共模输出信号G1和G2进行差分放大以相应产生补偿信号dcinp和dcinn供输入级消除直流失调。
现有的直流失调消除电路实际上采用的是一个闭环控制方法以产生补偿信号dcinp和dcinn以供输入级来消除直流失调；但是现有的直流失调消除电路只能应用于处于输入信号inp和inn幅度稳定且连续的应用环境中（如光通讯系统中，连续模式接收放大电路）的高速放大器，而不能应用于处于输入信号inp和inn幅度变化大且变化不连续的用于应用环境（如光通讯系统中，突发模式接收放大电路）的高速信号放大器中，这是因为现有的直流失调消除电路产生的补偿信号dcinp和dcinn不仅能根据由于工艺问题造成的直流失调来阐述，还能根据由于输入信号inp和inn本身的失调来产生；而在输入信号inp和inn幅度稳定且连续的应用环境中，补偿信号dcinp和dcinn能根据输入信号inp和inn的直流失调及时产生相应的变化以消除输入信号inp和inn的直流失调；但是在应用环境中输入信号inp和inn幅度变化大且变化不连续时，现有的直流失调消除电路如果补偿信号dcinp和dcinn的变化跟不上输入信号inp和inn的变化，那么补偿信号dcinp和dcinn不能起到消除作用，反而有可能产生一个逆作用，使得放大器的信号的失真，甚至引起放大器的震荡。
发明内容
本发明的目的在于提供一种直流失调消除电路以及直流失调消除方法，以克服现有技术的不足。
为了达成上述目的，本发明的解决方案是：
一种直流失调消除电路，其包括高速放大器、电压比较器、微处理器以及数模转换器；所述高速放大器包括具有直流失调消除功能的输入级、放大级以及输出缓冲级；所述输入级具有第一信号输入端Inp、第二信号输入端Inn、第一信号输出端Outp、第二信号输出端Outn以及第一直流补偿端DCinp和第二直流补偿端DCinn；所述第一信号输入端Inp和第二信号输入端Inn分别用于输入输入信号inp和inn；所述直流补偿端DCinp和DCinn分别用于输入补偿信号dcinp和dcinn，所述第一信号输出端Outp和第二信号输出端Outn分别用于输出第一输出信号outp1和outn1；所述第一输出信号outp1和outn1由输入级将输入信号inp和inn和补偿信号dcinp和dcinn进行处理后产生；所述放大级的同相输入端和反相输入端分别与第一信号输出端Outp和第二信号输出端Outn相连，所述放大级用于对第一输出信号outp1和outn1对进行放大以产生第二输出信号outp2和outn2；所述输出缓冲级的同相输入端和反相输入端与放大级的同相输出端和反相输出端相连，所述输出缓冲级用于缓冲第二输出信号outp2和outn2以产生输出信号outp和outn；所述电压比较器的同相输入端通过低通滤波器与输出缓冲级的同相输出端相连；所述电压比较器的反相输入端通过低通滤波器与输出缓冲级的反相输出端相连；两个所述低通滤波器用于对输出缓冲级的输出信号outp和outn分别进行滤波以提取输出信号outp和outn中的一对共模输出信号G1和G2；所述电压比较器用于对该共模输出信号G1和G2进行比较并将比较结果转化为数字逻辑信号DLS；所述微处理器与电压比较器的输出端相连；所述微处理器用于接收所述数字逻辑信号DLS并根据所述数字逻辑信号DLS产生数字控制信号DCS；所述数模转化器的数字信号输入端Din与微处理器相连，所述数模转换器的第一模拟信号输出端Aoutp和第二模拟信号输出端Aoutn分别与输出级的第一直流补偿端DCinp和第二直流补偿端DCinn相连，所述数模转换器用于接收数字控制信号DCS并根据数字控制信号DCS产生一对补偿信号dcinp和dcinn并分别输出到输入级的第一直流补偿端DCinp和第二直流补偿端DCinn。
所述数模转换器的数字信号输入端Din共有n个，n为大于等于2的正整数；n个数字信号输入端Din依次为第一数字信号输入端Din（1）到第n数字信号输入端Din（n）；所述数模转换器的数字信号输入端Din通过数字总线与微处理器相连；所述数模转换器包括第一转换电阻R01、第二转换电阻R02以及n个转换电路，n个转换电路依次为第一转换电路到第n转换电路；第一转换电阻R01的一端和第二转换电阻R02的一端接地；第一转换电路包括第一反相器F1、第一电流源i1、第一正相可控开关S1和第一反相可控开关K1，第一电流源i1的输入端连接工作电源VDD，第一电流源i1的输出端连接第一正相可控开关S1的输入端和第一反相可控开关K1的输入端；第一电流源i1的输出电流为i（0）；第一反相器F1的输入端连接第一数字信号输入端Din（1），第一反相器F1的输出端连接第一反相可控开关K1的控制端；第一反相可控开关K1的输出端连接第一转换电阻R01的另一端和所述数模转换器的第二模拟信号输出端Aoutn；第一正相可控开关S1的控制端连接第一数字信号输入端Din（1），第一正相可控开关S1的输出端连接第二转换电阻R02的另一端以及第一模拟信号输出端DCinp；第n转换电路包括第n反相器Fn、第n电流源in、第n正相可控开关Sn和第n反相可控开关Kn，第n电流源in的输入端连接工作电源VDD，第n电流源in的输出端连接第n正相可控开关Sn的输入端和第n反相可控开关Kn的输入端；第n电流源in的输出电流为i（n），i（n）等于2的n次方个i（0）；第n反相器Fn的输入端连接第n数字信号输入端Din（n），第n反相器Fn的输出端连接第n反相可控开关Kn的控制端；第n反相可控开关Kn的输出端连接第一转换电阻R01的另一端和所述数模转换器的第二模拟信号输出端Aoutn；第n正相可控开关Sn的控制端连接第n数字信号输入端Din（n），第n正相可控开关Sn的输出端连接第二转换电阻R02的另一端以及第一模拟信号输出端DCinp；第一正相可控开关S1到第n正相可控开关Sn以及第一反相可控开关K1到第n反相可控开关Kn的控制电平均相同。
所述输入级包括第一电阻R1、第二电阻R2、第一NMOS管Q1、第二NMOS管Q2、第三NMOS管Q3、第四NMOS管Q4、第一恒流源I0、第一压控电流源I1以及第二压控电流源I2；所述第一电阻R1一端连接工作电源VDD，第一电阻R1的另一端连接第一NMOS管Q1的漏极以及第三NMOS管Q3的漏极；所述第二电阻R2一端连接工作电源VDD，第二电阻R2的另一端连接第二NMOS管Q2的漏极以及第四NMOS管Q4的漏极；所述第一恒流源I0的输入端连接第一NMOS管Q1的源极以及第二NMOS管Q2的源极，第一恒流源I0的输出端接地；所述第一压控电流源I1的输入端连接第三NMOS管Q3的源极，第一压控电流源I1的输出端接地；所述第二压控电流源I2的输入端连接第四NMOS管Q4的源极，第二压控电流源I2的输出端接地；所述第一压控电流源I1的控制端与第二压控电流源I2的控制端分别为所述输入级的第二直流补偿端DCinn和第一直流补偿端DCinp；所述第三NMOS管Q3的栅极和第四NMOS管Q4的栅极连接偏置电源Vref；所述第三NMOS管Q3与第一NMOS管Q1以及第一电阻R1的公共端为所述输入级的第二信号输出端Outn；所述第四NMOS管Q4与第二NMOS管Q2以及第二电阻R2的公共端为所述输入级的第一信号输出端Outp；所述第一NMOS管Q1的栅极和第二NMOS管Q2的栅极分别为所述输入级的第一信号输入端Inp和第二信号输入端Inn。
所述输入级包括第三电阻R3、第四电阻R4、第五NMOS管Q5、第六NMOS管Q6、第七NMOS管Q7、第八NMOS管Q8、第二恒流源I3以及第三恒流源I4；所述第三电阻R3一端连接工作电源VDD，第三电阻R3的另一端连接第五NMOS管Q5的漏极以及第七NMOS管Q7的漏极；所述第四电阻R4一端连接工作电源VDD，第四电阻R4的另一端连接第六NMOS管Q6的漏极以及第八NMOS管Q8的漏极；所述第二恒流源I3的输入端连接第五NMOS管Q5的源极以及第六NMOS管Q6的源极，第二恒流源I3的输出端接地；所述第三恒流源I4的输入端连接第七NMOS管Q7的源极以及第八NMOS管Q8的源极，第三恒流源I4的输出端接地；所述第七NMOS管Q7的栅极和第八NMOS管Q8的栅极分别为所述输入级的第二直流补偿端DCinn和第一直流补偿端DCinp；所述第七NMOS管Q7与第五NMOS管Q5以及第三电阻R3的公共端为所述输入级的第二信号输出端Outn；所述第八NMOS管Q8与第六NMOS管Q6以及第四电阻R4的公共端为所述输入级的第一信号输出端Outp；所述第五NMOS管Q5的栅极和第六NMOS管Q6的栅极分别为所述输入级的第一信号输入端Inp和第二信号输入端Inn。
所述输入级包括第五电阻R5、第六电阻R6、第七电阻R7、第八电阻R8、电容C1、第九NMOS管Q9、第十NMOS管Q10以及第四恒流源I5；所述第五电阻R5一端连接工作电源VDD，第五电阻R5的另一端连接第九NMOS管Q9的漏极；所述第五电阻R5与第九NMOS管Q9的公共端为所述输入级的第二信号输出端Outn；所述第六电阻R6一端连接工作电源VDD，第六电阻R6的另一端连接第十NMOS管Q10；所述第六电阻R6与第十NMOS管Q10的公共端为所述输入级的第一信号输出端Outp；所述第七电阻R7一端连接第九NMOS管Q9的栅极，第七电阻R7的另一端连接电容C1的一端；所述第七电阻R7与第九NMOS管Q9的公共端为所述输入级的第一信号输入端Inp；所述第七电阻R7与电容C1的公共端为所述输入级的第二直流补偿端DCinn；所述第八电阻R8一端连接第十NMOS管Q10的栅极，第八电阻R8的另一端连接电容C1的另一端；所述第八电阻R8与第十NMOS管Q10的公共端为所述输入级的第二信号输入端Inn；所述第八电阻R8与电容C1的公共端为所述输入级的第一直流补偿端DCinp；所述第四恒流源I5的输入端连接第九NMOS管Q9的源极以及第十NMOS管Q10的源极，第四恒流源I5的输出端接地。
一种直流失调消除方法，所述消除方法基于上述的直流失调消除电路；所述消除方法应用于所述输入级的第一信号输入端Inp和第二信号输入端Inn没有输入信号inn和inp输入的应用环境，所述直流失调消除方法依次包括：
步骤一：微处理器预设一个十进制的初值并将该初值赋值给数字控制信号DCS；然后数模转换器接收数字控制信号DCS并根据数字控制信号DCS产生相应的补偿信号dcinp和dcinn以输出给输出级进行补偿；
步骤二：利用低通滤波器提出输出级的输出信号outp和outn中的共模输出信号G1和G2；然后电压比较器对共模输出信号G1和G2进行比较以输出数字逻辑信号DLS；其中当共模输出信号G1大于共模输出信号G2时，电压比较器输出的数字逻辑信号DLS为高电平；当共模输出信号G1小于共模输出信号G2时，电压比较器输出的数字逻辑信号DLS为低电平；
步骤三：微处理器读取电压比较器产生的数字逻辑信号DLS并对数字逻辑信号DLS进行判断，若数字逻辑信号DLS为高电平，则进入步骤四；若数字逻辑信号DLS为低电平，则进入步骤五；
步骤四：微处理器对初值的数值进行加一处理并将处理后的初值赋值给数字控制信号DCS，其次数模转换器根据数字控制信号DCS再产生相应的补偿信号dcinp和dcinn以输出给输出级进行补偿，然后重复步骤二，接着微处理器再次读取电压比较器的数字逻辑信号DLS并进行判断，若数字逻辑信号DLS为低电平，则微处理器保持数字控制信号DCS的赋值不变，否则重复步骤四；
步骤五：微处理器对初值的数值进行减一处理并将处理后的初值赋值给数字控制信号DCS，其次数模转换器根据数字控制信号DCS再产生相应的补偿信号dcinp和dcinn以输出给输出级进行补偿，然后重复步骤二，接着微处理器再次读取电压比较器的数字逻辑信号DLS并进行判断，若数字逻辑信号DLS为高电平，则微处理器保持数字控制信号DCS的赋值不变，否则重复步骤五。
采用上述方案后，本发明的所述直流失调消除电路是通过数字模拟混合控制方法来提供补偿信号dcinp和dcinn给输入级以对高速放大器进行直流失调消除，所述直流失调消除电路具有微处理器，因此通过微处理器能锁定补偿信号dcinp和dcinn以保证稳定消除工艺问题造成的直流失调消除，这样即使后续输入输入信号inp和inn时，锁定的补偿信号dcinp和dcinn还处于锁定状态，不会受到输入信号inp和inn的影响，所述的直流失调消除电路便可以只消除由于工艺问题造成的直流失调，能避免现有技术中存在由补偿信号没有根据输入信号inp和inn的变化而及时进行相应的变化以使得高速放大器不能正常工作的问题，因此所述的直流失调消除电路能工作在输入信号inp和inn幅度变化大且变化不连续时。
而本发明的所述直流失调消除方法，可以在高速放大器的输入级的没有输入信号inp和inn时，利用所述直流失调消除电路来产生补偿信号dcinp和dcinn以消除高速放大器由于工艺问题造成的直流失调，并且通过微处理器可以把补偿信号dcinp和dcinn锁定以保证稳定消除工艺问题造成的直流失调消除，这样后续输入的输入信号inp和inn幅度变化大且变化不连续时，能保证锁定的补偿信号dcinp和dcinn还处于锁定状态，不受输入信号inp和inn的影响，能避免现有技术中由补偿信号没有根据输入信号inp和inn的变化而及时进行相应的变化以使得高速放大器不能正常工作的问题。
附图说明
图1为现有的直流失调消除电路的结构示意图；
图2为本发明的直流失调消除电路的结构示意图；
图3为本发明的数模转化器的结构示意图；
图4为本发明的输入级的第一种结构示意图；
图5为本发明的输入级的第二种结构示意图；
图6为本发明的输入级的第三种结构示意图；
图7为本发明的直流失调消除方法的流程图。
具体实施方式
为了进一步解释本发明的技术方案，下面通过具体实施例来对本发明进行详细阐述。
如图2至图6所示，本发明揭示了一种直流失调消除电路，其包括高速放大器、电压比较器、微处理器以及数模转换器；所述高速放大器包括具有直流失调消除功能的输入级、放大级以及输出缓冲级；所述输入级具有第一信号输入端Inp、第二信号输入端Inn、第一信号输出端Outp、第二信号输出端Outn以及第一直流补偿端DCinp和第二直流补偿端DCinn；所述第一信号输入端Inp和第二信号输入端Inn分别用于输入输入信号inp和inn；所述直流补偿端DCinp和DCinn分别用于输入补偿信号dcinp和dcinn，所述第一信号输出端Outp和第二信号输出端Outn分别用于输出第一输出信号outp1和outn1；所述第一输出信号outp1和outn1由输入级将输入信号inp和inn和补偿信号dcinp和dcinn进行处理后产生；所述放大级的同相输入端和反相输入端分别与第一信号输出端Outp和第二信号输出端Outn相连，所述放大级用于对第一输出信号outp1和outn1对进行放大以产生第二输出信号outp2和outn2；所述输出缓冲级的同相输入端和反相输入端与放大级的同相输出端和反相输出端相连，所述输出缓冲级用于缓冲第二输出信号outp2和outn2以产生输出信号outp和outn；所述电压比较器的同相输入端通过低通滤波器与输出缓冲级的同相输出端相连；所述电压比较器的反相输入端通过低通滤波器与输出缓冲级的反相输出端相连；两个所述低通滤波器用于对输出缓冲级的输出信号outp和outn分别进行滤波以提取输出信号outp和outn中的一对共模输出信号G1和G2；所述电压比较器用于对该共模输出信号G1和G2进行比较并将比较结果转化为数字逻辑信号DLS；所述微处理器与电压比较器的输出端相连；所述微处理器用于接收所述数字逻辑信号DLS并根据所述数字逻辑信号DLS产生数字控制信号DCS；所述数模转化器的数字信号输入端Din与微处理器相连，所述数模转换器的第一模拟信号输出端Aoutp和第二模拟信号输出端Aoutn分别与输出级的第一直流补偿端DCinp和第二直流补偿端DCinn相连，所述数模转换器用于接收数字控制信号DCS并根据数字控制信号DCS产生一对补偿信号dcinp和dcinn并分别输出到输入级的第一直流补偿端DCinp和第二直流补偿端DCinn。
本发明的所述直流失调消除电路是通过数字模拟混合控制方法来提供补偿信号dcinp和dcinn给输入级以对高速放大器进行直流失调消除，所述直流失调消除电路具有微处理器，因此通过微处理器能锁定补偿信号dcinp和dcinn以保证稳定消除工艺问题造成的直流失调消除，这样即使后续输入输入信号inp和inn时，锁定的补偿信号dcinp和dcinn还处于锁定状态，不会受到输入信号inp和inn的影响，所述的直流失调消除电路便可以只消除由于工艺问题造成的直流失调，能避免现有技术中存在由补偿信号没有根据输入信号inp和inn的变化而及时进行相应的变化以使得高速放大器不能正常工作的问题，因此所述的直流失调消除电路能工作在输入信号inp和inn幅度变化大且变化不连续时。
为便于理解所述直流失调消除电路，下面具体阐述一下数模转换器和输入级的电路结构；而放大级可以为现有技术中的差分放大器和和限幅放大器的结合；输出缓冲级可以为输出缓冲器；所述低通滤波器和电压比较器均为本技术领域的常用技术就不在展开说明。
配合图3所示，所述数模转换器的数字信号输入端Din共有n个，n为大于等于2的正整数；n个数字信号输入端Din依次为第一数字信号输入端Din（1）到第n数字信号输入端Din（n）；所述数模转换器的数字信号输入端Din通过数字总线与微处理器相连；所述数模转换器包括第一转换电阻R01、第二转换电阻R02以及n个转换电路，n个转换电路依次为第一转换电路到第n转换电路；第一转换电阻R01的一端和第二转换电阻R02的一端接地；第一转换电路包括第一反相器F1、第一电流源i1、第一正相可控开关S1和第一反相可控开关K1，第一电流源i1的输入端连接工作电源VDD，第一电流源i1的输出端连接第一正相可控开关S1的输入端和第一反相可控开关K1的输入端；第一电流源i1的输出电流为i（0）；第一反相器F1的输入端连接第一数字信号输入端Din（1），第一反相器F1的输出端连接第一反相可控开关K1的控制端；第一反相可控开关K1的输出端连接第一转换电阻R01的另一端和所述数模转换器的第二模拟信号输出端Aoutn；第一正相可控开关S1的控制端连接第一数字信号输入端Din（1），第一正相可控开关S1的输出端连接第二转换电阻R02的另一端以及第一模拟信号输出端DCinp；第n转换电路包括第n反相器Fn、第n电流源in、第n正相可控开关Sn和第n反相可控开关Kn，第n电流源in的输入端连接工作电源VDD，第n电流源in的输出端连接第n正相可控开关Sn的输入端和第n反相可控开关Kn的输入端；第n电流源in的输出电流为i（n），i（n）等于2的n次方个i（0）；第n反相器Fn的输入端连接第n数字信号输入端Din（n），第n反相器Fn的输出端连接第n反相可控开关Kn的控制端；第n反相可控开关Kn的输出端连接第一转换电阻R01的另一端和所述数模转换器的第二模拟信号输出端Aoutn；第n正相可控开关Sn的控制端连接第n数字信号输入端Din（n），第n正相可控开关Sn的输出端连接第二转换电阻R02的另一端以及第一模拟信号输出端DCinp；第一正相可控开关S1到第n正相可控开关Sn以及第一反相可控开关K1到第n反相可控开关Kn的控制电平均相同。
本发明提供了三种输入级的结构，其中配合图4所示，所述输入级可以包括第一电阻R1、第二电阻R2、第一NMOS管Q1、第二NMOS管Q2、第三NMOS管Q3、第四NMOS管Q4、第一恒流源I0、第一压控电流源I1以及第二压控电流源I2；所述第一电阻R1一端连接工作电源VDD，第一电阻R1的另一端连接第一NMOS管Q1的漏极以及第三NMOS管Q3的漏极；所述第二电阻R2一端连接工作电源VDD，第二电阻R2的另一端连接第二NMOS管Q2的漏极以及第四NMOS管Q4的漏极；所述第一恒流源I0的输入端连接第一NMOS管Q1的源极以及第二NMOS管Q2的源极，第一恒流源I0的输出端接地；所述第一压控电流源I1的输入端连接第三NMOS管Q3的源极，第一压控电流源I1的输出端接地；所述第二压控电流源I2的输入端连接第四NMOS管Q4的源极，第二压控电流源I2的输出端接地；所述第一压控电流源I1的控制端与第二压控电流源I2的控制端分别为所述输入级的第二直流补偿端DCinn和第一直流补偿端DCinp；所述第三NMOS管Q3的栅极和第四NMOS管Q4的栅极连接偏置电源Vref；所述第三NMOS管Q3与第一NMOS管Q1以及第一电阻R1的公共端为所述输入级的第二信号输出端Outn；所述第四NMOS管Q4与第二NMOS管Q2以及第二电阻R2的公共端为所述输入级的第一信号输出端Outp；所述第一NMOS管Q1的栅极和第二NMOS管Q2的栅极分别为所述输入级的第一信号输入端Inp和第二信号输入端Inn。
配合图5所示，所述输入级也可以是包括第三电阻R3、第四电阻R4、第五NMOS管Q5、第六NMOS管Q6、第七NMOS管Q7、第八NMOS管Q8、第二恒流源I3以及第三恒流源I4；所述第三电阻R3一端连接工作电源VDD，第三电阻R3的另一端连接第五NMOS管Q5的漏极以及第七NMOS管Q7的漏极；所述第四电阻R4一端连接工作电源VDD，第四电阻R4的另一端连接第六NMOS管Q6的漏极以及第八NMOS管Q8的漏极；所述第二恒流源I3的输入端连接第五NMOS管Q5的源极以及第六NMOS管Q6的源极，第二恒流源I3的输出端接地；所述第三恒流源I4的输入端连接第七NMOS管Q7的源极以及第八NMOS管Q8的源极，第三恒流源I4的输出端接地；所述第七NMOS管Q7的栅极和第八NMOS管Q8的栅极分别为所述输入级的第二直流补偿端DCinn和第一直流补偿端DCinp；所述第七NMOS管Q7与第五NMOS管Q5以及第三电阻R3的公共端为所述输入级的第二信号输出端Outn；所述第八NMOS管Q8与第六NMOS管Q6以及第四电阻R4的公共端为所述输入级的第一信号输出端Outp；所述第五NMOS管Q5的栅极和第六NMOS管Q6的栅极分别为所述输入级的第一信号输入端Inp和第二信号输入端Inn。
配合图6所示，所述输入级还可以是包括第五电阻R5、第六电阻R6、第七电阻R7、第八电阻R8、电容C1、第九NMOS管Q9、第十NMOS管Q10以及第四恒流源I5；所述第五电阻R5一端连接工作电源VDD，第五电阻R5的另一端连接第九NMOS管Q9的漏极；所述第五电阻R5与第九NMOS管Q9的公共端为所述输入级的第二信号输出端Outn；所述第六电阻R6一端连接工作电源VDD，第六电阻R6的另一端连接第十NMOS管Q10；所述第六电阻R6与第十NMOS管Q10的公共端为所述输入级的第一信号输出端Outp；所述第七电阻R7一端连接第九NMOS管Q9的栅极，第七电阻R7的另一端连接电容C1的一端；所述第七电阻R7与第九NMOS管Q9的公共端为所述输入级的第一信号输入端Inp；所述第七电阻R7与电容C1的公共端为所述输入级的第二直流补偿端DCinn；所述第八电阻R8一端连接第十NMOS管Q10的栅极，第八电阻R8的另一端连接电容C1的另一端；所述第八电阻R8与第十NMOS管Q10的公共端为所述输入级的第二信号输入端Inn；所述第八电阻R8与电容C1的公共端为所述输入级的第一直流补偿端DCinp；所述第四恒流源I5的输入端连接第九NMOS管Q9的源极以及第十NMOS管Q10的源极，第四恒流源I5的输出端接地。
本发明还提供了一种直流失调消除方法，所述消除方法基于上述的直流失调消除电路；所述消除方法应用于所述输入级的第一信号输入端Inp和第二信号输入端Inn没有输入信号inn和inp输入的应用环境，配合图7所示，所述直流失调消除方法依次包括：
步骤一S1：微处理器预设一个十进制的初值并将该初值赋值给数字控制信号DCS；然后数模转换器接收数字控制信号DCS并根据数字控制信号DCS产生相应的补偿信号dcinp和dcinn以输出给输出级进行补偿；
步骤二S2：利用低通滤波器提出输出级的输出信号outp和outn中的共模输出信号G1和G2；然后电压比较器对共模输出信号G1和G2进行比较以输出数字逻辑信号DLS；其中当共模输出信号G1大于共模输出信号G2时，电压比较器输出的数字逻辑信号DLS为高电平；当共模输出信号G1小于共模输出信号G2时，电压比较器输出的数字逻辑信号DLS为低电平；
步骤三S3：微处理器读取电压比较器产生的数字逻辑信号DLS并对数字逻辑信号DLS进行判断，若数字逻辑信号DLS为高电平，则进入步骤四；若数字逻辑信号DLS为低电平，则进入步骤五；
骤四S4：微处理器对初值的数值进行加一处理并将处理后的初值赋值给数字控制信号DCS，其次数模转换器根据数字控制信号DCS再产生相应的补偿信号dcinp和dcinn以输出给输出级进行补偿，然后重复步骤二，接着微处理器再次读取电压比较器的数字逻辑信号DLS并进行判断，若数字逻辑信号DLS为低电平，则微处理器保持数字控制信号DCS的赋值不变，否则重复步骤四；补偿信号dcinp和dcinn锁定以保证稳定消除工艺问题造成的直流失调消除；
步骤五S5：微处理器对初值的数值进行减一处理并将处理后的初值赋值给数字控制信号DCS，其次数模转换器根据数字控制信号DCS再产生相应的补偿信号dcinp和dcinn以输出给输出级进行补偿，然后重复步骤二，接着微处理器再次读取电压比较器的数字逻辑信号DLS并进行判断，若数字逻辑信号DLS为高电平，则微处理器保持数字控制信号DCS的赋值不变，否则重复步骤五。
当微处理器保持数字控制信号DCS的赋值不变时，此时认定数模转换器通过此时的数字控制信号DCS产生补偿信号dcinp和dcinn已经消除工艺问题造成的直流失调消除，且微处理器保持数字控制信号DCS赋值不变，则相应的补偿信号dcinp和dcinn也不变，即补偿信号dcinp和dcinn被锁定。因此通过所述直流失调消除方法，可以在高速放大器的输入级的没有输入信号inp和inn时，利用所述直流失调消除电路来产生补偿信号dcinp和dcinn以消除高速放大器由于工艺问题造成的直流失调，并且通过微处理器可以把补偿信号dcinp和dcinn锁定以保证稳定消除工艺问题造成的直流失调消除，这样后续输入的输入信号inp和inn幅度变化大且变化不连续时，微处理器还能保证锁定的补偿信号dcinp和dcinn还处于锁定状态，不受输入信号inp和inn影响，因此所述的直流失调消除电路只消除了由于工艺问题造成的直流失调，能避免现有技术中由补偿信号没有根据输入信号inp和inn的变化而及时进行相应的变化以使得高速放大器不能正常工作的问题。
上述实施例和图式并非限定本发明的产品形态和式样，任何所属技术领域的普通技术人员对其所做的适当变化或修饰，皆应视为不脱离本发明的专利范畴。

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  1. 一种直流失调消除电路，其特征在于：包括高速放大器、电压比较器、微处理器以及数模转换器；
    所述高速放大器包括具有直流失调消除功能的输入级、放大级以及输出缓冲级；所述输入级具有第一信号输入端Inp、第二信号输入端Inn、第一信号输出端Outp、第二信号输出端Outn以及第一直流补偿端DCinp和第二直流补偿端DCinn；所述第一信号输入端Inp和第二信号输入端Inn分别用于输入输入信号inp和inn；所述直流补偿端DCinp和DCinn分别用于输入补偿信号dcinp和dcinn，所述第一信号输出端Outp和第二信号输出端Outn分别用于输出第一输出信号outp1和outn1；所述第一输出信号outp1和outn1由输入级将输入信号inp和inn和补偿信号dcinp和dcinn进行处理后产生；所述放大级的同相输入端和反相输入端分别与第一信号输出端Outp和第二信号输出端Outn相连，所述放大级用于对第一输出信号outp1和outn1对进行放大以产生第二输出信号outp2和outn2；所述输出缓冲级的同相输入端和反相输入端与放大级的同相输出端和反相输出端相连，所述输出缓冲级用于缓冲第二输出信号outp2和outn2以产生输出信号outp和outn；
    所述电压比较器的同相输入端通过低通滤波器与输出缓冲级的同相输出端相连；所述电压比较器的反相输入端通过低通滤波器与输出缓冲级的反相输出端相连；两个所述低通滤波器用于对输出缓冲级的输出信号outp和outn分别进行滤波以提取输出信号outp和outn中的一对共模输出信号G1和G2；所述电压比较器用于对该共模输出信号G1和G2进行比较并将比较结果转化为数字逻辑信号DLS；
    所述微处理器与电压比较器的输出端相连；所述微处理器用于接收所述数字逻辑信号DLS并根据所述数字逻辑信号DLS产生数字控制信号DCS；
    所述数模转化器的数字信号输入端Din与微处理器相连，所述数模转换器的第一模拟信号输出端Aoutp和第二模拟信号输出端Aoutn分别与输出级的第一直流补偿端DCinp和第二直流补偿端DCinn相连，所述数模转换器用于接收数字控制信号DCS并根据数字控制信号DCS产生一对补偿信号dcinp和dcinn并分别输出到输入级的第一直流补偿端DCinp和第二直流补偿端DCinn。
  2. 如权利要求1所述的直流失调消除电路，其特征在于：所述数模转换器的数字信号输入端Din共有n个，n为大于等于2的正整数；n个数字信号输入端Din依次为第一数字信号输入端Din（1）到第n数字信号输入端Din（n）；所述数模转换器的数字信号输入端Din通过数字总线与微处理器相连；
    所述数模转换器包括第一转换电阻R01、第二转换电阻R02以及n个转换电路，n个转换电路依次为第一转换电路到第n转换电路；第一转换电阻R01的一端和第二转换电阻R02的一端接地；
    第一转换电路包括第一反相器F1、第一电流源i1、第一正相可控开关S1和第一反相可控开关K1，第一电流源i1的输入端连接工作电源VDD，第一电流源i1的输出端连接第一正相可控开关S1的输入端和第一反相可控开关K1的输入端；第一电流源i1的输出电流为i（0）；第一反相器F1的输入端连接第一数字信号输入端Din（1），第一反相器F1的输出端连接第一反相可控开关K1的控制端；第一反相可控开关K1的输出端连接第一转换电阻R01的另一端和所述数模转换器的第二模拟信号输出端Aoutn；第一正相可控开关S1的控制端连接第一数字信号输入端Din（1），第一正相可控开关S1的输出端连接第二转换电阻R02的另一端以及第一模拟信号输出端DCinp；
    第n转换电路包括第n反相器Fn、第n电流源in、第n正相可控开关Sn和第n反相可控开关Kn，第n电流源in的输入端连接工作电源VDD，第n电流源in的输出端连接第n正相可控开关Sn的输入端和第n反相可控开关Kn的输入端；第n电流源in的输出电流为i（n），i（n）等于2的n次方个i（0）；第n反相器Fn的输入端连接第n数字信号输入端Din（n），第n反相器Fn的输出端连接第n反相可控开关Kn的控制端；第n反相可控开关Kn的输出端连接第一转换电阻R01的另一端和所述数模转换器的第二模拟信号输出端Aoutn；第n正相可控开关Sn的控制端连接第n数字信号输入端Din（n），第n正相可控开关Sn的输出端连接第二转换电阻R02的另一端以及第一模拟信号输出端DCinp；
    第一正相可控开关S1到第n正相可控开关Sn以及第一反相可控开关K1到第n反相可控开关Kn的控制电平均相同。
  3. 如权利要求2所述的直流失调消除电路，其特征在于：所述输入级包括第一电阻R1、第二电阻R2、第一NMOS管Q1、第二NMOS管Q2、第三NMOS管Q3、第四NMOS管Q4、第一恒流源I0、第一压控电流源I1以及第二压控电流源I2；
    所述第一电阻R1一端连接工作电源VDD，第一电阻R1的另一端连接第一NMOS管Q1的漏极以及第三NMOS管Q3的漏极；
    所述第二电阻R2一端连接工作电源VDD，第二电阻R2的另一端连接第二NMOS管Q2的漏极以及第四NMOS管Q4的漏极；
    所述第一恒流源I0的输入端连接第一NMOS管Q1的源极以及第二NMOS管Q2的源极，第一恒流源I0的输出端接地；
    所述第一压控电流源I1的输入端连接第三NMOS管Q3的源极，第一压控电流源I1的输出端接地；所述第二压控电流源I2的输入端连接第四NMOS管Q4的源极，第二压控电流源I2的输出端接地；所述第一压控电流源I1的控制端与第二压控电流源I2的控制端分别为所述输入级的第二直流补偿端DCinn和第一直流补偿端DCinp；
    所述第三NMOS管Q3的栅极和第四NMOS管Q4的栅极连接偏置电源Vref；所述第三NMOS管Q3与第一NMOS管Q1以及第一电阻R1的公共端为所述输入级的第二信号输出端Outn；所述第四NMOS管Q4与第二NMOS管Q2以及第二电阻R2的公共端为所述输入级的第一信号输出端Outp；所述第一NMOS管Q1的栅极和第二NMOS管Q2的栅极分别为所述输入级的第一信号输入端Inp和第二信号输入端Inn。
  4. 如权利要求2所述的直流失调消除电路，其特征在于：所述输入级包括第三电阻R3、第四电阻R4、第五NMOS管Q5、第六NMOS管Q6、第七NMOS管Q7、第八NMOS管Q8、第二恒流源I3以及第三恒流源I4；
    所述第三电阻R3一端连接工作电源VDD，第三电阻R3的另一端连接第五NMOS管Q5的漏极以及第七NMOS管Q7的漏极；
    所述第四电阻R4一端连接工作电源VDD，第四电阻R4的另一端连接第六NMOS管Q6的漏极以及第八NMOS管Q8的漏极；
    所述第二恒流源I3的输入端连接第五NMOS管Q5的源极以及第六NMOS管Q6的源极，第二恒流源I3的输出端接地；
    所述第三恒流源I4的输入端连接第七NMOS管Q7的源极以及第八NMOS管Q8的源极，第三恒流源I4的输出端接地；
    所述第七NMOS管Q7的栅极和第八NMOS管Q8的栅极分别为所述输入级的第二直流补偿端DCinn和第一直流补偿端DCinp；所述第七NMOS管Q7与第五NMOS管Q5以及第三电阻R3的公共端为所述输入级的第二信号输出端Outn；所述第八NMOS管Q8与第六NMOS管Q6以及第四电阻R4的公共端为所述输入级的第一信号输出端Outp；所述第五NMOS管Q5的栅极和第六NMOS管Q6的栅极分别为所述输入级的第一信号输入端Inp和第二信号输入端Inn。
  5. 如权利要求2所述的直流失调消除电路，其特征在于：所述输入级包括第五电阻R5、第六电阻R6、第七电阻R7、第八电阻R8、电容C1、第九NMOS管Q9、第十NMOS管Q10以及第四恒流源I5；
    所述第五电阻R5一端连接工作电源VDD，第五电阻R5的另一端连接第九NMOS管Q9的漏极；所述第五电阻R5与第九NMOS管Q9的公共端为所述输入级的第二信号输出端Outn；
    所述第六电阻R6一端连接工作电源VDD，第六电阻R6的另一端连接第十NMOS管Q10；所述第六电阻R6与第十NMOS管Q10的公共端为所述输入级的第一信号输出端Outp；
    所述第七电阻R7一端连接第九NMOS管Q9的栅极，第七电阻R7的另一端连接电容C1的一端；所述第七电阻R7与第九NMOS管Q9的公共端为所述输入级的第一信号输入端Inp；所述第七电阻R7与电容C1的公共端为所述输入级的第二直流补偿端DCinn；
    所述第八电阻R8一端连接第十NMOS管Q10的栅极，第八电阻R8的另一端连接电容C1的另一端；所述第八电阻R8与第十NMOS管Q10的公共端为所述输入级的第二信号输入端Inn；所述第八电阻R8与电容C1的公共端为所述输入级的第一直流补偿端DCinp；
    所述第四恒流源I5的输入端连接第九NMOS管Q9的源极以及第十NMOS管Q10的源极，第四恒流源I5的输出端接地。
  6. 一种直流失调消除方法，其特征在于：所述消除方法基于权利要求1至5任意一项所述的直流失调消除电路；所述消除方法应用于所述输入级的第一信号输入端Inp和第二信号输入端Inn没有输入信号inn和inp输入的应用环境，所述直流失调消除方法依次包括：
    步骤一：微处理器预设一个十进制的初值并将该初值赋值给数字控制信号DCS；然后数模转换器接收数字控制信号DCS并根据数字控制信号DCS产生相应的补偿信号dcinp和dcinn以输出给输出级进行补偿；
    步骤二：利用低通滤波器提出输出级的输出信号outp和outn中的共模输出信号G1和G2；然后电压比较器对共模输出信号G1和G2进行比较以输出数字逻辑信号DLS；其中当共模输出信号G1大于共模输出信号G2时，电压比较器输出的数字逻辑信号DLS为高电平；当共模输出信号G1小于共模输出信号G2时，电压比较器输出的数字逻辑信号DLS为低电平；
    步骤三：微处理器读取电压比较器产生的数字逻辑信号DLS并对数字逻辑信号DLS进行判断，若数字逻辑信号DLS为高电平，则进入步骤四；若数字逻辑信号DLS为低电平，则进入步骤五；
    步骤四：微处理器对初值的数值进行加一处理并将处理后的初值赋值给数字控制信号DCS，其次数模转换器根据数字控制信号DCS再产生相应的补偿信号dcinp和dcinn以输出给输出级进行补偿，然后重复步骤二，接着微处理器再次读取电压比较器的数字逻辑信号DLS并进行判断，若数字逻辑信号DLS为低电平，则微处理器保持数字控制信号DCS的赋值不变，否则重复步骤四；
    步骤五：微处理器对初值的数值进行减一处理并将处理后的初值赋值给数字控制信号DCS，其次数模转换器根据数字控制信号DCS再产生相应的补偿信号dcinp和dcinn以输出给输出级进行补偿，然后重复步骤二，接着微处理器再次读取电压比较器的数字逻辑信号DLS并进行判断，若数字逻辑信号DLS为高电平，则微处理器保持数字控制信号DCS的赋值不变，否则重复步骤五。
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