WO2019169524A1 - 波形信号检测方法及装置 - Google Patents

波形信号检测方法及装置 Download PDF

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Publication number
WO2019169524A1
WO2019169524A1 PCT/CN2018/077995 CN2018077995W WO2019169524A1 WO 2019169524 A1 WO2019169524 A1 WO 2019169524A1 CN 2018077995 W CN2018077995 W CN 2018077995W WO 2019169524 A1 WO2019169524 A1 WO 2019169524A1
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Prior art keywords
electrical signal
capture
sequence number
termination condition
waveform
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PCT/CN2018/077995
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English (en)
French (fr)
Inventor
冯春忆
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深圳市汇顶科技股份有限公司
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Application filed by 深圳市汇顶科技股份有限公司 filed Critical 深圳市汇顶科技股份有限公司
Priority to PCT/CN2018/077995 priority Critical patent/WO2019169524A1/zh
Priority to CN201880000261.XA priority patent/CN110446936B/zh
Publication of WO2019169524A1 publication Critical patent/WO2019169524A1/zh

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer

Definitions

  • the embodiments of the present invention relate to the field of circuit technologies, and in particular, to a waveform signal detecting method and apparatus.
  • I/O Input/Output, Input/Output
  • PWM Pulse Width Modulation
  • GPIO General
  • Purpose Input Output general-purpose input/output module, etc.
  • the common method of verification is to connect an external test device such as an oscilloscope or a logic analyzer to the I/O pin, and display the oscilloscope with a third-party software tool for the oscilloscope or logic analyzer. Or the waveform of the I/O pin output captured by the logic analyzer.
  • the staff can observe whether the module can work normally by observing or measuring the waveform output by the oscilloscope or logic analyzer and comparing it with the desired output waveform to determine whether the waveform output by these modules is in line with expectations.
  • one of the technical problems to be solved by the embodiments of the present application is to provide a method and a device for detecting a waveform signal, which are used to overcome the prior art, and verify a module that outputs a waveform through an I/O pin in a chip.
  • the verification efficiency is low.
  • a first aspect of the present application provides a waveform signal detecting method, including: when an acquisition time of a signal acquisition period arrives, the chip reads an electrical signal of a waveform to be measured outputted by the chip through an I/O port; and determines an electrical signal. Corresponding capture sequence number, and obtaining a desired level value corresponding to the capture sequence number from the preset desired output waveform data; if the level value of the electrical signal is consistent with the desired level value, generating an electrical signal corresponding to the capture sequence number
  • the capture record wherein the electrical signal capture record includes the level value and the capture time of the electrical signal; the capture sequence number is updated, and when the next acquisition time arrives, the return chip reads the electrical signal of the waveform to be tested outputted by the chip through the I/O port. The steps continue until the detection termination condition is met.
  • a waveform signal detecting apparatus including: an electrical signal collecting module, configured to read a self-test output of the chip through an I/O port when an acquisition time of a signal acquisition period arrives a waveform electrical signal; a desired level value determining module, configured to determine a capture sequence number corresponding to the electrical signal, and obtain a desired level value corresponding to the capture sequence number from the preset desired output waveform data; and capture the record generation module Generating an electrical signal capture record corresponding to the capture sequence number when the level value of the electrical signal coincides with the desired level value, wherein the electrical signal capture record includes a level value and a capture time of the electrical signal; a sequence number update module is configured to: The capture sequence number is updated, and when the next acquisition time arrives, the return electrical signal acquisition module continues to execute until the detection termination condition is met.
  • the chip periodically reads the electrical signal of the waveform to be tested outputted by itself through the I/O port, and uses the chip to capture the electrical signal of the waveform to be measured outputted by the chip.
  • the chip There is no need to rely on other external test equipment, which avoids the complicated operation of the configuration and connection of the external test equipment, and the problem of low verification efficiency.
  • the captured electrical signal if the level value is consistent with the preset level value, an electrical signal capture record is generated according to the level value and the capture time of the electrical signal, and the electrical signal capture is recorded in the follow-up and expectation.
  • the output waveform is compared and verified, the waveform that is inconsistent with the expectation can be quickly and accurately verified, which further improves the verification efficiency.
  • FIG. 1 is a flow chart showing a waveform signal detecting method according to Embodiment 1 of the present application.
  • FIG. 2 is a schematic flow chart of a waveform signal detecting method according to Embodiment 2 of the present application.
  • FIG. 3 is a schematic diagram showing waveforms corresponding to a desired output waveform data in the embodiment shown in FIG. 2;
  • FIG. 4 is a block diagram showing the structure of a waveform signal detecting apparatus according to Embodiment 3 of the present application.
  • FIG. 5 is a block diagram showing the structure of a waveform signal detecting apparatus according to Embodiment 4 of the present application.
  • FIG. 1 shows a flow chart of a waveform signal detecting method according to an embodiment of the present application.
  • the waveform signal detecting method includes:
  • the chip includes at least one I/O port, and functional modules in the chip are electrically connected to the I/O ports so that electrical signals can be read in or output through the I/O ports.
  • the I/O port of the output waveform (ie, the I/O pin) is used to acquire the electrical signal output from the I/O port of the output waveform.
  • the I/O port of the chip is used to output an electrical signal of the waveform to be measured. Then, if the I/O port can realize both the function of outputting an electrical signal and the function of reading an electrical signal, the chip can read the electrical signal of the waveform to be measured through the I/O port, thereby realizing the use of the chip itself. The output electrical signal is read back.
  • the chip is not limited to this, and the chip can also read the electrical signal of the waveform to be measured by other I/O ports having an electrical signal reading function other than the I/O port, so that the electrical signal output by the chip is read back by the chip. At this time, the two I/O ports need to be electrically connected.
  • the waveform to be tested can be acquired without relying on an external test device, thereby achieving the purpose of detecting the waveform to be measured.
  • a person skilled in the art can set a signal collection period according to requirements, such as a total acquisition duration, an acquisition interval, and the like, which is not specifically limited in this embodiment of the present application.
  • S102 Determine a capture sequence number corresponding to the electrical signal, and obtain a desired level value corresponding to the capture sequence number from the preset expected output waveform data.
  • preset desired output waveform data is pre-stored in the chip.
  • the preset desired output waveform data is used to indicate a desired level value that is output at a desired output time, and a waveform of a desired output can be obtained by a desired output time and a desired level value.
  • a corresponding desired level value can be obtained from the desired output waveform data.
  • the corresponding relationship may be appropriately set by a person skilled in the art according to actual conditions, and an accurate correspondence may be achieved.
  • the capture sequence number corresponding to the currently read electrical signal is determined, and then the desired level value corresponding to the electrical signal is determined. Based on this desired level value, it can be determined whether the electrical signal is a desired electrical signal, thereby determining whether to retain relevant information of the electrical signal.
  • S103 Determine whether the level value of the electrical signal is consistent with the desired level value.
  • the manner of determining whether the read electrical signal is a desired electrical signal may be determined by comparing whether the level value of the electrical signal is equal to the desired level value.
  • S104 If consistent, generating an electrical signal capture record corresponding to the capture sequence number, wherein the electrical signal capture record includes a level value of the electrical signal and a capture time.
  • the electrical signal is the desired electrical signal, and an electrical signal capture record corresponding to the captured sequence number is generated.
  • the electrical signal capture record includes the level value of the electrical signal and the capture time. Those skilled in the art can also set the electrical signal capture record to include other electrical signal related information according to specific test requirements.
  • the time of the acquisition interval can be set small, thereby increasing the frequency of reading the electrical signal.
  • more electrical signals are collected, and some electrical signals have little effect on the detection of the waveform signal, and the electrical signal capture record may not be generated.
  • the electrical signal capture record is generated according to the electrical signal consistent with the desired level value, and the inconsistent electrical signal is not recorded, which can reduce the steps in the detection process and also reduce the occupation of the storage space.
  • S105 Update the capture sequence number, and when the next acquisition time arrives, the step of returning the chip to read the electrical signal of the waveform to be tested outputted by the I/O port continues to be performed until the detection termination condition is satisfied.
  • each desired electrical signal corresponds to a capture sequence number
  • the capture sequence number needs to be updated. For example, the capture sequence number can be incremented by one.
  • the capture sequence number can be incremented by one.
  • the detection termination condition may be appropriately set by a person skilled in the art according to actual conditions, for example, the capture sequence number is greater than a preset maximum capture sequence number, or the acquisition time exceeds a preset acquisition time, or the number of times the electrical signal is read exceeds a preset maximum. The number of readings and the like, thereby collecting an electrical signal of the waveform to be tested, to subsequently detect the waveform to be tested.
  • the waveform signal detecting method the chip periodically reads the electrical signal of the waveform to be tested outputted by itself through the I/O port, and uses the chip to capture the electrical signal of the waveform to be tested output by itself, without relying on other external testing equipment, thereby avoiding
  • the operation of configuring and connecting external test equipment is complicated and the verification efficiency is low.
  • an electrical signal capture record is generated according to the level value and the capture time of the electrical signal, and the electrical signal capture is recorded in the follow-up and expectation.
  • the output waveform is compared and verified, the waveform that is inconsistent with the expectation can be quickly and accurately verified, which further improves the verification efficiency.
  • FIG. 2 is a flow chart showing a waveform signal detecting method according to Embodiment 2 of the present application. As shown in FIG. 2, the waveform signal detecting method includes:
  • the chip when the chip reads the electrical signal of the waveform to be tested outputted by the chip through the I/O port (ie, the I/O pin), the chip can directly output the I/O port of the electrical signal of the waveform to be tested. Read back the electrical signal.
  • the I/O port of the electrical signal outputting the waveform to be tested can be configured to float, pull up or pull down the I/O pin. In this way, no additional I/O ports or pins need to be set. , saving chip implementation costs.
  • the chip when the chip reads the electrical signal of the waveform to be tested outputted by the chip through the I/O port, the chip can read the electrical signal through another I/O port of the chip. In other words, the chip reads back the electrical signal through an I/O port other than the I/O port that outputs the electrical signal of the waveform to be measured. In this case, the I/O port of the electrical signal outputting the waveform to be tested is short-circuited with the I/O port of the read-back electrical signal to achieve electrical signal communication. In this way, reading the data of the I/O port of the electrical signal outputting the waveform to be tested via the intermediate I/O port simplifies the design and implementation of the electrical signal output and input.
  • time control is performed by a timer inside the chip.
  • the acquisition interval of the signal acquisition period is determined according to the frequency of the timer.
  • the chip reads back the electrical signal of the output waveform to be tested according to the timing frequency of the timer.
  • the accuracy of reading the electrical signal is derived from the ratio of the operating frequency of the timer to the operating frequency of the module that outputs the electrical signal to be measured. The higher the ratio, the higher the detection accuracy. high.
  • the chip When the chip reads the electrical signal, when the time recorded by the timer reaches the acquisition time of the signal acquisition period, the output electrical signal of the waveform to be tested is read.
  • S202 Determine a capture sequence number corresponding to the electrical signal, and obtain a desired level value corresponding to the capture sequence number from the preset expected output waveform data.
  • preset desired output waveform data is pre-stored in the chip.
  • the preset desired output waveform data is used to indicate a desired level value output at a desired output time, and a waveform of a desired output can be obtained according to a desired output time and a desired level value.
  • the predetermined desired output waveform data may be in the form of an array of desired output waveforms, the desired output waveform array comprising at least one array element, each array element including a desired level value.
  • each array element may also include a desired output time of a desired level value.
  • FIG. 3 An example of a waveform obtained from expected output waveform data is shown in FIG. 3, and an array of desired output waveforms can be preset in the chip:
  • Each of the square brackets represents an array element.
  • the first number in each array element represents the desired level value and the second number represents the desired output time. Taking the first array element as an example, the first "1" indicates that the desired level value is 1, that is, the high level, and the second "1" indicates that the expected output time is the first second. Of course, depending on the set time unit, the expected output time may be the first minute, the first millisecond, or the like.
  • the maximum value of the capture sequence number can be set according to the preset number of array elements in the desired output waveform array, and the two can be consistent.
  • Each capture sequence number corresponds to an array element in the desired output waveform array. Because the desired level value is included in the array element, obtaining the desired level value corresponding to the capture sequence number from the preset desired output waveform data includes: determining the array element serial number by capturing the sequence element number of the array of the desired output waveform array Corresponding array elements and reading the desired level values in the array elements. The capture sequence number corresponds to the sequence element number.
  • the desired level value of the capture sequence number can be obtained conveniently and quickly, and the desired level value corresponding to the electrical signal can be determined; on the other hand, the implementation of determining the desired level value is simplified. process.
  • the capture sequence number when the capture sequence number is 2, it corresponds to the second array element [0, 2] in the desired output waveform array, where the desired level value is 0.
  • the capture sequence number is initialized at the start of the waveform signal detection. In the present embodiment, the capture sequence number starts from 1.
  • S203 Determine whether the level value of the electrical signal is consistent with the desired level value; if they are consistent, perform steps 204-205; if not, perform step 206.
  • the array element number corresponding to the array element number is determined by capturing the sequence element number of the desired output waveform array, and the desired level value in the array element is read. Further, a desired level value corresponding to the currently read electrical signal can be determined. Whether the electrical signal is a desired electrical signal is determined based on whether the level value of the electrical signal coincides with a corresponding desired level value. If they match, the expected electrical signal is executed, and S204-205 is executed. If not, S206 is executed.
  • the level value of the electrical signal coincides with the desired level value, it indicates that the electrical signal is a desired electrical signal, and an electrical signal capture record is generated based on the electrical signal.
  • the electrical signal capture record is used to record the level value and capture time of the electrical signal for subsequent waveform detection.
  • updating the capture sequence number may be to increase the capture sequence number by 1 to implement the capture sequence number update in a simple manner, and may also make the subsequent desired level value determination and the electrical signal comparison easier.
  • the capture sequence number may be increased by a preset value according to a setting rule.
  • step S206 If the level value of the electrical signal does not match the expected level value, the original capture sequence number is used, and step S207 is performed.
  • the electrical signal is ignored, the original acquisition sequence number is continued, and the step S207 is performed to determine whether the detection termination condition is reached.
  • step S207 Determine whether the detection termination condition is satisfied; if yes, execute step S208; if not, return to step S201.
  • the detection termination condition is used to indicate whether to stop electrical signal acquisition. Those skilled in the art can set any suitable detection termination conditions as needed.
  • the detecting termination condition may include a first termination condition, where the first termination condition is used to indicate that the capture sequence number is greater than a preset maximum capture sequence number.
  • the preset maximum capture sequence number can be set as needed.
  • the preset maximum capture sequence number is the number of array elements in the desired output waveform array.
  • the detecting termination condition may further include a second termination condition for indicating that the acquisition time exceeds a preset acquisition time.
  • determining whether the detection termination condition is met it may be determined whether only the first termination condition is satisfied, or only whether the second termination condition is satisfied, or whether the first termination condition is satisfied, and whether the second termination condition is satisfied. Termination condition.
  • the detection is terminated.
  • the detection is terminated.
  • determining whether the detection termination condition is satisfied includes:
  • the detection is terminated. If the first termination condition is met, the detection is terminated. If the first termination condition is not met, it is determined whether the next acquisition time satisfies the second termination condition. That is, it is judged whether the acquisition time of the next cycle exceeds the preset acquisition time.
  • the detection is terminated. If the second termination condition is met, the detection is terminated. If the second termination condition is not satisfied, when the next acquisition time arrives, the returning chip reads the electrical signal of the waveform to be tested outputted by the I/O port through the I/O port, continues to read the next electrical signal, and judges the read Whether the next electrical signal is the desired signal. This cycle is repeated until the detection termination condition is reached, and the detection is stopped.
  • the capture sequence number is updated, it is necessary to first determine whether the first termination condition is satisfied, and if so, stop the detection; if not, determine whether the second termination condition is satisfied; if not, stop the detection; if not, Then, the process returns to step S201 to continue the execution.
  • the first termination condition may not be satisfied by default, and the second termination condition may be directly determined; if the second termination condition is satisfied, the detection is stopped; if not, the process returns to step S201 to continue execution. .
  • the chip can compare the capture record with a preset expected output waveform array and generate a detection result according to the comparison result. For example, determining the corresponding array element in the desired output waveform array by capturing the corresponding capture sequence number, and comparing the capture time in the capture record with the expected output time in the corresponding array element, thereby determining the desired level in the waveform to be tested. The deviation between the time of the value and the expected output time, thereby determining whether the waveform to be tested matches the preset desired output waveform.
  • an actual array of output waveforms can be generated based on the capture record and the corresponding capture sequence number, each capture record being an array element of the actual output waveform array. After that, it can be compared with the expected output waveform array by means of array calculation, and the detection result is obtained.
  • the actual output waveform is generated according to the capture record and the corresponding capture sequence number
  • the desired output waveform is generated according to the preset desired output waveform array
  • the actual output waveform is compared with the desired output waveform, and the detection result is obtained.
  • the waveform signal detection method starts the test, starts the module to be verified of the chip, and outputs the waveform to be tested through the I/O port. Capture sequence number is initialized, starting from 1.
  • the timer in the chip starts timing, and the chip reads the electrical signal of the waveform to be tested through the I/O port on it, and can read the electrical signal by using its own I/O port, and can not rely on the external test equipment.
  • the waveform signal detection method controls the detection flow by detecting termination conditions such as a maximum acquisition sequence number and a preset acquisition time, controls recording of an effective electrical signal by a desired level value, and determines an actual output waveform by a desired output time to obtain a Test Report.
  • the waveform signal detection method does not require manual intervention, and only uses the timer provided inside the chip, and can detect the actual output waveform according to the desired output waveform, and output a detection report.
  • FIG. 4 a block diagram of a waveform signal detecting apparatus according to a third embodiment of the present application is shown.
  • the waveform signal detecting device of this embodiment includes: an electrical signal collecting module 401, configured to read an electrical signal of the waveform to be tested output by the chip through the I/O port when the acquisition time of the signal collecting period arrives; the desired level value
  • the determining module 402 is configured to determine a capture sequence number corresponding to the electrical signal, and obtain a desired level value corresponding to the capture sequence number from the preset expected output waveform data
  • the level value comparison module 403 is configured to determine the electrical value of the electrical signal.
  • the capture record generating module 404 is configured to generate an electrical signal capture record corresponding to the capture sequence number when the level value of the electrical signal is consistent with the desired level value, wherein the electrical signal capture record The level value and the capture time of the electrical signal are included; the sequence number update module 405 is configured to update the capture sequence number, and when the next acquisition time arrives, the return electrical signal acquisition module 401 continues to execute until the detection termination condition is met.
  • the waveform signal detecting device chip periodically reads the electrical signal of the waveform to be tested outputted by the I/O port, and uses the chip to capture the electrical signal of the waveform to be tested output by the chip, without relying on other external testing equipment, thereby avoiding configuration.
  • the operation of connecting external test equipment is complicated, and the verification efficiency is low.
  • an electrical signal capture record is generated according to the level value and the capture time of the electrical signal, and the electrical signal capture is recorded in the follow-up and expectation.
  • the output waveform is compared and verified, the waveform that is inconsistent with the expectation can be quickly and accurately verified, which further improves the verification efficiency.
  • FIG. 5 a block diagram of a waveform signal detecting apparatus according to a fourth embodiment of the present application is shown.
  • the waveform signal detecting device includes: an electrical signal collecting module 501, configured to read an electrical signal of the waveform to be tested output by the chip through the I/O port when the acquisition time of the signal collecting period arrives; the desired level determining module 502 And determining a capture sequence number corresponding to the electrical signal, and obtaining a desired level value corresponding to the capture sequence number from the preset expected output waveform data; the level value comparison module 503 is configured to determine the level value of the electrical signal and Whether the desired level value is consistent; the capture record generation module 504 is configured to generate an electrical signal capture record corresponding to the capture sequence number when the level value of the electrical signal is consistent with the desired level value, wherein the electrical signal capture record includes the electrical signal The level value and the capture time; the sequence number update module 505 is configured to update the capture sequence number, and when the next acquisition time arrives, the return electrical signal acquisition module 501 continues to execute until the detection termination condition is met.
  • the device further includes: a sequence number retaining module 506, configured to use the original capture sequence number when the level value of the electrical signal does not match the expected level value, and return to the electrical signal acquisition module 501 to continue when the next acquisition time arrives. Execute until the detection termination condition is met.
  • a sequence number retaining module 506 configured to use the original capture sequence number when the level value of the electrical signal does not match the expected level value, and return to the electrical signal acquisition module 501 to continue when the next acquisition time arrives. Execute until the detection termination condition is met.
  • the predetermined desired output waveform data comprises an array of desired output waveforms, the desired output waveform array comprising at least one array element, each array element comprising a desired level value.
  • the desired level value determining module 502 is configured to determine a capture sequence number corresponding to the electrical signal, to capture an array element sequence number whose sequence number is an expected output waveform array, determine an array element corresponding to the array element serial number, and read the array element Expected level value.
  • each array element further includes a desired output time of the desired level value
  • the device further includes: a detection result generating module 507, configured to determine, according to the capture sequence number corresponding to each electrical signal capture record, after the detection termination condition is satisfied It is desirable to output the corresponding array elements in the waveform array, and compare the capture time in each electrical signal capture record with the expected output time in the corresponding array element, and generate a detection result according to the comparison result.
  • the detecting termination condition includes: a first termination condition and/or a second termination condition; wherein the first termination condition is used to indicate that the capture sequence number is greater than a preset maximum capture sequence number; and the second termination condition is used to indicate that the acquisition time exceeds The default acquisition time.
  • the determining by the sequence number updating module 505 until the detection termination condition is satisfied includes: determining whether the updated capture sequence number satisfies the first termination condition; if not, then Determining whether the next acquisition time satisfies the second termination condition; if not, the return electrical signal acquisition module 501 continues to execute when the next acquisition time arrives.
  • the electrical signal of the electrical signal acquisition module 501 reading the waveform to be tested outputted by the I/O port includes: reading the electrical signal through the I/O port of the electrical signal outputting the waveform to be tested; or Another I/O port reads the electrical signal.
  • the waveform signal detection method controls the detection flow by detecting termination conditions such as a maximum acquisition sequence number and a preset acquisition time, controls recording of an effective electrical signal by a desired level value, and determines an actual output waveform by a desired output time to obtain a Test Report.
  • the waveform signal detection method does not require manual intervention, and only uses the timer provided inside the chip, and can detect the actual output waveform according to the desired output waveform, and output a detection report.

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Abstract

一种波形信号检测方法及装置，该方法包括：在信号采集周期的采集时间到达时，芯片通过I/O端口读取自身输出的待测波形的电信号（S101）；确定电信号对应的捕获序号，并从预设的期望输出波形数据中，获取与捕获序号对应的期望电平值（S102）；若电信号的电平值与期望电平值一致，则生成与捕获序号对应的电信号捕获记录，其中，电信号捕获记录包括电信号的电平值和捕获时间（S104）；更新捕获序号，并在下一采集时间到达时，返回芯片通过I/O端口读取自身输出的待测波形的电信号的步骤继续执行，直至满足检测终止条件（S105）。该方法可以克服对芯片中通过I/O引脚输出波形的模块进行验证时，操作复杂，验证效率低下的缺陷。

Description

波形信号检测方法及装置 技术领域
本申请实施例涉及电路技术领域，尤其涉及一种波形信号检测方法及装置。
背景技术
从软件层面对芯片进行功能验证时，对于可以通过I/O(Input/Output,输入/输出)引脚输出波形的模块，如PWM模块(Pulse Width Modulation，脉冲宽度调制模块)，GPIO模块(General Purpose Input Output，通用输入/输出模块)等，验证的常用手段是在I/O引脚上外接外部测试设备如示波器或逻辑分析仪，配合示波器或逻辑分析仪配套的第三方软件工具，显示示波器或逻辑分析仪捕获到的I/O引脚输出的波形。工作人员通过观察或者测量示波器或逻辑分析仪输出的波形，将其与期望输出波形进行比对等方式，确定这些模块输出的波形是否符合预期，以判断该模块是否能正常工作。
但上述验证方法中，工作人员需要将芯片与外部测试设备连接，并进行设备配置，操作繁琐复杂，使得验证费时较多。可见，现有的利用外部测试设备对通过I/O引脚输出波形的模块进行功能验证时，操作复杂，验证效率低下。
发明内容
有鉴于此，本申请实施例所解决的技术问题之一在于提供一种波形信号检测方法及装置，用以克服现有技术中，对芯片中的通过I/O引脚输出波形的模块进行验证时，操作复杂，验证效率低下的缺陷。
本申请实施例的第一方面，提供一种波形信号检测方法，包括：在信号采集周期的采集时间到达时，芯片通过I/O端口读取自身输出的待测波形的电信号；确定电信号对应的捕获序号，并从预设的期望输出波形数据中，获取与捕获序号对应的期望电平值；若电信号的电平值与期望电平值一致，则生成与捕获序号对应的电信号捕获记录，其中，电信号捕获记录包括电信号的电平值和捕获时间；更新捕获序号，并在下一采集时间到达时，返回芯片通过I/O端口读取自身输出的待测波形的电信号的步骤继续执行，直至满足 检测终止条件。
根据本申请实施例的第二方面，提供一种波形信号检测装置，包括：电信号采集模块，用于在信号采集周期的采集时间到达时，芯片通过I/O端口读取自身输出的待测波形的电信号；期望电平值确定模块，用于确定电信号对应的捕获序号，并从预设的期望输出波形数据中，获取与捕获序号对应的期望电平值；捕获记录生成模块，用于当电信号的电平值与期望电平值一致时，生成与捕获序号对应的电信号捕获记录，其中，电信号捕获记录包括电信号的电平值和捕获时间；序号更新模块，用于更新捕获序号，并在下一采集时间到达时，返回电信号采集模块继续执行，直至满足检测终止条件。
由以上技术方案可见，本申请实施例的波形信号检测方案，芯片周期性通过I/O端口读取自身输出的待测波形的电信号，利用芯片对自身输出的待测波形的电信号进行捕获，无需依赖其他外部测试设备，避免了配置和连接外部测试设备存在的操作复杂，验证效率低下的问题。进一步地，对于捕获到的电信号，若其电平值与预设电平值一致，将根据该电信号的电平值和捕获时间生成电信号捕获记录，该电信号捕获记录在后续与期望输出波形进行比对验证时，可以快速、准确验证出与期望不一致的波形，进一步提高了验证效率。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1示出了根据本申请的实施例一的波形信号检测方法的流程示意图；
图2示出了根据本申请的实施例二的波形信号检测方法的流程示意图；
图3示出了图2所示实施例中的一种期望输出波形数据对应的波形示意图；
图4示出了根据本申请的实施例三的一种波形信号检测装置的结构框图；
图5示出了根据本申请的实施例四的一种波形信号检测装置的结构框图。
具体实施方式
为使得本申请实施例的发明目的、特征、优点能够更加的明显和易懂，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请实施例一部分实施例，而非全部实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请实施例保护的范围。
下面结合本申请实施例附图进一步说明本申请实施例具体实现。
实施例一
图1示出了根据本申请的实施例的波形信号检测方法的流程示意图。如图1所示，该波形信号检测方法包括：
S101：在信号采集周期的采集时间到达时，芯片通过I/O端口读取自身输出的待测波形的电信号。
对芯片进行测试，尤其是对芯片内部的一些能够通过I/O端口输出波形的模块(例如，PWM模块)进行测试时，可以通过判断I/O端口输出波形是否符合预期波形，从而确定被测试的模块是否符合要求。
芯片包括至少一个I/O端口，芯片中的功能模块与这些I/O端口电连接，以便能够通过这些I/O端口读入或输出电信号。
为了能够获取I/O端口输出的波形，在一种可行方式中，通过芯片的I/O端口(即I/O引脚)采集输出波形的I/O端口输出的电信号。例如，芯片的其中一个I/O端口用于输出待测波形的电信号。那么，如果这个I/O端口既可以实现输出电信号的功能也可以实现读取电信号的功能，则芯片可以通过这个I/O端口对待测波形的电信号进行读取，实现利用芯片将自身输出的电信号读回。但不限于此，芯片也可以通过这个I/O端口之外的具有电信号读取功能的其它I/O端口对待测波形的电信号进行读取，实现利用芯片将自身输出的电信号读回，此时，这两个I/O端口需要实现电连接。通过这种芯片读取自身输出的待测波形的电信号的方式，可以在不依赖外部测试设备的情况下获取待测波形，从而实现对待测波形进行检测的目的。
需要说明的是，在一次测试过程中，本领域技术人员能够根据需求设置信号采集周期，如采集总时长、采集间隔等等，本申请实施例对此不做具体限定。
S102：确定电信号对应的捕获序号，并从预设的期望输出波形数据中，获取与捕获序号对应的期望电平值。
在本实施方式中，为了减少人工参与，降低步骤繁琐度，在芯片中预存了预设的期望输出波形数据。预设的期望输出波形数据用于指示在期望输出时间输出的期望电平值，通过期望输出时间和期望电平值，可获得期望输出的波形。
通过捕获序号，可以从期望输出波形数据中获取对应的期望电平值。其中，该对应关系可以由本领域技术人员根据实际情况适当设置，能达到准确对应即可。
在读取到电信号后，确定当前读取到的电信号对应的捕获序号，进而确定该电信号对应的期望电平值。根据这一期望电平值可以确定该电信号是否为期望的电信号，进而确定是否保留这一电信号的相关信息。
S103：确定电信号的电平值与期望电平值是否一致。
在本实施方式中，确定读取到的电信号是否为期望的电信号的方式可以采用比较电信号的电平值与期望电平值是否相等的方式来确定二者是否一致。
S104：若一致，则生成与捕获序号对应的电信号捕获记录，其中，电信号捕获记录包括电信号的电平值和捕获时间。
若电信号的电平值与期望电平值相等，则两者一致，那么表示该电信号为期望的电信号，生成与捕获序号对应的电信号捕获记录。电信号捕获记录包括电信号的电平值及捕获时间。本领域技术人员还可以根据具体测试需求设置电信号捕获记录包括其他电信号相关信息。
在本实施方式中，芯片在进行电信号读取时，为了保证检测精度，可以将采集间隔的时间设置的较小，从而提升读取电信号的频率。但此种情况下采集的电信号较多，且部分电信号对于波形信号检测的作用不大，则可以不生成电信号捕获记录。根据与期望电平值一致的电信号生成电信号捕获记录，而对不一致的电信号不进行记录，可以减少检测过程中的步骤，也可以降低存储空间的占用。
S105：更新捕获序号，并在下一采集时间到达时，返回芯片通过I/O端口读取自身输出的待测波形的电信号的步骤继续执行，直至满足检测终止条件。
由于每个期望的电信号均对应一个捕获序号，因此，当生成电信号捕获记录后，需更新捕获序号，例如，可以将捕获序号加一。这样，当下一采集时间到达时，返回S101，继续读取下一电信号。直至满足检测终止条件。
其中，检测终止条件可以由本领域技术人员根据实际情况适当设置，例如，捕获序号大于预设的最大捕获序号，或者采集时间超过预设的采集时间，或者电信号的读取次数超过预设的最大读取次数等等，由此采集待测波形的电信号，以在后续进行待测波形的检测。
该波形信号检测方法，芯片周期性通过I/O端口读取自身输出的待测波形的电信号，利用芯片对自身输出的待测波形的电信号进行捕获，无需依赖其他外部测试设备，避免了配置和连接外部测试设备存在的操作复杂，验证效率低下的问题。进一步地，对于捕获到的电信号，若其电平值与预设电平值一致，将根据该电信号的电平值和捕获时间生成电信号捕获记录，该电信号捕获记录在后续与期望输出波形进行比对验证时，可以快速、准确验证出与期望不一致的波形，进一步提高了验证效率。
实施例二
图2示出了根据本申请的实施例二的波形信号检测方法的流程示意图。如图2所示，该波形信号检测方法包括：
S201：在信号采集周期的采集时间到达时，芯片通过I/O端口读取自身输出的待测波形的电信号。
在一种可行方式中，芯片通过I/O端口(即I/O引脚)读取自身输出的待测波形的电信号时，芯片可以通过输出待测波形的电信号的I/O端口直接读回该电信号。
在此种情况下，该输出待测波形的电信号的I/O端口可以配置为I/O引脚悬空、上拉或者下拉，这种方式下，无需设置额外的I/O端口或引脚，节省了芯片实现成本。
在另一种可行方式中，芯片通过I/O端口读取自身输出的待测波形的电 信号时，芯片可以通过芯片的另一I/O端口读取电信号。换而言之，芯片通过输出待测波形的电信号的I/O端口之外的I/O端口将电信号读回。在此种情况下，输出待测波形的电信号的I/O端口与读回电信号的I/O端口之间短接，以实现电信号的连通。这种方式下，经由中间I/O端口读取输出待测波形的电信号的I/O端口的数据，可以简化电信号输出和输入的设计和实现。
在本实施方式中，通过芯片内部的定时器进行时间控制。例如，根据定时器的频率确定信号采集周期的采集间隔时间。芯片根据定时器的计时频率来读回输出的待测波形的电信号。在使用这种方式检测输出的波形信号是否符合预期时，读取电信号的精度来源于定时器工作频率与输出待测波形的电信号的模块工作频率的比值，比值越高，则检测精度越高。
芯片在读取电信号时，当定时器记录的时间到达信号采集周期的采集时间，则读取输出的待测波形的电信号。
S202：确定电信号对应的捕获序号，并从预设的期望输出波形数据中，获取与捕获序号对应的期望电平值。
在本实施方式中，为了减少人工参与，降低步骤繁琐度，在芯片中预存了预设的期望输出波形数据。预设的期望输出波形数据用于指示在期望输出时间输出的期望电平值，根据期望输出时间和期望电平值可以获得期望输出的波形。
本领域技术人员可以根据需求选择确定以何种形式预存期望输出波形数据。在一种可行方式中，预设的期望输出波形数据可以采用期望输出波形数组的形式，期望输出波形数组包括至少一个数组元素，每个数组元素包括期望电平值。可选地，每个数组元素还可以包括期望电平值的期望输出时间。具体格式如下：
{[期望电平1，期望时间T1]，[期望电平0，期望时间T2]，…}。
一种根据期望输出波形数据获得的波形示例如图3所示，在芯片中可以预设如下期望输出波形数组：
{[1，1]，[0，2]，[1，4]，[0，7]，[1，8]，[0，9]，[1，11]，[0，12]}。其中每个中括号表示一个数组元素。每个数组元素中的第一个数字表示期望电平值，第二个数字表示期望输出时间。以第一个数组元素为例，第一个“1”表示期望电平值为1，即高电平，第二个“1”表示期望输出时 间为第1秒。当然，根据设置的时间单位不同，期望输出时间也可以是第1分钟、第1毫秒等。
捕获序号的最大值可以根据预设的期望输出波形数组中的数组元素数量设置，二者可以保持一致。
每个捕获序号都对应期望输出波形数组中的一个数组元素。因数组元素中包括期望电平值，则从预设的期望输出波形数据中，获取与捕获序号对应的期望电平值包括：以捕获序号为期望输出波形数组的数组元素序号，确定数组元素序号对应的数组元素，并读取数组元素中的期望电平值。捕获序号与数组元素序号对应，一方面，可以方便快捷地获取捕获序号的期望电平值，进而可以确定电信号对应的期望电平值；另一方面，也简化了确定期望电平值的实现过程。
如图3所示的期望输出波形数据，捕获序号为1时，对应期望输出波形数组中的第一个数组元素[1，1]，其中的期望电平值为1。当捕获序号为2时，对应期望输出波形数组中的第二个数组元素[0，2]，其中的期望电平值为0。
捕获序号在开始波形信号检测时初始化，在本实施例中，捕获序号从1开始。
S203：确定电信号的电平值与期望电平值是否一致；若一致，则执行步骤204-205；若不一致，则执行步骤206。
在读取到电信号并确定电信号对应的捕获序号后，以捕获序号为期望输出波形数组的数组元素序号，确定数组元素序号对应的数组元素，并读取数组元素中的期望电平值，进而可以确定与当前读取到的电信号对应的期望电平值。根据该电信号的电平值是否与对应的期望电平值一致判断该电信号是否为期望的电信号。若一致则为期望电信号，进而执行S204-205，若不一致则执行S206。
S204：若一致，则生成与捕获序号对应的电信号捕获记录，其中，电信号捕获记录包括电信号的电平值和捕获时间。
若电信号的电平值与期望电平值一致，则表示该电信号为期望的电信号，根据该电信号生成电信号捕获记录。该电信号捕获记录用于记录电信号的电平值和捕获时间，以便后续进行待测波形检测。
S205：更新捕获序号，然后执行步骤S207。
在一种可行方式中，更新捕获序号可以是将捕获序号加1，以使用简单方式实现捕获序号更新，也可使得后续期望电平值确定和电信号的比对更为简单。但不限于此，也可以根据设定规则，将捕获序号增加预设值。通过更新捕获序号并判断更新后的捕获序号是否超出预设的最大捕获序号可以保证及时终止检测，避免检测时间过长，提升检测效率。
S206：若电信号的电平值与期望电平值不一致，则使用原捕获序号，并执行步骤S207。
若电信号的电平值与对应的期望电平值不一致，则忽略该电信号，继续使用原捕获序号，并进行S207步骤执行，以判断是否达到检测终止条件。
S207：判断是否满足检测终止条件；若满足，则执行步骤S208；若不满足，则返回步骤S201。
检测终止条件用于指示是否停止电信号捕获。本领域技术人员可以根据需要设置任意适当的检测终止条件。
在一种可行方式中，检测终止条件可以包括第一终止条件，第一终止条件用于指示捕获序号大于预设的最大捕获序号。其中，预设的最大捕获序号可以根据需要设定。在本实施方式中，预设的最大捕获序号为期望输出波形数组中的数组元素数量。检测终止条件还可以包括第二终止条件，第二终止条件用于指示采集时间超过预设的采集时间。
需要说明的是，在判断是否满足检测终止条件时，可以仅判断是否满足第一终止条件，或者仅判断是否满足第二终止条件，或者既判断是否满足第一终止条件，又判断是否满足第二终止条件。
例如，若更新后的捕获序号大于预设的最大捕获序号，则终止检测。
又例如，若下一采集时间超出预设的采集时间，则终止检测。
再例如，当检测终止条件同时包括第一和第二终止条件时，判断是否满足检测终止条件包括：
确定更新后的捕获序号是否满足第一终止条件。即判断更新后的捕获序号是否大于最大捕获序号。
若满足第一终止条件，则终止检测。若不满足第一终止条件，则确定下一采集时间是否满足第二终止条件。即判断下一周期的采集时间是否超过预 设的采集时间。
若满足第二终止条件，则终止检测。若不满足第二终止条件，则在下一采集时间到达时，返回芯片通过I/O端口读取自身输出的待测波形的电信号的步骤，继续读取下一电信号，并判断读取的下一电信号是否为需要的信号。如此循环往复，直至达到检测终止条件，则停止检测。
对于更新了捕获序号的情况，需要先判断第一终止条件是否满足，若满足，则停止检测；若不满足，则再判断第二终止条件是否满足；若满足，则停止检测；若不满足，则返回步骤S201继续执行。
对于使用原捕获序号的情况，则可默认为第一终止条件不满足，可直接进行第二终止条件的判断；若满足第二终止条件，则停止检测；若不满足，则返回步骤S201继续执行。
S208：在检测终止条件满足后，根据各电信号捕获记录对应的捕获序号确定在期望输出波形数组中对应的数组元素，并比较各电信号捕获记录中的捕获时间与对应的数组元素中的期望输出时间，并根据比较结果生成检测结果。
当满足检测终止条件后，芯片可以将捕获记录与预设的期望输出波形数组比较，并根据比较结果生成检测结果。例如，通过捕获记录对应的捕获序号确定期望输出波形数组中对应的数组元素，将捕获记录中的捕获时间与对应的数组元素中的期望输出时间比对，从而确定待测波形中出现期望电平值的时间与期望输出时间之间的偏差，进而确定待测波形与预设的期望输出波形是否符合。
当然，在其他实施方式中，可以根据捕获记录和对应的捕获序号生成实际输出波形数组，每个捕获记录均为实际输出波形数组的一个数组元素。之后可以通过数组计算的方式与期望输出波形数组比较，并获得检测结果。或者，根据捕获记录和对应的捕获序号生成实际输出波形，并根据预设的期望输出波形数组生成期望输出波形，并将实际输出波形与期望输出波形进行比较，并获得检测结果。
该波形信号检测方法，开始进行测试时，启动芯片的待验证模块，通过I/O端口输出待测波形。捕获序号进行初始化，从1开始。芯片内的定时器启动计时，芯片通过其上的I/O端口读取待测波形的电信号，由于采用自身 的I/O端口读取电信号，可以不依赖外部测试设备。
该波形信号检测方法通过检测终止条件如最大捕获序号和预设的采集时间控制检测流程，通过期望电平值控制对有效电信号的记录，通过期望输出时间对实际输出波形进行判断，以得出检测报告。该波形信号检测方法无需人工干预，仅使用芯片内部提供的定时器，便可以根据期望输出波形，对实际输出波形进行检测，并输出检测报告。
实施例三
如图4所示，示出了根据本申请的实施例三的一种波形信号检测装置的结构框图。
本实施例的波形信号检测装置包括：电信号采集模块401，用于在信号采集周期的采集时间到达时，芯片通过I/O端口读取自身输出的待测波形的电信号；期望电平值确定模块402，用于确定电信号对应的捕获序号，并从预设的期望输出波形数据中，获取与捕获序号对应的期望电平值；电平值比较模块403，用于确定电信号的电平值与期望电平值是否一致；捕获记录生成模块404，用于当电信号的电平值与期望电平值一致时，生成与捕获序号对应的电信号捕获记录，其中，电信号捕获记录包括电信号的电平值和捕获时间；序号更新模块405，用于更新捕获序号，并在下一采集时间到达时，返回电信号采集模块401继续执行，直至满足检测终止条件。
该波形信号检测装置芯片周期性通过I/O端口读取自身输出的待测波形的电信号，利用芯片对自身输出的待测波形的电信号进行捕获，无需依赖其他外部测试设备，避免了配置和连接外部测试设备存在的操作复杂，验证效率低下的问题。进一步地，对于捕获到的电信号，若其电平值与预设电平值一致，将根据该电信号的电平值和捕获时间生成电信号捕获记录，该电信号捕获记录在后续与期望输出波形进行比对验证时，可以快速、准确验证出与期望不一致的波形，进一步提高了验证效率。
实施例四
如图5所示，示出了根据本申请的实施例四的一种波形信号检测装置的结构框图。
该波形信号检测装置包括：电信号采集模块501，用于在信号采集周期的采集时间到达时，芯片通过I/O端口读取自身输出的待测波形的电信号；期望电平值确定模块502，用于确定电信号对应的捕获序号，并从预设的期望输出波形数据中，获取与捕获序号对应的期望电平值；电平值比较模块503，用于确定电信号的电平值与期望电平值是否一致；捕获记录生成模块504，用于当电信号的电平值与期望电平值一致时，生成与捕获序号对应的电信号捕获记录，其中，电信号捕获记录包括电信号的电平值和捕获时间；序号更新模块505，用于更新捕获序号，并在下一采集时间到达时，返回电信号采集模块501继续执行，直至满足检测终止条件。
可选地，装置还包括：序号保留模块506，用于当电信号的电平值与期望电平值不一致时，使用原捕获序号，并在下一采集时间到达时，返回电信号采集模块501继续执行，直至满足检测终止条件。
可选地，预设的期望输出波形数据包括期望输出波形数组，期望输出波形数组包括至少一个数组元素，每个数组元素包括期望电平值。
可选地，期望电平值确定模块502用于确定电信号对应的捕获序号，以捕获序号为期望输出波形数组的数组元素序号，确定数组元素序号对应的数组元素，并读取数组元素中的期望电平值。
可选地，每个数组元素还包括期望电平值的期望输出时间；装置还包括：检测结果生成模块507，用于在检测终止条件满足后，根据各电信号捕获记录对应的捕获序号确定在期望输出波形数组中对应的数组元素，并比较各电信号捕获记录中的捕获时间与对应的数组元素中的期望输出时间，并根据比较结果生成检测结果。
可选地，检测终止条件包括：第一终止条件和/或第二终止条件；其中，第一终止条件用于指示捕获序号大于预设的最大捕获序号；第二终止条件用于指示采集时间超过预设的采集时间。
可选地，当检测终止条件包括第一和第二终止条件时，序号更新模块505对直至满足检测终止条件的判断包括：确定更新后的捕获序号是否满足第一终止条件；若不满足，则确定下一采集时间是否满足第二终止条件；若不满足，则在下一采集时间到达时，返回电信号采集模块501继续执行。
可选地，电信号采集模块501的通过I/O端口读取自身输出的待测波形 的电信号包括：通过输出待测波形的电信号的I/O端口读回电信号；或者，通过芯片的另一I/O端口读取电信号。
该波形信号检测方法通过检测终止条件如最大捕获序号和预设的采集时间控制检测流程，通过期望电平值控制对有效电信号的记录，通过期望输出时间对实际输出波形进行判断，以得出检测报告。该波形信号检测方法无需人工干预，仅使用芯片内部提供的定时器，便可以根据期望输出波形，对实际输出波形进行检测，并输出检测报告。最后应说明的是：以上实施例仅用以说明本申请实施例的技术方案，而非对其限制；尽管参照前述实施例对本申请实施例进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的精神和范围。

Claims (16)

  1. 一种波形信号检测方法，包括：
    在信号采集周期的采集时间到达时，芯片通过I/O端口读取自身输出的待测波形的电信号；
    确定所述电信号对应的捕获序号，并从预设的期望输出波形数据中，获取与所述捕获序号对应的期望电平值；
    若所述电信号的电平值与所述期望电平值一致，则生成与所述捕获序号对应的电信号捕获记录，其中，所述电信号捕获记录包括所述电信号的电平值和捕获时间；
    更新所述捕获序号，并在下一采集时间到达时，返回所述芯片通过I/O端口读取自身输出的待测波形的电信号的步骤继续执行，直至满足检测终止条件。
  2. 根据权利要求1所述的方法，其中，所述方法还包括：
    若所述电信号的电平值与所述期望电平值不一致，则使用原捕获序号，并在下一采集时间到达时，返回所述芯片通过I/O端口读取自身输出的待测波形的电信号的步骤继续执行，直至满足所述检测终止条件。
  3. 根据权利要求1或2所述的方法，其中，所述预设的期望输出波形数据包括期望输出波形数组，所述期望输出波形数组包括至少一个数组元素，每个所述数组元素包括期望电平值。
  4. 根据权利要求3所述的方法，其中，所述从预设的期望输出波形数据中，获取与所述捕获序号对应的期望电平值，包括：
    以所述捕获序号为所述期望输出波形数组的数组元素序号，确定所述数组元素序号对应的数组元素，并读取所述数组元素中的期望电平值。
  5. 根据权利要求3所述的方法，其中，每个所述数组元素还包括所述期望电平值的期望输出时间；
    所述方法还包括：在所述检测终止条件满足后，根据各电信号捕获记录对应的捕获序号确定在所述期望输出波形数组中对应的数组元素，并比较各电信号捕获记录中的捕获时间与对应的数组元素中的期望输出时间，并根据比较结果生成检测结果。
  6. 根据权利要求1所述的方法，其中，所述检测终止条件包括：第一 终止条件和/或第二终止条件；
    其中，
    所述第一终止条件用于指示所述捕获序号大于预设的最大捕获序号；所述第二终止条件用于指示所述采集时间超过预设的采集时间。
  7. 根据权利要求6所述的方法，其中，当所述检测终止条件包括所述第一和第二终止条件时，所述直至满足检测终止条件，包括：
    确定更新后的所述捕获序号是否满足所述第一终止条件；
    若不满足所述第一终止条件，则确定所述下一采集时间是否满足所述第二终止条件；
    若不满足所述第二终止条件，则在所述下一采集时间到达时，返回所述芯片通过I/O端口读取自身输出的待测波形的电信号的步骤继续执行。
  8. 根据权利要求1所述的方法，其中，芯片通过I/O端口读取自身输出的待测波形的电信号，包括：
    所述芯片通过输出待测波形的电信号的所述I/O端口读回所述电信号；
    或者，
    所述芯片通过所述芯片的另一I/O端口读取所述电信号。
  9. 一种波形信号检测装置，包括：
    电信号采集模块，用于在信号采集周期的采集时间到达时，芯片通过I/O端口读取自身输出的待测波形的电信号；
    期望电平值确定模块，用于确定所述电信号对应的捕获序号，并从预设的期望输出波形数据中，获取与所述捕获序号对应的期望电平值；
    捕获记录生成模块，用于当电信号的电平值与期望电平值一致时，生成与所述捕获序号对应的电信号捕获记录，其中，所述电信号捕获记录包括所述电信号的电平值和捕获时间；
    序号更新模块，用于更新所述捕获序号，并在下一采集时间到达时，返回所述电信号采集模块继续执行，直至满足检测终止条件。
  10. 根据权利要求9所述的装置，其中，所述装置还包括：
    序号保留模块，用于当所述电信号的电平值与所述期望电平值不一致时，使用原捕获序号，并在下一采集时间到达时，返回所述电信号采集模块继续执行，直至满足所述检测终止条件。
  11. 根据权利要求9或10所述的装置，其中，所述预设的期望输出波形数据包括期望输出波形数组，所述期望输出波形数组包括至少一个数组元素，每个所述数组元素包括期望电平值。
  12. 根据权利要求11所述的装置，其中，所述期望电平值确定模块用于确定所述电信号对应的捕获序号，以所述捕获序号为所述期望输出波形数组的数组元素序号，确定所述数组元素序号对应的数组元素，并读取所述数组元素中的期望电平值。
  13. 根据权利要求11所述的装置，其中，每个所述数组元素还包括所述期望电平值的期望输出时间；
    所述装置还包括：检测结果生成模块，用于在所述检测终止条件满足后，根据各电信号捕获记录对应的捕获序号确定在所述期望输出波形数组中对应的数组元素，并比较各电信号捕获记录中的捕获时间与对应的数组元素中的期望输出时间，并根据比较结果生成检测结果。
  14. 根据权利要求9所述的装置，其中，所述检测终止条件包括：第一终止条件和/或第二终止条件；其中，所述第一终止条件用于指示所述捕获序号大于预设的最大捕获序号；所述第二终止条件用于指示所述采集时间超过预设的采集时间。
  15. 根据权利要求14所述的装置，其中，当所述检测终止条件包括所述第一和第二终止条件时，所述序号更新模块对直至满足检测终止条件的判断包括：确定更新后的所述捕获序号是否满足所述第一终止条件；若不满足所述第一终止条件，则确定所述下一采集时间是否满足所述第二终止条件；若不满足所述第二终止条件，则在所述下一采集时间到达时，返回所述电信号采集模块继续执行。
  16. 根据权利要求9所述的装置，其中，所述电信号采集模块的通过I/O端口读取自身输出的待测波形的电信号包括：通过输出待测波形的电信号的所述I/O端口读回所述电信号；或者，通过所述芯片的另一I/O端口读取所述电信号。
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