WO2019148592A1 - 低温多晶硅薄膜晶体管及其制作方法 - Google Patents

低温多晶硅薄膜晶体管及其制作方法 Download PDF

Info

Publication number
WO2019148592A1
WO2019148592A1 PCT/CN2018/078660 CN2018078660W WO2019148592A1 WO 2019148592 A1 WO2019148592 A1 WO 2019148592A1 CN 2018078660 W CN2018078660 W CN 2018078660W WO 2019148592 A1 WO2019148592 A1 WO 2019148592A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
substrate
film transistor
polysilicon
thin film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2018/078660
Other languages
English (en)
French (fr)
Inventor
易国霞
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Original Assignee
Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd filed Critical Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority to US15/776,347 priority Critical patent/US20200273999A1/en
Publication of WO2019148592A1 publication Critical patent/WO2019148592A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0314—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral top-gate TFTs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6731—Top-gate only TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6741—Group IV materials, e.g. germanium or silicon carbide
    • H10D30/6743—Silicon
    • H10D30/6745—Polycrystalline or microcrystalline silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/213—Channel regions of field-effect devices
    • H10D62/221—Channel regions of field-effect devices of FETs
    • H10D62/235—Channel regions of field-effect devices of FETs of IGFETs
    • H10D62/292—Non-planar channels of IGFETs

Definitions

  • the invention belongs to the technical field of fabrication of thin film transistors, and in particular to a low temperature polysilicon thin film transistor and a fabrication method thereof.
  • an amorphous silicon thin film transistor (a-Si TFT) is widely used as a switching element of a display panel, but the a-Si TFT satisfies a thin type, a light weight, a high definition, a high brightness, a high reliability, and a low power consumption. Other requirements are still limited.
  • Lower Temperature Polycrystal Silicon (LTPS) TFTs have a polysilicon layer with high electron mobility compared to a-Si TFTs, and thus have significant advantages in meeting the above requirements.
  • the LTPS TFT has a high electron mobility and a large heat generation, which is disadvantageous for improving the reliability of the product.
  • the present invention provides a low temperature polysilicon thin film transistor which reduces heat generation by reducing a channel width and a method of fabricating the same.
  • a low temperature polysilicon thin film transistor comprising: a ring-shaped polysilicon layer on a substrate; a first insulating layer on the substrate and the polysilicon layer; a gate on the first insulating layer; a second insulating layer on the first insulating layer and the gate; a source and a drain on the second insulating layer, the source and the The drains respectively penetrate the second insulating layer and the first insulating layer to respectively contact the polysilicon layer.
  • the longitudinal cross-sectional shape of the polysilicon layer includes two triangular-like shapes that are axisymmetric, and the triangular-like shape includes a first straight side, a second straight side, and an arc side, and the first straight side is located on the substrate Upper end, the first end of the second straight side is connected to the first end of the first straight side, and the arc side is connected to the second end of the first straight side and the second straight side Between the two ends, the arc edge is concave inwardly toward the triangular shape.
  • the polysilicon layer has a circular cross-sectional shape.
  • cross-sectional area of the inner cavity of the polysilicon layer gradually decreases in a direction away from the substrate.
  • the low temperature polysilicon thin film transistor further includes a buffer layer between the substrate and the polysilicon layer.
  • a method of fabricating a low temperature polysilicon thin film transistor comprising: forming a ring-like polysilicon layer on a substrate; forming a first insulation on the substrate and the polysilicon layer Forming a gate on the first insulating layer; forming a second insulating layer on the first insulating layer and the gate; forming a source and a drain on the second insulating layer, The source and the drain respectively penetrate the second insulating layer and the first insulating layer to respectively contact the polysilicon layer.
  • the method of forming a ring-shaped polysilicon layer on a substrate comprises: forming a flat layer on the substrate, the flat layer has a longitudinal cross-sectional shape that is inferior arc, and the flat layer has a circular cross-sectional shape Forming an amorphous silicon layer on the substrate and the planar layer, the amorphous silicon layer including a first portion on the substrate and a second portion on the planar layer; Forming an annular ring-shaped photoresist layer on the junction of the portion and the second portion; etching an amorphous silicon layer other than the amorphous silicon layer under the photoresist layer; and removing the photoresist layer
  • the ring-shaped amorphous silicon layer is removed to form a ring-like amorphous silicon layer; the ring-shaped amorphous silicon layer is crystallized by solid phase crystallization to form a ring-like polysilicon layer.
  • the angle of the slope angle of the flat layer is 60° to 70°.
  • the flat layer has a thickness of 2.5 ⁇ m to 3 ⁇ m.
  • the manufacturing method further includes: forming a buffer layer on the substrate.
  • the invention has the beneficial effects that the invention can reduce the channel width of the transistor by fabricating the polysilicon layer with a ring-like shape, thereby facilitating heat dissipation of the transistor, improving the stability of the transistor, and further facilitating high-resolution and low-power processing. Consumed display panel.
  • FIG. 1 is a schematic structural view of a low temperature polysilicon thin film transistor according to an embodiment of the present invention
  • FIG. 2 is a projection view of a polysilicon layer on a buffer layer in accordance with an embodiment of the present invention
  • FIG. 3 is a schematic view showing a longitudinal sectional shape of a polysilicon layer according to an embodiment of the present invention.
  • FIGS. 4A through 4F are process diagrams of a low temperature polysilicon thin film transistor in accordance with an embodiment of the present invention.
  • 5A through 5F are process diagrams of a polysilicon layer in accordance with an embodiment of the present invention.
  • Figure 6 is a schematic illustration of the slope angle of a flat layer in accordance with an embodiment of the present invention.
  • FIG. 1 is a schematic structural view of a low temperature polysilicon thin film transistor according to an embodiment of the present invention.
  • a low temperature polysilicon thin film transistor includes a substrate 100, a buffer layer 200, a polysilicon layer 300, a first insulating layer 400, a gate 500, a second insulating layer 600, a source 700, and a drain 800. .
  • the substrate 100 can be, for example, a glass substrate.
  • the buffer layer 200 is disposed on the substrate 100.
  • the buffer layer 200 may be composed of, for example, a silicon nitride (SiN x ) layer and a silicon oxide (SioO x ) layer, but the present invention is not limited thereto.
  • the buffer layer 200 is disposed in order to prevent metal ions in the substrate 100 from diffusing to the polysilicon layer 300, reducing defect center formation and leakage current generation. Therefore, the arrangement of the buffer layer 200 is a preferred arrangement, and as another embodiment of the present invention, the buffer layer 200 may not be provided.
  • the polysilicon layer 300 is disposed on the buffer layer 200.
  • the polysilicon layer 300 is ring-like, but the invention is not limited thereto.
  • the cross-sectional shape of the polysilicon layer 300 has a circular ring shape.
  • the cross section of the polysilicon layer 300 refers to a cross section facing the polysilicon layer 300 in parallel with the surface of the buffer layer 200 carrying the polysilicon layer 300. That is, the projection of the polysilicon layer 300 on the buffer layer 200 has a circular ring shape.
  • FIG. 2 is a projection view of a polysilicon layer on a buffer layer in accordance with an embodiment of the present invention.
  • the longitudinal cross-sectional shape of the polysilicon layer 300 includes two axial-symmetric triangular shapes, that is, the longitudinal cross-sectional shape of the polysilicon layer 300 shown in FIG.
  • the longitudinal section of the polysilicon layer 300 refers to a section facing the polysilicon layer 300 perpendicular to the surface of the buffer layer 200 carrying the polysilicon layer 300.
  • FIG. 3 is a schematic view of a longitudinal cross-sectional shape of a polysilicon layer in accordance with an embodiment of the present invention.
  • the longitudinal cross-sectional shape of the polysilicon layer 300 includes two axial-like triangular shapes 300A.
  • Each of the triangular shapes 300A includes a first straight side 310, a second straight side 320, and an arc side 330.
  • the first straight edge 310 is located on the buffer layer 200.
  • the first end of the second straight side 320 is connected to the first end of the first straight side 310, and the second end of the second straight side 320 is away from the second end of the first straight side 310, that is, the second straight side 320 and the first end
  • the straight sides 310 have a predetermined angle (for example, an acute angle).
  • the arc edge 330 is connected between the second end of the first straight side 310 and the second end of the second straight side 320, and the arc side 330 is within the triangle-like shape 300A (ie, by the first straight side 310, the second straight side
  • the inner portion formed by the combination of 320 and the arc edge 330 is concave.
  • the curvature of each point on the arc side 330 is equal, that is, the arc side 330 is an arc.
  • the cross-sectional area of the inner cavity of the polysilicon layer 300 gradually decreases in a direction away from the buffer layer 200.
  • the inner cavity of the polysilicon layer 300 is formed by circumferentially extending the arcuate sides 330 of the two axially-shaped triangular shapes 300A.
  • the pattern structure of the ring-like polysilicon layer 300 according to the embodiment of the present invention can reduce the channel width of the thin film transistor.
  • the first insulating layer 400 is disposed on the buffer layer 200 and the polysilicon layer 300, and the first insulating layer 400 is also used to protect the polysilicon layer 300.
  • a first insulating layer 400 may be a single layer of SiN x or SiO x, may be a SiN x / SiO x laminate structure.
  • the gate 500 is disposed on the first insulating layer 400.
  • the gate 500 may be, for example, a molybdenum aluminum molybdenum (MoAlMo) structure or a titanium aluminum titanium (TiAlTi) structure.
  • the second insulating layer 600 is disposed on the first insulating layer 400 and the gate 500, and the second insulating layer 600 is also used to protect the gate 500.
  • the second insulating layer 600 may be a single layer of SiN x or SiO x, may be a SiN x / SiO x laminate structure.
  • the source 700 and the drain 800 are spaced apart from each other on the second insulating layer 600.
  • the source 700 and the drain 800 may be, for example, a molybdenum aluminum molybdenum (MoAlMo) structure or a titanium aluminum titanium (TiAlTi) structure.
  • MoAlMo molybdenum aluminum molybdenum
  • TiAlTi titanium aluminum titanium
  • the source 700 and the drain 800 penetrate the second insulating layer 600 and the first insulating layer 400, respectively, to be in contact with the polysilicon layer 300, respectively.
  • the contact area is small, which also contributes to the reduction of the channel width of the thin film transistor.
  • FIGS. 4A through 4F are process diagrams of a low temperature polysilicon thin film transistor in accordance with an embodiment of the present invention.
  • Step 1 Referring to FIG. 4A, a buffer layer 200 is formed on the substrate 100. When the buffer layer 200 is not present, this step can be omitted.
  • Step 2 Referring to FIG. 4B, a polysilicon layer 300 of a ring-like shape is formed on the buffer layer 200.
  • 5A through 5F are process diagrams of a polysilicon layer in accordance with an embodiment of the present invention.
  • a flat layer PLN is formed on the buffer layer 200.
  • the longitudinal cross-sectional shape of the flat layer PLN is inferior arc, and the cross-sectional shape of the flat layer PLN is circular.
  • the longitudinal plane of the flat layer PLN refers to a section which faces the flat layer PLN in parallel with the surface of the buffer layer 200 which carries the flat layer PLN.
  • the longitudinal section of the flat layer PLN refers to a section facing the flat layer PLN perpendicular to the surface of the buffer layer 200 carrying the flat layer PLN.
  • the flat layer PLN having a predetermined pattern may be formed by coating a flat material layer and performing a process of exposure, development, etching, or the like on the flat material layer.
  • FIG. 6 is a schematic illustration of the slope angle of a flat layer in accordance with an embodiment of the present invention. Referring to FIG. 6, the contact point of the circular arc of the flat layer PLN and the buffer layer 200 is set to point A, and the arc tangent L1 of the flat layer PLN is formed at point A, and the arc tangent L1 and the carrying flat layer of the buffer layer 200 are applied. The angle (elastic angle) ⁇ between the surfaces of the PLN is the slope angle.
  • an amorphous silicon layer NS is formed on the buffer layer 200 and the flat layer PLN, the amorphous silicon layer including a first portion NS1 on the buffer layer 200 and a second portion NS2 on the flat layer PLN.
  • an annular ring-shaped photoresist layer PR is formed at the junction of the first portion NS1 and the second portion NS2.
  • the photoresist layer PR having a predetermined pattern may be formed by applying a photoresist material layer and subjecting the photoresist material layer to exposure, development, etching, or the like.
  • the shape of the photoresist layer PR is substantially the same as the shape of the polysilicon layer 300 described above, that is, the cross-sectional shape of the photoresist layer PR is also annular; and the longitudinal cross-sectional shape of the photoresist layer PR also includes two triangle-like axes. shape.
  • the amorphous silicon layer NS is etched to form a ring-like amorphous silicon layer NS, and the photoresist layer PR is removed.
  • the structural shape of the ring-like amorphous silicon layer NS is also substantially the same as that of the above-described ring-like polysilicon layer 300, that is, the cross-sectional shape of the ring-like amorphous silicon layer NS also has a circular ring shape; Further, the longitudinal cross-sectional shape of the ring-shaped amorphous silicon layer NS also includes two triangular-like shapes that are axisymmetric.
  • the flat layer PLN is etched away.
  • the ring-like amorphous silicon layer NS is crystallized by solid phase crystallization to form a ring-like polysilicon layer 300.
  • Step 3 Referring to FIG. 4C, a first insulating layer 400 is formed on the buffer layer 200 and the polysilicon layer 300.
  • Step 4 Referring to FIG. 4D, a gate 500 is formed on the first insulating layer 400.
  • Step 5 Referring to FIG. 4E, a second insulating layer 600 is formed on the first insulating layer 400 and the gate 500.
  • Step 6 Referring to FIG. 4F, a source 700 and a drain 800 are formed on the second insulating layer 600.
  • the source 700 and the drain 800 penetrate the second insulating layer 600 and the first insulating layer 400, respectively, to respectively form the polysilicon layer 300. contact.
  • the channel width of the transistor can be reduced, thereby facilitating heat dissipation of the transistor, improving the stability of the transistor, and further facilitating the fabrication of high resolution. Rate, low power display panel.

Landscapes

  • Thin Film Transistor (AREA)

Abstract

一种低温多晶硅薄膜晶体管及其制造方法。该薄膜晶体管包括：在基板（100）上的呈类环状的多晶硅层（300），该多晶硅层（300）的纵截面形状包括轴对称的两个类三角形；在基板（100）和多晶硅层（300）上的第一绝缘层（400）；在第一绝缘层（400）上的栅极（500）；在第一绝缘层（400）上和栅极（500）上的第二绝缘层（600）；在第二绝缘层（600）上的源极（700）和漏极（800），源极（700）和漏极（800）分别贯穿第二绝缘层（600）和第一绝缘层（400）以分别与多晶硅层（300）接触。

Description

低温多晶硅薄膜晶体管及其制作方法 技术领域
本发明属于薄膜晶体管的制作技术领域，具体地讲，涉及一种低温多晶硅薄膜晶体管及其制作方法。
背景技术
目前，作为显示面板的开关元件而广泛采用的是非晶硅薄膜三极管(a-Si TFT)，但a-Si TFT在满足薄型、轻量、高精细度、高亮度、高可靠性、低功耗等要求仍受到限制。低温多晶硅(Lower Temperature Polycrystal Silicon，LTPS)TFT与a-Si TFT相比，具有高电子迁移率的多晶硅层，因此在满足上述要求方面，具有明显优势。
但是，LTPS TFT在具有高电子迁移率的同时，其发热量也随之变大，不利于提高产品的可靠性。
发明内容
为实现上述的目的，本发明提供了一种通过减小沟道宽度来降低发热量的低温多晶硅薄膜晶体管及其制作方法。
根据本发明的一方面，提供了一种低温多晶硅薄膜晶体管，其包括：在基板上的呈类环状的多晶硅层；在所述基板和所述多晶硅层上的第一绝缘层；在所述第一绝缘层上的栅极；在所述第一绝缘层上和所述栅极上的第二绝缘层；在所述第二绝缘层上的源极和漏极，所述源极和所述漏极分别贯穿所述第二绝缘层和所述第一绝缘层，以分别与所述多晶硅层接触。
进一步地，所述多晶硅层的纵截面形状包括轴对称的两个类三角形状，所述类三角形状包括第一直边、第二直边和弧边，所述第一直边位于所述基板上，所述第二直边的第一端与所述第一直边的第一端连接，所述弧边连接在所述第一直边的第二端和所述第二直边的第二端之间，所述弧边向所述类三角形状以 内内凹。
进一步地，所述多晶硅层的横截面形状呈圆环形。
进一步地，所述多晶硅层的内腔的横截面面积沿着远离所述基板的方向逐渐减小。
进一步地，所述低温多晶硅薄膜晶体管还包括在所述基板和多晶硅层之间缓冲层。
根据本发明的另一方面，还提供了一种低温多晶硅薄膜晶体管的制作方法，其包括：在基板上形成呈类环状的多晶硅层；在所述基板和所述多晶硅层上形成第一绝缘层；在所述第一绝缘层上形成栅极；在所述第一绝缘层上和所述栅极上形成第二绝缘层；在所述第二绝缘层上形成源极和漏极，所述源极和所述漏极分别贯穿所述第二绝缘层和所述第一绝缘层，以分别与所述多晶硅层接触。
进一步地，所述在基板上形成呈类环状的多晶硅层的方法包括：在基板上形成平坦层，所述平坦层的纵截面形状呈劣弧，所述平坦层的横截面形状呈圆形；在所述基板和所述平坦层上形成非晶硅层，所述非晶硅层包括位于所述基板上的第一部和位于所述平坦层上的第二部；在所述第一部和所述第二部的衔接处上形成类环状的光阻层；将除所述光阻层下的非晶硅层之外的非晶硅层刻蚀去除；将所述光阻层去除，以形成类环状的非晶硅层；利用固相晶化法对类环状的非晶硅层进行晶化，以形成类环状的多晶硅层。
进一步地，所述平坦层的坡度角的角度为60°～70°。
进一步地，所述平坦层的厚度为2.5μm～3μm。
进一步地，在基板上形成呈类环状的多晶硅层之前，所述制作方法还包括：在基板上形成缓冲层。
本发明的有益效果：本发明通过制作具有类环状的多晶硅层，可以减小晶体管的沟道宽度，从而更利于晶体管的散热，提升晶体管的稳定性，进而有利于制作高分辨率、低功耗的显示面板。
附图说明
通过结合附图进行的以下描述，本发明的实施例的上述和其它方面、特点和优点将变得更加清楚，附图中：
图1是根据本发明的实施例的低温多晶硅薄膜晶体管的结构示意图；
图2是根据本发明的实施例的多晶硅层在缓冲层上的投影图；
图3是根据本发明的实施例的多晶硅层的纵截面形状的示意图；
图4A至图4F是根据本发明的实施例的低温多晶硅薄膜晶体管的制程图；
图5A至图5F是根据本发明的实施例的多晶硅层的制程图；
图6是根据本发明的实施例的平坦层的坡度角的示意图。
具体实施方式
以下，将参照附图来详细描述本发明的实施例。然而，可以以许多不同的形式来实施本发明，并且本发明不应该被解释为限制于这里阐述的具体实施例。相反，提供这些实施例是为了解释本发明的原理及其实际应用，从而使本领域的其他技术人员能够理解本发明的各种实施例和适合于特定预期应用的各种修改。
在附图中，为了清楚起见，夸大了层和区域的厚度。相同的标号在整个说明书和附图中表示相同的元器件。
将理解的是，当诸如层、膜、区域或基底等的元件被称作“在”或者“形成在”另一元件“上”时，该元件可以直接在或者直接形成在所述另一元件上，或者也可以存在中间元件。可选择地，当元件被称作“直接在”或者“直接形成在”另一元件“上”时，不存在中间元件。
图1是根据本发明的实施例的低温多晶硅薄膜晶体管的结构示意图。
参照图1，根据本发明的实施例的低温多晶硅薄膜晶体管包括基板100、缓冲层200、多晶硅层300、第一绝缘层400、栅极500、第二绝缘层600、源极700和漏极800。
基板100可例如是玻璃基板。缓冲层200设置于基板100上。在本实施例中，缓冲层200可例如是由氮化硅(SiN x)层和氧化硅(SioO x)叠层构成，但本发明并不限制于此。这里，缓冲层200的设置是为了防止基板100中的金属离子扩散到多晶硅层300，降低缺陷中心形成和漏电流产生。因此，缓冲层200的设置为一优选设置，作为本发明的另一实施方式，缓冲层200不设置也可以。
多晶硅层300设置于缓冲层200上。多晶硅层300呈类环状，但本发明并不限制于此。
具体地，多晶硅层300的横截面形状呈圆环形状。这里，多晶硅层300的横截面指的是以与缓冲层200的承载多晶硅层300的表面平行的面对多晶硅层300进行的截面。也就是说，多晶硅层300在缓冲层200上的投影呈圆环形状。具体可以参照图2，图2是根据本发明的实施例的多晶硅层在缓冲层上的投影图。
多晶硅层300的纵截面形状包括轴对称的两个类三角形状，即图1所示的多晶硅层300的纵截面形状。这里，多晶硅层300的纵截面指的以与缓冲层200的承载多晶硅层300的表面垂直的面对多晶硅层300进行的截面。此外，为了便于图示和标记，利用图3单独示出多晶硅层300的纵截面形状。图3是根据本发明的实施例的多晶硅层的纵截面形状的示意图。
一并参照图1和图3，多晶硅层300的纵截面形状包括轴对称的两个类三角形状300A。每个类三角形状300A包括第一直边310、第二直边320和弧边330。第一直边310位于缓冲层200上。第二直边320的第一端与第一直边310的第一端连接，第二直边320的第二端远离第一直边310的第二端，即第二直边320与第一直边310之间具有预定的夹角(例如锐角)。弧边330连接在第一直边310的第二端和第二直边320的第二端之间，并且弧边330向类三角形状300A以内(即由第一直边310、第二直边320和弧边330合围而形成的内部)内凹。
在本实施例中，优选地，弧边330上每个点的曲率相等，也就是说，弧边330为圆弧。
进一步地，多晶硅层300内腔的横截面面积沿着远离缓冲层200的方向逐 渐减小。这里，多晶硅层300内腔由轴对称的两个类三角形状300A的弧边330沿圆周延伸形成。
如此，根据本发明的实施例的类环状的多晶硅层300的图案结构，可以减小薄膜晶体管的沟道宽度。
第一绝缘层400设置于缓冲层200和多晶硅层300上，并且第一绝缘层400还用于保护多晶硅层300。第一绝缘层400可以是单层的SiN x或者SiO x，也可以是SiN x/SiO x叠层结构。
栅极500设置于第一绝缘层400上。栅极500可例如是钼铝钼(MoAlMo)结构或钛铝钛(TiAlTi)结构。
第二绝缘层600设置于第一绝缘层400和栅极500上，并且第二绝缘层600还用于保护栅极500。第二绝缘层600可以是单层的SiN x或者SiO x，也可以是SiN x/SiO x叠层结构。
源极700和漏极800彼此间隔设置于第二绝缘层600上。源极700和漏极800可例如是钼铝钼(MoAlMo)结构或钛铝钛(TiAlTi)结构。源极700和漏极800分别贯穿第二绝缘层600和第一绝缘层400，以分别与多晶硅层300接触。这里，由于源极700和漏极800分别与两个类三角形状300A的第二直边320进行接触，接触面积较小，从而也有利于薄膜晶体管的沟道宽度的减小化。
以下将对根据本发明的实施例的低温多晶硅薄膜晶体管的制作方法进行详细描述。图4A至图4F是根据本发明的实施例的低温多晶硅薄膜晶体管的制程图。
步骤一：参照图4A，在基板100上形成缓冲层200。当缓冲层200不存在时，可以将该步骤一省略。
步骤二：参照图4B，在缓冲层200上形成呈类环状的多晶硅层300。
图5A至图5F是根据本发明的实施例的多晶硅层的制程图。
首先，参照图5A，在缓冲层200上形成平坦层PLN，平坦层PLN的纵截面形状呈劣弧，平坦层PLN的横截面形状呈圆形。这里，平坦层PLN的纵截 面指的是以与缓冲层200的承载平坦层PLN的表面平行的面对平坦层PLN进行的截面。平坦层PLN的纵截面指的以与缓冲层200的承载平坦层PLN的表面垂直的面对平坦层PLN进行的截面。这里，可以通过涂布平坦材料层，并对平坦材料层进行曝光、显影、刻蚀等处理而形成具有预定图案的平坦层PLN。
进一步地，平坦层PLN的厚度为2.5μm～3μm，但本发明并不限制于此。此外，平坦层PLN的坡度角的角度为60°～70°，但本发明并不限制于此。图6是根据本发明的实施例的平坦层的坡度角的示意图。参照图6，平坦层PLN的圆弧与缓冲层200的接触点被设定为A点，在A点做平坦层PLN的圆弧切线L1，那么圆弧切线L1与缓冲层200的承载平坦层PLN的表面之间的夹角(锐角)α即为坡度角。
其次，参照图5B，在缓冲层200和平坦层PLN上形成非晶硅层NS，该非晶硅层包括位于缓冲层200上的第一部NS1和位于平坦层PLN上的第二部NS2。
接着，参照图5C，在第一部NS1和第二部NS2的衔接处形成类环状的光阻层PR。这里，可以通过涂布光阻材料层，并对光阻材料层进行曝光、显影、刻蚀等处理而形成具有预定图案的光阻层PR。光阻层PR的形状与上述的多晶硅层300的形状大体相同，即光阻层PR的横截面形状也呈圆环形状；并且光阻层PR的纵截面形状也包括轴对称的两个类三角形状。
接着，参照图5D，对非晶硅层NS进行刻蚀，以形成类环状的非晶硅层NS，并将将光阻层PR去除。这里，类环状的非晶硅层NS的结构形状也与上述的类环状的多晶硅层300的形状大体相同，即类环状的非晶硅层NS的横截面形状也呈圆环形状；并且类环状的非晶硅层NS的纵截面形状也包括轴对称的两个类三角形状。
接着，参照图5E，将平坦层PLN刻蚀去除。
最后，参照图5F，利用固相晶化法对类环状的非晶硅层NS进行晶化，以形成类环状的多晶硅层300。
步骤三：参照图4C，在缓冲层200和多晶硅层300上形成第一绝缘层400。
步骤四：参照图4D，在第一绝缘层400上形成栅极500。
步骤五：参照图4E，在第一绝缘层400和栅极500上形成第二绝缘层600。
步骤六：参照图4F，在第二绝缘层600上形成源极700和漏极800，源极700和漏极800分别贯穿第二绝缘层600和第一绝缘层400，以分别与多晶硅层300接触。
综上所述，根据本发明的实施例，通过制作具有类环状的多晶硅层，可以减小晶体管的沟道宽度，从而更利于晶体管的散热，提升晶体管的稳定性，进而有利于制作高分辨率、低功耗的显示面板。
虽然已经参照特定实施例示出并描述了本发明，但是本领域的技术人员将理解：在不脱离由权利要求及其等同物限定的本发明的精神和范围的情况下，可在此进行形式和细节上的各种变化。

Claims (13)

  1. 一种低温多晶硅薄膜晶体管，其中，包括：
    在基板上的呈类环状的多晶硅层；
    在所述基板和所述多晶硅层上的第一绝缘层；
    在所述第一绝缘层上的栅极；
    在所述第一绝缘层上和所述栅极上的第二绝缘层；
    在所述第二绝缘层上的源极和漏极，所述源极和所述漏极分别贯穿所述第二绝缘层和所述第一绝缘层，以分别与所述多晶硅层接触。
  2. 根据权利要求1所述的低温多晶硅薄膜晶体管，其中，所述多晶硅层的纵截面形状包括轴对称的两个类三角形状，所述类三角形状包括第一直边、第二直边和弧边，所述第一直边位于所述基板上，所述第二直边的第一端与所述第一直边的第一端连接，所述弧边连接在所述第一直边的第二端和所述第二直边的第二端之间，所述弧边向所述类三角形状以内内凹。
  3. 根据权利要求1所述的低温多晶硅薄膜晶体管，其中，所述多晶硅层的横截面形状呈圆环形。
  4. 根据权利要求2所述的低温多晶硅薄膜晶体管，其中，所述多晶硅层的横截面形状呈圆环形。
  5. 根据权利要求3所述的低温多晶硅薄膜晶体管，其中，所述多晶硅层的内腔的横截面面积沿着远离所述基板的方向逐渐减小。
  6. 根据权利要求4所述的低温多晶硅薄膜晶体管，其中，所述多晶硅层的内腔的横截面面积沿着远离所述基板的方向逐渐减小。
  7. 根据权利要求1所述的低温多晶硅薄膜晶体管，其中，所述低温多晶硅薄膜晶体管还包括在所述基板和多晶硅层之间缓冲层。
  8. 一种低温多晶硅薄膜晶体管的制作方法，其中，包括：
    在基板上形成呈类环状的多晶硅层；
    在所述基板和所述多晶硅层上形成第一绝缘层；
    在所述第一绝缘层上形成栅极；
    在所述第一绝缘层上和所述栅极上形成第二绝缘层；
    在所述第二绝缘层上形成源极和漏极，所述源极和所述漏极分别贯穿所述第二绝缘层和所述第一绝缘层，以分别与所述多晶硅层接触。
  9. 根据权利要求8所述的低温多晶硅薄膜晶体管的制作方法，其中，所述在基板上形成呈类环状的多晶硅层的方法包括：
    在基板上形成平坦层，所述平坦层的纵截面形状呈劣弧，所述平坦层的横截面形状呈圆形；
    在所述基板和所述平坦层上形成非晶硅层，所述非晶硅层包括位于所述基板上的第一部和位于所述平坦层上的第二部；
    在所述第一部和所述第二部的衔接处上形成类环状的光阻层；
    对所述非晶硅层进行刻蚀，以形成类环状的非晶硅层，并去除所述光阻层；
    将所述平坦层刻蚀去除；
    利用固相晶化法对类环状的非晶硅层进行晶化，以形成类环状的多晶硅层。
  10. 根据权利要求9所述的低温多晶硅薄膜晶体管的制作方法，其中，所述平坦层的坡度角的角度为60°～70°。
  11. 根据权利要求9所述的低温多晶硅薄膜晶体管的制作方法，其中，所述平坦层的厚度为2.5μm～3μm。
  12. 根据权利要求10所述的低温多晶硅薄膜晶体管的制作方法，其中， 所述平坦层的厚度为2.5μm～3μm。
  13. 根据权利要求8所述的低温多晶硅薄膜晶体管的制作方法，其中，在基板上形成呈类环状的多晶硅层之前，所述制作方法还包括：在基板上形成缓冲层。
PCT/CN2018/078660 2018-01-30 2018-03-12 低温多晶硅薄膜晶体管及其制作方法 Ceased WO2019148592A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/776,347 US20200273999A1 (en) 2018-01-30 2018-03-12 Low-temperature polysilicon (ltps) thin film transistor (tft) and the manufacturing method thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201810090423.5 2018-01-30
CN201810090423.5A CN108336132A (zh) 2018-01-30 2018-01-30 低温多晶硅薄膜晶体管及其制作方法

Publications (1)

Publication Number Publication Date
WO2019148592A1 true WO2019148592A1 (zh) 2019-08-08

Family

ID=62926338

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2018/078660 Ceased WO2019148592A1 (zh) 2018-01-30 2018-03-12 低温多晶硅薄膜晶体管及其制作方法

Country Status (3)

Country Link
US (1) US20200273999A1 (zh)
CN (1) CN108336132A (zh)
WO (1) WO2019148592A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10658392B1 (en) * 2018-11-15 2020-05-19 Mikro Mesa Technology Co., Ltd. Micro light-emitting diode display device and micro light-emitting diode driving circuit thereof

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1719584A (zh) * 2004-07-09 2006-01-11 精工爱普生株式会社 薄膜晶体管的制造方法、电光学装置和电子仪器
US20110180787A1 (en) * 2008-07-03 2011-07-28 Postech Academy-Industry Foundation Ink-Jet Print Ink and Organic Thin Film Transister Using Thereof
CN103680327A (zh) * 2013-12-27 2014-03-26 京东方科技集团股份有限公司 阵列基板及显示装置
CN104483793A (zh) * 2014-12-30 2015-04-01 深圳市华星光电技术有限公司 Tft-lcd像素结构及其制作方法
CN106449407A (zh) * 2016-07-08 2017-02-22 清华大学 环形栅薄膜晶体管及其制备方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160190157A1 (en) * 2014-12-30 2016-06-30 Shenzhen China Star Optoelectronics Technology Co. Ltd. Pixel structure and manufacturing method thereof
CN106057680B (zh) * 2016-07-08 2019-05-31 清华大学 环形栅薄膜晶体管及其制备方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1719584A (zh) * 2004-07-09 2006-01-11 精工爱普生株式会社 薄膜晶体管的制造方法、电光学装置和电子仪器
US20110180787A1 (en) * 2008-07-03 2011-07-28 Postech Academy-Industry Foundation Ink-Jet Print Ink and Organic Thin Film Transister Using Thereof
CN103680327A (zh) * 2013-12-27 2014-03-26 京东方科技集团股份有限公司 阵列基板及显示装置
CN104483793A (zh) * 2014-12-30 2015-04-01 深圳市华星光电技术有限公司 Tft-lcd像素结构及其制作方法
CN106449407A (zh) * 2016-07-08 2017-02-22 清华大学 环形栅薄膜晶体管及其制备方法

Also Published As

Publication number Publication date
US20200273999A1 (en) 2020-08-27
CN108336132A (zh) 2018-07-27

Similar Documents

Publication Publication Date Title
CN105390451B (zh) 低温多晶硅tft基板的制作方法
RU2634087C1 (ru) Тонкопленочный транзистор из низкотемпературного поликристаллического кремния и способ его изготовления
WO2016201609A1 (zh) 金属氧化物薄膜晶体管、显示面板及两者的制备方法
WO2017107274A1 (zh) 一种低温多晶硅薄膜晶体管及其制备方法
WO2015096350A1 (zh) 阵列基板及其制备方法
WO2015188522A1 (zh) 薄膜晶体管及其制作方法、显示装置
CN109841581B (zh) 薄膜晶体管及其制备方法、阵列基板、显示面板及装置
WO2019174195A1 (zh) 低温多晶硅、薄膜晶体管及阵列基板的制作方法
US10170506B2 (en) LTPS array substrate and method for producing the same
WO2020077861A1 (zh) 一种阵列基板及其制备方法
WO2019210602A1 (zh) 阵列基板及其制造方法、显示面板
WO2019148592A1 (zh) 低温多晶硅薄膜晶体管及其制作方法
WO2016011755A1 (zh) 薄膜晶体管及其制备方法、显示基板和显示设备
US9257290B2 (en) Low temperature poly-silicon thin film transistor and manufacturing method thereof
US11133196B2 (en) Gate electrode and method for manufacturing the same, and method for manufacturing array substrate
US10600825B2 (en) Manufacturing method for TFT array substrate and TFT array substrate
WO2022073303A1 (zh) 阵列基板及其制作方法、显示装置
WO2019223195A1 (zh) Tft阵列基板的制作方法及tft阵列基板
WO2019019266A1 (zh) 低温多晶硅薄膜晶体管及其制作方法、显示设备
JP2002043577A (ja) 薄膜半導体装置及びその製造方法
TWI611587B (zh) 氧化物薄膜電晶體
JPS60161672A (ja) 薄膜トランジスタとその製造方法
CN104022042B (zh) 低温多晶硅薄膜晶体管的制作方法和阵列基板的制作方法
JP4011690B2 (ja) 半導体装置の製造方法
WO2018040287A1 (zh) 薄膜晶体管及其制作方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18903842

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 18903842

Country of ref document: EP

Kind code of ref document: A1